460 lines · c
1/* SPDX-License-Identifier: GPL-2.0 */2#ifndef OXYGEN_REGS_H_INCLUDED3#define OXYGEN_REGS_H_INCLUDED4 5/* recording channel A */6#define OXYGEN_DMA_A_ADDRESS 0x00 /* 32-bit base address */7#define OXYGEN_DMA_A_COUNT 0x04 /* buffer counter (dwords) */8#define OXYGEN_DMA_A_TCOUNT 0x06 /* interrupt counter (dwords) */9 10/* recording channel B */11#define OXYGEN_DMA_B_ADDRESS 0x0812#define OXYGEN_DMA_B_COUNT 0x0c13#define OXYGEN_DMA_B_TCOUNT 0x0e14 15/* recording channel C */16#define OXYGEN_DMA_C_ADDRESS 0x1017#define OXYGEN_DMA_C_COUNT 0x1418#define OXYGEN_DMA_C_TCOUNT 0x1619 20/* SPDIF playback channel */21#define OXYGEN_DMA_SPDIF_ADDRESS 0x1822#define OXYGEN_DMA_SPDIF_COUNT 0x1c23#define OXYGEN_DMA_SPDIF_TCOUNT 0x1e24 25/* multichannel playback channel */26#define OXYGEN_DMA_MULTICH_ADDRESS 0x2027#define OXYGEN_DMA_MULTICH_COUNT 0x24 /* 24 bits */28#define OXYGEN_DMA_MULTICH_TCOUNT 0x28 /* 24 bits */29 30/* AC'97 (front panel) playback channel */31#define OXYGEN_DMA_AC97_ADDRESS 0x3032#define OXYGEN_DMA_AC97_COUNT 0x3433#define OXYGEN_DMA_AC97_TCOUNT 0x3634 35/* all registers 0x00..0x36 return current position on read */36 37#define OXYGEN_DMA_STATUS 0x40 /* 1 = running, 0 = stop */38#define OXYGEN_CHANNEL_A 0x0139#define OXYGEN_CHANNEL_B 0x0240#define OXYGEN_CHANNEL_C 0x0441#define OXYGEN_CHANNEL_SPDIF 0x0842#define OXYGEN_CHANNEL_MULTICH 0x1043#define OXYGEN_CHANNEL_AC97 0x2044 45#define OXYGEN_DMA_PAUSE 0x41 /* 1 = pause */46/* OXYGEN_CHANNEL_* */47 48#define OXYGEN_DMA_RESET 0x4249/* OXYGEN_CHANNEL_* */50 51#define OXYGEN_PLAY_CHANNELS 0x4352#define OXYGEN_PLAY_CHANNELS_MASK 0x0353#define OXYGEN_PLAY_CHANNELS_2 0x0054#define OXYGEN_PLAY_CHANNELS_4 0x0155#define OXYGEN_PLAY_CHANNELS_6 0x0256#define OXYGEN_PLAY_CHANNELS_8 0x0357#define OXYGEN_DMA_A_BURST_MASK 0x0458#define OXYGEN_DMA_A_BURST_8 0x00 /* dwords */59#define OXYGEN_DMA_A_BURST_16 0x0460#define OXYGEN_DMA_MULTICH_BURST_MASK 0x0861#define OXYGEN_DMA_MULTICH_BURST_8 0x0062#define OXYGEN_DMA_MULTICH_BURST_16 0x0863 64#define OXYGEN_INTERRUPT_MASK 0x4465/* OXYGEN_CHANNEL_* */66#define OXYGEN_INT_SPDIF_IN_DETECT 0x010067#define OXYGEN_INT_MCU 0x020068#define OXYGEN_INT_2WIRE 0x040069#define OXYGEN_INT_GPIO 0x080070#define OXYGEN_INT_MCB 0x200071#define OXYGEN_INT_AC97 0x400072 73#define OXYGEN_INTERRUPT_STATUS 0x4674/* OXYGEN_CHANNEL_* amd OXYGEN_INT_* */75#define OXYGEN_INT_MIDI 0x100076 77#define OXYGEN_MISC 0x4878#define OXYGEN_MISC_WRITE_PCI_SUBID 0x0179#define OXYGEN_MISC_LATENCY_3F 0x0280#define OXYGEN_MISC_REC_C_FROM_SPDIF 0x0481#define OXYGEN_MISC_REC_B_FROM_AC97 0x0882#define OXYGEN_MISC_REC_A_FROM_MULTICH 0x1083#define OXYGEN_MISC_PCI_MEM_W_1_CLOCK 0x2084#define OXYGEN_MISC_MIDI 0x4085#define OXYGEN_MISC_CRYSTAL_MASK 0x8086#define OXYGEN_MISC_CRYSTAL_24576 0x0087#define OXYGEN_MISC_CRYSTAL_27 0x80 /* MHz */88 89#define OXYGEN_REC_FORMAT 0x4a90#define OXYGEN_REC_FORMAT_A_MASK 0x0391#define OXYGEN_REC_FORMAT_A_SHIFT 092#define OXYGEN_REC_FORMAT_B_MASK 0x0c93#define OXYGEN_REC_FORMAT_B_SHIFT 294#define OXYGEN_REC_FORMAT_C_MASK 0x3095#define OXYGEN_REC_FORMAT_C_SHIFT 496#define OXYGEN_FORMAT_16 0x0097#define OXYGEN_FORMAT_24 0x0198#define OXYGEN_FORMAT_32 0x0299 100#define OXYGEN_PLAY_FORMAT 0x4b101#define OXYGEN_SPDIF_FORMAT_MASK 0x03102#define OXYGEN_SPDIF_FORMAT_SHIFT 0103#define OXYGEN_MULTICH_FORMAT_MASK 0x0c104#define OXYGEN_MULTICH_FORMAT_SHIFT 2105/* OXYGEN_FORMAT_* */106 107#define OXYGEN_REC_CHANNELS 0x4c108#define OXYGEN_REC_CHANNELS_MASK 0x07109#define OXYGEN_REC_CHANNELS_2_2_2 0x00 /* DMA A, B, C */110#define OXYGEN_REC_CHANNELS_4_2_2 0x01111#define OXYGEN_REC_CHANNELS_6_0_2 0x02112#define OXYGEN_REC_CHANNELS_6_2_0 0x03113#define OXYGEN_REC_CHANNELS_8_0_0 0x04114 115#define OXYGEN_FUNCTION 0x50116#define OXYGEN_FUNCTION_CLOCK_MASK 0x01117#define OXYGEN_FUNCTION_CLOCK_PLL 0x00118#define OXYGEN_FUNCTION_CLOCK_CRYSTAL 0x01119#define OXYGEN_FUNCTION_RESET_CODEC 0x02120#define OXYGEN_FUNCTION_RESET_POL 0x04121#define OXYGEN_FUNCTION_PWDN 0x08122#define OXYGEN_FUNCTION_PWDN_EN 0x10123#define OXYGEN_FUNCTION_PWDN_POL 0x20124#define OXYGEN_FUNCTION_2WIRE_SPI_MASK 0x40125#define OXYGEN_FUNCTION_SPI 0x00126#define OXYGEN_FUNCTION_2WIRE 0x40127#define OXYGEN_FUNCTION_ENABLE_SPI_4_5 0x80 /* 0 = EEPROM */128 129#define OXYGEN_I2S_MULTICH_FORMAT 0x60130#define OXYGEN_I2S_RATE_MASK 0x0007 /* LRCK */131#define OXYGEN_RATE_32000 0x0000132#define OXYGEN_RATE_44100 0x0001133#define OXYGEN_RATE_48000 0x0002134#define OXYGEN_RATE_64000 0x0003135#define OXYGEN_RATE_88200 0x0004136#define OXYGEN_RATE_96000 0x0005137#define OXYGEN_RATE_176400 0x0006138#define OXYGEN_RATE_192000 0x0007139#define OXYGEN_I2S_FORMAT_MASK 0x0008140#define OXYGEN_I2S_FORMAT_I2S 0x0000141#define OXYGEN_I2S_FORMAT_LJUST 0x0008142#define OXYGEN_I2S_MCLK_MASK 0x0030 /* MCLK/LRCK */143#define OXYGEN_I2S_MCLK_SHIFT 4144#define MCLK_128 0145#define MCLK_256 1146#define MCLK_512 2147#define OXYGEN_I2S_MCLK(f) (((f) & 3) << OXYGEN_I2S_MCLK_SHIFT)148#define OXYGEN_I2S_BITS_MASK 0x00c0149#define OXYGEN_I2S_BITS_16 0x0000150#define OXYGEN_I2S_BITS_20 0x0040151#define OXYGEN_I2S_BITS_24 0x0080152#define OXYGEN_I2S_BITS_32 0x00c0153#define OXYGEN_I2S_MASTER 0x0100154#define OXYGEN_I2S_BCLK_MASK 0x0600 /* BCLK/LRCK */155#define OXYGEN_I2S_BCLK_64 0x0000156#define OXYGEN_I2S_BCLK_128 0x0200157#define OXYGEN_I2S_BCLK_256 0x0400158#define OXYGEN_I2S_MUTE_MCLK 0x0800159 160#define OXYGEN_I2S_A_FORMAT 0x62161#define OXYGEN_I2S_B_FORMAT 0x64162#define OXYGEN_I2S_C_FORMAT 0x66163/* like OXYGEN_I2S_MULTICH_FORMAT */164 165#define OXYGEN_SPDIF_CONTROL 0x70166#define OXYGEN_SPDIF_OUT_ENABLE 0x00000002167#define OXYGEN_SPDIF_LOOPBACK 0x00000004 /* in to out */168#define OXYGEN_SPDIF_SENSE_MASK 0x00000008169#define OXYGEN_SPDIF_LOCK_MASK 0x00000010170#define OXYGEN_SPDIF_RATE_MASK 0x00000020171#define OXYGEN_SPDIF_SPDVALID 0x00000040172#define OXYGEN_SPDIF_SENSE_PAR 0x00000200173#define OXYGEN_SPDIF_LOCK_PAR 0x00000400174#define OXYGEN_SPDIF_SENSE_STATUS 0x00000800175#define OXYGEN_SPDIF_LOCK_STATUS 0x00001000176#define OXYGEN_SPDIF_SENSE_INT 0x00002000 /* r/wc */177#define OXYGEN_SPDIF_LOCK_INT 0x00004000 /* r/wc */178#define OXYGEN_SPDIF_RATE_INT 0x00008000 /* r/wc */179#define OXYGEN_SPDIF_IN_CLOCK_MASK 0x00010000180#define OXYGEN_SPDIF_IN_CLOCK_96 0x00000000 /* <= 96 kHz */181#define OXYGEN_SPDIF_IN_CLOCK_192 0x00010000 /* > 96 kHz */182#define OXYGEN_SPDIF_OUT_RATE_MASK 0x07000000183#define OXYGEN_SPDIF_OUT_RATE_SHIFT 24184/* OXYGEN_RATE_* << OXYGEN_SPDIF_OUT_RATE_SHIFT */185 186#define OXYGEN_SPDIF_OUTPUT_BITS 0x74187#define OXYGEN_SPDIF_NONAUDIO 0x00000002188#define OXYGEN_SPDIF_C 0x00000004189#define OXYGEN_SPDIF_PREEMPHASIS 0x00000008190#define OXYGEN_SPDIF_CATEGORY_MASK 0x000007f0191#define OXYGEN_SPDIF_CATEGORY_SHIFT 4192#define OXYGEN_SPDIF_ORIGINAL 0x00000800193#define OXYGEN_SPDIF_CS_RATE_MASK 0x0000f000194#define OXYGEN_SPDIF_CS_RATE_SHIFT 12195#define OXYGEN_SPDIF_V 0x00010000 /* 0 = valid */196 197#define OXYGEN_SPDIF_INPUT_BITS 0x78198/* 32 bits, IEC958_AES_* */199 200#define OXYGEN_EEPROM_CONTROL 0x80201#define OXYGEN_EEPROM_ADDRESS_MASK 0x7f202#define OXYGEN_EEPROM_DIR_MASK 0x80203#define OXYGEN_EEPROM_DIR_READ 0x00204#define OXYGEN_EEPROM_DIR_WRITE 0x80205 206#define OXYGEN_EEPROM_STATUS 0x81207#define OXYGEN_EEPROM_VALID 0x40208#define OXYGEN_EEPROM_BUSY 0x80209 210#define OXYGEN_EEPROM_DATA 0x82 /* 16 bits */211 212#define OXYGEN_2WIRE_CONTROL 0x90213#define OXYGEN_2WIRE_DIR_MASK 0x01214#define OXYGEN_2WIRE_DIR_WRITE 0x00215#define OXYGEN_2WIRE_DIR_READ 0x01216#define OXYGEN_2WIRE_ADDRESS_MASK 0xfe /* slave device address */217#define OXYGEN_2WIRE_ADDRESS_SHIFT 1218 219#define OXYGEN_2WIRE_MAP 0x91 /* address, 8 bits */220#define OXYGEN_2WIRE_DATA 0x92 /* data, 16 bits */221 222#define OXYGEN_2WIRE_BUS_STATUS 0x94223#define OXYGEN_2WIRE_BUSY 0x0001224#define OXYGEN_2WIRE_LENGTH_MASK 0x0002225#define OXYGEN_2WIRE_LENGTH_8 0x0000226#define OXYGEN_2WIRE_LENGTH_16 0x0002227#define OXYGEN_2WIRE_MANUAL_READ 0x0004 /* 0 = auto read */228#define OXYGEN_2WIRE_WRITE_MAP_ONLY 0x0008229#define OXYGEN_2WIRE_SLAVE_AD_MASK 0x0030 /* AD0, AD1 */230#define OXYGEN_2WIRE_INTERRUPT_MASK 0x0040 /* 0 = int. if not responding */231#define OXYGEN_2WIRE_SLAVE_NO_RESPONSE 0x0080232#define OXYGEN_2WIRE_SPEED_MASK 0x0100233#define OXYGEN_2WIRE_SPEED_STANDARD 0x0000234#define OXYGEN_2WIRE_SPEED_FAST 0x0100235#define OXYGEN_2WIRE_CLOCK_SYNC 0x0200236#define OXYGEN_2WIRE_BUS_RESET 0x0400237 238#define OXYGEN_SPI_CONTROL 0x98239#define OXYGEN_SPI_BUSY 0x01 /* read */240#define OXYGEN_SPI_TRIGGER 0x01 /* write */241#define OXYGEN_SPI_DATA_LENGTH_MASK 0x02242#define OXYGEN_SPI_DATA_LENGTH_2 0x00243#define OXYGEN_SPI_DATA_LENGTH_3 0x02244#define OXYGEN_SPI_CLOCK_MASK 0x0c245#define OXYGEN_SPI_CLOCK_160 0x00 /* ns */246#define OXYGEN_SPI_CLOCK_320 0x04247#define OXYGEN_SPI_CLOCK_640 0x08248#define OXYGEN_SPI_CLOCK_1280 0x0c249#define OXYGEN_SPI_CODEC_MASK 0x70 /* 0..5 */250#define OXYGEN_SPI_CODEC_SHIFT 4251#define OXYGEN_SPI_CEN_MASK 0x80252#define OXYGEN_SPI_CEN_LATCH_CLOCK_LO 0x00253#define OXYGEN_SPI_CEN_LATCH_CLOCK_HI 0x80254 255#define OXYGEN_SPI_DATA1 0x99256#define OXYGEN_SPI_DATA2 0x9a257#define OXYGEN_SPI_DATA3 0x9b258 259#define OXYGEN_MPU401 0xa0260 261#define OXYGEN_MPU401_CONTROL 0xa2262#define OXYGEN_MPU401_LOOPBACK 0x01 /* TXD to RXD */263 264#define OXYGEN_GPI_DATA 0xa4265/* bits 0..5 = pin XGPI0..XGPI5 */266 267#define OXYGEN_GPI_INTERRUPT_MASK 0xa5268/* bits 0..5, 1 = enable */269 270#define OXYGEN_GPIO_DATA 0xa6271/* bits 0..9 */272 273#define OXYGEN_GPIO_CONTROL 0xa8274/* bits 0..9, 0 = input, 1 = output */275#define OXYGEN_GPIO1_XSLAVE_RDY 0x8000276 277#define OXYGEN_GPIO_INTERRUPT_MASK 0xaa278/* bits 0..9, 1 = enable */279 280#define OXYGEN_DEVICE_SENSE 0xac281#define OXYGEN_HEAD_PHONE_DETECT 0x01282#define OXYGEN_HEAD_PHONE_MASK 0x06283#define OXYGEN_HEAD_PHONE_PASSIVE_SPK 0x00284#define OXYGEN_HEAD_PHONE_HP 0x02285#define OXYGEN_HEAD_PHONE_ACTIVE_SPK 0x04286 287#define OXYGEN_MCU_2WIRE_DATA 0xb0288 289#define OXYGEN_MCU_2WIRE_MAP 0xb2290 291#define OXYGEN_MCU_2WIRE_STATUS 0xb3292#define OXYGEN_MCU_2WIRE_BUSY 0x01293#define OXYGEN_MCU_2WIRE_LENGTH_MASK 0x06294#define OXYGEN_MCU_2WIRE_LENGTH_1 0x00295#define OXYGEN_MCU_2WIRE_LENGTH_2 0x02296#define OXYGEN_MCU_2WIRE_LENGTH_3 0x04297#define OXYGEN_MCU_2WIRE_WRITE 0x08 /* r/wc */298#define OXYGEN_MCU_2WIRE_READ 0x10 /* r/wc */299#define OXYGEN_MCU_2WIRE_DRV_XACT_FAIL 0x20 /* r/wc */300#define OXYGEN_MCU_2WIRE_RESET 0x40301 302#define OXYGEN_MCU_2WIRE_CONTROL 0xb4303#define OXYGEN_MCU_2WIRE_DRV_ACK 0x01304#define OXYGEN_MCU_2WIRE_DRV_XACT 0x02305#define OXYGEN_MCU_2WIRE_INT_MASK 0x04306#define OXYGEN_MCU_2WIRE_SYNC_MASK 0x08307#define OXYGEN_MCU_2WIRE_SYNC_RDY_PIN 0x00308#define OXYGEN_MCU_2WIRE_SYNC_DATA 0x08309#define OXYGEN_MCU_2WIRE_ADDRESS_MASK 0x30310#define OXYGEN_MCU_2WIRE_ADDRESS_10 0x00311#define OXYGEN_MCU_2WIRE_ADDRESS_12 0x10312#define OXYGEN_MCU_2WIRE_ADDRESS_14 0x20313#define OXYGEN_MCU_2WIRE_ADDRESS_16 0x30314#define OXYGEN_MCU_2WIRE_INT_POL 0x40315#define OXYGEN_MCU_2WIRE_SYNC_ENABLE 0x80316 317#define OXYGEN_PLAY_ROUTING 0xc0318#define OXYGEN_PLAY_MUTE01 0x0001319#define OXYGEN_PLAY_MUTE23 0x0002320#define OXYGEN_PLAY_MUTE45 0x0004321#define OXYGEN_PLAY_MUTE67 0x0008322#define OXYGEN_PLAY_MUTE_MASK 0x000f323#define OXYGEN_PLAY_MULTICH_MASK 0x0010324#define OXYGEN_PLAY_MULTICH_I2S_DAC 0x0000325#define OXYGEN_PLAY_MULTICH_AC97 0x0010326#define OXYGEN_PLAY_SPDIF_MASK 0x00e0327#define OXYGEN_PLAY_SPDIF_SPDIF 0x0000328#define OXYGEN_PLAY_SPDIF_MULTICH_01 0x0020329#define OXYGEN_PLAY_SPDIF_MULTICH_23 0x0040330#define OXYGEN_PLAY_SPDIF_MULTICH_45 0x0060331#define OXYGEN_PLAY_SPDIF_MULTICH_67 0x0080332#define OXYGEN_PLAY_SPDIF_REC_A 0x00a0333#define OXYGEN_PLAY_SPDIF_REC_B 0x00c0334#define OXYGEN_PLAY_SPDIF_I2S_ADC_3 0x00e0335#define OXYGEN_PLAY_DAC0_SOURCE_MASK 0x0300336#define OXYGEN_PLAY_DAC0_SOURCE_SHIFT 8337#define OXYGEN_PLAY_DAC1_SOURCE_MASK 0x0c00338#define OXYGEN_PLAY_DAC1_SOURCE_SHIFT 10339#define OXYGEN_PLAY_DAC2_SOURCE_MASK 0x3000340#define OXYGEN_PLAY_DAC2_SOURCE_SHIFT 12341#define OXYGEN_PLAY_DAC3_SOURCE_MASK 0xc000342#define OXYGEN_PLAY_DAC3_SOURCE_SHIFT 14343 344#define OXYGEN_REC_ROUTING 0xc2345#define OXYGEN_MUTE_I2S_ADC_1 0x01346#define OXYGEN_MUTE_I2S_ADC_2 0x02347#define OXYGEN_MUTE_I2S_ADC_3 0x04348#define OXYGEN_REC_A_ROUTE_MASK 0x08349#define OXYGEN_REC_A_ROUTE_I2S_ADC_1 0x00350#define OXYGEN_REC_A_ROUTE_AC97_0 0x08351#define OXYGEN_REC_B_ROUTE_MASK 0x10352#define OXYGEN_REC_B_ROUTE_I2S_ADC_2 0x00353#define OXYGEN_REC_B_ROUTE_AC97_1 0x10354#define OXYGEN_REC_C_ROUTE_MASK 0x20355#define OXYGEN_REC_C_ROUTE_SPDIF 0x00356#define OXYGEN_REC_C_ROUTE_I2S_ADC_3 0x20357 358#define OXYGEN_ADC_MONITOR 0xc3359#define OXYGEN_ADC_MONITOR_A 0x01360#define OXYGEN_ADC_MONITOR_A_HALF_VOL 0x02361#define OXYGEN_ADC_MONITOR_B 0x04362#define OXYGEN_ADC_MONITOR_B_HALF_VOL 0x08363#define OXYGEN_ADC_MONITOR_C 0x10364#define OXYGEN_ADC_MONITOR_C_HALF_VOL 0x20365 366#define OXYGEN_A_MONITOR_ROUTING 0xc4367#define OXYGEN_A_MONITOR_ROUTE_0_MASK 0x03368#define OXYGEN_A_MONITOR_ROUTE_0_SHIFT 0369#define OXYGEN_A_MONITOR_ROUTE_1_MASK 0x0c370#define OXYGEN_A_MONITOR_ROUTE_1_SHIFT 2371#define OXYGEN_A_MONITOR_ROUTE_2_MASK 0x30372#define OXYGEN_A_MONITOR_ROUTE_2_SHIFT 4373#define OXYGEN_A_MONITOR_ROUTE_3_MASK 0xc0374#define OXYGEN_A_MONITOR_ROUTE_3_SHIFT 6375 376#define OXYGEN_AC97_CONTROL 0xd0377#define OXYGEN_AC97_COLD_RESET 0x0001378#define OXYGEN_AC97_SUSPENDED 0x0002 /* read */379#define OXYGEN_AC97_RESUME 0x0002 /* write */380#define OXYGEN_AC97_CLOCK_DISABLE 0x0004381#define OXYGEN_AC97_NO_CODEC_0 0x0008382#define OXYGEN_AC97_CODEC_0 0x0010383#define OXYGEN_AC97_CODEC_1 0x0020384 385#define OXYGEN_AC97_INTERRUPT_MASK 0xd2386#define OXYGEN_AC97_INT_READ_DONE 0x01387#define OXYGEN_AC97_INT_WRITE_DONE 0x02388#define OXYGEN_AC97_INT_CODEC_0 0x10389#define OXYGEN_AC97_INT_CODEC_1 0x20390 391#define OXYGEN_AC97_INTERRUPT_STATUS 0xd3392/* OXYGEN_AC97_INT_* */393 394#define OXYGEN_AC97_OUT_CONFIG 0xd4395#define OXYGEN_AC97_CODEC1_SLOT3 0x00000001396#define OXYGEN_AC97_CODEC1_SLOT3_VSR 0x00000002397#define OXYGEN_AC97_CODEC1_SLOT4 0x00000010398#define OXYGEN_AC97_CODEC1_SLOT4_VSR 0x00000020399#define OXYGEN_AC97_CODEC0_FRONTL 0x00000100400#define OXYGEN_AC97_CODEC0_FRONTR 0x00000200401#define OXYGEN_AC97_CODEC0_SIDEL 0x00000400402#define OXYGEN_AC97_CODEC0_SIDER 0x00000800403#define OXYGEN_AC97_CODEC0_CENTER 0x00001000404#define OXYGEN_AC97_CODEC0_BASE 0x00002000405#define OXYGEN_AC97_CODEC0_REARL 0x00004000406#define OXYGEN_AC97_CODEC0_REARR 0x00008000407 408#define OXYGEN_AC97_IN_CONFIG 0xd8409#define OXYGEN_AC97_CODEC1_LINEL 0x00000001410#define OXYGEN_AC97_CODEC1_LINEL_VSR 0x00000002411#define OXYGEN_AC97_CODEC1_LINEL_16 0x00000000412#define OXYGEN_AC97_CODEC1_LINEL_18 0x00000004413#define OXYGEN_AC97_CODEC1_LINEL_20 0x00000008414#define OXYGEN_AC97_CODEC1_LINER 0x00000010415#define OXYGEN_AC97_CODEC1_LINER_VSR 0x00000020416#define OXYGEN_AC97_CODEC1_LINER_16 0x00000000417#define OXYGEN_AC97_CODEC1_LINER_18 0x00000040418#define OXYGEN_AC97_CODEC1_LINER_20 0x00000080419#define OXYGEN_AC97_CODEC0_LINEL 0x00000100420#define OXYGEN_AC97_CODEC0_LINER 0x00000200421 422#define OXYGEN_AC97_REGS 0xdc423#define OXYGEN_AC97_REG_DATA_MASK 0x0000ffff424#define OXYGEN_AC97_REG_ADDR_MASK 0x007f0000425#define OXYGEN_AC97_REG_ADDR_SHIFT 16426#define OXYGEN_AC97_REG_DIR_MASK 0x00800000427#define OXYGEN_AC97_REG_DIR_WRITE 0x00000000428#define OXYGEN_AC97_REG_DIR_READ 0x00800000429#define OXYGEN_AC97_REG_CODEC_MASK 0x01000000430#define OXYGEN_AC97_REG_CODEC_SHIFT 24431 432#define OXYGEN_TEST 0xe0433#define OXYGEN_TEST_RAM_SUCCEEDED 0x01434#define OXYGEN_TEST_PLAYBACK_RAM 0x02435#define OXYGEN_TEST_RECORD_RAM 0x04436#define OXYGEN_TEST_PLL 0x08437#define OXYGEN_TEST_2WIRE_LOOPBACK 0x10438 439#define OXYGEN_DMA_FLUSH 0xe1440/* OXYGEN_CHANNEL_* */441 442#define OXYGEN_CODEC_VERSION 0xe4443#define OXYGEN_CODEC_ID_MASK 0x07444 445#define OXYGEN_REVISION 0xe6446#define OXYGEN_PACKAGE_ID_MASK 0x0007447#define OXYGEN_PACKAGE_ID_8786 0x0004448#define OXYGEN_PACKAGE_ID_8787 0x0006449#define OXYGEN_PACKAGE_ID_8788 0x0007450#define OXYGEN_REVISION_MASK 0xfff8451#define OXYGEN_REVISION_2 0x0008452 453#define OXYGEN_OFFSIN_48K 0xe8454#define OXYGEN_OFFSBASE_48K 0xe9455#define OXYGEN_OFFSBASE_MASK 0x0fff456#define OXYGEN_OFFSIN_44K 0xec457#define OXYGEN_OFFSBASE_44K 0xed458 459#endif460