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1// SPDX-License-Identifier: GPL-2.0-or-later2/*3 * ALSA driver for RME Hammerfall DSP audio interface(s)4 *5 * Copyright (c) 2002 Paul Davis6 * Marcus Andersson7 * Thomas Charbonnel8 */9 10#include <linux/init.h>11#include <linux/delay.h>12#include <linux/interrupt.h>13#include <linux/pci.h>14#include <linux/firmware.h>15#include <linux/module.h>16#include <linux/math64.h>17#include <linux/vmalloc.h>18#include <linux/io.h>19#include <linux/nospec.h>20 21#include <sound/core.h>22#include <sound/control.h>23#include <sound/pcm.h>24#include <sound/info.h>25#include <sound/asoundef.h>26#include <sound/rawmidi.h>27#include <sound/hwdep.h>28#include <sound/initval.h>29#include <sound/hdsp.h>30 31#include <asm/byteorder.h>32#include <asm/current.h>33 34static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */35static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */36static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */37 38module_param_array(index, int, NULL, 0444);39MODULE_PARM_DESC(index, "Index value for RME Hammerfall DSP interface.");40module_param_array(id, charp, NULL, 0444);41MODULE_PARM_DESC(id, "ID string for RME Hammerfall DSP interface.");42module_param_array(enable, bool, NULL, 0444);43MODULE_PARM_DESC(enable, "Enable/disable specific Hammerfall DSP soundcards.");44MODULE_AUTHOR("Paul Davis <paul@linuxaudiosystems.com>, Marcus Andersson, Thomas Charbonnel <thomas@undata.org>");45MODULE_DESCRIPTION("RME Hammerfall DSP");46MODULE_LICENSE("GPL");47MODULE_FIRMWARE("rpm_firmware.bin");48MODULE_FIRMWARE("multiface_firmware.bin");49MODULE_FIRMWARE("multiface_firmware_rev11.bin");50MODULE_FIRMWARE("digiface_firmware.bin");51MODULE_FIRMWARE("digiface_firmware_rev11.bin");52 53#define HDSP_MAX_CHANNELS 2654#define HDSP_MAX_DS_CHANNELS 1455#define HDSP_MAX_QS_CHANNELS 856#define DIGIFACE_SS_CHANNELS 2657#define DIGIFACE_DS_CHANNELS 1458#define MULTIFACE_SS_CHANNELS 1859#define MULTIFACE_DS_CHANNELS 1460#define H9652_SS_CHANNELS 2661#define H9652_DS_CHANNELS 1462/* This does not include possible Analog Extension Boards63 AEBs are detected at card initialization64*/65#define H9632_SS_CHANNELS 1266#define H9632_DS_CHANNELS 867#define H9632_QS_CHANNELS 468#define RPM_CHANNELS 669 70/* Write registers. These are defined as byte-offsets from the iobase value.71 */72#define HDSP_resetPointer 073#define HDSP_freqReg 074#define HDSP_outputBufferAddress 3275#define HDSP_inputBufferAddress 3676#define HDSP_controlRegister 6477#define HDSP_interruptConfirmation 9678#define HDSP_outputEnable 12879#define HDSP_control2Reg 25680#define HDSP_midiDataOut0 35281#define HDSP_midiDataOut1 35682#define HDSP_fifoData 36883#define HDSP_inputEnable 38484 85/* Read registers. These are defined as byte-offsets from the iobase value86 */87 88#define HDSP_statusRegister 089#define HDSP_timecode 12890#define HDSP_status2Register 19291#define HDSP_midiDataIn0 36092#define HDSP_midiDataIn1 36493#define HDSP_midiStatusOut0 38494#define HDSP_midiStatusOut1 38895#define HDSP_midiStatusIn0 39296#define HDSP_midiStatusIn1 39697#define HDSP_fifoStatus 40098 99/* the meters are regular i/o-mapped registers, but offset100 considerably from the rest. the peak registers are reset101 when read; the least-significant 4 bits are full-scale counters;102 the actual peak value is in the most-significant 24 bits.103*/104 105#define HDSP_playbackPeakLevel 4096 /* 26 * 32 bit values */106#define HDSP_inputPeakLevel 4224 /* 26 * 32 bit values */107#define HDSP_outputPeakLevel 4352 /* (26+2) * 32 bit values */108#define HDSP_playbackRmsLevel 4612 /* 26 * 64 bit values */109#define HDSP_inputRmsLevel 4868 /* 26 * 64 bit values */110 111 112/* This is for H9652 cards113 Peak values are read downward from the base114 Rms values are read upward115 There are rms values for the outputs too116 26*3 values are read in ss mode117 14*3 in ds mode, with no gap between values118*/119#define HDSP_9652_peakBase 7164120#define HDSP_9652_rmsBase 4096121 122/* c.f. the hdsp_9632_meters_t struct */123#define HDSP_9632_metersBase 4096124 125#define HDSP_IO_EXTENT 7168126 127/* control2 register bits */128 129#define HDSP_TMS 0x01130#define HDSP_TCK 0x02131#define HDSP_TDI 0x04132#define HDSP_JTAG 0x08133#define HDSP_PWDN 0x10134#define HDSP_PROGRAM 0x020135#define HDSP_CONFIG_MODE_0 0x040136#define HDSP_CONFIG_MODE_1 0x080137#define HDSP_VERSION_BIT (0x100 | HDSP_S_LOAD)138#define HDSP_BIGENDIAN_MODE 0x200139#define HDSP_RD_MULTIPLE 0x400140#define HDSP_9652_ENABLE_MIXER 0x800141#define HDSP_S200 0x800142#define HDSP_S300 (0x100 | HDSP_S200) /* dummy, purpose of 0x100 unknown */143#define HDSP_CYCLIC_MODE 0x1000144#define HDSP_TDO 0x10000000145 146#define HDSP_S_PROGRAM (HDSP_CYCLIC_MODE|HDSP_PROGRAM|HDSP_CONFIG_MODE_0)147#define HDSP_S_LOAD (HDSP_CYCLIC_MODE|HDSP_PROGRAM|HDSP_CONFIG_MODE_1)148 149/* Control Register bits */150 151#define HDSP_Start (1<<0) /* start engine */152#define HDSP_Latency0 (1<<1) /* buffer size = 2^n where n is defined by Latency{2,1,0} */153#define HDSP_Latency1 (1<<2) /* [ see above ] */154#define HDSP_Latency2 (1<<3) /* [ see above ] */155#define HDSP_ClockModeMaster (1<<4) /* 1=Master, 0=Slave/Autosync */156#define HDSP_AudioInterruptEnable (1<<5) /* what do you think ? */157#define HDSP_Frequency0 (1<<6) /* 0=44.1kHz/88.2kHz/176.4kHz 1=48kHz/96kHz/192kHz */158#define HDSP_Frequency1 (1<<7) /* 0=32kHz/64kHz/128kHz */159#define HDSP_DoubleSpeed (1<<8) /* 0=normal speed, 1=double speed */160#define HDSP_SPDIFProfessional (1<<9) /* 0=consumer, 1=professional */161#define HDSP_SPDIFEmphasis (1<<10) /* 0=none, 1=on */162#define HDSP_SPDIFNonAudio (1<<11) /* 0=off, 1=on */163#define HDSP_SPDIFOpticalOut (1<<12) /* 1=use 1st ADAT connector for SPDIF, 0=do not */164#define HDSP_SyncRef2 (1<<13)165#define HDSP_SPDIFInputSelect0 (1<<14)166#define HDSP_SPDIFInputSelect1 (1<<15)167#define HDSP_SyncRef0 (1<<16)168#define HDSP_SyncRef1 (1<<17)169#define HDSP_AnalogExtensionBoard (1<<18) /* For H9632 cards */170#define HDSP_XLRBreakoutCable (1<<20) /* For H9632 cards */171#define HDSP_Midi0InterruptEnable (1<<22)172#define HDSP_Midi1InterruptEnable (1<<23)173#define HDSP_LineOut (1<<24)174#define HDSP_ADGain0 (1<<25) /* From here : H9632 specific */175#define HDSP_ADGain1 (1<<26)176#define HDSP_DAGain0 (1<<27)177#define HDSP_DAGain1 (1<<28)178#define HDSP_PhoneGain0 (1<<29)179#define HDSP_PhoneGain1 (1<<30)180#define HDSP_QuadSpeed (1<<31)181 182/* RPM uses some of the registers for special purposes */183#define HDSP_RPM_Inp12 0x04A00184#define HDSP_RPM_Inp12_Phon_6dB 0x00800 /* Dolby */185#define HDSP_RPM_Inp12_Phon_0dB 0x00000 /* .. */186#define HDSP_RPM_Inp12_Phon_n6dB 0x04000 /* inp_0 */187#define HDSP_RPM_Inp12_Line_0dB 0x04200 /* Dolby+PRO */188#define HDSP_RPM_Inp12_Line_n6dB 0x00200 /* PRO */189 190#define HDSP_RPM_Inp34 0x32000191#define HDSP_RPM_Inp34_Phon_6dB 0x20000 /* SyncRef1 */192#define HDSP_RPM_Inp34_Phon_0dB 0x00000 /* .. */193#define HDSP_RPM_Inp34_Phon_n6dB 0x02000 /* SyncRef2 */194#define HDSP_RPM_Inp34_Line_0dB 0x30000 /* SyncRef1+SyncRef0 */195#define HDSP_RPM_Inp34_Line_n6dB 0x10000 /* SyncRef0 */196 197#define HDSP_RPM_Bypass 0x01000198 199#define HDSP_RPM_Disconnect 0x00001200 201#define HDSP_ADGainMask (HDSP_ADGain0|HDSP_ADGain1)202#define HDSP_ADGainMinus10dBV HDSP_ADGainMask203#define HDSP_ADGainPlus4dBu (HDSP_ADGain0)204#define HDSP_ADGainLowGain 0205 206#define HDSP_DAGainMask (HDSP_DAGain0|HDSP_DAGain1)207#define HDSP_DAGainHighGain HDSP_DAGainMask208#define HDSP_DAGainPlus4dBu (HDSP_DAGain0)209#define HDSP_DAGainMinus10dBV 0210 211#define HDSP_PhoneGainMask (HDSP_PhoneGain0|HDSP_PhoneGain1)212#define HDSP_PhoneGain0dB HDSP_PhoneGainMask213#define HDSP_PhoneGainMinus6dB (HDSP_PhoneGain0)214#define HDSP_PhoneGainMinus12dB 0215 216#define HDSP_LatencyMask (HDSP_Latency0|HDSP_Latency1|HDSP_Latency2)217#define HDSP_FrequencyMask (HDSP_Frequency0|HDSP_Frequency1|HDSP_DoubleSpeed|HDSP_QuadSpeed)218 219#define HDSP_SPDIFInputMask (HDSP_SPDIFInputSelect0|HDSP_SPDIFInputSelect1)220#define HDSP_SPDIFInputADAT1 0221#define HDSP_SPDIFInputCoaxial (HDSP_SPDIFInputSelect0)222#define HDSP_SPDIFInputCdrom (HDSP_SPDIFInputSelect1)223#define HDSP_SPDIFInputAES (HDSP_SPDIFInputSelect0|HDSP_SPDIFInputSelect1)224 225#define HDSP_SyncRefMask (HDSP_SyncRef0|HDSP_SyncRef1|HDSP_SyncRef2)226#define HDSP_SyncRef_ADAT1 0227#define HDSP_SyncRef_ADAT2 (HDSP_SyncRef0)228#define HDSP_SyncRef_ADAT3 (HDSP_SyncRef1)229#define HDSP_SyncRef_SPDIF (HDSP_SyncRef0|HDSP_SyncRef1)230#define HDSP_SyncRef_WORD (HDSP_SyncRef2)231#define HDSP_SyncRef_ADAT_SYNC (HDSP_SyncRef0|HDSP_SyncRef2)232 233/* Sample Clock Sources */234 235#define HDSP_CLOCK_SOURCE_AUTOSYNC 0236#define HDSP_CLOCK_SOURCE_INTERNAL_32KHZ 1237#define HDSP_CLOCK_SOURCE_INTERNAL_44_1KHZ 2238#define HDSP_CLOCK_SOURCE_INTERNAL_48KHZ 3239#define HDSP_CLOCK_SOURCE_INTERNAL_64KHZ 4240#define HDSP_CLOCK_SOURCE_INTERNAL_88_2KHZ 5241#define HDSP_CLOCK_SOURCE_INTERNAL_96KHZ 6242#define HDSP_CLOCK_SOURCE_INTERNAL_128KHZ 7243#define HDSP_CLOCK_SOURCE_INTERNAL_176_4KHZ 8244#define HDSP_CLOCK_SOURCE_INTERNAL_192KHZ 9245 246/* Preferred sync reference choices - used by "pref_sync_ref" control switch */247 248#define HDSP_SYNC_FROM_WORD 0249#define HDSP_SYNC_FROM_SPDIF 1250#define HDSP_SYNC_FROM_ADAT1 2251#define HDSP_SYNC_FROM_ADAT_SYNC 3252#define HDSP_SYNC_FROM_ADAT2 4253#define HDSP_SYNC_FROM_ADAT3 5254 255/* SyncCheck status */256 257#define HDSP_SYNC_CHECK_NO_LOCK 0258#define HDSP_SYNC_CHECK_LOCK 1259#define HDSP_SYNC_CHECK_SYNC 2260 261/* AutoSync references - used by "autosync_ref" control switch */262 263#define HDSP_AUTOSYNC_FROM_WORD 0264#define HDSP_AUTOSYNC_FROM_ADAT_SYNC 1265#define HDSP_AUTOSYNC_FROM_SPDIF 2266#define HDSP_AUTOSYNC_FROM_NONE 3267#define HDSP_AUTOSYNC_FROM_ADAT1 4268#define HDSP_AUTOSYNC_FROM_ADAT2 5269#define HDSP_AUTOSYNC_FROM_ADAT3 6270 271/* Possible sources of S/PDIF input */272 273#define HDSP_SPDIFIN_OPTICAL 0 /* optical (ADAT1) */274#define HDSP_SPDIFIN_COAXIAL 1 /* coaxial (RCA) */275#define HDSP_SPDIFIN_INTERNAL 2 /* internal (CDROM) */276#define HDSP_SPDIFIN_AES 3 /* xlr for H9632 (AES)*/277 278#define HDSP_Frequency32KHz HDSP_Frequency0279#define HDSP_Frequency44_1KHz HDSP_Frequency1280#define HDSP_Frequency48KHz (HDSP_Frequency1|HDSP_Frequency0)281#define HDSP_Frequency64KHz (HDSP_DoubleSpeed|HDSP_Frequency0)282#define HDSP_Frequency88_2KHz (HDSP_DoubleSpeed|HDSP_Frequency1)283#define HDSP_Frequency96KHz (HDSP_DoubleSpeed|HDSP_Frequency1|HDSP_Frequency0)284/* For H9632 cards */285#define HDSP_Frequency128KHz (HDSP_QuadSpeed|HDSP_DoubleSpeed|HDSP_Frequency0)286#define HDSP_Frequency176_4KHz (HDSP_QuadSpeed|HDSP_DoubleSpeed|HDSP_Frequency1)287#define HDSP_Frequency192KHz (HDSP_QuadSpeed|HDSP_DoubleSpeed|HDSP_Frequency1|HDSP_Frequency0)288/* RME says n = 104857600000000, but in the windows MADI driver, I see:289 return 104857600000000 / rate; // 100 MHz290 return 110100480000000 / rate; // 105 MHz291*/292#define DDS_NUMERATOR 104857600000000ULL /* = 2^20 * 10^8 */293 294#define hdsp_encode_latency(x) (((x)<<1) & HDSP_LatencyMask)295#define hdsp_decode_latency(x) (((x) & HDSP_LatencyMask)>>1)296 297#define hdsp_encode_spdif_in(x) (((x)&0x3)<<14)298#define hdsp_decode_spdif_in(x) (((x)>>14)&0x3)299 300/* Status Register bits */301 302#define HDSP_audioIRQPending (1<<0)303#define HDSP_Lock2 (1<<1) /* this is for Digiface and H9652 */304#define HDSP_spdifFrequency3 HDSP_Lock2 /* this is for H9632 only */305#define HDSP_Lock1 (1<<2)306#define HDSP_Lock0 (1<<3)307#define HDSP_SPDIFSync (1<<4)308#define HDSP_TimecodeLock (1<<5)309#define HDSP_BufferPositionMask 0x000FFC0 /* Bit 6..15 : h/w buffer pointer */310#define HDSP_Sync2 (1<<16)311#define HDSP_Sync1 (1<<17)312#define HDSP_Sync0 (1<<18)313#define HDSP_DoubleSpeedStatus (1<<19)314#define HDSP_ConfigError (1<<20)315#define HDSP_DllError (1<<21)316#define HDSP_spdifFrequency0 (1<<22)317#define HDSP_spdifFrequency1 (1<<23)318#define HDSP_spdifFrequency2 (1<<24)319#define HDSP_SPDIFErrorFlag (1<<25)320#define HDSP_BufferID (1<<26)321#define HDSP_TimecodeSync (1<<27)322#define HDSP_AEBO (1<<28) /* H9632 specific Analog Extension Boards */323#define HDSP_AEBI (1<<29) /* 0 = present, 1 = absent */324#define HDSP_midi0IRQPending (1<<30)325#define HDSP_midi1IRQPending (1<<31)326 327#define HDSP_spdifFrequencyMask (HDSP_spdifFrequency0|HDSP_spdifFrequency1|HDSP_spdifFrequency2)328#define HDSP_spdifFrequencyMask_9632 (HDSP_spdifFrequency0|\329 HDSP_spdifFrequency1|\330 HDSP_spdifFrequency2|\331 HDSP_spdifFrequency3)332 333#define HDSP_spdifFrequency32KHz (HDSP_spdifFrequency0)334#define HDSP_spdifFrequency44_1KHz (HDSP_spdifFrequency1)335#define HDSP_spdifFrequency48KHz (HDSP_spdifFrequency0|HDSP_spdifFrequency1)336 337#define HDSP_spdifFrequency64KHz (HDSP_spdifFrequency2)338#define HDSP_spdifFrequency88_2KHz (HDSP_spdifFrequency0|HDSP_spdifFrequency2)339#define HDSP_spdifFrequency96KHz (HDSP_spdifFrequency2|HDSP_spdifFrequency1)340 341/* This is for H9632 cards */342#define HDSP_spdifFrequency128KHz (HDSP_spdifFrequency0|\343 HDSP_spdifFrequency1|\344 HDSP_spdifFrequency2)345#define HDSP_spdifFrequency176_4KHz HDSP_spdifFrequency3346#define HDSP_spdifFrequency192KHz (HDSP_spdifFrequency3|HDSP_spdifFrequency0)347 348/* Status2 Register bits */349 350#define HDSP_version0 (1<<0)351#define HDSP_version1 (1<<1)352#define HDSP_version2 (1<<2)353#define HDSP_wc_lock (1<<3)354#define HDSP_wc_sync (1<<4)355#define HDSP_inp_freq0 (1<<5)356#define HDSP_inp_freq1 (1<<6)357#define HDSP_inp_freq2 (1<<7)358#define HDSP_SelSyncRef0 (1<<8)359#define HDSP_SelSyncRef1 (1<<9)360#define HDSP_SelSyncRef2 (1<<10)361 362#define HDSP_wc_valid (HDSP_wc_lock|HDSP_wc_sync)363 364#define HDSP_systemFrequencyMask (HDSP_inp_freq0|HDSP_inp_freq1|HDSP_inp_freq2)365#define HDSP_systemFrequency32 (HDSP_inp_freq0)366#define HDSP_systemFrequency44_1 (HDSP_inp_freq1)367#define HDSP_systemFrequency48 (HDSP_inp_freq0|HDSP_inp_freq1)368#define HDSP_systemFrequency64 (HDSP_inp_freq2)369#define HDSP_systemFrequency88_2 (HDSP_inp_freq0|HDSP_inp_freq2)370#define HDSP_systemFrequency96 (HDSP_inp_freq1|HDSP_inp_freq2)371/* FIXME : more values for 9632 cards ? */372 373#define HDSP_SelSyncRefMask (HDSP_SelSyncRef0|HDSP_SelSyncRef1|HDSP_SelSyncRef2)374#define HDSP_SelSyncRef_ADAT1 0375#define HDSP_SelSyncRef_ADAT2 (HDSP_SelSyncRef0)376#define HDSP_SelSyncRef_ADAT3 (HDSP_SelSyncRef1)377#define HDSP_SelSyncRef_SPDIF (HDSP_SelSyncRef0|HDSP_SelSyncRef1)378#define HDSP_SelSyncRef_WORD (HDSP_SelSyncRef2)379#define HDSP_SelSyncRef_ADAT_SYNC (HDSP_SelSyncRef0|HDSP_SelSyncRef2)380 381/* Card state flags */382 383#define HDSP_InitializationComplete (1<<0)384#define HDSP_FirmwareLoaded (1<<1)385#define HDSP_FirmwareCached (1<<2)386 387/* FIFO wait times, defined in terms of 1/10ths of msecs */388 389#define HDSP_LONG_WAIT 5000390#define HDSP_SHORT_WAIT 30391 392#define UNITY_GAIN 32768393#define MINUS_INFINITY_GAIN 0394 395/* the size of a substream (1 mono data stream) */396 397#define HDSP_CHANNEL_BUFFER_SAMPLES (16*1024)398#define HDSP_CHANNEL_BUFFER_BYTES (4*HDSP_CHANNEL_BUFFER_SAMPLES)399 400/* the size of the area we need to allocate for DMA transfers. the401 size is the same regardless of the number of channels - the402 Multiface still uses the same memory area.403 404 Note that we allocate 1 more channel than is apparently needed405 because the h/w seems to write 1 byte beyond the end of the last406 page. Sigh.407*/408 409#define HDSP_DMA_AREA_BYTES ((HDSP_MAX_CHANNELS+1) * HDSP_CHANNEL_BUFFER_BYTES)410#define HDSP_DMA_AREA_KILOBYTES (HDSP_DMA_AREA_BYTES/1024)411 412#define HDSP_FIRMWARE_SIZE (24413 * 4)413 414struct hdsp_9632_meters {415 u32 input_peak[16];416 u32 playback_peak[16];417 u32 output_peak[16];418 u32 xxx_peak[16];419 u32 padding[64];420 u32 input_rms_low[16];421 u32 playback_rms_low[16];422 u32 output_rms_low[16];423 u32 xxx_rms_low[16];424 u32 input_rms_high[16];425 u32 playback_rms_high[16];426 u32 output_rms_high[16];427 u32 xxx_rms_high[16];428};429 430struct hdsp_midi {431 struct hdsp *hdsp;432 int id;433 struct snd_rawmidi *rmidi;434 struct snd_rawmidi_substream *input;435 struct snd_rawmidi_substream *output;436 signed char istimer; /* timer in use */437 struct timer_list timer;438 spinlock_t lock;439 int pending;440};441 442struct hdsp {443 spinlock_t lock;444 struct snd_pcm_substream *capture_substream;445 struct snd_pcm_substream *playback_substream;446 struct hdsp_midi midi[2];447 struct work_struct midi_work;448 int use_midi_work;449 int precise_ptr;450 u32 control_register; /* cached value */451 u32 control2_register; /* cached value */452 u32 creg_spdif;453 u32 creg_spdif_stream;454 int clock_source_locked;455 char *card_name; /* digiface/multiface/rpm */456 enum HDSP_IO_Type io_type; /* ditto, but for code use */457 unsigned short firmware_rev;458 unsigned short state; /* stores state bits */459 const struct firmware *firmware;460 u32 *fw_uploaded;461 size_t period_bytes; /* guess what this is */462 unsigned char max_channels;463 unsigned char qs_in_channels; /* quad speed mode for H9632 */464 unsigned char ds_in_channels;465 unsigned char ss_in_channels; /* different for multiface/digiface */466 unsigned char qs_out_channels;467 unsigned char ds_out_channels;468 unsigned char ss_out_channels;469 u32 io_loopback; /* output loopback channel states*/470 471 /* DMA buffers; those are copied instances from the original snd_dma_buf472 * objects (which are managed via devres) for the address alignments473 */474 struct snd_dma_buffer capture_dma_buf;475 struct snd_dma_buffer playback_dma_buf;476 unsigned char *capture_buffer; /* suitably aligned address */477 unsigned char *playback_buffer; /* suitably aligned address */478 479 pid_t capture_pid;480 pid_t playback_pid;481 int running;482 int system_sample_rate;483 const signed char *channel_map;484 int dev;485 int irq;486 unsigned long port;487 void __iomem *iobase;488 struct snd_card *card;489 struct snd_pcm *pcm;490 struct snd_hwdep *hwdep;491 struct pci_dev *pci;492 struct snd_kcontrol *spdif_ctl;493 unsigned short mixer_matrix[HDSP_MATRIX_MIXER_SIZE];494 unsigned int dds_value; /* last value written to freq register */495};496 497/* These tables map the ALSA channels 1..N to the channels that we498 need to use in order to find the relevant channel buffer. RME499 refer to this kind of mapping as between "the ADAT channel and500 the DMA channel." We index it using the logical audio channel,501 and the value is the DMA channel (i.e. channel buffer number)502 where the data for that channel can be read/written from/to.503*/504 505static const signed char channel_map_df_ss[HDSP_MAX_CHANNELS] = {506 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,507 18, 19, 20, 21, 22, 23, 24, 25508};509 510static const char channel_map_mf_ss[HDSP_MAX_CHANNELS] = { /* Multiface */511 /* Analog */512 0, 1, 2, 3, 4, 5, 6, 7,513 /* ADAT 2 */514 16, 17, 18, 19, 20, 21, 22, 23,515 /* SPDIF */516 24, 25,517 -1, -1, -1, -1, -1, -1, -1, -1518};519 520static const signed char channel_map_ds[HDSP_MAX_CHANNELS] = {521 /* ADAT channels are remapped */522 1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23,523 /* channels 12 and 13 are S/PDIF */524 24, 25,525 /* others don't exist */526 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1527};528 529static const signed char channel_map_H9632_ss[HDSP_MAX_CHANNELS] = {530 /* ADAT channels */531 0, 1, 2, 3, 4, 5, 6, 7,532 /* SPDIF */533 8, 9,534 /* Analog */535 10, 11,536 /* AO4S-192 and AI4S-192 extension boards */537 12, 13, 14, 15,538 /* others don't exist */539 -1, -1, -1, -1, -1, -1, -1, -1,540 -1, -1541};542 543static const signed char channel_map_H9632_ds[HDSP_MAX_CHANNELS] = {544 /* ADAT */545 1, 3, 5, 7,546 /* SPDIF */547 8, 9,548 /* Analog */549 10, 11,550 /* AO4S-192 and AI4S-192 extension boards */551 12, 13, 14, 15,552 /* others don't exist */553 -1, -1, -1, -1, -1, -1, -1, -1,554 -1, -1, -1, -1, -1, -1555};556 557static const signed char channel_map_H9632_qs[HDSP_MAX_CHANNELS] = {558 /* ADAT is disabled in this mode */559 /* SPDIF */560 8, 9,561 /* Analog */562 10, 11,563 /* AO4S-192 and AI4S-192 extension boards */564 12, 13, 14, 15,565 /* others don't exist */566 -1, -1, -1, -1, -1, -1, -1, -1,567 -1, -1, -1, -1, -1, -1, -1, -1,568 -1, -1569};570 571static struct snd_dma_buffer *572snd_hammerfall_get_buffer(struct pci_dev *pci, size_t size)573{574 return snd_devm_alloc_pages(&pci->dev, SNDRV_DMA_TYPE_DEV, size);575}576 577static const struct pci_device_id snd_hdsp_ids[] = {578 {579 .vendor = PCI_VENDOR_ID_XILINX,580 .device = PCI_DEVICE_ID_XILINX_HAMMERFALL_DSP,581 .subvendor = PCI_ANY_ID,582 .subdevice = PCI_ANY_ID,583 }, /* RME Hammerfall-DSP */584 { 0, },585};586 587MODULE_DEVICE_TABLE(pci, snd_hdsp_ids);588 589/* prototypes */590static int snd_hdsp_create_alsa_devices(struct snd_card *card, struct hdsp *hdsp);591static int snd_hdsp_create_pcm(struct snd_card *card, struct hdsp *hdsp);592static int snd_hdsp_enable_io (struct hdsp *hdsp);593static void snd_hdsp_initialize_midi_flush (struct hdsp *hdsp);594static void snd_hdsp_initialize_channels (struct hdsp *hdsp);595static int hdsp_fifo_wait(struct hdsp *hdsp, int count, int timeout);596static int hdsp_autosync_ref(struct hdsp *hdsp);597static int snd_hdsp_set_defaults(struct hdsp *hdsp);598static void snd_hdsp_9652_enable_mixer (struct hdsp *hdsp);599 600static int hdsp_playback_to_output_key (struct hdsp *hdsp, int in, int out)601{602 switch (hdsp->io_type) {603 case Multiface:604 case Digiface:605 case RPM:606 default:607 if (hdsp->firmware_rev == 0xa)608 return (64 * out) + (32 + (in));609 else610 return (52 * out) + (26 + (in));611 case H9632:612 return (32 * out) + (16 + (in));613 case H9652:614 return (52 * out) + (26 + (in));615 }616}617 618static int hdsp_input_to_output_key (struct hdsp *hdsp, int in, int out)619{620 switch (hdsp->io_type) {621 case Multiface:622 case Digiface:623 case RPM:624 default:625 if (hdsp->firmware_rev == 0xa)626 return (64 * out) + in;627 else628 return (52 * out) + in;629 case H9632:630 return (32 * out) + in;631 case H9652:632 return (52 * out) + in;633 }634}635 636static void hdsp_write(struct hdsp *hdsp, int reg, int val)637{638 writel(val, hdsp->iobase + reg);639}640 641static unsigned int hdsp_read(struct hdsp *hdsp, int reg)642{643 return readl (hdsp->iobase + reg);644}645 646static int hdsp_check_for_iobox (struct hdsp *hdsp)647{648 int i;649 650 if (hdsp->io_type == H9652 || hdsp->io_type == H9632) return 0;651 for (i = 0; i < 500; i++) {652 if (0 == (hdsp_read(hdsp, HDSP_statusRegister) &653 HDSP_ConfigError)) {654 if (i) {655 dev_dbg(hdsp->card->dev,656 "IO box found after %d ms\n",657 (20 * i));658 }659 return 0;660 }661 msleep(20);662 }663 dev_err(hdsp->card->dev, "no IO box connected!\n");664 hdsp->state &= ~HDSP_FirmwareLoaded;665 return -EIO;666}667 668static int hdsp_wait_for_iobox(struct hdsp *hdsp, unsigned int loops,669 unsigned int delay)670{671 unsigned int i;672 673 if (hdsp->io_type == H9652 || hdsp->io_type == H9632)674 return 0;675 676 for (i = 0; i != loops; ++i) {677 if (hdsp_read(hdsp, HDSP_statusRegister) & HDSP_ConfigError)678 msleep(delay);679 else {680 dev_dbg(hdsp->card->dev, "iobox found after %ums!\n",681 i * delay);682 return 0;683 }684 }685 686 dev_info(hdsp->card->dev, "no IO box connected!\n");687 hdsp->state &= ~HDSP_FirmwareLoaded;688 return -EIO;689}690 691static int snd_hdsp_load_firmware_from_cache(struct hdsp *hdsp) {692 693 int i;694 unsigned long flags;695 const u32 *cache;696 697 if (hdsp->fw_uploaded)698 cache = hdsp->fw_uploaded;699 else {700 if (!hdsp->firmware)701 return -ENODEV;702 cache = (u32 *)hdsp->firmware->data;703 if (!cache)704 return -ENODEV;705 }706 707 if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {708 709 dev_info(hdsp->card->dev, "loading firmware\n");710 711 hdsp_write (hdsp, HDSP_control2Reg, HDSP_S_PROGRAM);712 hdsp_write (hdsp, HDSP_fifoData, 0);713 714 if (hdsp_fifo_wait (hdsp, 0, HDSP_LONG_WAIT)) {715 dev_info(hdsp->card->dev,716 "timeout waiting for download preparation\n");717 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S200);718 return -EIO;719 }720 721 hdsp_write (hdsp, HDSP_control2Reg, HDSP_S_LOAD);722 723 for (i = 0; i < HDSP_FIRMWARE_SIZE / 4; ++i) {724 hdsp_write(hdsp, HDSP_fifoData, cache[i]);725 if (hdsp_fifo_wait (hdsp, 127, HDSP_LONG_WAIT)) {726 dev_info(hdsp->card->dev,727 "timeout during firmware loading\n");728 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S200);729 return -EIO;730 }731 }732 733 hdsp_fifo_wait(hdsp, 3, HDSP_LONG_WAIT);734 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S200);735 736 ssleep(3);737#ifdef SNDRV_BIG_ENDIAN738 hdsp->control2_register = HDSP_BIGENDIAN_MODE;739#else740 hdsp->control2_register = 0;741#endif742 hdsp_write (hdsp, HDSP_control2Reg, hdsp->control2_register);743 dev_info(hdsp->card->dev, "finished firmware loading\n");744 745 }746 if (hdsp->state & HDSP_InitializationComplete) {747 dev_info(hdsp->card->dev,748 "firmware loaded from cache, restoring defaults\n");749 spin_lock_irqsave(&hdsp->lock, flags);750 snd_hdsp_set_defaults(hdsp);751 spin_unlock_irqrestore(&hdsp->lock, flags);752 }753 754 hdsp->state |= HDSP_FirmwareLoaded;755 756 return 0;757}758 759static int hdsp_get_iobox_version (struct hdsp *hdsp)760{761 if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {762 763 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S_LOAD);764 hdsp_write(hdsp, HDSP_fifoData, 0);765 766 if (hdsp_fifo_wait(hdsp, 0, HDSP_SHORT_WAIT) < 0) {767 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S300);768 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S_LOAD);769 }770 771 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S200 | HDSP_PROGRAM);772 hdsp_write (hdsp, HDSP_fifoData, 0);773 if (hdsp_fifo_wait(hdsp, 0, HDSP_SHORT_WAIT) < 0)774 goto set_multi;775 776 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S_LOAD);777 hdsp_write(hdsp, HDSP_fifoData, 0);778 if (hdsp_fifo_wait(hdsp, 0, HDSP_SHORT_WAIT) == 0) {779 hdsp->io_type = Digiface;780 dev_info(hdsp->card->dev, "Digiface found\n");781 return 0;782 }783 784 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S300);785 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S_LOAD);786 hdsp_write(hdsp, HDSP_fifoData, 0);787 if (hdsp_fifo_wait(hdsp, 0, HDSP_SHORT_WAIT) == 0)788 goto set_multi;789 790 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S300);791 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S_LOAD);792 hdsp_write(hdsp, HDSP_fifoData, 0);793 if (hdsp_fifo_wait(hdsp, 0, HDSP_SHORT_WAIT) < 0)794 goto set_multi;795 796 hdsp->io_type = RPM;797 dev_info(hdsp->card->dev, "RPM found\n");798 return 0;799 } else {800 /* firmware was already loaded, get iobox type */801 if (hdsp_read(hdsp, HDSP_status2Register) & HDSP_version2)802 hdsp->io_type = RPM;803 else if (hdsp_read(hdsp, HDSP_status2Register) & HDSP_version1)804 hdsp->io_type = Multiface;805 else806 hdsp->io_type = Digiface;807 }808 return 0;809 810set_multi:811 hdsp->io_type = Multiface;812 dev_info(hdsp->card->dev, "Multiface found\n");813 return 0;814}815 816 817static int hdsp_request_fw_loader(struct hdsp *hdsp);818 819static int hdsp_check_for_firmware (struct hdsp *hdsp, int load_on_demand)820{821 if (hdsp->io_type == H9652 || hdsp->io_type == H9632)822 return 0;823 if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {824 hdsp->state &= ~HDSP_FirmwareLoaded;825 if (! load_on_demand)826 return -EIO;827 dev_err(hdsp->card->dev, "firmware not present.\n");828 /* try to load firmware */829 if (! (hdsp->state & HDSP_FirmwareCached)) {830 if (! hdsp_request_fw_loader(hdsp))831 return 0;832 dev_err(hdsp->card->dev,833 "No firmware loaded nor cached, please upload firmware.\n");834 return -EIO;835 }836 if (snd_hdsp_load_firmware_from_cache(hdsp) != 0) {837 dev_err(hdsp->card->dev,838 "Firmware loading from cache failed, please upload manually.\n");839 return -EIO;840 }841 }842 return 0;843}844 845 846static int hdsp_fifo_wait(struct hdsp *hdsp, int count, int timeout)847{848 int i;849 850 /* the fifoStatus registers reports on how many words851 are available in the command FIFO.852 */853 854 for (i = 0; i < timeout; i++) {855 856 if ((int)(hdsp_read (hdsp, HDSP_fifoStatus) & 0xff) <= count)857 return 0;858 859 /* not very friendly, but we only do this during a firmware860 load and changing the mixer, so we just put up with it.861 */862 863 udelay (100);864 }865 866 dev_warn(hdsp->card->dev,867 "wait for FIFO status <= %d failed after %d iterations\n",868 count, timeout);869 return -1;870}871 872static int hdsp_read_gain (struct hdsp *hdsp, unsigned int addr)873{874 if (addr >= HDSP_MATRIX_MIXER_SIZE)875 return 0;876 877 return hdsp->mixer_matrix[addr];878}879 880static int hdsp_write_gain(struct hdsp *hdsp, unsigned int addr, unsigned short data)881{882 unsigned int ad;883 884 if (addr >= HDSP_MATRIX_MIXER_SIZE)885 return -1;886 887 if (hdsp->io_type == H9652 || hdsp->io_type == H9632) {888 889 /* from martin bjornsen:890 891 "You can only write dwords to the892 mixer memory which contain two893 mixer values in the low and high894 word. So if you want to change895 value 0 you have to read value 1896 from the cache and write both to897 the first dword in the mixer898 memory."899 */900 901 if (hdsp->io_type == H9632 && addr >= 512)902 return 0;903 904 if (hdsp->io_type == H9652 && addr >= 1352)905 return 0;906 907 hdsp->mixer_matrix[addr] = data;908 909 910 /* `addr' addresses a 16-bit wide address, but911 the address space accessed via hdsp_write912 uses byte offsets. put another way, addr913 varies from 0 to 1351, but to access the914 corresponding memory location, we need915 to access 0 to 2703 ...916 */917 ad = addr/2;918 919 hdsp_write (hdsp, 4096 + (ad*4),920 (hdsp->mixer_matrix[(addr&0x7fe)+1] << 16) +921 hdsp->mixer_matrix[addr&0x7fe]);922 923 return 0;924 925 } else {926 927 ad = (addr << 16) + data;928 929 if (hdsp_fifo_wait(hdsp, 127, HDSP_LONG_WAIT))930 return -1;931 932 hdsp_write (hdsp, HDSP_fifoData, ad);933 hdsp->mixer_matrix[addr] = data;934 935 }936 937 return 0;938}939 940static int snd_hdsp_use_is_exclusive(struct hdsp *hdsp)941{942 unsigned long flags;943 int ret = 1;944 945 spin_lock_irqsave(&hdsp->lock, flags);946 if ((hdsp->playback_pid != hdsp->capture_pid) &&947 (hdsp->playback_pid >= 0) && (hdsp->capture_pid >= 0))948 ret = 0;949 spin_unlock_irqrestore(&hdsp->lock, flags);950 return ret;951}952 953static int hdsp_spdif_sample_rate(struct hdsp *hdsp)954{955 unsigned int status = hdsp_read(hdsp, HDSP_statusRegister);956 unsigned int rate_bits = (status & HDSP_spdifFrequencyMask);957 958 /* For the 9632, the mask is different */959 if (hdsp->io_type == H9632)960 rate_bits = (status & HDSP_spdifFrequencyMask_9632);961 962 if (status & HDSP_SPDIFErrorFlag)963 return 0;964 965 switch (rate_bits) {966 case HDSP_spdifFrequency32KHz: return 32000;967 case HDSP_spdifFrequency44_1KHz: return 44100;968 case HDSP_spdifFrequency48KHz: return 48000;969 case HDSP_spdifFrequency64KHz: return 64000;970 case HDSP_spdifFrequency88_2KHz: return 88200;971 case HDSP_spdifFrequency96KHz: return 96000;972 case HDSP_spdifFrequency128KHz:973 if (hdsp->io_type == H9632) return 128000;974 break;975 case HDSP_spdifFrequency176_4KHz:976 if (hdsp->io_type == H9632) return 176400;977 break;978 case HDSP_spdifFrequency192KHz:979 if (hdsp->io_type == H9632) return 192000;980 break;981 default:982 break;983 }984 dev_warn(hdsp->card->dev,985 "unknown spdif frequency status; bits = 0x%x, status = 0x%x\n",986 rate_bits, status);987 return 0;988}989 990static int hdsp_external_sample_rate(struct hdsp *hdsp)991{992 unsigned int status2 = hdsp_read(hdsp, HDSP_status2Register);993 unsigned int rate_bits = status2 & HDSP_systemFrequencyMask;994 995 /* For the 9632 card, there seems to be no bit for indicating external996 * sample rate greater than 96kHz. The card reports the corresponding997 * single speed. So the best means seems to get spdif rate when998 * autosync reference is spdif */999 if (hdsp->io_type == H9632 &&1000 hdsp_autosync_ref(hdsp) == HDSP_AUTOSYNC_FROM_SPDIF)1001 return hdsp_spdif_sample_rate(hdsp);1002 1003 switch (rate_bits) {1004 case HDSP_systemFrequency32: return 32000;1005 case HDSP_systemFrequency44_1: return 44100;1006 case HDSP_systemFrequency48: return 48000;1007 case HDSP_systemFrequency64: return 64000;1008 case HDSP_systemFrequency88_2: return 88200;1009 case HDSP_systemFrequency96: return 96000;1010 default:1011 return 0;1012 }1013}1014 1015static void hdsp_compute_period_size(struct hdsp *hdsp)1016{1017 hdsp->period_bytes = 1 << ((hdsp_decode_latency(hdsp->control_register) + 8));1018}1019 1020static snd_pcm_uframes_t hdsp_hw_pointer(struct hdsp *hdsp)1021{1022 int position;1023 1024 position = hdsp_read(hdsp, HDSP_statusRegister);1025 1026 if (!hdsp->precise_ptr)1027 return (position & HDSP_BufferID) ? (hdsp->period_bytes / 4) : 0;1028 1029 position &= HDSP_BufferPositionMask;1030 position /= 4;1031 position &= (hdsp->period_bytes/2) - 1;1032 return position;1033}1034 1035static void hdsp_reset_hw_pointer(struct hdsp *hdsp)1036{1037 hdsp_write (hdsp, HDSP_resetPointer, 0);1038 if (hdsp->io_type == H9632 && hdsp->firmware_rev >= 152)1039 /* HDSP_resetPointer = HDSP_freqReg, which is strange and1040 * requires (?) to write again DDS value after a reset pointer1041 * (at least, it works like this) */1042 hdsp_write (hdsp, HDSP_freqReg, hdsp->dds_value);1043}1044 1045static void hdsp_start_audio(struct hdsp *s)1046{1047 s->control_register |= (HDSP_AudioInterruptEnable | HDSP_Start);1048 hdsp_write(s, HDSP_controlRegister, s->control_register);1049}1050 1051static void hdsp_stop_audio(struct hdsp *s)1052{1053 s->control_register &= ~(HDSP_Start | HDSP_AudioInterruptEnable);1054 hdsp_write(s, HDSP_controlRegister, s->control_register);1055}1056 1057static void hdsp_silence_playback(struct hdsp *hdsp)1058{1059 memset(hdsp->playback_buffer, 0, HDSP_DMA_AREA_BYTES);1060}1061 1062static int hdsp_set_interrupt_interval(struct hdsp *s, unsigned int frames)1063{1064 int n;1065 1066 spin_lock_irq(&s->lock);1067 1068 frames >>= 7;1069 n = 0;1070 while (frames) {1071 n++;1072 frames >>= 1;1073 }1074 1075 s->control_register &= ~HDSP_LatencyMask;1076 s->control_register |= hdsp_encode_latency(n);1077 1078 hdsp_write(s, HDSP_controlRegister, s->control_register);1079 1080 hdsp_compute_period_size(s);1081 1082 spin_unlock_irq(&s->lock);1083 1084 return 0;1085}1086 1087static void hdsp_set_dds_value(struct hdsp *hdsp, int rate)1088{1089 u64 n;1090 1091 if (rate >= 112000)1092 rate /= 4;1093 else if (rate >= 56000)1094 rate /= 2;1095 1096 n = DDS_NUMERATOR;1097 n = div_u64(n, rate);1098 /* n should be less than 2^32 for being written to FREQ register */1099 snd_BUG_ON(n >> 32);1100 /* HDSP_freqReg and HDSP_resetPointer are the same, so keep the DDS1101 value to write it after a reset */1102 hdsp->dds_value = n;1103 hdsp_write(hdsp, HDSP_freqReg, hdsp->dds_value);1104}1105 1106static int hdsp_set_rate(struct hdsp *hdsp, int rate, int called_internally)1107{1108 int reject_if_open = 0;1109 int current_rate;1110 int rate_bits;1111 1112 /* ASSUMPTION: hdsp->lock is either held, or1113 there is no need for it (e.g. during module1114 initialization).1115 */1116 1117 if (!(hdsp->control_register & HDSP_ClockModeMaster)) {1118 if (called_internally) {1119 /* request from ctl or card initialization */1120 dev_err(hdsp->card->dev,1121 "device is not running as a clock master: cannot set sample rate.\n");1122 return -1;1123 } else {1124 /* hw_param request while in AutoSync mode */1125 int external_freq = hdsp_external_sample_rate(hdsp);1126 int spdif_freq = hdsp_spdif_sample_rate(hdsp);1127 1128 if ((spdif_freq == external_freq*2) && (hdsp_autosync_ref(hdsp) >= HDSP_AUTOSYNC_FROM_ADAT1))1129 dev_info(hdsp->card->dev,1130 "Detected ADAT in double speed mode\n");1131 else if (hdsp->io_type == H9632 && (spdif_freq == external_freq*4) && (hdsp_autosync_ref(hdsp) >= HDSP_AUTOSYNC_FROM_ADAT1))1132 dev_info(hdsp->card->dev,1133 "Detected ADAT in quad speed mode\n");1134 else if (rate != external_freq) {1135 dev_info(hdsp->card->dev,1136 "No AutoSync source for requested rate\n");1137 return -1;1138 }1139 }1140 }1141 1142 current_rate = hdsp->system_sample_rate;1143 1144 /* Changing from a "single speed" to a "double speed" rate is1145 not allowed if any substreams are open. This is because1146 such a change causes a shift in the location of1147 the DMA buffers and a reduction in the number of available1148 buffers.1149 1150 Note that a similar but essentially insoluble problem1151 exists for externally-driven rate changes. All we can do1152 is to flag rate changes in the read/write routines. */1153 1154 if (rate > 96000 && hdsp->io_type != H9632)1155 return -EINVAL;1156 1157 switch (rate) {1158 case 32000:1159 if (current_rate > 48000)1160 reject_if_open = 1;1161 rate_bits = HDSP_Frequency32KHz;1162 break;1163 case 44100:1164 if (current_rate > 48000)1165 reject_if_open = 1;1166 rate_bits = HDSP_Frequency44_1KHz;1167 break;1168 case 48000:1169 if (current_rate > 48000)1170 reject_if_open = 1;1171 rate_bits = HDSP_Frequency48KHz;1172 break;1173 case 64000:1174 if (current_rate <= 48000 || current_rate > 96000)1175 reject_if_open = 1;1176 rate_bits = HDSP_Frequency64KHz;1177 break;1178 case 88200:1179 if (current_rate <= 48000 || current_rate > 96000)1180 reject_if_open = 1;1181 rate_bits = HDSP_Frequency88_2KHz;1182 break;1183 case 96000:1184 if (current_rate <= 48000 || current_rate > 96000)1185 reject_if_open = 1;1186 rate_bits = HDSP_Frequency96KHz;1187 break;1188 case 128000:1189 if (current_rate < 128000)1190 reject_if_open = 1;1191 rate_bits = HDSP_Frequency128KHz;1192 break;1193 case 176400:1194 if (current_rate < 128000)1195 reject_if_open = 1;1196 rate_bits = HDSP_Frequency176_4KHz;1197 break;1198 case 192000:1199 if (current_rate < 128000)1200 reject_if_open = 1;1201 rate_bits = HDSP_Frequency192KHz;1202 break;1203 default:1204 return -EINVAL;1205 }1206 1207 if (reject_if_open && (hdsp->capture_pid >= 0 || hdsp->playback_pid >= 0)) {1208 dev_warn(hdsp->card->dev,1209 "cannot change speed mode (capture PID = %d, playback PID = %d)\n",1210 hdsp->capture_pid,1211 hdsp->playback_pid);1212 return -EBUSY;1213 }1214 1215 hdsp->control_register &= ~HDSP_FrequencyMask;1216 hdsp->control_register |= rate_bits;1217 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);1218 1219 /* For HDSP9632 rev 152, need to set DDS value in FREQ register */1220 if (hdsp->io_type == H9632 && hdsp->firmware_rev >= 152)1221 hdsp_set_dds_value(hdsp, rate);1222 1223 if (rate >= 128000) {1224 hdsp->channel_map = channel_map_H9632_qs;1225 } else if (rate > 48000) {1226 if (hdsp->io_type == H9632)1227 hdsp->channel_map = channel_map_H9632_ds;1228 else1229 hdsp->channel_map = channel_map_ds;1230 } else {1231 switch (hdsp->io_type) {1232 case RPM:1233 case Multiface:1234 hdsp->channel_map = channel_map_mf_ss;1235 break;1236 case Digiface:1237 case H9652:1238 hdsp->channel_map = channel_map_df_ss;1239 break;1240 case H9632:1241 hdsp->channel_map = channel_map_H9632_ss;1242 break;1243 default:1244 /* should never happen */1245 break;1246 }1247 }1248 1249 hdsp->system_sample_rate = rate;1250 1251 return 0;1252}1253 1254/*----------------------------------------------------------------------------1255 MIDI1256 ----------------------------------------------------------------------------*/1257 1258static unsigned char snd_hdsp_midi_read_byte (struct hdsp *hdsp, int id)1259{1260 /* the hardware already does the relevant bit-mask with 0xff */1261 if (id)1262 return hdsp_read(hdsp, HDSP_midiDataIn1);1263 else1264 return hdsp_read(hdsp, HDSP_midiDataIn0);1265}1266 1267static void snd_hdsp_midi_write_byte (struct hdsp *hdsp, int id, int val)1268{1269 /* the hardware already does the relevant bit-mask with 0xff */1270 if (id)1271 hdsp_write(hdsp, HDSP_midiDataOut1, val);1272 else1273 hdsp_write(hdsp, HDSP_midiDataOut0, val);1274}1275 1276static int snd_hdsp_midi_input_available (struct hdsp *hdsp, int id)1277{1278 if (id)1279 return (hdsp_read(hdsp, HDSP_midiStatusIn1) & 0xff);1280 else1281 return (hdsp_read(hdsp, HDSP_midiStatusIn0) & 0xff);1282}1283 1284static int snd_hdsp_midi_output_possible (struct hdsp *hdsp, int id)1285{1286 int fifo_bytes_used;1287 1288 if (id)1289 fifo_bytes_used = hdsp_read(hdsp, HDSP_midiStatusOut1) & 0xff;1290 else1291 fifo_bytes_used = hdsp_read(hdsp, HDSP_midiStatusOut0) & 0xff;1292 1293 if (fifo_bytes_used < 128)1294 return 128 - fifo_bytes_used;1295 else1296 return 0;1297}1298 1299static void snd_hdsp_flush_midi_input (struct hdsp *hdsp, int id)1300{1301 int count = 256;1302 1303 while (snd_hdsp_midi_input_available(hdsp, id) && --count)1304 snd_hdsp_midi_read_byte(hdsp, id);1305}1306 1307static int snd_hdsp_midi_output_write (struct hdsp_midi *hmidi)1308{1309 unsigned long flags;1310 int n_pending;1311 int to_write;1312 int i;1313 unsigned char buf[128];1314 1315 /* Output is not interrupt driven */1316 1317 spin_lock_irqsave (&hmidi->lock, flags);1318 if (hmidi->output) {1319 if (!snd_rawmidi_transmit_empty (hmidi->output)) {1320 n_pending = snd_hdsp_midi_output_possible(hmidi->hdsp, hmidi->id);1321 if (n_pending > 0) {1322 if (n_pending > (int)sizeof (buf))1323 n_pending = sizeof (buf);1324 1325 to_write = snd_rawmidi_transmit(hmidi->output, buf, n_pending);1326 if (to_write > 0) {1327 for (i = 0; i < to_write; ++i)1328 snd_hdsp_midi_write_byte (hmidi->hdsp, hmidi->id, buf[i]);1329 }1330 }1331 }1332 }1333 spin_unlock_irqrestore (&hmidi->lock, flags);1334 return 0;1335}1336 1337static int snd_hdsp_midi_input_read (struct hdsp_midi *hmidi)1338{1339 unsigned char buf[128]; /* this buffer is designed to match the MIDI input FIFO size */1340 unsigned long flags;1341 int n_pending;1342 int i;1343 1344 spin_lock_irqsave (&hmidi->lock, flags);1345 n_pending = snd_hdsp_midi_input_available(hmidi->hdsp, hmidi->id);1346 if (n_pending > 0) {1347 if (hmidi->input) {1348 if (n_pending > (int)sizeof (buf))1349 n_pending = sizeof (buf);1350 for (i = 0; i < n_pending; ++i)1351 buf[i] = snd_hdsp_midi_read_byte (hmidi->hdsp, hmidi->id);1352 if (n_pending)1353 snd_rawmidi_receive (hmidi->input, buf, n_pending);1354 } else {1355 /* flush the MIDI input FIFO */1356 while (--n_pending)1357 snd_hdsp_midi_read_byte (hmidi->hdsp, hmidi->id);1358 }1359 }1360 hmidi->pending = 0;1361 if (hmidi->id)1362 hmidi->hdsp->control_register |= HDSP_Midi1InterruptEnable;1363 else1364 hmidi->hdsp->control_register |= HDSP_Midi0InterruptEnable;1365 hdsp_write(hmidi->hdsp, HDSP_controlRegister, hmidi->hdsp->control_register);1366 spin_unlock_irqrestore (&hmidi->lock, flags);1367 return snd_hdsp_midi_output_write (hmidi);1368}1369 1370static void snd_hdsp_midi_input_trigger(struct snd_rawmidi_substream *substream, int up)1371{1372 struct hdsp *hdsp;1373 struct hdsp_midi *hmidi;1374 unsigned long flags;1375 u32 ie;1376 1377 hmidi = (struct hdsp_midi *) substream->rmidi->private_data;1378 hdsp = hmidi->hdsp;1379 ie = hmidi->id ? HDSP_Midi1InterruptEnable : HDSP_Midi0InterruptEnable;1380 spin_lock_irqsave (&hdsp->lock, flags);1381 if (up) {1382 if (!(hdsp->control_register & ie)) {1383 snd_hdsp_flush_midi_input (hdsp, hmidi->id);1384 hdsp->control_register |= ie;1385 }1386 } else {1387 hdsp->control_register &= ~ie;1388 }1389 1390 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);1391 spin_unlock_irqrestore (&hdsp->lock, flags);1392}1393 1394static void snd_hdsp_midi_output_timer(struct timer_list *t)1395{1396 struct hdsp_midi *hmidi = from_timer(hmidi, t, timer);1397 unsigned long flags;1398 1399 snd_hdsp_midi_output_write(hmidi);1400 spin_lock_irqsave (&hmidi->lock, flags);1401 1402 /* this does not bump hmidi->istimer, because the1403 kernel automatically removed the timer when it1404 expired, and we are now adding it back, thus1405 leaving istimer wherever it was set before.1406 */1407 1408 if (hmidi->istimer)1409 mod_timer(&hmidi->timer, 1 + jiffies);1410 1411 spin_unlock_irqrestore (&hmidi->lock, flags);1412}1413 1414static void snd_hdsp_midi_output_trigger(struct snd_rawmidi_substream *substream, int up)1415{1416 struct hdsp_midi *hmidi;1417 unsigned long flags;1418 1419 hmidi = (struct hdsp_midi *) substream->rmidi->private_data;1420 spin_lock_irqsave (&hmidi->lock, flags);1421 if (up) {1422 if (!hmidi->istimer) {1423 timer_setup(&hmidi->timer, snd_hdsp_midi_output_timer,1424 0);1425 mod_timer(&hmidi->timer, 1 + jiffies);1426 hmidi->istimer++;1427 }1428 } else {1429 if (hmidi->istimer && --hmidi->istimer <= 0)1430 del_timer (&hmidi->timer);1431 }1432 spin_unlock_irqrestore (&hmidi->lock, flags);1433 if (up)1434 snd_hdsp_midi_output_write(hmidi);1435}1436 1437static int snd_hdsp_midi_input_open(struct snd_rawmidi_substream *substream)1438{1439 struct hdsp_midi *hmidi;1440 1441 hmidi = (struct hdsp_midi *) substream->rmidi->private_data;1442 spin_lock_irq (&hmidi->lock);1443 snd_hdsp_flush_midi_input (hmidi->hdsp, hmidi->id);1444 hmidi->input = substream;1445 spin_unlock_irq (&hmidi->lock);1446 1447 return 0;1448}1449 1450static int snd_hdsp_midi_output_open(struct snd_rawmidi_substream *substream)1451{1452 struct hdsp_midi *hmidi;1453 1454 hmidi = (struct hdsp_midi *) substream->rmidi->private_data;1455 spin_lock_irq (&hmidi->lock);1456 hmidi->output = substream;1457 spin_unlock_irq (&hmidi->lock);1458 1459 return 0;1460}1461 1462static int snd_hdsp_midi_input_close(struct snd_rawmidi_substream *substream)1463{1464 struct hdsp_midi *hmidi;1465 1466 snd_hdsp_midi_input_trigger (substream, 0);1467 1468 hmidi = (struct hdsp_midi *) substream->rmidi->private_data;1469 spin_lock_irq (&hmidi->lock);1470 hmidi->input = NULL;1471 spin_unlock_irq (&hmidi->lock);1472 1473 return 0;1474}1475 1476static int snd_hdsp_midi_output_close(struct snd_rawmidi_substream *substream)1477{1478 struct hdsp_midi *hmidi;1479 1480 snd_hdsp_midi_output_trigger (substream, 0);1481 1482 hmidi = (struct hdsp_midi *) substream->rmidi->private_data;1483 spin_lock_irq (&hmidi->lock);1484 hmidi->output = NULL;1485 spin_unlock_irq (&hmidi->lock);1486 1487 return 0;1488}1489 1490static const struct snd_rawmidi_ops snd_hdsp_midi_output =1491{1492 .open = snd_hdsp_midi_output_open,1493 .close = snd_hdsp_midi_output_close,1494 .trigger = snd_hdsp_midi_output_trigger,1495};1496 1497static const struct snd_rawmidi_ops snd_hdsp_midi_input =1498{1499 .open = snd_hdsp_midi_input_open,1500 .close = snd_hdsp_midi_input_close,1501 .trigger = snd_hdsp_midi_input_trigger,1502};1503 1504static int snd_hdsp_create_midi (struct snd_card *card, struct hdsp *hdsp, int id)1505{1506 char buf[40];1507 1508 hdsp->midi[id].id = id;1509 hdsp->midi[id].rmidi = NULL;1510 hdsp->midi[id].input = NULL;1511 hdsp->midi[id].output = NULL;1512 hdsp->midi[id].hdsp = hdsp;1513 hdsp->midi[id].istimer = 0;1514 hdsp->midi[id].pending = 0;1515 spin_lock_init (&hdsp->midi[id].lock);1516 1517 snprintf(buf, sizeof(buf), "%s MIDI %d", card->shortname, id + 1);1518 if (snd_rawmidi_new (card, buf, id, 1, 1, &hdsp->midi[id].rmidi) < 0)1519 return -1;1520 1521 sprintf(hdsp->midi[id].rmidi->name, "HDSP MIDI %d", id+1);1522 hdsp->midi[id].rmidi->private_data = &hdsp->midi[id];1523 1524 snd_rawmidi_set_ops (hdsp->midi[id].rmidi, SNDRV_RAWMIDI_STREAM_OUTPUT, &snd_hdsp_midi_output);1525 snd_rawmidi_set_ops (hdsp->midi[id].rmidi, SNDRV_RAWMIDI_STREAM_INPUT, &snd_hdsp_midi_input);1526 1527 hdsp->midi[id].rmidi->info_flags |= SNDRV_RAWMIDI_INFO_OUTPUT |1528 SNDRV_RAWMIDI_INFO_INPUT |1529 SNDRV_RAWMIDI_INFO_DUPLEX;1530 1531 return 0;1532}1533 1534/*-----------------------------------------------------------------------------1535 Control Interface1536 ----------------------------------------------------------------------------*/1537 1538static u32 snd_hdsp_convert_from_aes(struct snd_aes_iec958 *aes)1539{1540 u32 val = 0;1541 val |= (aes->status[0] & IEC958_AES0_PROFESSIONAL) ? HDSP_SPDIFProfessional : 0;1542 val |= (aes->status[0] & IEC958_AES0_NONAUDIO) ? HDSP_SPDIFNonAudio : 0;1543 if (val & HDSP_SPDIFProfessional)1544 val |= (aes->status[0] & IEC958_AES0_PRO_EMPHASIS_5015) ? HDSP_SPDIFEmphasis : 0;1545 else1546 val |= (aes->status[0] & IEC958_AES0_CON_EMPHASIS_5015) ? HDSP_SPDIFEmphasis : 0;1547 return val;1548}1549 1550static void snd_hdsp_convert_to_aes(struct snd_aes_iec958 *aes, u32 val)1551{1552 aes->status[0] = ((val & HDSP_SPDIFProfessional) ? IEC958_AES0_PROFESSIONAL : 0) |1553 ((val & HDSP_SPDIFNonAudio) ? IEC958_AES0_NONAUDIO : 0);1554 if (val & HDSP_SPDIFProfessional)1555 aes->status[0] |= (val & HDSP_SPDIFEmphasis) ? IEC958_AES0_PRO_EMPHASIS_5015 : 0;1556 else1557 aes->status[0] |= (val & HDSP_SPDIFEmphasis) ? IEC958_AES0_CON_EMPHASIS_5015 : 0;1558}1559 1560static int snd_hdsp_control_spdif_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)1561{1562 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;1563 uinfo->count = 1;1564 return 0;1565}1566 1567static int snd_hdsp_control_spdif_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)1568{1569 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);1570 1571 snd_hdsp_convert_to_aes(&ucontrol->value.iec958, hdsp->creg_spdif);1572 return 0;1573}1574 1575static int snd_hdsp_control_spdif_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)1576{1577 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);1578 int change;1579 u32 val;1580 1581 val = snd_hdsp_convert_from_aes(&ucontrol->value.iec958);1582 spin_lock_irq(&hdsp->lock);1583 change = val != hdsp->creg_spdif;1584 hdsp->creg_spdif = val;1585 spin_unlock_irq(&hdsp->lock);1586 return change;1587}1588 1589static int snd_hdsp_control_spdif_stream_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)1590{1591 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;1592 uinfo->count = 1;1593 return 0;1594}1595 1596static int snd_hdsp_control_spdif_stream_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)1597{1598 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);1599 1600 snd_hdsp_convert_to_aes(&ucontrol->value.iec958, hdsp->creg_spdif_stream);1601 return 0;1602}1603 1604static int snd_hdsp_control_spdif_stream_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)1605{1606 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);1607 int change;1608 u32 val;1609 1610 val = snd_hdsp_convert_from_aes(&ucontrol->value.iec958);1611 spin_lock_irq(&hdsp->lock);1612 change = val != hdsp->creg_spdif_stream;1613 hdsp->creg_spdif_stream = val;1614 hdsp->control_register &= ~(HDSP_SPDIFProfessional | HDSP_SPDIFNonAudio | HDSP_SPDIFEmphasis);1615 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register |= val);1616 spin_unlock_irq(&hdsp->lock);1617 return change;1618}1619 1620static int snd_hdsp_control_spdif_mask_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)1621{1622 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;1623 uinfo->count = 1;1624 return 0;1625}1626 1627static int snd_hdsp_control_spdif_mask_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)1628{1629 ucontrol->value.iec958.status[0] = kcontrol->private_value;1630 return 0;1631}1632 1633#define HDSP_SPDIF_IN(xname, xindex) \1634{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \1635 .name = xname, \1636 .index = xindex, \1637 .info = snd_hdsp_info_spdif_in, \1638 .get = snd_hdsp_get_spdif_in, \1639 .put = snd_hdsp_put_spdif_in }1640 1641static unsigned int hdsp_spdif_in(struct hdsp *hdsp)1642{1643 return hdsp_decode_spdif_in(hdsp->control_register & HDSP_SPDIFInputMask);1644}1645 1646static int hdsp_set_spdif_input(struct hdsp *hdsp, int in)1647{1648 hdsp->control_register &= ~HDSP_SPDIFInputMask;1649 hdsp->control_register |= hdsp_encode_spdif_in(in);1650 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);1651 return 0;1652}1653 1654static int snd_hdsp_info_spdif_in(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)1655{1656 static const char * const texts[4] = {1657 "Optical", "Coaxial", "Internal", "AES"1658 };1659 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);1660 1661 return snd_ctl_enum_info(uinfo, 1, (hdsp->io_type == H9632) ? 4 : 3,1662 texts);1663}1664 1665static int snd_hdsp_get_spdif_in(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)1666{1667 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);1668 1669 ucontrol->value.enumerated.item[0] = hdsp_spdif_in(hdsp);1670 return 0;1671}1672 1673static int snd_hdsp_put_spdif_in(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)1674{1675 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);1676 int change;1677 unsigned int val;1678 1679 if (!snd_hdsp_use_is_exclusive(hdsp))1680 return -EBUSY;1681 val = ucontrol->value.enumerated.item[0] % ((hdsp->io_type == H9632) ? 4 : 3);1682 spin_lock_irq(&hdsp->lock);1683 change = val != hdsp_spdif_in(hdsp);1684 if (change)1685 hdsp_set_spdif_input(hdsp, val);1686 spin_unlock_irq(&hdsp->lock);1687 return change;1688}1689 1690#define HDSP_TOGGLE_SETTING(xname, xindex) \1691{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \1692 .name = xname, \1693 .private_value = xindex, \1694 .info = snd_hdsp_info_toggle_setting, \1695 .get = snd_hdsp_get_toggle_setting, \1696 .put = snd_hdsp_put_toggle_setting \1697}1698 1699static int hdsp_toggle_setting(struct hdsp *hdsp, u32 regmask)1700{1701 return (hdsp->control_register & regmask) ? 1 : 0;1702}1703 1704static int hdsp_set_toggle_setting(struct hdsp *hdsp, u32 regmask, int out)1705{1706 if (out)1707 hdsp->control_register |= regmask;1708 else1709 hdsp->control_register &= ~regmask;1710 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);1711 1712 return 0;1713}1714 1715#define snd_hdsp_info_toggle_setting snd_ctl_boolean_mono_info1716 1717static int snd_hdsp_get_toggle_setting(struct snd_kcontrol *kcontrol,1718 struct snd_ctl_elem_value *ucontrol)1719{1720 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);1721 u32 regmask = kcontrol->private_value;1722 1723 spin_lock_irq(&hdsp->lock);1724 ucontrol->value.integer.value[0] = hdsp_toggle_setting(hdsp, regmask);1725 spin_unlock_irq(&hdsp->lock);1726 return 0;1727}1728 1729static int snd_hdsp_put_toggle_setting(struct snd_kcontrol *kcontrol,1730 struct snd_ctl_elem_value *ucontrol)1731{1732 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);1733 u32 regmask = kcontrol->private_value;1734 int change;1735 unsigned int val;1736 1737 if (!snd_hdsp_use_is_exclusive(hdsp))1738 return -EBUSY;1739 val = ucontrol->value.integer.value[0] & 1;1740 spin_lock_irq(&hdsp->lock);1741 change = (int) val != hdsp_toggle_setting(hdsp, regmask);1742 if (change)1743 hdsp_set_toggle_setting(hdsp, regmask, val);1744 spin_unlock_irq(&hdsp->lock);1745 return change;1746}1747 1748#define HDSP_SPDIF_SAMPLE_RATE(xname, xindex) \1749{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \1750 .name = xname, \1751 .index = xindex, \1752 .access = SNDRV_CTL_ELEM_ACCESS_READ, \1753 .info = snd_hdsp_info_spdif_sample_rate, \1754 .get = snd_hdsp_get_spdif_sample_rate \1755}1756 1757static int snd_hdsp_info_spdif_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)1758{1759 static const char * const texts[] = {1760 "32000", "44100", "48000", "64000", "88200", "96000",1761 "None", "128000", "176400", "192000"1762 };1763 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);1764 1765 return snd_ctl_enum_info(uinfo, 1, (hdsp->io_type == H9632) ? 10 : 7,1766 texts);1767}1768 1769static int snd_hdsp_get_spdif_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)1770{1771 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);1772 1773 switch (hdsp_spdif_sample_rate(hdsp)) {1774 case 32000:1775 ucontrol->value.enumerated.item[0] = 0;1776 break;1777 case 44100:1778 ucontrol->value.enumerated.item[0] = 1;1779 break;1780 case 48000:1781 ucontrol->value.enumerated.item[0] = 2;1782 break;1783 case 64000:1784 ucontrol->value.enumerated.item[0] = 3;1785 break;1786 case 88200:1787 ucontrol->value.enumerated.item[0] = 4;1788 break;1789 case 96000:1790 ucontrol->value.enumerated.item[0] = 5;1791 break;1792 case 128000:1793 ucontrol->value.enumerated.item[0] = 7;1794 break;1795 case 176400:1796 ucontrol->value.enumerated.item[0] = 8;1797 break;1798 case 192000:1799 ucontrol->value.enumerated.item[0] = 9;1800 break;1801 default:1802 ucontrol->value.enumerated.item[0] = 6;1803 }1804 return 0;1805}1806 1807#define HDSP_SYSTEM_SAMPLE_RATE(xname, xindex) \1808{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \1809 .name = xname, \1810 .index = xindex, \1811 .access = SNDRV_CTL_ELEM_ACCESS_READ, \1812 .info = snd_hdsp_info_system_sample_rate, \1813 .get = snd_hdsp_get_system_sample_rate \1814}1815 1816static int snd_hdsp_info_system_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)1817{1818 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;1819 uinfo->count = 1;1820 return 0;1821}1822 1823static int snd_hdsp_get_system_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)1824{1825 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);1826 1827 ucontrol->value.enumerated.item[0] = hdsp->system_sample_rate;1828 return 0;1829}1830 1831#define HDSP_AUTOSYNC_SAMPLE_RATE(xname, xindex) \1832{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \1833 .name = xname, \1834 .index = xindex, \1835 .access = SNDRV_CTL_ELEM_ACCESS_READ, \1836 .info = snd_hdsp_info_autosync_sample_rate, \1837 .get = snd_hdsp_get_autosync_sample_rate \1838}1839 1840static int snd_hdsp_info_autosync_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)1841{1842 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);1843 static const char * const texts[] = {1844 "32000", "44100", "48000", "64000", "88200", "96000",1845 "None", "128000", "176400", "192000"1846 };1847 1848 return snd_ctl_enum_info(uinfo, 1, (hdsp->io_type == H9632) ? 10 : 7,1849 texts);1850}1851 1852static int snd_hdsp_get_autosync_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)1853{1854 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);1855 1856 switch (hdsp_external_sample_rate(hdsp)) {1857 case 32000:1858 ucontrol->value.enumerated.item[0] = 0;1859 break;1860 case 44100:1861 ucontrol->value.enumerated.item[0] = 1;1862 break;1863 case 48000:1864 ucontrol->value.enumerated.item[0] = 2;1865 break;1866 case 64000:1867 ucontrol->value.enumerated.item[0] = 3;1868 break;1869 case 88200:1870 ucontrol->value.enumerated.item[0] = 4;1871 break;1872 case 96000:1873 ucontrol->value.enumerated.item[0] = 5;1874 break;1875 case 128000:1876 ucontrol->value.enumerated.item[0] = 7;1877 break;1878 case 176400:1879 ucontrol->value.enumerated.item[0] = 8;1880 break;1881 case 192000:1882 ucontrol->value.enumerated.item[0] = 9;1883 break;1884 default:1885 ucontrol->value.enumerated.item[0] = 6;1886 }1887 return 0;1888}1889 1890#define HDSP_SYSTEM_CLOCK_MODE(xname, xindex) \1891{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \1892 .name = xname, \1893 .index = xindex, \1894 .access = SNDRV_CTL_ELEM_ACCESS_READ, \1895 .info = snd_hdsp_info_system_clock_mode, \1896 .get = snd_hdsp_get_system_clock_mode \1897}1898 1899static int hdsp_system_clock_mode(struct hdsp *hdsp)1900{1901 if (hdsp->control_register & HDSP_ClockModeMaster)1902 return 0;1903 else if (hdsp_external_sample_rate(hdsp) != hdsp->system_sample_rate)1904 return 0;1905 return 1;1906}1907 1908static int snd_hdsp_info_system_clock_mode(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)1909{1910 static const char * const texts[] = {"Master", "Slave" };1911 1912 return snd_ctl_enum_info(uinfo, 1, 2, texts);1913}1914 1915static int snd_hdsp_get_system_clock_mode(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)1916{1917 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);1918 1919 ucontrol->value.enumerated.item[0] = hdsp_system_clock_mode(hdsp);1920 return 0;1921}1922 1923#define HDSP_CLOCK_SOURCE(xname, xindex) \1924{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \1925 .name = xname, \1926 .index = xindex, \1927 .info = snd_hdsp_info_clock_source, \1928 .get = snd_hdsp_get_clock_source, \1929 .put = snd_hdsp_put_clock_source \1930}1931 1932static int hdsp_clock_source(struct hdsp *hdsp)1933{1934 if (hdsp->control_register & HDSP_ClockModeMaster) {1935 switch (hdsp->system_sample_rate) {1936 case 32000:1937 return 1;1938 case 44100:1939 return 2;1940 case 48000:1941 return 3;1942 case 64000:1943 return 4;1944 case 88200:1945 return 5;1946 case 96000:1947 return 6;1948 case 128000:1949 return 7;1950 case 176400:1951 return 8;1952 case 192000:1953 return 9;1954 default:1955 return 3;1956 }1957 } else {1958 return 0;1959 }1960}1961 1962static int hdsp_set_clock_source(struct hdsp *hdsp, int mode)1963{1964 int rate;1965 switch (mode) {1966 case HDSP_CLOCK_SOURCE_AUTOSYNC:1967 if (hdsp_external_sample_rate(hdsp) != 0) {1968 if (!hdsp_set_rate(hdsp, hdsp_external_sample_rate(hdsp), 1)) {1969 hdsp->control_register &= ~HDSP_ClockModeMaster;1970 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);1971 return 0;1972 }1973 }1974 return -1;1975 case HDSP_CLOCK_SOURCE_INTERNAL_32KHZ:1976 rate = 32000;1977 break;1978 case HDSP_CLOCK_SOURCE_INTERNAL_44_1KHZ:1979 rate = 44100;1980 break;1981 case HDSP_CLOCK_SOURCE_INTERNAL_48KHZ:1982 rate = 48000;1983 break;1984 case HDSP_CLOCK_SOURCE_INTERNAL_64KHZ:1985 rate = 64000;1986 break;1987 case HDSP_CLOCK_SOURCE_INTERNAL_88_2KHZ:1988 rate = 88200;1989 break;1990 case HDSP_CLOCK_SOURCE_INTERNAL_96KHZ:1991 rate = 96000;1992 break;1993 case HDSP_CLOCK_SOURCE_INTERNAL_128KHZ:1994 rate = 128000;1995 break;1996 case HDSP_CLOCK_SOURCE_INTERNAL_176_4KHZ:1997 rate = 176400;1998 break;1999 case HDSP_CLOCK_SOURCE_INTERNAL_192KHZ:2000 rate = 192000;2001 break;2002 default:2003 rate = 48000;2004 }2005 hdsp->control_register |= HDSP_ClockModeMaster;2006 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);2007 hdsp_set_rate(hdsp, rate, 1);2008 return 0;2009}2010 2011static int snd_hdsp_info_clock_source(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)2012{2013 static const char * const texts[] = {2014 "AutoSync", "Internal 32.0 kHz", "Internal 44.1 kHz",2015 "Internal 48.0 kHz", "Internal 64.0 kHz", "Internal 88.2 kHz",2016 "Internal 96.0 kHz", "Internal 128 kHz", "Internal 176.4 kHz",2017 "Internal 192.0 KHz"2018 };2019 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);2020 2021 return snd_ctl_enum_info(uinfo, 1, (hdsp->io_type == H9632) ? 10 : 7,2022 texts);2023}2024 2025static int snd_hdsp_get_clock_source(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)2026{2027 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);2028 2029 ucontrol->value.enumerated.item[0] = hdsp_clock_source(hdsp);2030 return 0;2031}2032 2033static int snd_hdsp_put_clock_source(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)2034{2035 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);2036 int change;2037 int val;2038 2039 if (!snd_hdsp_use_is_exclusive(hdsp))2040 return -EBUSY;2041 val = ucontrol->value.enumerated.item[0];2042 if (val < 0) val = 0;2043 if (hdsp->io_type == H9632) {2044 if (val > 9)2045 val = 9;2046 } else {2047 if (val > 6)2048 val = 6;2049 }2050 spin_lock_irq(&hdsp->lock);2051 if (val != hdsp_clock_source(hdsp))2052 change = (hdsp_set_clock_source(hdsp, val) == 0) ? 1 : 0;2053 else2054 change = 0;2055 spin_unlock_irq(&hdsp->lock);2056 return change;2057}2058 2059#define snd_hdsp_info_clock_source_lock snd_ctl_boolean_mono_info2060 2061static int snd_hdsp_get_clock_source_lock(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)2062{2063 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);2064 2065 ucontrol->value.integer.value[0] = hdsp->clock_source_locked;2066 return 0;2067}2068 2069static int snd_hdsp_put_clock_source_lock(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)2070{2071 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);2072 int change;2073 2074 change = (int)ucontrol->value.integer.value[0] != hdsp->clock_source_locked;2075 if (change)2076 hdsp->clock_source_locked = !!ucontrol->value.integer.value[0];2077 return change;2078}2079 2080#define HDSP_DA_GAIN(xname, xindex) \2081{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \2082 .name = xname, \2083 .index = xindex, \2084 .info = snd_hdsp_info_da_gain, \2085 .get = snd_hdsp_get_da_gain, \2086 .put = snd_hdsp_put_da_gain \2087}2088 2089static int hdsp_da_gain(struct hdsp *hdsp)2090{2091 switch (hdsp->control_register & HDSP_DAGainMask) {2092 case HDSP_DAGainHighGain:2093 return 0;2094 case HDSP_DAGainPlus4dBu:2095 return 1;2096 case HDSP_DAGainMinus10dBV:2097 return 2;2098 default:2099 return 1;2100 }2101}2102 2103static int hdsp_set_da_gain(struct hdsp *hdsp, int mode)2104{2105 hdsp->control_register &= ~HDSP_DAGainMask;2106 switch (mode) {2107 case 0:2108 hdsp->control_register |= HDSP_DAGainHighGain;2109 break;2110 case 1:2111 hdsp->control_register |= HDSP_DAGainPlus4dBu;2112 break;2113 case 2:2114 hdsp->control_register |= HDSP_DAGainMinus10dBV;2115 break;2116 default:2117 return -1;2118 2119 }2120 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);2121 return 0;2122}2123 2124static int snd_hdsp_info_da_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)2125{2126 static const char * const texts[] = {"Hi Gain", "+4 dBu", "-10 dbV"};2127 2128 return snd_ctl_enum_info(uinfo, 1, 3, texts);2129}2130 2131static int snd_hdsp_get_da_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)2132{2133 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);2134 2135 ucontrol->value.enumerated.item[0] = hdsp_da_gain(hdsp);2136 return 0;2137}2138 2139static int snd_hdsp_put_da_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)2140{2141 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);2142 int change;2143 int val;2144 2145 if (!snd_hdsp_use_is_exclusive(hdsp))2146 return -EBUSY;2147 val = ucontrol->value.enumerated.item[0];2148 if (val < 0) val = 0;2149 if (val > 2) val = 2;2150 spin_lock_irq(&hdsp->lock);2151 if (val != hdsp_da_gain(hdsp))2152 change = (hdsp_set_da_gain(hdsp, val) == 0) ? 1 : 0;2153 else2154 change = 0;2155 spin_unlock_irq(&hdsp->lock);2156 return change;2157}2158 2159#define HDSP_AD_GAIN(xname, xindex) \2160{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \2161 .name = xname, \2162 .index = xindex, \2163 .info = snd_hdsp_info_ad_gain, \2164 .get = snd_hdsp_get_ad_gain, \2165 .put = snd_hdsp_put_ad_gain \2166}2167 2168static int hdsp_ad_gain(struct hdsp *hdsp)2169{2170 switch (hdsp->control_register & HDSP_ADGainMask) {2171 case HDSP_ADGainMinus10dBV:2172 return 0;2173 case HDSP_ADGainPlus4dBu:2174 return 1;2175 case HDSP_ADGainLowGain:2176 return 2;2177 default:2178 return 1;2179 }2180}2181 2182static int hdsp_set_ad_gain(struct hdsp *hdsp, int mode)2183{2184 hdsp->control_register &= ~HDSP_ADGainMask;2185 switch (mode) {2186 case 0:2187 hdsp->control_register |= HDSP_ADGainMinus10dBV;2188 break;2189 case 1:2190 hdsp->control_register |= HDSP_ADGainPlus4dBu;2191 break;2192 case 2:2193 hdsp->control_register |= HDSP_ADGainLowGain;2194 break;2195 default:2196 return -1;2197 2198 }2199 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);2200 return 0;2201}2202 2203static int snd_hdsp_info_ad_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)2204{2205 static const char * const texts[] = {"-10 dBV", "+4 dBu", "Lo Gain"};2206 2207 return snd_ctl_enum_info(uinfo, 1, 3, texts);2208}2209 2210static int snd_hdsp_get_ad_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)2211{2212 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);2213 2214 ucontrol->value.enumerated.item[0] = hdsp_ad_gain(hdsp);2215 return 0;2216}2217 2218static int snd_hdsp_put_ad_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)2219{2220 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);2221 int change;2222 int val;2223 2224 if (!snd_hdsp_use_is_exclusive(hdsp))2225 return -EBUSY;2226 val = ucontrol->value.enumerated.item[0];2227 if (val < 0) val = 0;2228 if (val > 2) val = 2;2229 spin_lock_irq(&hdsp->lock);2230 if (val != hdsp_ad_gain(hdsp))2231 change = (hdsp_set_ad_gain(hdsp, val) == 0) ? 1 : 0;2232 else2233 change = 0;2234 spin_unlock_irq(&hdsp->lock);2235 return change;2236}2237 2238#define HDSP_PHONE_GAIN(xname, xindex) \2239{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \2240 .name = xname, \2241 .index = xindex, \2242 .info = snd_hdsp_info_phone_gain, \2243 .get = snd_hdsp_get_phone_gain, \2244 .put = snd_hdsp_put_phone_gain \2245}2246 2247static int hdsp_phone_gain(struct hdsp *hdsp)2248{2249 switch (hdsp->control_register & HDSP_PhoneGainMask) {2250 case HDSP_PhoneGain0dB:2251 return 0;2252 case HDSP_PhoneGainMinus6dB:2253 return 1;2254 case HDSP_PhoneGainMinus12dB:2255 return 2;2256 default:2257 return 0;2258 }2259}2260 2261static int hdsp_set_phone_gain(struct hdsp *hdsp, int mode)2262{2263 hdsp->control_register &= ~HDSP_PhoneGainMask;2264 switch (mode) {2265 case 0:2266 hdsp->control_register |= HDSP_PhoneGain0dB;2267 break;2268 case 1:2269 hdsp->control_register |= HDSP_PhoneGainMinus6dB;2270 break;2271 case 2:2272 hdsp->control_register |= HDSP_PhoneGainMinus12dB;2273 break;2274 default:2275 return -1;2276 2277 }2278 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);2279 return 0;2280}2281 2282static int snd_hdsp_info_phone_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)2283{2284 static const char * const texts[] = {"0 dB", "-6 dB", "-12 dB"};2285 2286 return snd_ctl_enum_info(uinfo, 1, 3, texts);2287}2288 2289static int snd_hdsp_get_phone_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)2290{2291 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);2292 2293 ucontrol->value.enumerated.item[0] = hdsp_phone_gain(hdsp);2294 return 0;2295}2296 2297static int snd_hdsp_put_phone_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)2298{2299 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);2300 int change;2301 int val;2302 2303 if (!snd_hdsp_use_is_exclusive(hdsp))2304 return -EBUSY;2305 val = ucontrol->value.enumerated.item[0];2306 if (val < 0) val = 0;2307 if (val > 2) val = 2;2308 spin_lock_irq(&hdsp->lock);2309 if (val != hdsp_phone_gain(hdsp))2310 change = (hdsp_set_phone_gain(hdsp, val) == 0) ? 1 : 0;2311 else2312 change = 0;2313 spin_unlock_irq(&hdsp->lock);2314 return change;2315}2316 2317#define HDSP_PREF_SYNC_REF(xname, xindex) \2318{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \2319 .name = xname, \2320 .index = xindex, \2321 .info = snd_hdsp_info_pref_sync_ref, \2322 .get = snd_hdsp_get_pref_sync_ref, \2323 .put = snd_hdsp_put_pref_sync_ref \2324}2325 2326static int hdsp_pref_sync_ref(struct hdsp *hdsp)2327{2328 /* Notice that this looks at the requested sync source,2329 not the one actually in use.2330 */2331 2332 switch (hdsp->control_register & HDSP_SyncRefMask) {2333 case HDSP_SyncRef_ADAT1:2334 return HDSP_SYNC_FROM_ADAT1;2335 case HDSP_SyncRef_ADAT2:2336 return HDSP_SYNC_FROM_ADAT2;2337 case HDSP_SyncRef_ADAT3:2338 return HDSP_SYNC_FROM_ADAT3;2339 case HDSP_SyncRef_SPDIF:2340 return HDSP_SYNC_FROM_SPDIF;2341 case HDSP_SyncRef_WORD:2342 return HDSP_SYNC_FROM_WORD;2343 case HDSP_SyncRef_ADAT_SYNC:2344 return HDSP_SYNC_FROM_ADAT_SYNC;2345 default:2346 return HDSP_SYNC_FROM_WORD;2347 }2348 return 0;2349}2350 2351static int hdsp_set_pref_sync_ref(struct hdsp *hdsp, int pref)2352{2353 hdsp->control_register &= ~HDSP_SyncRefMask;2354 switch (pref) {2355 case HDSP_SYNC_FROM_ADAT1:2356 hdsp->control_register &= ~HDSP_SyncRefMask; /* clear SyncRef bits */2357 break;2358 case HDSP_SYNC_FROM_ADAT2:2359 hdsp->control_register |= HDSP_SyncRef_ADAT2;2360 break;2361 case HDSP_SYNC_FROM_ADAT3:2362 hdsp->control_register |= HDSP_SyncRef_ADAT3;2363 break;2364 case HDSP_SYNC_FROM_SPDIF:2365 hdsp->control_register |= HDSP_SyncRef_SPDIF;2366 break;2367 case HDSP_SYNC_FROM_WORD:2368 hdsp->control_register |= HDSP_SyncRef_WORD;2369 break;2370 case HDSP_SYNC_FROM_ADAT_SYNC:2371 hdsp->control_register |= HDSP_SyncRef_ADAT_SYNC;2372 break;2373 default:2374 return -1;2375 }2376 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);2377 return 0;2378}2379 2380static int snd_hdsp_info_pref_sync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)2381{2382 static const char * const texts[] = {2383 "Word", "IEC958", "ADAT1", "ADAT Sync", "ADAT2", "ADAT3"2384 };2385 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);2386 int num_items;2387 2388 switch (hdsp->io_type) {2389 case Digiface:2390 case H9652:2391 num_items = 6;2392 break;2393 case Multiface:2394 num_items = 4;2395 break;2396 case H9632:2397 num_items = 3;2398 break;2399 default:2400 return -EINVAL;2401 }2402 2403 return snd_ctl_enum_info(uinfo, 1, num_items, texts);2404}2405 2406static int snd_hdsp_get_pref_sync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)2407{2408 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);2409 2410 ucontrol->value.enumerated.item[0] = hdsp_pref_sync_ref(hdsp);2411 return 0;2412}2413 2414static int snd_hdsp_put_pref_sync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)2415{2416 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);2417 int change, max;2418 unsigned int val;2419 2420 if (!snd_hdsp_use_is_exclusive(hdsp))2421 return -EBUSY;2422 2423 switch (hdsp->io_type) {2424 case Digiface:2425 case H9652:2426 max = 6;2427 break;2428 case Multiface:2429 max = 4;2430 break;2431 case H9632:2432 max = 3;2433 break;2434 default:2435 return -EIO;2436 }2437 2438 val = ucontrol->value.enumerated.item[0] % max;2439 spin_lock_irq(&hdsp->lock);2440 change = (int)val != hdsp_pref_sync_ref(hdsp);2441 hdsp_set_pref_sync_ref(hdsp, val);2442 spin_unlock_irq(&hdsp->lock);2443 return change;2444}2445 2446#define HDSP_AUTOSYNC_REF(xname, xindex) \2447{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \2448 .name = xname, \2449 .index = xindex, \2450 .access = SNDRV_CTL_ELEM_ACCESS_READ, \2451 .info = snd_hdsp_info_autosync_ref, \2452 .get = snd_hdsp_get_autosync_ref, \2453}2454 2455static int hdsp_autosync_ref(struct hdsp *hdsp)2456{2457 /* This looks at the autosync selected sync reference */2458 unsigned int status2 = hdsp_read(hdsp, HDSP_status2Register);2459 2460 switch (status2 & HDSP_SelSyncRefMask) {2461 case HDSP_SelSyncRef_WORD:2462 return HDSP_AUTOSYNC_FROM_WORD;2463 case HDSP_SelSyncRef_ADAT_SYNC:2464 return HDSP_AUTOSYNC_FROM_ADAT_SYNC;2465 case HDSP_SelSyncRef_SPDIF:2466 return HDSP_AUTOSYNC_FROM_SPDIF;2467 case HDSP_SelSyncRefMask:2468 return HDSP_AUTOSYNC_FROM_NONE;2469 case HDSP_SelSyncRef_ADAT1:2470 return HDSP_AUTOSYNC_FROM_ADAT1;2471 case HDSP_SelSyncRef_ADAT2:2472 return HDSP_AUTOSYNC_FROM_ADAT2;2473 case HDSP_SelSyncRef_ADAT3:2474 return HDSP_AUTOSYNC_FROM_ADAT3;2475 default:2476 return HDSP_AUTOSYNC_FROM_WORD;2477 }2478 return 0;2479}2480 2481static int snd_hdsp_info_autosync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)2482{2483 static const char * const texts[] = {2484 "Word", "ADAT Sync", "IEC958", "None", "ADAT1", "ADAT2", "ADAT3"2485 };2486 2487 return snd_ctl_enum_info(uinfo, 1, 7, texts);2488}2489 2490static int snd_hdsp_get_autosync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)2491{2492 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);2493 2494 ucontrol->value.enumerated.item[0] = hdsp_autosync_ref(hdsp);2495 return 0;2496}2497 2498#define HDSP_PRECISE_POINTER(xname, xindex) \2499{ .iface = SNDRV_CTL_ELEM_IFACE_CARD, \2500 .name = xname, \2501 .index = xindex, \2502 .info = snd_hdsp_info_precise_pointer, \2503 .get = snd_hdsp_get_precise_pointer, \2504 .put = snd_hdsp_put_precise_pointer \2505}2506 2507static int hdsp_set_precise_pointer(struct hdsp *hdsp, int precise)2508{2509 if (precise)2510 hdsp->precise_ptr = 1;2511 else2512 hdsp->precise_ptr = 0;2513 return 0;2514}2515 2516#define snd_hdsp_info_precise_pointer snd_ctl_boolean_mono_info2517 2518static int snd_hdsp_get_precise_pointer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)2519{2520 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);2521 2522 spin_lock_irq(&hdsp->lock);2523 ucontrol->value.integer.value[0] = hdsp->precise_ptr;2524 spin_unlock_irq(&hdsp->lock);2525 return 0;2526}2527 2528static int snd_hdsp_put_precise_pointer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)2529{2530 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);2531 int change;2532 unsigned int val;2533 2534 if (!snd_hdsp_use_is_exclusive(hdsp))2535 return -EBUSY;2536 val = ucontrol->value.integer.value[0] & 1;2537 spin_lock_irq(&hdsp->lock);2538 change = (int)val != hdsp->precise_ptr;2539 hdsp_set_precise_pointer(hdsp, val);2540 spin_unlock_irq(&hdsp->lock);2541 return change;2542}2543 2544#define HDSP_USE_MIDI_WORK(xname, xindex) \2545{ .iface = SNDRV_CTL_ELEM_IFACE_CARD, \2546 .name = xname, \2547 .index = xindex, \2548 .info = snd_hdsp_info_use_midi_work, \2549 .get = snd_hdsp_get_use_midi_work, \2550 .put = snd_hdsp_put_use_midi_work \2551}2552 2553static int hdsp_set_use_midi_work(struct hdsp *hdsp, int use_work)2554{2555 if (use_work)2556 hdsp->use_midi_work = 1;2557 else2558 hdsp->use_midi_work = 0;2559 return 0;2560}2561 2562#define snd_hdsp_info_use_midi_work snd_ctl_boolean_mono_info2563 2564static int snd_hdsp_get_use_midi_work(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)2565{2566 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);2567 2568 spin_lock_irq(&hdsp->lock);2569 ucontrol->value.integer.value[0] = hdsp->use_midi_work;2570 spin_unlock_irq(&hdsp->lock);2571 return 0;2572}2573 2574static int snd_hdsp_put_use_midi_work(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)2575{2576 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);2577 int change;2578 unsigned int val;2579 2580 if (!snd_hdsp_use_is_exclusive(hdsp))2581 return -EBUSY;2582 val = ucontrol->value.integer.value[0] & 1;2583 spin_lock_irq(&hdsp->lock);2584 change = (int)val != hdsp->use_midi_work;2585 hdsp_set_use_midi_work(hdsp, val);2586 spin_unlock_irq(&hdsp->lock);2587 return change;2588}2589 2590#define HDSP_MIXER(xname, xindex) \2591{ .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \2592 .name = xname, \2593 .index = xindex, \2594 .device = 0, \2595 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \2596 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \2597 .info = snd_hdsp_info_mixer, \2598 .get = snd_hdsp_get_mixer, \2599 .put = snd_hdsp_put_mixer \2600}2601 2602static int snd_hdsp_info_mixer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)2603{2604 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;2605 uinfo->count = 3;2606 uinfo->value.integer.min = 0;2607 uinfo->value.integer.max = 65536;2608 uinfo->value.integer.step = 1;2609 return 0;2610}2611 2612static int snd_hdsp_get_mixer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)2613{2614 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);2615 int source;2616 int destination;2617 int addr;2618 2619 source = ucontrol->value.integer.value[0];2620 destination = ucontrol->value.integer.value[1];2621 2622 if (source >= hdsp->max_channels)2623 addr = hdsp_playback_to_output_key(hdsp,source-hdsp->max_channels,destination);2624 else2625 addr = hdsp_input_to_output_key(hdsp,source, destination);2626 2627 spin_lock_irq(&hdsp->lock);2628 ucontrol->value.integer.value[2] = hdsp_read_gain (hdsp, addr);2629 spin_unlock_irq(&hdsp->lock);2630 return 0;2631}2632 2633static int snd_hdsp_put_mixer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)2634{2635 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);2636 int change;2637 int source;2638 int destination;2639 int gain;2640 int addr;2641 2642 if (!snd_hdsp_use_is_exclusive(hdsp))2643 return -EBUSY;2644 2645 source = ucontrol->value.integer.value[0];2646 destination = ucontrol->value.integer.value[1];2647 2648 if (source >= hdsp->max_channels)2649 addr = hdsp_playback_to_output_key(hdsp,source-hdsp->max_channels, destination);2650 else2651 addr = hdsp_input_to_output_key(hdsp,source, destination);2652 2653 gain = ucontrol->value.integer.value[2];2654 2655 spin_lock_irq(&hdsp->lock);2656 change = gain != hdsp_read_gain(hdsp, addr);2657 if (change)2658 hdsp_write_gain(hdsp, addr, gain);2659 spin_unlock_irq(&hdsp->lock);2660 return change;2661}2662 2663#define HDSP_WC_SYNC_CHECK(xname, xindex) \2664{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \2665 .name = xname, \2666 .index = xindex, \2667 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \2668 .info = snd_hdsp_info_sync_check, \2669 .get = snd_hdsp_get_wc_sync_check \2670}2671 2672static int snd_hdsp_info_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)2673{2674 static const char * const texts[] = {"No Lock", "Lock", "Sync" };2675 2676 return snd_ctl_enum_info(uinfo, 1, 3, texts);2677}2678 2679static int hdsp_wc_sync_check(struct hdsp *hdsp)2680{2681 int status2 = hdsp_read(hdsp, HDSP_status2Register);2682 if (status2 & HDSP_wc_lock) {2683 if (status2 & HDSP_wc_sync)2684 return 2;2685 else2686 return 1;2687 } else2688 return 0;2689 return 0;2690}2691 2692static int snd_hdsp_get_wc_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)2693{2694 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);2695 2696 ucontrol->value.enumerated.item[0] = hdsp_wc_sync_check(hdsp);2697 return 0;2698}2699 2700#define HDSP_SPDIF_SYNC_CHECK(xname, xindex) \2701{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \2702 .name = xname, \2703 .index = xindex, \2704 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \2705 .info = snd_hdsp_info_sync_check, \2706 .get = snd_hdsp_get_spdif_sync_check \2707}2708 2709static int hdsp_spdif_sync_check(struct hdsp *hdsp)2710{2711 int status = hdsp_read(hdsp, HDSP_statusRegister);2712 if (status & HDSP_SPDIFErrorFlag)2713 return 0;2714 else {2715 if (status & HDSP_SPDIFSync)2716 return 2;2717 else2718 return 1;2719 }2720 return 0;2721}2722 2723static int snd_hdsp_get_spdif_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)2724{2725 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);2726 2727 ucontrol->value.enumerated.item[0] = hdsp_spdif_sync_check(hdsp);2728 return 0;2729}2730 2731#define HDSP_ADATSYNC_SYNC_CHECK(xname, xindex) \2732{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \2733 .name = xname, \2734 .index = xindex, \2735 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \2736 .info = snd_hdsp_info_sync_check, \2737 .get = snd_hdsp_get_adatsync_sync_check \2738}2739 2740static int hdsp_adatsync_sync_check(struct hdsp *hdsp)2741{2742 int status = hdsp_read(hdsp, HDSP_statusRegister);2743 if (status & HDSP_TimecodeLock) {2744 if (status & HDSP_TimecodeSync)2745 return 2;2746 else2747 return 1;2748 } else2749 return 0;2750}2751 2752static int snd_hdsp_get_adatsync_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)2753{2754 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);2755 2756 ucontrol->value.enumerated.item[0] = hdsp_adatsync_sync_check(hdsp);2757 return 0;2758}2759 2760#define HDSP_ADAT_SYNC_CHECK \2761{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \2762 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \2763 .info = snd_hdsp_info_sync_check, \2764 .get = snd_hdsp_get_adat_sync_check \2765}2766 2767static int hdsp_adat_sync_check(struct hdsp *hdsp, int idx)2768{2769 int status = hdsp_read(hdsp, HDSP_statusRegister);2770 2771 if (status & (HDSP_Lock0>>idx)) {2772 if (status & (HDSP_Sync0>>idx))2773 return 2;2774 else2775 return 1;2776 } else2777 return 0;2778}2779 2780static int snd_hdsp_get_adat_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)2781{2782 int offset;2783 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);2784 2785 offset = ucontrol->id.index - 1;2786 if (snd_BUG_ON(offset < 0))2787 return -EINVAL;2788 2789 switch (hdsp->io_type) {2790 case Digiface:2791 case H9652:2792 if (offset >= 3)2793 return -EINVAL;2794 break;2795 case Multiface:2796 case H9632:2797 if (offset >= 1)2798 return -EINVAL;2799 break;2800 default:2801 return -EIO;2802 }2803 2804 ucontrol->value.enumerated.item[0] = hdsp_adat_sync_check(hdsp, offset);2805 return 0;2806}2807 2808#define HDSP_DDS_OFFSET(xname, xindex) \2809{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \2810 .name = xname, \2811 .index = xindex, \2812 .info = snd_hdsp_info_dds_offset, \2813 .get = snd_hdsp_get_dds_offset, \2814 .put = snd_hdsp_put_dds_offset \2815}2816 2817static int hdsp_dds_offset(struct hdsp *hdsp)2818{2819 u64 n;2820 unsigned int dds_value = hdsp->dds_value;2821 int system_sample_rate = hdsp->system_sample_rate;2822 2823 if (!dds_value)2824 return 0;2825 2826 n = DDS_NUMERATOR;2827 /*2828 * dds_value = n / rate2829 * rate = n / dds_value2830 */2831 n = div_u64(n, dds_value);2832 if (system_sample_rate >= 112000)2833 n *= 4;2834 else if (system_sample_rate >= 56000)2835 n *= 2;2836 return ((int)n) - system_sample_rate;2837}2838 2839static int hdsp_set_dds_offset(struct hdsp *hdsp, int offset_hz)2840{2841 int rate = hdsp->system_sample_rate + offset_hz;2842 hdsp_set_dds_value(hdsp, rate);2843 return 0;2844}2845 2846static int snd_hdsp_info_dds_offset(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)2847{2848 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;2849 uinfo->count = 1;2850 uinfo->value.integer.min = -5000;2851 uinfo->value.integer.max = 5000;2852 return 0;2853}2854 2855static int snd_hdsp_get_dds_offset(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)2856{2857 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);2858 2859 ucontrol->value.integer.value[0] = hdsp_dds_offset(hdsp);2860 return 0;2861}2862 2863static int snd_hdsp_put_dds_offset(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)2864{2865 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);2866 int change;2867 int val;2868 2869 if (!snd_hdsp_use_is_exclusive(hdsp))2870 return -EBUSY;2871 val = ucontrol->value.integer.value[0];2872 spin_lock_irq(&hdsp->lock);2873 if (val != hdsp_dds_offset(hdsp))2874 change = (hdsp_set_dds_offset(hdsp, val) == 0) ? 1 : 0;2875 else2876 change = 0;2877 spin_unlock_irq(&hdsp->lock);2878 return change;2879}2880 2881static const struct snd_kcontrol_new snd_hdsp_9632_controls[] = {2882HDSP_DA_GAIN("DA Gain", 0),2883HDSP_AD_GAIN("AD Gain", 0),2884HDSP_PHONE_GAIN("Phones Gain", 0),2885HDSP_TOGGLE_SETTING("XLR Breakout Cable", HDSP_XLRBreakoutCable),2886HDSP_DDS_OFFSET("DDS Sample Rate Offset", 0)2887};2888 2889static const struct snd_kcontrol_new snd_hdsp_controls[] = {2890{2891 .iface = SNDRV_CTL_ELEM_IFACE_PCM,2892 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),2893 .info = snd_hdsp_control_spdif_info,2894 .get = snd_hdsp_control_spdif_get,2895 .put = snd_hdsp_control_spdif_put,2896},2897{2898 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE,2899 .iface = SNDRV_CTL_ELEM_IFACE_PCM,2900 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),2901 .info = snd_hdsp_control_spdif_stream_info,2902 .get = snd_hdsp_control_spdif_stream_get,2903 .put = snd_hdsp_control_spdif_stream_put,2904},2905{2906 .access = SNDRV_CTL_ELEM_ACCESS_READ,2907 .iface = SNDRV_CTL_ELEM_IFACE_PCM,2908 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,CON_MASK),2909 .info = snd_hdsp_control_spdif_mask_info,2910 .get = snd_hdsp_control_spdif_mask_get,2911 .private_value = IEC958_AES0_NONAUDIO |2912 IEC958_AES0_PROFESSIONAL |2913 IEC958_AES0_CON_EMPHASIS,2914},2915{2916 .access = SNDRV_CTL_ELEM_ACCESS_READ,2917 .iface = SNDRV_CTL_ELEM_IFACE_PCM,2918 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PRO_MASK),2919 .info = snd_hdsp_control_spdif_mask_info,2920 .get = snd_hdsp_control_spdif_mask_get,2921 .private_value = IEC958_AES0_NONAUDIO |2922 IEC958_AES0_PROFESSIONAL |2923 IEC958_AES0_PRO_EMPHASIS,2924},2925HDSP_MIXER("Mixer", 0),2926HDSP_SPDIF_IN("IEC958 Input Connector", 0),2927HDSP_TOGGLE_SETTING("IEC958 Output also on ADAT1", HDSP_SPDIFOpticalOut),2928HDSP_TOGGLE_SETTING("IEC958 Professional Bit", HDSP_SPDIFProfessional),2929HDSP_TOGGLE_SETTING("IEC958 Emphasis Bit", HDSP_SPDIFEmphasis),2930HDSP_TOGGLE_SETTING("IEC958 Non-audio Bit", HDSP_SPDIFNonAudio),2931/* 'Sample Clock Source' complies with the alsa control naming scheme */2932HDSP_CLOCK_SOURCE("Sample Clock Source", 0),2933{2934 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,2935 .name = "Sample Clock Source Locking",2936 .info = snd_hdsp_info_clock_source_lock,2937 .get = snd_hdsp_get_clock_source_lock,2938 .put = snd_hdsp_put_clock_source_lock,2939},2940HDSP_SYSTEM_CLOCK_MODE("System Clock Mode", 0),2941HDSP_PREF_SYNC_REF("Preferred Sync Reference", 0),2942HDSP_AUTOSYNC_REF("AutoSync Reference", 0),2943HDSP_SPDIF_SAMPLE_RATE("SPDIF Sample Rate", 0),2944HDSP_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),2945/* 'External Rate' complies with the alsa control naming scheme */2946HDSP_AUTOSYNC_SAMPLE_RATE("External Rate", 0),2947HDSP_WC_SYNC_CHECK("Word Clock Lock Status", 0),2948HDSP_SPDIF_SYNC_CHECK("SPDIF Lock Status", 0),2949HDSP_ADATSYNC_SYNC_CHECK("ADAT Sync Lock Status", 0),2950HDSP_TOGGLE_SETTING("Line Out", HDSP_LineOut),2951HDSP_PRECISE_POINTER("Precise Pointer", 0),2952HDSP_USE_MIDI_WORK("Use Midi Tasklet", 0),2953};2954 2955 2956static int hdsp_rpm_input12(struct hdsp *hdsp)2957{2958 switch (hdsp->control_register & HDSP_RPM_Inp12) {2959 case HDSP_RPM_Inp12_Phon_6dB:2960 return 0;2961 case HDSP_RPM_Inp12_Phon_n6dB:2962 return 2;2963 case HDSP_RPM_Inp12_Line_0dB:2964 return 3;2965 case HDSP_RPM_Inp12_Line_n6dB:2966 return 4;2967 }2968 return 1;2969}2970 2971 2972static int snd_hdsp_get_rpm_input12(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)2973{2974 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);2975 2976 ucontrol->value.enumerated.item[0] = hdsp_rpm_input12(hdsp);2977 return 0;2978}2979 2980 2981static int hdsp_set_rpm_input12(struct hdsp *hdsp, int mode)2982{2983 hdsp->control_register &= ~HDSP_RPM_Inp12;2984 switch (mode) {2985 case 0:2986 hdsp->control_register |= HDSP_RPM_Inp12_Phon_6dB;2987 break;2988 case 1:2989 break;2990 case 2:2991 hdsp->control_register |= HDSP_RPM_Inp12_Phon_n6dB;2992 break;2993 case 3:2994 hdsp->control_register |= HDSP_RPM_Inp12_Line_0dB;2995 break;2996 case 4:2997 hdsp->control_register |= HDSP_RPM_Inp12_Line_n6dB;2998 break;2999 default:3000 return -1;3001 }3002 3003 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);3004 return 0;3005}3006 3007 3008static int snd_hdsp_put_rpm_input12(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)3009{3010 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);3011 int change;3012 int val;3013 3014 if (!snd_hdsp_use_is_exclusive(hdsp))3015 return -EBUSY;3016 val = ucontrol->value.enumerated.item[0];3017 if (val < 0)3018 val = 0;3019 if (val > 4)3020 val = 4;3021 spin_lock_irq(&hdsp->lock);3022 if (val != hdsp_rpm_input12(hdsp))3023 change = (hdsp_set_rpm_input12(hdsp, val) == 0) ? 1 : 0;3024 else3025 change = 0;3026 spin_unlock_irq(&hdsp->lock);3027 return change;3028}3029 3030 3031static int snd_hdsp_info_rpm_input(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)3032{3033 static const char * const texts[] = {3034 "Phono +6dB", "Phono 0dB", "Phono -6dB", "Line 0dB", "Line -6dB"3035 };3036 3037 return snd_ctl_enum_info(uinfo, 1, 5, texts);3038}3039 3040 3041static int hdsp_rpm_input34(struct hdsp *hdsp)3042{3043 switch (hdsp->control_register & HDSP_RPM_Inp34) {3044 case HDSP_RPM_Inp34_Phon_6dB:3045 return 0;3046 case HDSP_RPM_Inp34_Phon_n6dB:3047 return 2;3048 case HDSP_RPM_Inp34_Line_0dB:3049 return 3;3050 case HDSP_RPM_Inp34_Line_n6dB:3051 return 4;3052 }3053 return 1;3054}3055 3056 3057static int snd_hdsp_get_rpm_input34(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)3058{3059 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);3060 3061 ucontrol->value.enumerated.item[0] = hdsp_rpm_input34(hdsp);3062 return 0;3063}3064 3065 3066static int hdsp_set_rpm_input34(struct hdsp *hdsp, int mode)3067{3068 hdsp->control_register &= ~HDSP_RPM_Inp34;3069 switch (mode) {3070 case 0:3071 hdsp->control_register |= HDSP_RPM_Inp34_Phon_6dB;3072 break;3073 case 1:3074 break;3075 case 2:3076 hdsp->control_register |= HDSP_RPM_Inp34_Phon_n6dB;3077 break;3078 case 3:3079 hdsp->control_register |= HDSP_RPM_Inp34_Line_0dB;3080 break;3081 case 4:3082 hdsp->control_register |= HDSP_RPM_Inp34_Line_n6dB;3083 break;3084 default:3085 return -1;3086 }3087 3088 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);3089 return 0;3090}3091 3092 3093static int snd_hdsp_put_rpm_input34(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)3094{3095 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);3096 int change;3097 int val;3098 3099 if (!snd_hdsp_use_is_exclusive(hdsp))3100 return -EBUSY;3101 val = ucontrol->value.enumerated.item[0];3102 if (val < 0)3103 val = 0;3104 if (val > 4)3105 val = 4;3106 spin_lock_irq(&hdsp->lock);3107 if (val != hdsp_rpm_input34(hdsp))3108 change = (hdsp_set_rpm_input34(hdsp, val) == 0) ? 1 : 0;3109 else3110 change = 0;3111 spin_unlock_irq(&hdsp->lock);3112 return change;3113}3114 3115 3116/* RPM Bypass switch */3117static int hdsp_rpm_bypass(struct hdsp *hdsp)3118{3119 return (hdsp->control_register & HDSP_RPM_Bypass) ? 1 : 0;3120}3121 3122 3123static int snd_hdsp_get_rpm_bypass(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)3124{3125 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);3126 3127 ucontrol->value.integer.value[0] = hdsp_rpm_bypass(hdsp);3128 return 0;3129}3130 3131 3132static int hdsp_set_rpm_bypass(struct hdsp *hdsp, int on)3133{3134 if (on)3135 hdsp->control_register |= HDSP_RPM_Bypass;3136 else3137 hdsp->control_register &= ~HDSP_RPM_Bypass;3138 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);3139 return 0;3140}3141 3142 3143static int snd_hdsp_put_rpm_bypass(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)3144{3145 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);3146 int change;3147 unsigned int val;3148 3149 if (!snd_hdsp_use_is_exclusive(hdsp))3150 return -EBUSY;3151 val = ucontrol->value.integer.value[0] & 1;3152 spin_lock_irq(&hdsp->lock);3153 change = (int)val != hdsp_rpm_bypass(hdsp);3154 hdsp_set_rpm_bypass(hdsp, val);3155 spin_unlock_irq(&hdsp->lock);3156 return change;3157}3158 3159 3160static int snd_hdsp_info_rpm_bypass(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)3161{3162 static const char * const texts[] = {"On", "Off"};3163 3164 return snd_ctl_enum_info(uinfo, 1, 2, texts);3165}3166 3167 3168/* RPM Disconnect switch */3169static int hdsp_rpm_disconnect(struct hdsp *hdsp)3170{3171 return (hdsp->control_register & HDSP_RPM_Disconnect) ? 1 : 0;3172}3173 3174 3175static int snd_hdsp_get_rpm_disconnect(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)3176{3177 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);3178 3179 ucontrol->value.integer.value[0] = hdsp_rpm_disconnect(hdsp);3180 return 0;3181}3182 3183 3184static int hdsp_set_rpm_disconnect(struct hdsp *hdsp, int on)3185{3186 if (on)3187 hdsp->control_register |= HDSP_RPM_Disconnect;3188 else3189 hdsp->control_register &= ~HDSP_RPM_Disconnect;3190 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);3191 return 0;3192}3193 3194 3195static int snd_hdsp_put_rpm_disconnect(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)3196{3197 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);3198 int change;3199 unsigned int val;3200 3201 if (!snd_hdsp_use_is_exclusive(hdsp))3202 return -EBUSY;3203 val = ucontrol->value.integer.value[0] & 1;3204 spin_lock_irq(&hdsp->lock);3205 change = (int)val != hdsp_rpm_disconnect(hdsp);3206 hdsp_set_rpm_disconnect(hdsp, val);3207 spin_unlock_irq(&hdsp->lock);3208 return change;3209}3210 3211static int snd_hdsp_info_rpm_disconnect(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)3212{3213 static const char * const texts[] = {"On", "Off"};3214 3215 return snd_ctl_enum_info(uinfo, 1, 2, texts);3216}3217 3218static const struct snd_kcontrol_new snd_hdsp_rpm_controls[] = {3219 {3220 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,3221 .name = "RPM Bypass",3222 .get = snd_hdsp_get_rpm_bypass,3223 .put = snd_hdsp_put_rpm_bypass,3224 .info = snd_hdsp_info_rpm_bypass3225 },3226 {3227 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,3228 .name = "RPM Disconnect",3229 .get = snd_hdsp_get_rpm_disconnect,3230 .put = snd_hdsp_put_rpm_disconnect,3231 .info = snd_hdsp_info_rpm_disconnect3232 },3233 {3234 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,3235 .name = "Input 1/2",3236 .get = snd_hdsp_get_rpm_input12,3237 .put = snd_hdsp_put_rpm_input12,3238 .info = snd_hdsp_info_rpm_input3239 },3240 {3241 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,3242 .name = "Input 3/4",3243 .get = snd_hdsp_get_rpm_input34,3244 .put = snd_hdsp_put_rpm_input34,3245 .info = snd_hdsp_info_rpm_input3246 },3247 HDSP_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),3248 HDSP_MIXER("Mixer", 0)3249};3250 3251static const struct snd_kcontrol_new snd_hdsp_96xx_aeb =3252 HDSP_TOGGLE_SETTING("Analog Extension Board",3253 HDSP_AnalogExtensionBoard);3254static struct snd_kcontrol_new snd_hdsp_adat_sync_check = HDSP_ADAT_SYNC_CHECK;3255 3256 3257static bool hdsp_loopback_get(struct hdsp *const hdsp, const u8 channel)3258{3259 return hdsp->io_loopback & (1 << channel);3260}3261 3262static int hdsp_loopback_set(struct hdsp *const hdsp, const u8 channel, const bool enable)3263{3264 if (hdsp_loopback_get(hdsp, channel) == enable)3265 return 0;3266 3267 hdsp->io_loopback ^= (1 << channel);3268 3269 hdsp_write(hdsp, HDSP_inputEnable + (4 * (hdsp->max_channels + channel)), enable);3270 3271 return 1;3272}3273 3274static int snd_hdsp_loopback_get(struct snd_kcontrol *const kcontrol,3275 struct snd_ctl_elem_value *const ucontrol)3276{3277 struct hdsp *const hdsp = snd_kcontrol_chip(kcontrol);3278 const u8 channel = snd_ctl_get_ioff(kcontrol, &ucontrol->id);3279 3280 if (channel >= hdsp->max_channels)3281 return -ENOENT;3282 3283 ucontrol->value.integer.value[0] = hdsp_loopback_get(hdsp, channel);3284 3285 return 0;3286}3287 3288static int snd_hdsp_loopback_put(struct snd_kcontrol *const kcontrol,3289 struct snd_ctl_elem_value *const ucontrol)3290{3291 struct hdsp *const hdsp = snd_kcontrol_chip(kcontrol);3292 const u8 channel = snd_ctl_get_ioff(kcontrol, &ucontrol->id);3293 const bool enable = ucontrol->value.integer.value[0] & 1;3294 3295 if (channel >= hdsp->max_channels)3296 return -ENOENT;3297 3298 return hdsp_loopback_set(hdsp, channel, enable);3299}3300 3301static struct snd_kcontrol_new snd_hdsp_loopback_control = {3302 .iface = SNDRV_CTL_ELEM_IFACE_HWDEP,3303 .name = "Output Loopback",3304 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE,3305 .info = snd_ctl_boolean_mono_info,3306 .get = snd_hdsp_loopback_get,3307 .put = snd_hdsp_loopback_put3308};3309 3310static int snd_hdsp_create_controls(struct snd_card *card, struct hdsp *hdsp)3311{3312 unsigned int idx;3313 int err;3314 struct snd_kcontrol *kctl;3315 3316 if (hdsp->io_type == RPM) {3317 /* RPM Bypass, Disconnect and Input switches */3318 for (idx = 0; idx < ARRAY_SIZE(snd_hdsp_rpm_controls); idx++) {3319 err = snd_ctl_add(card, snd_ctl_new1(&snd_hdsp_rpm_controls[idx], hdsp));3320 if (err < 0)3321 return err;3322 }3323 return 0;3324 }3325 3326 for (idx = 0; idx < ARRAY_SIZE(snd_hdsp_controls); idx++) {3327 kctl = snd_ctl_new1(&snd_hdsp_controls[idx], hdsp);3328 err = snd_ctl_add(card, kctl);3329 if (err < 0)3330 return err;3331 if (idx == 1) /* IEC958 (S/PDIF) Stream */3332 hdsp->spdif_ctl = kctl;3333 }3334 3335 /* ADAT SyncCheck status */3336 snd_hdsp_adat_sync_check.name = "ADAT Lock Status";3337 snd_hdsp_adat_sync_check.index = 1;3338 kctl = snd_ctl_new1(&snd_hdsp_adat_sync_check, hdsp);3339 err = snd_ctl_add(card, kctl);3340 if (err < 0)3341 return err;3342 if (hdsp->io_type == Digiface || hdsp->io_type == H9652) {3343 for (idx = 1; idx < 3; ++idx) {3344 snd_hdsp_adat_sync_check.index = idx+1;3345 kctl = snd_ctl_new1(&snd_hdsp_adat_sync_check, hdsp);3346 err = snd_ctl_add(card, kctl);3347 if (err < 0)3348 return err;3349 }3350 }3351 3352 /* DA, AD and Phone gain and XLR breakout cable controls for H9632 cards */3353 if (hdsp->io_type == H9632) {3354 for (idx = 0; idx < ARRAY_SIZE(snd_hdsp_9632_controls); idx++) {3355 kctl = snd_ctl_new1(&snd_hdsp_9632_controls[idx], hdsp);3356 err = snd_ctl_add(card, kctl);3357 if (err < 0)3358 return err;3359 }3360 }3361 3362 /* Output loopback controls for H9632 cards */3363 if (hdsp->io_type == H9632) {3364 snd_hdsp_loopback_control.count = hdsp->max_channels;3365 kctl = snd_ctl_new1(&snd_hdsp_loopback_control, hdsp);3366 if (kctl == NULL)3367 return -ENOMEM;3368 err = snd_ctl_add(card, kctl);3369 if (err < 0)3370 return err;3371 }3372 3373 /* AEB control for H96xx card */3374 if (hdsp->io_type == H9632 || hdsp->io_type == H9652) {3375 kctl = snd_ctl_new1(&snd_hdsp_96xx_aeb, hdsp);3376 err = snd_ctl_add(card, kctl);3377 if (err < 0)3378 return err;3379 }3380 3381 return 0;3382}3383 3384/*------------------------------------------------------------3385 /proc interface3386 ------------------------------------------------------------*/3387 3388static void3389snd_hdsp_proc_read(struct snd_info_entry *entry, struct snd_info_buffer *buffer)3390{3391 struct hdsp *hdsp = entry->private_data;3392 unsigned int status;3393 unsigned int status2;3394 char *pref_sync_ref;3395 char *autosync_ref;3396 char *system_clock_mode;3397 char *clock_source;3398 int x;3399 3400 status = hdsp_read(hdsp, HDSP_statusRegister);3401 status2 = hdsp_read(hdsp, HDSP_status2Register);3402 3403 snd_iprintf(buffer, "%s (Card #%d)\n", hdsp->card_name,3404 hdsp->card->number + 1);3405 snd_iprintf(buffer, "Buffers: capture %p playback %p\n",3406 hdsp->capture_buffer, hdsp->playback_buffer);3407 snd_iprintf(buffer, "IRQ: %d Registers bus: 0x%lx VM: 0x%lx\n",3408 hdsp->irq, hdsp->port, (unsigned long)hdsp->iobase);3409 snd_iprintf(buffer, "Control register: 0x%x\n", hdsp->control_register);3410 snd_iprintf(buffer, "Control2 register: 0x%x\n",3411 hdsp->control2_register);3412 snd_iprintf(buffer, "Status register: 0x%x\n", status);3413 snd_iprintf(buffer, "Status2 register: 0x%x\n", status2);3414 3415 if (hdsp_check_for_iobox(hdsp)) {3416 snd_iprintf(buffer, "No I/O box connected.\n"3417 "Please connect one and upload firmware.\n");3418 return;3419 }3420 3421 if (hdsp_check_for_firmware(hdsp, 0)) {3422 if (hdsp->state & HDSP_FirmwareCached) {3423 if (snd_hdsp_load_firmware_from_cache(hdsp) != 0) {3424 snd_iprintf(buffer, "Firmware loading from "3425 "cache failed, "3426 "please upload manually.\n");3427 return;3428 }3429 } else {3430 int err;3431 3432 err = hdsp_request_fw_loader(hdsp);3433 if (err < 0) {3434 snd_iprintf(buffer,3435 "No firmware loaded nor cached, "3436 "please upload firmware.\n");3437 return;3438 }3439 }3440 }3441 3442 snd_iprintf(buffer, "FIFO status: %d\n", hdsp_read(hdsp, HDSP_fifoStatus) & 0xff);3443 snd_iprintf(buffer, "MIDI1 Output status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusOut0));3444 snd_iprintf(buffer, "MIDI1 Input status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusIn0));3445 snd_iprintf(buffer, "MIDI2 Output status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusOut1));3446 snd_iprintf(buffer, "MIDI2 Input status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusIn1));3447 snd_iprintf(buffer, "Use Midi Tasklet: %s\n", hdsp->use_midi_work ? "on" : "off");3448 3449 snd_iprintf(buffer, "\n");3450 3451 x = 1 << (6 + hdsp_decode_latency(hdsp->control_register & HDSP_LatencyMask));3452 3453 snd_iprintf(buffer, "Buffer Size (Latency): %d samples (2 periods of %lu bytes)\n", x, (unsigned long) hdsp->period_bytes);3454 snd_iprintf(buffer, "Hardware pointer (frames): %ld\n", hdsp_hw_pointer(hdsp));3455 snd_iprintf(buffer, "Precise pointer: %s\n", hdsp->precise_ptr ? "on" : "off");3456 snd_iprintf(buffer, "Line out: %s\n", (hdsp->control_register & HDSP_LineOut) ? "on" : "off");3457 3458 snd_iprintf(buffer, "Firmware version: %d\n", (status2&HDSP_version0)|(status2&HDSP_version1)<<1|(status2&HDSP_version2)<<2);3459 3460 snd_iprintf(buffer, "\n");3461 3462 switch (hdsp_clock_source(hdsp)) {3463 case HDSP_CLOCK_SOURCE_AUTOSYNC:3464 clock_source = "AutoSync";3465 break;3466 case HDSP_CLOCK_SOURCE_INTERNAL_32KHZ:3467 clock_source = "Internal 32 kHz";3468 break;3469 case HDSP_CLOCK_SOURCE_INTERNAL_44_1KHZ:3470 clock_source = "Internal 44.1 kHz";3471 break;3472 case HDSP_CLOCK_SOURCE_INTERNAL_48KHZ:3473 clock_source = "Internal 48 kHz";3474 break;3475 case HDSP_CLOCK_SOURCE_INTERNAL_64KHZ:3476 clock_source = "Internal 64 kHz";3477 break;3478 case HDSP_CLOCK_SOURCE_INTERNAL_88_2KHZ:3479 clock_source = "Internal 88.2 kHz";3480 break;3481 case HDSP_CLOCK_SOURCE_INTERNAL_96KHZ:3482 clock_source = "Internal 96 kHz";3483 break;3484 case HDSP_CLOCK_SOURCE_INTERNAL_128KHZ:3485 clock_source = "Internal 128 kHz";3486 break;3487 case HDSP_CLOCK_SOURCE_INTERNAL_176_4KHZ:3488 clock_source = "Internal 176.4 kHz";3489 break;3490 case HDSP_CLOCK_SOURCE_INTERNAL_192KHZ:3491 clock_source = "Internal 192 kHz";3492 break;3493 default:3494 clock_source = "Error";3495 }3496 snd_iprintf (buffer, "Sample Clock Source: %s\n", clock_source);3497 3498 if (hdsp_system_clock_mode(hdsp))3499 system_clock_mode = "Slave";3500 else3501 system_clock_mode = "Master";3502 3503 switch (hdsp_pref_sync_ref (hdsp)) {3504 case HDSP_SYNC_FROM_WORD:3505 pref_sync_ref = "Word Clock";3506 break;3507 case HDSP_SYNC_FROM_ADAT_SYNC:3508 pref_sync_ref = "ADAT Sync";3509 break;3510 case HDSP_SYNC_FROM_SPDIF:3511 pref_sync_ref = "SPDIF";3512 break;3513 case HDSP_SYNC_FROM_ADAT1:3514 pref_sync_ref = "ADAT1";3515 break;3516 case HDSP_SYNC_FROM_ADAT2:3517 pref_sync_ref = "ADAT2";3518 break;3519 case HDSP_SYNC_FROM_ADAT3:3520 pref_sync_ref = "ADAT3";3521 break;3522 default:3523 pref_sync_ref = "Word Clock";3524 break;3525 }3526 snd_iprintf (buffer, "Preferred Sync Reference: %s\n", pref_sync_ref);3527 3528 switch (hdsp_autosync_ref (hdsp)) {3529 case HDSP_AUTOSYNC_FROM_WORD:3530 autosync_ref = "Word Clock";3531 break;3532 case HDSP_AUTOSYNC_FROM_ADAT_SYNC:3533 autosync_ref = "ADAT Sync";3534 break;3535 case HDSP_AUTOSYNC_FROM_SPDIF:3536 autosync_ref = "SPDIF";3537 break;3538 case HDSP_AUTOSYNC_FROM_NONE:3539 autosync_ref = "None";3540 break;3541 case HDSP_AUTOSYNC_FROM_ADAT1:3542 autosync_ref = "ADAT1";3543 break;3544 case HDSP_AUTOSYNC_FROM_ADAT2:3545 autosync_ref = "ADAT2";3546 break;3547 case HDSP_AUTOSYNC_FROM_ADAT3:3548 autosync_ref = "ADAT3";3549 break;3550 default:3551 autosync_ref = "---";3552 break;3553 }3554 snd_iprintf (buffer, "AutoSync Reference: %s\n", autosync_ref);3555 3556 snd_iprintf (buffer, "AutoSync Frequency: %d\n", hdsp_external_sample_rate(hdsp));3557 3558 snd_iprintf (buffer, "System Clock Mode: %s\n", system_clock_mode);3559 3560 snd_iprintf (buffer, "System Clock Frequency: %d\n", hdsp->system_sample_rate);3561 snd_iprintf (buffer, "System Clock Locked: %s\n", hdsp->clock_source_locked ? "Yes" : "No");3562 3563 snd_iprintf(buffer, "\n");3564 3565 if (hdsp->io_type != RPM) {3566 switch (hdsp_spdif_in(hdsp)) {3567 case HDSP_SPDIFIN_OPTICAL:3568 snd_iprintf(buffer, "IEC958 input: Optical\n");3569 break;3570 case HDSP_SPDIFIN_COAXIAL:3571 snd_iprintf(buffer, "IEC958 input: Coaxial\n");3572 break;3573 case HDSP_SPDIFIN_INTERNAL:3574 snd_iprintf(buffer, "IEC958 input: Internal\n");3575 break;3576 case HDSP_SPDIFIN_AES:3577 snd_iprintf(buffer, "IEC958 input: AES\n");3578 break;3579 default:3580 snd_iprintf(buffer, "IEC958 input: ???\n");3581 break;3582 }3583 }3584 3585 if (RPM == hdsp->io_type) {3586 if (hdsp->control_register & HDSP_RPM_Bypass)3587 snd_iprintf(buffer, "RPM Bypass: disabled\n");3588 else3589 snd_iprintf(buffer, "RPM Bypass: enabled\n");3590 if (hdsp->control_register & HDSP_RPM_Disconnect)3591 snd_iprintf(buffer, "RPM disconnected\n");3592 else3593 snd_iprintf(buffer, "RPM connected\n");3594 3595 switch (hdsp->control_register & HDSP_RPM_Inp12) {3596 case HDSP_RPM_Inp12_Phon_6dB:3597 snd_iprintf(buffer, "Input 1/2: Phono, 6dB\n");3598 break;3599 case HDSP_RPM_Inp12_Phon_0dB:3600 snd_iprintf(buffer, "Input 1/2: Phono, 0dB\n");3601 break;3602 case HDSP_RPM_Inp12_Phon_n6dB:3603 snd_iprintf(buffer, "Input 1/2: Phono, -6dB\n");3604 break;3605 case HDSP_RPM_Inp12_Line_0dB:3606 snd_iprintf(buffer, "Input 1/2: Line, 0dB\n");3607 break;3608 case HDSP_RPM_Inp12_Line_n6dB:3609 snd_iprintf(buffer, "Input 1/2: Line, -6dB\n");3610 break;3611 default:3612 snd_iprintf(buffer, "Input 1/2: ???\n");3613 }3614 3615 switch (hdsp->control_register & HDSP_RPM_Inp34) {3616 case HDSP_RPM_Inp34_Phon_6dB:3617 snd_iprintf(buffer, "Input 3/4: Phono, 6dB\n");3618 break;3619 case HDSP_RPM_Inp34_Phon_0dB:3620 snd_iprintf(buffer, "Input 3/4: Phono, 0dB\n");3621 break;3622 case HDSP_RPM_Inp34_Phon_n6dB:3623 snd_iprintf(buffer, "Input 3/4: Phono, -6dB\n");3624 break;3625 case HDSP_RPM_Inp34_Line_0dB:3626 snd_iprintf(buffer, "Input 3/4: Line, 0dB\n");3627 break;3628 case HDSP_RPM_Inp34_Line_n6dB:3629 snd_iprintf(buffer, "Input 3/4: Line, -6dB\n");3630 break;3631 default:3632 snd_iprintf(buffer, "Input 3/4: ???\n");3633 }3634 3635 } else {3636 if (hdsp->control_register & HDSP_SPDIFOpticalOut)3637 snd_iprintf(buffer, "IEC958 output: Coaxial & ADAT1\n");3638 else3639 snd_iprintf(buffer, "IEC958 output: Coaxial only\n");3640 3641 if (hdsp->control_register & HDSP_SPDIFProfessional)3642 snd_iprintf(buffer, "IEC958 quality: Professional\n");3643 else3644 snd_iprintf(buffer, "IEC958 quality: Consumer\n");3645 3646 if (hdsp->control_register & HDSP_SPDIFEmphasis)3647 snd_iprintf(buffer, "IEC958 emphasis: on\n");3648 else3649 snd_iprintf(buffer, "IEC958 emphasis: off\n");3650 3651 if (hdsp->control_register & HDSP_SPDIFNonAudio)3652 snd_iprintf(buffer, "IEC958 NonAudio: on\n");3653 else3654 snd_iprintf(buffer, "IEC958 NonAudio: off\n");3655 x = hdsp_spdif_sample_rate(hdsp);3656 if (x != 0)3657 snd_iprintf(buffer, "IEC958 sample rate: %d\n", x);3658 else3659 snd_iprintf(buffer, "IEC958 sample rate: Error flag set\n");3660 }3661 snd_iprintf(buffer, "\n");3662 3663 /* Sync Check */3664 x = status & HDSP_Sync0;3665 if (status & HDSP_Lock0)3666 snd_iprintf(buffer, "ADAT1: %s\n", x ? "Sync" : "Lock");3667 else3668 snd_iprintf(buffer, "ADAT1: No Lock\n");3669 3670 switch (hdsp->io_type) {3671 case Digiface:3672 case H9652:3673 x = status & HDSP_Sync1;3674 if (status & HDSP_Lock1)3675 snd_iprintf(buffer, "ADAT2: %s\n", x ? "Sync" : "Lock");3676 else3677 snd_iprintf(buffer, "ADAT2: No Lock\n");3678 x = status & HDSP_Sync2;3679 if (status & HDSP_Lock2)3680 snd_iprintf(buffer, "ADAT3: %s\n", x ? "Sync" : "Lock");3681 else3682 snd_iprintf(buffer, "ADAT3: No Lock\n");3683 break;3684 default:3685 /* relax */3686 break;3687 }3688 3689 x = status & HDSP_SPDIFSync;3690 if (status & HDSP_SPDIFErrorFlag)3691 snd_iprintf (buffer, "SPDIF: No Lock\n");3692 else3693 snd_iprintf (buffer, "SPDIF: %s\n", x ? "Sync" : "Lock");3694 3695 x = status2 & HDSP_wc_sync;3696 if (status2 & HDSP_wc_lock)3697 snd_iprintf (buffer, "Word Clock: %s\n", x ? "Sync" : "Lock");3698 else3699 snd_iprintf (buffer, "Word Clock: No Lock\n");3700 3701 x = status & HDSP_TimecodeSync;3702 if (status & HDSP_TimecodeLock)3703 snd_iprintf(buffer, "ADAT Sync: %s\n", x ? "Sync" : "Lock");3704 else3705 snd_iprintf(buffer, "ADAT Sync: No Lock\n");3706 3707 snd_iprintf(buffer, "\n");3708 3709 /* Informations about H9632 specific controls */3710 if (hdsp->io_type == H9632) {3711 char *tmp;3712 3713 switch (hdsp_ad_gain(hdsp)) {3714 case 0:3715 tmp = "-10 dBV";3716 break;3717 case 1:3718 tmp = "+4 dBu";3719 break;3720 default:3721 tmp = "Lo Gain";3722 break;3723 }3724 snd_iprintf(buffer, "AD Gain : %s\n", tmp);3725 3726 switch (hdsp_da_gain(hdsp)) {3727 case 0:3728 tmp = "Hi Gain";3729 break;3730 case 1:3731 tmp = "+4 dBu";3732 break;3733 default:3734 tmp = "-10 dBV";3735 break;3736 }3737 snd_iprintf(buffer, "DA Gain : %s\n", tmp);3738 3739 switch (hdsp_phone_gain(hdsp)) {3740 case 0:3741 tmp = "0 dB";3742 break;3743 case 1:3744 tmp = "-6 dB";3745 break;3746 default:3747 tmp = "-12 dB";3748 break;3749 }3750 snd_iprintf(buffer, "Phones Gain : %s\n", tmp);3751 3752 snd_iprintf(buffer, "XLR Breakout Cable : %s\n",3753 hdsp_toggle_setting(hdsp, HDSP_XLRBreakoutCable) ?3754 "yes" : "no");3755 3756 if (hdsp->control_register & HDSP_AnalogExtensionBoard)3757 snd_iprintf(buffer, "AEB : on (ADAT1 internal)\n");3758 else3759 snd_iprintf(buffer, "AEB : off (ADAT1 external)\n");3760 snd_iprintf(buffer, "\n");3761 }3762 3763}3764 3765static void snd_hdsp_proc_init(struct hdsp *hdsp)3766{3767 snd_card_ro_proc_new(hdsp->card, "hdsp", hdsp, snd_hdsp_proc_read);3768}3769 3770static int snd_hdsp_initialize_memory(struct hdsp *hdsp)3771{3772 struct snd_dma_buffer *capture_dma, *playback_dma;3773 3774 capture_dma = snd_hammerfall_get_buffer(hdsp->pci, HDSP_DMA_AREA_BYTES);3775 playback_dma = snd_hammerfall_get_buffer(hdsp->pci, HDSP_DMA_AREA_BYTES);3776 if (!capture_dma || !playback_dma) {3777 dev_err(hdsp->card->dev,3778 "%s: no buffers available\n", hdsp->card_name);3779 return -ENOMEM;3780 }3781 3782 /* copy to the own data for alignment */3783 hdsp->capture_dma_buf = *capture_dma;3784 hdsp->playback_dma_buf = *playback_dma;3785 3786 /* Align to bus-space 64K boundary */3787 hdsp->capture_dma_buf.addr = ALIGN(capture_dma->addr, 0x10000ul);3788 hdsp->playback_dma_buf.addr = ALIGN(playback_dma->addr, 0x10000ul);3789 3790 /* Tell the card where it is */3791 hdsp_write(hdsp, HDSP_inputBufferAddress, hdsp->capture_dma_buf.addr);3792 hdsp_write(hdsp, HDSP_outputBufferAddress, hdsp->playback_dma_buf.addr);3793 3794 hdsp->capture_dma_buf.area += hdsp->capture_dma_buf.addr - capture_dma->addr;3795 hdsp->playback_dma_buf.area += hdsp->playback_dma_buf.addr - playback_dma->addr;3796 hdsp->capture_buffer = hdsp->capture_dma_buf.area;3797 hdsp->playback_buffer = hdsp->playback_dma_buf.area;3798 3799 return 0;3800}3801 3802static int snd_hdsp_set_defaults(struct hdsp *hdsp)3803{3804 unsigned int i;3805 3806 /* ASSUMPTION: hdsp->lock is either held, or3807 there is no need to hold it (e.g. during module3808 initialization).3809 */3810 3811 /* set defaults:3812 3813 SPDIF Input via Coax3814 Master clock mode3815 maximum latency (7 => 2^7 = 8192 samples, 64Kbyte buffer,3816 which implies 2 4096 sample, 32Kbyte periods).3817 Enable line out.3818 */3819 3820 hdsp->control_register = HDSP_ClockModeMaster |3821 HDSP_SPDIFInputCoaxial |3822 hdsp_encode_latency(7) |3823 HDSP_LineOut;3824 3825 3826 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);3827 3828#ifdef SNDRV_BIG_ENDIAN3829 hdsp->control2_register = HDSP_BIGENDIAN_MODE;3830#else3831 hdsp->control2_register = 0;3832#endif3833 if (hdsp->io_type == H9652)3834 snd_hdsp_9652_enable_mixer (hdsp);3835 else3836 hdsp_write (hdsp, HDSP_control2Reg, hdsp->control2_register);3837 3838 hdsp_reset_hw_pointer(hdsp);3839 hdsp_compute_period_size(hdsp);3840 3841 /* silence everything */3842 3843 for (i = 0; i < HDSP_MATRIX_MIXER_SIZE; ++i)3844 hdsp->mixer_matrix[i] = MINUS_INFINITY_GAIN;3845 3846 for (i = 0; i < ((hdsp->io_type == H9652 || hdsp->io_type == H9632) ? 1352 : HDSP_MATRIX_MIXER_SIZE); ++i) {3847 if (hdsp_write_gain (hdsp, i, MINUS_INFINITY_GAIN))3848 return -EIO;3849 }3850 3851 /* H9632 specific defaults */3852 if (hdsp->io_type == H9632) {3853 hdsp->control_register |= (HDSP_DAGainPlus4dBu | HDSP_ADGainPlus4dBu | HDSP_PhoneGain0dB);3854 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);3855 }3856 3857 /* set a default rate so that the channel map is set up.3858 */3859 3860 hdsp_set_rate(hdsp, 48000, 1);3861 3862 return 0;3863}3864 3865static void hdsp_midi_work(struct work_struct *work)3866{3867 struct hdsp *hdsp = container_of(work, struct hdsp, midi_work);3868 3869 if (hdsp->midi[0].pending)3870 snd_hdsp_midi_input_read (&hdsp->midi[0]);3871 if (hdsp->midi[1].pending)3872 snd_hdsp_midi_input_read (&hdsp->midi[1]);3873}3874 3875static irqreturn_t snd_hdsp_interrupt(int irq, void *dev_id)3876{3877 struct hdsp *hdsp = (struct hdsp *) dev_id;3878 unsigned int status;3879 int audio;3880 int midi0;3881 int midi1;3882 unsigned int midi0status;3883 unsigned int midi1status;3884 int schedule = 0;3885 3886 status = hdsp_read(hdsp, HDSP_statusRegister);3887 3888 audio = status & HDSP_audioIRQPending;3889 midi0 = status & HDSP_midi0IRQPending;3890 midi1 = status & HDSP_midi1IRQPending;3891 3892 if (!audio && !midi0 && !midi1)3893 return IRQ_NONE;3894 3895 hdsp_write(hdsp, HDSP_interruptConfirmation, 0);3896 3897 midi0status = hdsp_read (hdsp, HDSP_midiStatusIn0) & 0xff;3898 midi1status = hdsp_read (hdsp, HDSP_midiStatusIn1) & 0xff;3899 3900 if (!(hdsp->state & HDSP_InitializationComplete))3901 return IRQ_HANDLED;3902 3903 if (audio) {3904 if (hdsp->capture_substream)3905 snd_pcm_period_elapsed(hdsp->pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream);3906 3907 if (hdsp->playback_substream)3908 snd_pcm_period_elapsed(hdsp->pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream);3909 }3910 3911 if (midi0 && midi0status) {3912 if (hdsp->use_midi_work) {3913 /* we disable interrupts for this input until processing is done */3914 hdsp->control_register &= ~HDSP_Midi0InterruptEnable;3915 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);3916 hdsp->midi[0].pending = 1;3917 schedule = 1;3918 } else {3919 snd_hdsp_midi_input_read (&hdsp->midi[0]);3920 }3921 }3922 if (hdsp->io_type != Multiface && hdsp->io_type != RPM && hdsp->io_type != H9632 && midi1 && midi1status) {3923 if (hdsp->use_midi_work) {3924 /* we disable interrupts for this input until processing is done */3925 hdsp->control_register &= ~HDSP_Midi1InterruptEnable;3926 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);3927 hdsp->midi[1].pending = 1;3928 schedule = 1;3929 } else {3930 snd_hdsp_midi_input_read (&hdsp->midi[1]);3931 }3932 }3933 if (hdsp->use_midi_work && schedule)3934 queue_work(system_highpri_wq, &hdsp->midi_work);3935 return IRQ_HANDLED;3936}3937 3938static snd_pcm_uframes_t snd_hdsp_hw_pointer(struct snd_pcm_substream *substream)3939{3940 struct hdsp *hdsp = snd_pcm_substream_chip(substream);3941 return hdsp_hw_pointer(hdsp);3942}3943 3944static signed char *hdsp_channel_buffer_location(struct hdsp *hdsp,3945 int stream,3946 int channel)3947 3948{3949 int mapped_channel;3950 3951 if (snd_BUG_ON(channel < 0 || channel >= hdsp->max_channels))3952 return NULL;3953 3954 mapped_channel = hdsp->channel_map[channel];3955 if (mapped_channel < 0)3956 return NULL;3957 3958 if (stream == SNDRV_PCM_STREAM_CAPTURE)3959 return hdsp->capture_buffer + (mapped_channel * HDSP_CHANNEL_BUFFER_BYTES);3960 else3961 return hdsp->playback_buffer + (mapped_channel * HDSP_CHANNEL_BUFFER_BYTES);3962}3963 3964static int snd_hdsp_playback_copy(struct snd_pcm_substream *substream,3965 int channel, unsigned long pos,3966 struct iov_iter *src, unsigned long count)3967{3968 struct hdsp *hdsp = snd_pcm_substream_chip(substream);3969 signed char *channel_buf;3970 3971 if (snd_BUG_ON(pos + count > HDSP_CHANNEL_BUFFER_BYTES))3972 return -EINVAL;3973 3974 channel_buf = hdsp_channel_buffer_location (hdsp, substream->pstr->stream, channel);3975 if (snd_BUG_ON(!channel_buf))3976 return -EIO;3977 if (copy_from_iter(channel_buf + pos, count, src) != count)3978 return -EFAULT;3979 return 0;3980}3981 3982static int snd_hdsp_capture_copy(struct snd_pcm_substream *substream,3983 int channel, unsigned long pos,3984 struct iov_iter *dst, unsigned long count)3985{3986 struct hdsp *hdsp = snd_pcm_substream_chip(substream);3987 signed char *channel_buf;3988 3989 if (snd_BUG_ON(pos + count > HDSP_CHANNEL_BUFFER_BYTES))3990 return -EINVAL;3991 3992 channel_buf = hdsp_channel_buffer_location (hdsp, substream->pstr->stream, channel);3993 if (snd_BUG_ON(!channel_buf))3994 return -EIO;3995 if (copy_to_iter(channel_buf + pos, count, dst) != count)3996 return -EFAULT;3997 return 0;3998}3999 4000static int snd_hdsp_hw_silence(struct snd_pcm_substream *substream,4001 int channel, unsigned long pos,4002 unsigned long count)4003{4004 struct hdsp *hdsp = snd_pcm_substream_chip(substream);4005 signed char *channel_buf;4006 4007 channel_buf = hdsp_channel_buffer_location (hdsp, substream->pstr->stream, channel);4008 if (snd_BUG_ON(!channel_buf))4009 return -EIO;4010 memset(channel_buf + pos, 0, count);4011 return 0;4012}4013 4014static int snd_hdsp_reset(struct snd_pcm_substream *substream)4015{4016 struct snd_pcm_runtime *runtime = substream->runtime;4017 struct hdsp *hdsp = snd_pcm_substream_chip(substream);4018 struct snd_pcm_substream *other;4019 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)4020 other = hdsp->capture_substream;4021 else4022 other = hdsp->playback_substream;4023 if (hdsp->running)4024 runtime->status->hw_ptr = hdsp_hw_pointer(hdsp);4025 else4026 runtime->status->hw_ptr = 0;4027 if (other) {4028 struct snd_pcm_substream *s;4029 struct snd_pcm_runtime *oruntime = other->runtime;4030 snd_pcm_group_for_each_entry(s, substream) {4031 if (s == other) {4032 oruntime->status->hw_ptr = runtime->status->hw_ptr;4033 break;4034 }4035 }4036 }4037 return 0;4038}4039 4040static int snd_hdsp_hw_params(struct snd_pcm_substream *substream,4041 struct snd_pcm_hw_params *params)4042{4043 struct hdsp *hdsp = snd_pcm_substream_chip(substream);4044 int err;4045 pid_t this_pid;4046 pid_t other_pid;4047 4048 if (hdsp_check_for_iobox (hdsp))4049 return -EIO;4050 4051 if (hdsp_check_for_firmware(hdsp, 1))4052 return -EIO;4053 4054 spin_lock_irq(&hdsp->lock);4055 4056 if (substream->pstr->stream == SNDRV_PCM_STREAM_PLAYBACK) {4057 hdsp->control_register &= ~(HDSP_SPDIFProfessional | HDSP_SPDIFNonAudio | HDSP_SPDIFEmphasis);4058 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register |= hdsp->creg_spdif_stream);4059 this_pid = hdsp->playback_pid;4060 other_pid = hdsp->capture_pid;4061 } else {4062 this_pid = hdsp->capture_pid;4063 other_pid = hdsp->playback_pid;4064 }4065 4066 if ((other_pid > 0) && (this_pid != other_pid)) {4067 4068 /* The other stream is open, and not by the same4069 task as this one. Make sure that the parameters4070 that matter are the same.4071 */4072 4073 if (params_rate(params) != hdsp->system_sample_rate) {4074 spin_unlock_irq(&hdsp->lock);4075 _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_RATE);4076 return -EBUSY;4077 }4078 4079 if (params_period_size(params) != hdsp->period_bytes / 4) {4080 spin_unlock_irq(&hdsp->lock);4081 _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_PERIOD_SIZE);4082 return -EBUSY;4083 }4084 4085 /* We're fine. */4086 4087 spin_unlock_irq(&hdsp->lock);4088 return 0;4089 4090 } else {4091 spin_unlock_irq(&hdsp->lock);4092 }4093 4094 /* how to make sure that the rate matches an externally-set one ?4095 */4096 4097 spin_lock_irq(&hdsp->lock);4098 if (! hdsp->clock_source_locked) {4099 err = hdsp_set_rate(hdsp, params_rate(params), 0);4100 if (err < 0) {4101 spin_unlock_irq(&hdsp->lock);4102 _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_RATE);4103 return err;4104 }4105 }4106 spin_unlock_irq(&hdsp->lock);4107 4108 err = hdsp_set_interrupt_interval(hdsp, params_period_size(params));4109 if (err < 0) {4110 _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_PERIOD_SIZE);4111 return err;4112 }4113 4114 return 0;4115}4116 4117static int snd_hdsp_channel_info(struct snd_pcm_substream *substream,4118 struct snd_pcm_channel_info *info)4119{4120 struct hdsp *hdsp = snd_pcm_substream_chip(substream);4121 unsigned int channel = info->channel;4122 4123 if (snd_BUG_ON(channel >= hdsp->max_channels))4124 return -EINVAL;4125 channel = array_index_nospec(channel, hdsp->max_channels);4126 4127 if (hdsp->channel_map[channel] < 0)4128 return -EINVAL;4129 4130 info->offset = hdsp->channel_map[channel] * HDSP_CHANNEL_BUFFER_BYTES;4131 info->first = 0;4132 info->step = 32;4133 return 0;4134}4135 4136static int snd_hdsp_ioctl(struct snd_pcm_substream *substream,4137 unsigned int cmd, void *arg)4138{4139 switch (cmd) {4140 case SNDRV_PCM_IOCTL1_RESET:4141 return snd_hdsp_reset(substream);4142 case SNDRV_PCM_IOCTL1_CHANNEL_INFO:4143 return snd_hdsp_channel_info(substream, arg);4144 default:4145 break;4146 }4147 4148 return snd_pcm_lib_ioctl(substream, cmd, arg);4149}4150 4151static int snd_hdsp_trigger(struct snd_pcm_substream *substream, int cmd)4152{4153 struct hdsp *hdsp = snd_pcm_substream_chip(substream);4154 struct snd_pcm_substream *other;4155 int running;4156 4157 if (hdsp_check_for_iobox (hdsp))4158 return -EIO;4159 4160 if (hdsp_check_for_firmware(hdsp, 0)) /* no auto-loading in trigger */4161 return -EIO;4162 4163 spin_lock(&hdsp->lock);4164 running = hdsp->running;4165 switch (cmd) {4166 case SNDRV_PCM_TRIGGER_START:4167 running |= 1 << substream->stream;4168 break;4169 case SNDRV_PCM_TRIGGER_STOP:4170 running &= ~(1 << substream->stream);4171 break;4172 default:4173 snd_BUG();4174 spin_unlock(&hdsp->lock);4175 return -EINVAL;4176 }4177 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)4178 other = hdsp->capture_substream;4179 else4180 other = hdsp->playback_substream;4181 4182 if (other) {4183 struct snd_pcm_substream *s;4184 snd_pcm_group_for_each_entry(s, substream) {4185 if (s == other) {4186 snd_pcm_trigger_done(s, substream);4187 if (cmd == SNDRV_PCM_TRIGGER_START)4188 running |= 1 << s->stream;4189 else4190 running &= ~(1 << s->stream);4191 goto _ok;4192 }4193 }4194 if (cmd == SNDRV_PCM_TRIGGER_START) {4195 if (!(running & (1 << SNDRV_PCM_STREAM_PLAYBACK)) &&4196 substream->stream == SNDRV_PCM_STREAM_CAPTURE)4197 hdsp_silence_playback(hdsp);4198 } else {4199 if (running &&4200 substream->stream == SNDRV_PCM_STREAM_PLAYBACK)4201 hdsp_silence_playback(hdsp);4202 }4203 } else {4204 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)4205 hdsp_silence_playback(hdsp);4206 }4207 _ok:4208 snd_pcm_trigger_done(substream, substream);4209 if (!hdsp->running && running)4210 hdsp_start_audio(hdsp);4211 else if (hdsp->running && !running)4212 hdsp_stop_audio(hdsp);4213 hdsp->running = running;4214 spin_unlock(&hdsp->lock);4215 4216 return 0;4217}4218 4219static int snd_hdsp_prepare(struct snd_pcm_substream *substream)4220{4221 struct hdsp *hdsp = snd_pcm_substream_chip(substream);4222 int result = 0;4223 4224 if (hdsp_check_for_iobox (hdsp))4225 return -EIO;4226 4227 if (hdsp_check_for_firmware(hdsp, 1))4228 return -EIO;4229 4230 spin_lock_irq(&hdsp->lock);4231 if (!hdsp->running)4232 hdsp_reset_hw_pointer(hdsp);4233 spin_unlock_irq(&hdsp->lock);4234 return result;4235}4236 4237static const struct snd_pcm_hardware snd_hdsp_playback_subinfo =4238{4239 .info = (SNDRV_PCM_INFO_MMAP |4240 SNDRV_PCM_INFO_MMAP_VALID |4241 SNDRV_PCM_INFO_NONINTERLEAVED |4242 SNDRV_PCM_INFO_SYNC_START |4243 SNDRV_PCM_INFO_DOUBLE),4244#ifdef SNDRV_BIG_ENDIAN4245 .formats = SNDRV_PCM_FMTBIT_S32_BE,4246#else4247 .formats = SNDRV_PCM_FMTBIT_S32_LE,4248#endif4249 .rates = (SNDRV_PCM_RATE_32000 |4250 SNDRV_PCM_RATE_44100 |4251 SNDRV_PCM_RATE_48000 |4252 SNDRV_PCM_RATE_64000 |4253 SNDRV_PCM_RATE_88200 |4254 SNDRV_PCM_RATE_96000),4255 .rate_min = 32000,4256 .rate_max = 96000,4257 .channels_min = 6,4258 .channels_max = HDSP_MAX_CHANNELS,4259 .buffer_bytes_max = HDSP_CHANNEL_BUFFER_BYTES * HDSP_MAX_CHANNELS,4260 .period_bytes_min = (64 * 4) * 10,4261 .period_bytes_max = (8192 * 4) * HDSP_MAX_CHANNELS,4262 .periods_min = 2,4263 .periods_max = 2,4264 .fifo_size = 04265};4266 4267static const struct snd_pcm_hardware snd_hdsp_capture_subinfo =4268{4269 .info = (SNDRV_PCM_INFO_MMAP |4270 SNDRV_PCM_INFO_MMAP_VALID |4271 SNDRV_PCM_INFO_NONINTERLEAVED |4272 SNDRV_PCM_INFO_SYNC_START),4273#ifdef SNDRV_BIG_ENDIAN4274 .formats = SNDRV_PCM_FMTBIT_S32_BE,4275#else4276 .formats = SNDRV_PCM_FMTBIT_S32_LE,4277#endif4278 .rates = (SNDRV_PCM_RATE_32000 |4279 SNDRV_PCM_RATE_44100 |4280 SNDRV_PCM_RATE_48000 |4281 SNDRV_PCM_RATE_64000 |4282 SNDRV_PCM_RATE_88200 |4283 SNDRV_PCM_RATE_96000),4284 .rate_min = 32000,4285 .rate_max = 96000,4286 .channels_min = 5,4287 .channels_max = HDSP_MAX_CHANNELS,4288 .buffer_bytes_max = HDSP_CHANNEL_BUFFER_BYTES * HDSP_MAX_CHANNELS,4289 .period_bytes_min = (64 * 4) * 10,4290 .period_bytes_max = (8192 * 4) * HDSP_MAX_CHANNELS,4291 .periods_min = 2,4292 .periods_max = 2,4293 .fifo_size = 04294};4295 4296static const unsigned int hdsp_period_sizes[] = { 64, 128, 256, 512, 1024, 2048, 4096, 8192 };4297 4298static const struct snd_pcm_hw_constraint_list hdsp_hw_constraints_period_sizes = {4299 .count = ARRAY_SIZE(hdsp_period_sizes),4300 .list = hdsp_period_sizes,4301 .mask = 04302};4303 4304static int snd_hdsp_hw_rule_in_channels(struct snd_pcm_hw_params *params,4305 struct snd_pcm_hw_rule *rule)4306{4307 struct hdsp *hdsp = rule->private;4308 struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);4309 if (hdsp->io_type == H9632) {4310 unsigned int list[3];4311 list[0] = hdsp->qs_in_channels;4312 list[1] = hdsp->ds_in_channels;4313 list[2] = hdsp->ss_in_channels;4314 return snd_interval_list(c, 3, list, 0);4315 } else {4316 unsigned int list[2];4317 list[0] = hdsp->ds_in_channels;4318 list[1] = hdsp->ss_in_channels;4319 return snd_interval_list(c, 2, list, 0);4320 }4321}4322 4323static int snd_hdsp_hw_rule_out_channels(struct snd_pcm_hw_params *params,4324 struct snd_pcm_hw_rule *rule)4325{4326 unsigned int list[3];4327 struct hdsp *hdsp = rule->private;4328 struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);4329 if (hdsp->io_type == H9632) {4330 list[0] = hdsp->qs_out_channels;4331 list[1] = hdsp->ds_out_channels;4332 list[2] = hdsp->ss_out_channels;4333 return snd_interval_list(c, 3, list, 0);4334 } else {4335 list[0] = hdsp->ds_out_channels;4336 list[1] = hdsp->ss_out_channels;4337 }4338 return snd_interval_list(c, 2, list, 0);4339}4340 4341static int snd_hdsp_hw_rule_in_channels_rate(struct snd_pcm_hw_params *params,4342 struct snd_pcm_hw_rule *rule)4343{4344 struct hdsp *hdsp = rule->private;4345 struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);4346 struct snd_interval *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);4347 if (r->min > 96000 && hdsp->io_type == H9632) {4348 struct snd_interval t = {4349 .min = hdsp->qs_in_channels,4350 .max = hdsp->qs_in_channels,4351 .integer = 1,4352 };4353 return snd_interval_refine(c, &t);4354 } else if (r->min > 48000 && r->max <= 96000) {4355 struct snd_interval t = {4356 .min = hdsp->ds_in_channels,4357 .max = hdsp->ds_in_channels,4358 .integer = 1,4359 };4360 return snd_interval_refine(c, &t);4361 } else if (r->max < 64000) {4362 struct snd_interval t = {4363 .min = hdsp->ss_in_channels,4364 .max = hdsp->ss_in_channels,4365 .integer = 1,4366 };4367 return snd_interval_refine(c, &t);4368 }4369 return 0;4370}4371 4372static int snd_hdsp_hw_rule_out_channels_rate(struct snd_pcm_hw_params *params,4373 struct snd_pcm_hw_rule *rule)4374{4375 struct hdsp *hdsp = rule->private;4376 struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);4377 struct snd_interval *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);4378 if (r->min > 96000 && hdsp->io_type == H9632) {4379 struct snd_interval t = {4380 .min = hdsp->qs_out_channels,4381 .max = hdsp->qs_out_channels,4382 .integer = 1,4383 };4384 return snd_interval_refine(c, &t);4385 } else if (r->min > 48000 && r->max <= 96000) {4386 struct snd_interval t = {4387 .min = hdsp->ds_out_channels,4388 .max = hdsp->ds_out_channels,4389 .integer = 1,4390 };4391 return snd_interval_refine(c, &t);4392 } else if (r->max < 64000) {4393 struct snd_interval t = {4394 .min = hdsp->ss_out_channels,4395 .max = hdsp->ss_out_channels,4396 .integer = 1,4397 };4398 return snd_interval_refine(c, &t);4399 }4400 return 0;4401}4402 4403static int snd_hdsp_hw_rule_rate_out_channels(struct snd_pcm_hw_params *params,4404 struct snd_pcm_hw_rule *rule)4405{4406 struct hdsp *hdsp = rule->private;4407 struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);4408 struct snd_interval *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);4409 if (c->min >= hdsp->ss_out_channels) {4410 struct snd_interval t = {4411 .min = 32000,4412 .max = 48000,4413 .integer = 1,4414 };4415 return snd_interval_refine(r, &t);4416 } else if (c->max <= hdsp->qs_out_channels && hdsp->io_type == H9632) {4417 struct snd_interval t = {4418 .min = 128000,4419 .max = 192000,4420 .integer = 1,4421 };4422 return snd_interval_refine(r, &t);4423 } else if (c->max <= hdsp->ds_out_channels) {4424 struct snd_interval t = {4425 .min = 64000,4426 .max = 96000,4427 .integer = 1,4428 };4429 return snd_interval_refine(r, &t);4430 }4431 return 0;4432}4433 4434static int snd_hdsp_hw_rule_rate_in_channels(struct snd_pcm_hw_params *params,4435 struct snd_pcm_hw_rule *rule)4436{4437 struct hdsp *hdsp = rule->private;4438 struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);4439 struct snd_interval *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);4440 if (c->min >= hdsp->ss_in_channels) {4441 struct snd_interval t = {4442 .min = 32000,4443 .max = 48000,4444 .integer = 1,4445 };4446 return snd_interval_refine(r, &t);4447 } else if (c->max <= hdsp->qs_in_channels && hdsp->io_type == H9632) {4448 struct snd_interval t = {4449 .min = 128000,4450 .max = 192000,4451 .integer = 1,4452 };4453 return snd_interval_refine(r, &t);4454 } else if (c->max <= hdsp->ds_in_channels) {4455 struct snd_interval t = {4456 .min = 64000,4457 .max = 96000,4458 .integer = 1,4459 };4460 return snd_interval_refine(r, &t);4461 }4462 return 0;4463}4464 4465static int snd_hdsp_playback_open(struct snd_pcm_substream *substream)4466{4467 struct hdsp *hdsp = snd_pcm_substream_chip(substream);4468 struct snd_pcm_runtime *runtime = substream->runtime;4469 4470 if (hdsp_check_for_iobox (hdsp))4471 return -EIO;4472 4473 if (hdsp_check_for_firmware(hdsp, 1))4474 return -EIO;4475 4476 spin_lock_irq(&hdsp->lock);4477 4478 snd_pcm_set_sync(substream);4479 4480 runtime->hw = snd_hdsp_playback_subinfo;4481 snd_pcm_set_runtime_buffer(substream, &hdsp->playback_dma_buf);4482 4483 hdsp->playback_pid = current->pid;4484 hdsp->playback_substream = substream;4485 4486 spin_unlock_irq(&hdsp->lock);4487 4488 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);4489 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE, &hdsp_hw_constraints_period_sizes);4490 if (hdsp->clock_source_locked) {4491 runtime->hw.rate_min = runtime->hw.rate_max = hdsp->system_sample_rate;4492 } else if (hdsp->io_type == H9632) {4493 runtime->hw.rate_max = 192000;4494 runtime->hw.rates |= (SNDRV_PCM_RATE_128000 |4495 SNDRV_PCM_RATE_176400 |4496 SNDRV_PCM_RATE_192000);4497 }4498 if (hdsp->io_type == H9632) {4499 runtime->hw.channels_min = hdsp->qs_out_channels;4500 runtime->hw.channels_max = hdsp->ss_out_channels;4501 }4502 4503 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,4504 snd_hdsp_hw_rule_out_channels, hdsp,4505 SNDRV_PCM_HW_PARAM_CHANNELS, -1);4506 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,4507 snd_hdsp_hw_rule_out_channels_rate, hdsp,4508 SNDRV_PCM_HW_PARAM_RATE, -1);4509 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,4510 snd_hdsp_hw_rule_rate_out_channels, hdsp,4511 SNDRV_PCM_HW_PARAM_CHANNELS, -1);4512 4513 if (RPM != hdsp->io_type) {4514 hdsp->creg_spdif_stream = hdsp->creg_spdif;4515 hdsp->spdif_ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;4516 snd_ctl_notify(hdsp->card, SNDRV_CTL_EVENT_MASK_VALUE |4517 SNDRV_CTL_EVENT_MASK_INFO, &hdsp->spdif_ctl->id);4518 }4519 return 0;4520}4521 4522static int snd_hdsp_playback_release(struct snd_pcm_substream *substream)4523{4524 struct hdsp *hdsp = snd_pcm_substream_chip(substream);4525 4526 spin_lock_irq(&hdsp->lock);4527 4528 hdsp->playback_pid = -1;4529 hdsp->playback_substream = NULL;4530 4531 spin_unlock_irq(&hdsp->lock);4532 4533 if (RPM != hdsp->io_type) {4534 hdsp->spdif_ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;4535 snd_ctl_notify(hdsp->card, SNDRV_CTL_EVENT_MASK_VALUE |4536 SNDRV_CTL_EVENT_MASK_INFO, &hdsp->spdif_ctl->id);4537 }4538 return 0;4539}4540 4541 4542static int snd_hdsp_capture_open(struct snd_pcm_substream *substream)4543{4544 struct hdsp *hdsp = snd_pcm_substream_chip(substream);4545 struct snd_pcm_runtime *runtime = substream->runtime;4546 4547 if (hdsp_check_for_iobox (hdsp))4548 return -EIO;4549 4550 if (hdsp_check_for_firmware(hdsp, 1))4551 return -EIO;4552 4553 spin_lock_irq(&hdsp->lock);4554 4555 snd_pcm_set_sync(substream);4556 4557 runtime->hw = snd_hdsp_capture_subinfo;4558 snd_pcm_set_runtime_buffer(substream, &hdsp->capture_dma_buf);4559 4560 hdsp->capture_pid = current->pid;4561 hdsp->capture_substream = substream;4562 4563 spin_unlock_irq(&hdsp->lock);4564 4565 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);4566 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE, &hdsp_hw_constraints_period_sizes);4567 if (hdsp->io_type == H9632) {4568 runtime->hw.channels_min = hdsp->qs_in_channels;4569 runtime->hw.channels_max = hdsp->ss_in_channels;4570 runtime->hw.rate_max = 192000;4571 runtime->hw.rates |= (SNDRV_PCM_RATE_128000 |4572 SNDRV_PCM_RATE_176400 |4573 SNDRV_PCM_RATE_192000);4574 }4575 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,4576 snd_hdsp_hw_rule_in_channels, hdsp,4577 SNDRV_PCM_HW_PARAM_CHANNELS, -1);4578 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,4579 snd_hdsp_hw_rule_in_channels_rate, hdsp,4580 SNDRV_PCM_HW_PARAM_RATE, -1);4581 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,4582 snd_hdsp_hw_rule_rate_in_channels, hdsp,4583 SNDRV_PCM_HW_PARAM_CHANNELS, -1);4584 return 0;4585}4586 4587static int snd_hdsp_capture_release(struct snd_pcm_substream *substream)4588{4589 struct hdsp *hdsp = snd_pcm_substream_chip(substream);4590 4591 spin_lock_irq(&hdsp->lock);4592 4593 hdsp->capture_pid = -1;4594 hdsp->capture_substream = NULL;4595 4596 spin_unlock_irq(&hdsp->lock);4597 return 0;4598}4599 4600/* helper functions for copying meter values */4601static inline int copy_u32_le(void __user *dest, void __iomem *src)4602{4603 u32 val = readl(src);4604 return copy_to_user(dest, &val, 4);4605}4606 4607static inline int copy_u64_le(void __user *dest, void __iomem *src_low, void __iomem *src_high)4608{4609 u32 rms_low, rms_high;4610 u64 rms;4611 rms_low = readl(src_low);4612 rms_high = readl(src_high);4613 rms = ((u64)rms_high << 32) | rms_low;4614 return copy_to_user(dest, &rms, 8);4615}4616 4617static inline int copy_u48_le(void __user *dest, void __iomem *src_low, void __iomem *src_high)4618{4619 u32 rms_low, rms_high;4620 u64 rms;4621 rms_low = readl(src_low) & 0xffffff00;4622 rms_high = readl(src_high) & 0xffffff00;4623 rms = ((u64)rms_high << 32) | rms_low;4624 return copy_to_user(dest, &rms, 8);4625}4626 4627static int hdsp_9652_get_peak(struct hdsp *hdsp, struct hdsp_peak_rms __user *peak_rms)4628{4629 int doublespeed = 0;4630 int i, j, channels, ofs;4631 4632 if (hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DoubleSpeedStatus)4633 doublespeed = 1;4634 channels = doublespeed ? 14 : 26;4635 for (i = 0, j = 0; i < 26; ++i) {4636 if (doublespeed && (i & 4))4637 continue;4638 ofs = HDSP_9652_peakBase - j * 4;4639 if (copy_u32_le(&peak_rms->input_peaks[i], hdsp->iobase + ofs))4640 return -EFAULT;4641 ofs -= channels * 4;4642 if (copy_u32_le(&peak_rms->playback_peaks[i], hdsp->iobase + ofs))4643 return -EFAULT;4644 ofs -= channels * 4;4645 if (copy_u32_le(&peak_rms->output_peaks[i], hdsp->iobase + ofs))4646 return -EFAULT;4647 ofs = HDSP_9652_rmsBase + j * 8;4648 if (copy_u48_le(&peak_rms->input_rms[i], hdsp->iobase + ofs,4649 hdsp->iobase + ofs + 4))4650 return -EFAULT;4651 ofs += channels * 8;4652 if (copy_u48_le(&peak_rms->playback_rms[i], hdsp->iobase + ofs,4653 hdsp->iobase + ofs + 4))4654 return -EFAULT;4655 ofs += channels * 8;4656 if (copy_u48_le(&peak_rms->output_rms[i], hdsp->iobase + ofs,4657 hdsp->iobase + ofs + 4))4658 return -EFAULT;4659 j++;4660 }4661 return 0;4662}4663 4664static int hdsp_9632_get_peak(struct hdsp *hdsp, struct hdsp_peak_rms __user *peak_rms)4665{4666 int i, j;4667 struct hdsp_9632_meters __iomem *m;4668 int doublespeed = 0;4669 4670 if (hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DoubleSpeedStatus)4671 doublespeed = 1;4672 m = (struct hdsp_9632_meters __iomem *)(hdsp->iobase+HDSP_9632_metersBase);4673 for (i = 0, j = 0; i < 16; ++i, ++j) {4674 if (copy_u32_le(&peak_rms->input_peaks[i], &m->input_peak[j]))4675 return -EFAULT;4676 if (copy_u32_le(&peak_rms->playback_peaks[i], &m->playback_peak[j]))4677 return -EFAULT;4678 if (copy_u32_le(&peak_rms->output_peaks[i], &m->output_peak[j]))4679 return -EFAULT;4680 if (copy_u64_le(&peak_rms->input_rms[i], &m->input_rms_low[j],4681 &m->input_rms_high[j]))4682 return -EFAULT;4683 if (copy_u64_le(&peak_rms->playback_rms[i], &m->playback_rms_low[j],4684 &m->playback_rms_high[j]))4685 return -EFAULT;4686 if (copy_u64_le(&peak_rms->output_rms[i], &m->output_rms_low[j],4687 &m->output_rms_high[j]))4688 return -EFAULT;4689 if (doublespeed && i == 3) i += 4;4690 }4691 return 0;4692}4693 4694static int hdsp_get_peak(struct hdsp *hdsp, struct hdsp_peak_rms __user *peak_rms)4695{4696 int i;4697 4698 for (i = 0; i < 26; i++) {4699 if (copy_u32_le(&peak_rms->playback_peaks[i],4700 hdsp->iobase + HDSP_playbackPeakLevel + i * 4))4701 return -EFAULT;4702 if (copy_u32_le(&peak_rms->input_peaks[i],4703 hdsp->iobase + HDSP_inputPeakLevel + i * 4))4704 return -EFAULT;4705 }4706 for (i = 0; i < 28; i++) {4707 if (copy_u32_le(&peak_rms->output_peaks[i],4708 hdsp->iobase + HDSP_outputPeakLevel + i * 4))4709 return -EFAULT;4710 }4711 for (i = 0; i < 26; ++i) {4712 if (copy_u64_le(&peak_rms->playback_rms[i],4713 hdsp->iobase + HDSP_playbackRmsLevel + i * 8 + 4,4714 hdsp->iobase + HDSP_playbackRmsLevel + i * 8))4715 return -EFAULT;4716 if (copy_u64_le(&peak_rms->input_rms[i],4717 hdsp->iobase + HDSP_inputRmsLevel + i * 8 + 4,4718 hdsp->iobase + HDSP_inputRmsLevel + i * 8))4719 return -EFAULT;4720 }4721 return 0;4722}4723 4724static int snd_hdsp_hwdep_ioctl(struct snd_hwdep *hw, struct file *file, unsigned int cmd, unsigned long arg)4725{4726 struct hdsp *hdsp = hw->private_data;4727 void __user *argp = (void __user *)arg;4728 int err;4729 4730 switch (cmd) {4731 case SNDRV_HDSP_IOCTL_GET_PEAK_RMS: {4732 struct hdsp_peak_rms __user *peak_rms = (struct hdsp_peak_rms __user *)arg;4733 4734 err = hdsp_check_for_iobox(hdsp);4735 if (err < 0)4736 return err;4737 4738 err = hdsp_check_for_firmware(hdsp, 1);4739 if (err < 0)4740 return err;4741 4742 if (!(hdsp->state & HDSP_FirmwareLoaded)) {4743 dev_err(hdsp->card->dev,4744 "firmware needs to be uploaded to the card.\n");4745 return -EINVAL;4746 }4747 4748 switch (hdsp->io_type) {4749 case H9652:4750 return hdsp_9652_get_peak(hdsp, peak_rms);4751 case H9632:4752 return hdsp_9632_get_peak(hdsp, peak_rms);4753 default:4754 return hdsp_get_peak(hdsp, peak_rms);4755 }4756 }4757 case SNDRV_HDSP_IOCTL_GET_CONFIG_INFO: {4758 struct hdsp_config_info info;4759 unsigned long flags;4760 int i;4761 4762 err = hdsp_check_for_iobox(hdsp);4763 if (err < 0)4764 return err;4765 4766 err = hdsp_check_for_firmware(hdsp, 1);4767 if (err < 0)4768 return err;4769 4770 memset(&info, 0, sizeof(info));4771 spin_lock_irqsave(&hdsp->lock, flags);4772 info.pref_sync_ref = (unsigned char)hdsp_pref_sync_ref(hdsp);4773 info.wordclock_sync_check = (unsigned char)hdsp_wc_sync_check(hdsp);4774 if (hdsp->io_type != H9632)4775 info.adatsync_sync_check = (unsigned char)hdsp_adatsync_sync_check(hdsp);4776 info.spdif_sync_check = (unsigned char)hdsp_spdif_sync_check(hdsp);4777 for (i = 0; i < ((hdsp->io_type != Multiface && hdsp->io_type != RPM && hdsp->io_type != H9632) ? 3 : 1); ++i)4778 info.adat_sync_check[i] = (unsigned char)hdsp_adat_sync_check(hdsp, i);4779 info.spdif_in = (unsigned char)hdsp_spdif_in(hdsp);4780 info.spdif_out = (unsigned char)hdsp_toggle_setting(hdsp,4781 HDSP_SPDIFOpticalOut);4782 info.spdif_professional = (unsigned char)4783 hdsp_toggle_setting(hdsp, HDSP_SPDIFProfessional);4784 info.spdif_emphasis = (unsigned char)4785 hdsp_toggle_setting(hdsp, HDSP_SPDIFEmphasis);4786 info.spdif_nonaudio = (unsigned char)4787 hdsp_toggle_setting(hdsp, HDSP_SPDIFNonAudio);4788 info.spdif_sample_rate = hdsp_spdif_sample_rate(hdsp);4789 info.system_sample_rate = hdsp->system_sample_rate;4790 info.autosync_sample_rate = hdsp_external_sample_rate(hdsp);4791 info.system_clock_mode = (unsigned char)hdsp_system_clock_mode(hdsp);4792 info.clock_source = (unsigned char)hdsp_clock_source(hdsp);4793 info.autosync_ref = (unsigned char)hdsp_autosync_ref(hdsp);4794 info.line_out = (unsigned char)4795 hdsp_toggle_setting(hdsp, HDSP_LineOut);4796 if (hdsp->io_type == H9632) {4797 info.da_gain = (unsigned char)hdsp_da_gain(hdsp);4798 info.ad_gain = (unsigned char)hdsp_ad_gain(hdsp);4799 info.phone_gain = (unsigned char)hdsp_phone_gain(hdsp);4800 info.xlr_breakout_cable =4801 (unsigned char)hdsp_toggle_setting(hdsp,4802 HDSP_XLRBreakoutCable);4803 4804 } else if (hdsp->io_type == RPM) {4805 info.da_gain = (unsigned char) hdsp_rpm_input12(hdsp);4806 info.ad_gain = (unsigned char) hdsp_rpm_input34(hdsp);4807 }4808 if (hdsp->io_type == H9632 || hdsp->io_type == H9652)4809 info.analog_extension_board =4810 (unsigned char)hdsp_toggle_setting(hdsp,4811 HDSP_AnalogExtensionBoard);4812 spin_unlock_irqrestore(&hdsp->lock, flags);4813 if (copy_to_user(argp, &info, sizeof(info)))4814 return -EFAULT;4815 break;4816 }4817 case SNDRV_HDSP_IOCTL_GET_9632_AEB: {4818 struct hdsp_9632_aeb h9632_aeb;4819 4820 if (hdsp->io_type != H9632) return -EINVAL;4821 h9632_aeb.aebi = hdsp->ss_in_channels - H9632_SS_CHANNELS;4822 h9632_aeb.aebo = hdsp->ss_out_channels - H9632_SS_CHANNELS;4823 if (copy_to_user(argp, &h9632_aeb, sizeof(h9632_aeb)))4824 return -EFAULT;4825 break;4826 }4827 case SNDRV_HDSP_IOCTL_GET_VERSION: {4828 struct hdsp_version hdsp_version;4829 int err;4830 4831 if (hdsp->io_type == H9652 || hdsp->io_type == H9632) return -EINVAL;4832 if (hdsp->io_type == Undefined) {4833 err = hdsp_get_iobox_version(hdsp);4834 if (err < 0)4835 return err;4836 }4837 memset(&hdsp_version, 0, sizeof(hdsp_version));4838 hdsp_version.io_type = hdsp->io_type;4839 hdsp_version.firmware_rev = hdsp->firmware_rev;4840 if (copy_to_user(argp, &hdsp_version, sizeof(hdsp_version)))4841 return -EFAULT;4842 break;4843 }4844 case SNDRV_HDSP_IOCTL_UPLOAD_FIRMWARE: {4845 struct hdsp_firmware firmware;4846 u32 __user *firmware_data;4847 int err;4848 4849 if (hdsp->io_type == H9652 || hdsp->io_type == H9632) return -EINVAL;4850 /* SNDRV_HDSP_IOCTL_GET_VERSION must have been called */4851 if (hdsp->io_type == Undefined) return -EINVAL;4852 4853 if (hdsp->state & (HDSP_FirmwareCached | HDSP_FirmwareLoaded))4854 return -EBUSY;4855 4856 dev_info(hdsp->card->dev,4857 "initializing firmware upload\n");4858 if (copy_from_user(&firmware, argp, sizeof(firmware)))4859 return -EFAULT;4860 firmware_data = (u32 __user *)firmware.firmware_data;4861 4862 if (hdsp_check_for_iobox (hdsp))4863 return -EIO;4864 4865 if (!hdsp->fw_uploaded) {4866 hdsp->fw_uploaded = vmalloc(HDSP_FIRMWARE_SIZE);4867 if (!hdsp->fw_uploaded)4868 return -ENOMEM;4869 }4870 4871 if (copy_from_user(hdsp->fw_uploaded, firmware_data,4872 HDSP_FIRMWARE_SIZE)) {4873 vfree(hdsp->fw_uploaded);4874 hdsp->fw_uploaded = NULL;4875 return -EFAULT;4876 }4877 4878 hdsp->state |= HDSP_FirmwareCached;4879 4880 err = snd_hdsp_load_firmware_from_cache(hdsp);4881 if (err < 0)4882 return err;4883 4884 if (!(hdsp->state & HDSP_InitializationComplete)) {4885 err = snd_hdsp_enable_io(hdsp);4886 if (err < 0)4887 return err;4888 4889 snd_hdsp_initialize_channels(hdsp);4890 snd_hdsp_initialize_midi_flush(hdsp);4891 4892 err = snd_hdsp_create_alsa_devices(hdsp->card, hdsp);4893 if (err < 0) {4894 dev_err(hdsp->card->dev,4895 "error creating alsa devices\n");4896 return err;4897 }4898 }4899 break;4900 }4901 case SNDRV_HDSP_IOCTL_GET_MIXER: {4902 struct hdsp_mixer __user *mixer = (struct hdsp_mixer __user *)argp;4903 if (copy_to_user(mixer->matrix, hdsp->mixer_matrix, sizeof(unsigned short)*HDSP_MATRIX_MIXER_SIZE))4904 return -EFAULT;4905 break;4906 }4907 default:4908 return -EINVAL;4909 }4910 return 0;4911}4912 4913static const struct snd_pcm_ops snd_hdsp_playback_ops = {4914 .open = snd_hdsp_playback_open,4915 .close = snd_hdsp_playback_release,4916 .ioctl = snd_hdsp_ioctl,4917 .hw_params = snd_hdsp_hw_params,4918 .prepare = snd_hdsp_prepare,4919 .trigger = snd_hdsp_trigger,4920 .pointer = snd_hdsp_hw_pointer,4921 .copy = snd_hdsp_playback_copy,4922 .fill_silence = snd_hdsp_hw_silence,4923};4924 4925static const struct snd_pcm_ops snd_hdsp_capture_ops = {4926 .open = snd_hdsp_capture_open,4927 .close = snd_hdsp_capture_release,4928 .ioctl = snd_hdsp_ioctl,4929 .hw_params = snd_hdsp_hw_params,4930 .prepare = snd_hdsp_prepare,4931 .trigger = snd_hdsp_trigger,4932 .pointer = snd_hdsp_hw_pointer,4933 .copy = snd_hdsp_capture_copy,4934};4935 4936static int snd_hdsp_create_hwdep(struct snd_card *card, struct hdsp *hdsp)4937{4938 struct snd_hwdep *hw;4939 int err;4940 4941 err = snd_hwdep_new(card, "HDSP hwdep", 0, &hw);4942 if (err < 0)4943 return err;4944 4945 hdsp->hwdep = hw;4946 hw->private_data = hdsp;4947 strcpy(hw->name, "HDSP hwdep interface");4948 4949 hw->ops.ioctl = snd_hdsp_hwdep_ioctl;4950 hw->ops.ioctl_compat = snd_hdsp_hwdep_ioctl;4951 4952 return 0;4953}4954 4955static int snd_hdsp_create_pcm(struct snd_card *card, struct hdsp *hdsp)4956{4957 struct snd_pcm *pcm;4958 int err;4959 4960 err = snd_pcm_new(card, hdsp->card_name, 0, 1, 1, &pcm);4961 if (err < 0)4962 return err;4963 4964 hdsp->pcm = pcm;4965 pcm->private_data = hdsp;4966 strcpy(pcm->name, hdsp->card_name);4967 4968 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_hdsp_playback_ops);4969 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_hdsp_capture_ops);4970 4971 pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX;4972 4973 return 0;4974}4975 4976static void snd_hdsp_9652_enable_mixer (struct hdsp *hdsp)4977{4978 hdsp->control2_register |= HDSP_9652_ENABLE_MIXER;4979 hdsp_write (hdsp, HDSP_control2Reg, hdsp->control2_register);4980}4981 4982static int snd_hdsp_enable_io (struct hdsp *hdsp)4983{4984 int i;4985 4986 if (hdsp_fifo_wait (hdsp, 0, 100)) {4987 dev_err(hdsp->card->dev,4988 "enable_io fifo_wait failed\n");4989 return -EIO;4990 }4991 4992 for (i = 0; i < hdsp->max_channels; ++i) {4993 hdsp_write (hdsp, HDSP_inputEnable + (4 * i), 1);4994 hdsp_write (hdsp, HDSP_outputEnable + (4 * i), 1);4995 }4996 4997 return 0;4998}4999 5000static void snd_hdsp_initialize_channels(struct hdsp *hdsp)5001{5002 int status, aebi_channels, aebo_channels, i;5003 5004 switch (hdsp->io_type) {5005 case Digiface:5006 hdsp->card_name = "RME Hammerfall DSP + Digiface";5007 hdsp->ss_in_channels = hdsp->ss_out_channels = DIGIFACE_SS_CHANNELS;5008 hdsp->ds_in_channels = hdsp->ds_out_channels = DIGIFACE_DS_CHANNELS;5009 break;5010 5011 case H9652:5012 hdsp->card_name = "RME Hammerfall HDSP 9652";5013 hdsp->ss_in_channels = hdsp->ss_out_channels = H9652_SS_CHANNELS;5014 hdsp->ds_in_channels = hdsp->ds_out_channels = H9652_DS_CHANNELS;5015 break;5016 5017 case H9632:5018 status = hdsp_read(hdsp, HDSP_statusRegister);5019 /* HDSP_AEBx bits are low when AEB are connected */5020 aebi_channels = (status & HDSP_AEBI) ? 0 : 4;5021 aebo_channels = (status & HDSP_AEBO) ? 0 : 4;5022 hdsp->card_name = "RME Hammerfall HDSP 9632";5023 hdsp->ss_in_channels = H9632_SS_CHANNELS+aebi_channels;5024 hdsp->ds_in_channels = H9632_DS_CHANNELS+aebi_channels;5025 hdsp->qs_in_channels = H9632_QS_CHANNELS+aebi_channels;5026 hdsp->ss_out_channels = H9632_SS_CHANNELS+aebo_channels;5027 hdsp->ds_out_channels = H9632_DS_CHANNELS+aebo_channels;5028 hdsp->qs_out_channels = H9632_QS_CHANNELS+aebo_channels;5029 /* Disable loopback of output channels, as the set function5030 * only sets on a change we fake all bits (channels) as enabled.5031 */5032 hdsp->io_loopback = 0xffffffff;5033 for (i = 0; i < hdsp->max_channels; ++i)5034 hdsp_loopback_set(hdsp, i, false);5035 break;5036 5037 case Multiface:5038 hdsp->card_name = "RME Hammerfall DSP + Multiface";5039 hdsp->ss_in_channels = hdsp->ss_out_channels = MULTIFACE_SS_CHANNELS;5040 hdsp->ds_in_channels = hdsp->ds_out_channels = MULTIFACE_DS_CHANNELS;5041 break;5042 5043 case RPM:5044 hdsp->card_name = "RME Hammerfall DSP + RPM";5045 hdsp->ss_in_channels = RPM_CHANNELS-1;5046 hdsp->ss_out_channels = RPM_CHANNELS;5047 hdsp->ds_in_channels = RPM_CHANNELS-1;5048 hdsp->ds_out_channels = RPM_CHANNELS;5049 break;5050 5051 default:5052 /* should never get here */5053 break;5054 }5055}5056 5057static void snd_hdsp_initialize_midi_flush (struct hdsp *hdsp)5058{5059 snd_hdsp_flush_midi_input (hdsp, 0);5060 snd_hdsp_flush_midi_input (hdsp, 1);5061}5062 5063static int snd_hdsp_create_alsa_devices(struct snd_card *card, struct hdsp *hdsp)5064{5065 int err;5066 5067 err = snd_hdsp_create_pcm(card, hdsp);5068 if (err < 0) {5069 dev_err(card->dev,5070 "Error creating pcm interface\n");5071 return err;5072 }5073 5074 5075 err = snd_hdsp_create_midi(card, hdsp, 0);5076 if (err < 0) {5077 dev_err(card->dev,5078 "Error creating first midi interface\n");5079 return err;5080 }5081 5082 if (hdsp->io_type == Digiface || hdsp->io_type == H9652) {5083 err = snd_hdsp_create_midi(card, hdsp, 1);5084 if (err < 0) {5085 dev_err(card->dev,5086 "Error creating second midi interface\n");5087 return err;5088 }5089 }5090 5091 err = snd_hdsp_create_controls(card, hdsp);5092 if (err < 0) {5093 dev_err(card->dev,5094 "Error creating ctl interface\n");5095 return err;5096 }5097 5098 snd_hdsp_proc_init(hdsp);5099 5100 hdsp->system_sample_rate = -1;5101 hdsp->playback_pid = -1;5102 hdsp->capture_pid = -1;5103 hdsp->capture_substream = NULL;5104 hdsp->playback_substream = NULL;5105 5106 err = snd_hdsp_set_defaults(hdsp);5107 if (err < 0) {5108 dev_err(card->dev,5109 "Error setting default values\n");5110 return err;5111 }5112 5113 if (!(hdsp->state & HDSP_InitializationComplete)) {5114 strcpy(card->shortname, "Hammerfall DSP");5115 sprintf(card->longname, "%s at 0x%lx, irq %d", hdsp->card_name,5116 hdsp->port, hdsp->irq);5117 5118 err = snd_card_register(card);5119 if (err < 0) {5120 dev_err(card->dev,5121 "error registering card\n");5122 return err;5123 }5124 hdsp->state |= HDSP_InitializationComplete;5125 }5126 5127 return 0;5128}5129 5130/* load firmware via hotplug fw loader */5131static int hdsp_request_fw_loader(struct hdsp *hdsp)5132{5133 const char *fwfile;5134 const struct firmware *fw;5135 int err;5136 5137 if (hdsp->io_type == H9652 || hdsp->io_type == H9632)5138 return 0;5139 if (hdsp->io_type == Undefined) {5140 err = hdsp_get_iobox_version(hdsp);5141 if (err < 0)5142 return err;5143 if (hdsp->io_type == H9652 || hdsp->io_type == H9632)5144 return 0;5145 }5146 5147 /* caution: max length of firmware filename is 30! */5148 switch (hdsp->io_type) {5149 case RPM:5150 fwfile = "rpm_firmware.bin";5151 break;5152 case Multiface:5153 if (hdsp->firmware_rev == 0xa)5154 fwfile = "multiface_firmware.bin";5155 else5156 fwfile = "multiface_firmware_rev11.bin";5157 break;5158 case Digiface:5159 if (hdsp->firmware_rev == 0xa)5160 fwfile = "digiface_firmware.bin";5161 else5162 fwfile = "digiface_firmware_rev11.bin";5163 break;5164 default:5165 dev_err(hdsp->card->dev,5166 "invalid io_type %d\n", hdsp->io_type);5167 return -EINVAL;5168 }5169 5170 if (request_firmware(&fw, fwfile, &hdsp->pci->dev)) {5171 dev_err(hdsp->card->dev,5172 "cannot load firmware %s\n", fwfile);5173 return -ENOENT;5174 }5175 if (fw->size < HDSP_FIRMWARE_SIZE) {5176 dev_err(hdsp->card->dev,5177 "too short firmware size %d (expected %d)\n",5178 (int)fw->size, HDSP_FIRMWARE_SIZE);5179 release_firmware(fw);5180 return -EINVAL;5181 }5182 5183 hdsp->firmware = fw;5184 5185 hdsp->state |= HDSP_FirmwareCached;5186 5187 err = snd_hdsp_load_firmware_from_cache(hdsp);5188 if (err < 0)5189 return err;5190 5191 if (!(hdsp->state & HDSP_InitializationComplete)) {5192 err = snd_hdsp_enable_io(hdsp);5193 if (err < 0)5194 return err;5195 5196 err = snd_hdsp_create_hwdep(hdsp->card, hdsp);5197 if (err < 0) {5198 dev_err(hdsp->card->dev,5199 "error creating hwdep device\n");5200 return err;5201 }5202 snd_hdsp_initialize_channels(hdsp);5203 snd_hdsp_initialize_midi_flush(hdsp);5204 err = snd_hdsp_create_alsa_devices(hdsp->card, hdsp);5205 if (err < 0) {5206 dev_err(hdsp->card->dev,5207 "error creating alsa devices\n");5208 return err;5209 }5210 }5211 return 0;5212}5213 5214static int snd_hdsp_create(struct snd_card *card,5215 struct hdsp *hdsp)5216{5217 struct pci_dev *pci = hdsp->pci;5218 int err;5219 int is_9652 = 0;5220 int is_9632 = 0;5221 5222 hdsp->irq = -1;5223 hdsp->state = 0;5224 hdsp->midi[0].rmidi = NULL;5225 hdsp->midi[1].rmidi = NULL;5226 hdsp->midi[0].input = NULL;5227 hdsp->midi[1].input = NULL;5228 hdsp->midi[0].output = NULL;5229 hdsp->midi[1].output = NULL;5230 hdsp->midi[0].pending = 0;5231 hdsp->midi[1].pending = 0;5232 spin_lock_init(&hdsp->midi[0].lock);5233 spin_lock_init(&hdsp->midi[1].lock);5234 hdsp->iobase = NULL;5235 hdsp->control_register = 0;5236 hdsp->control2_register = 0;5237 hdsp->io_type = Undefined;5238 hdsp->max_channels = 26;5239 5240 hdsp->card = card;5241 5242 spin_lock_init(&hdsp->lock);5243 5244 INIT_WORK(&hdsp->midi_work, hdsp_midi_work);5245 5246 pci_read_config_word(hdsp->pci, PCI_CLASS_REVISION, &hdsp->firmware_rev);5247 hdsp->firmware_rev &= 0xff;5248 5249 /* From Martin Bjoernsen :5250 "It is important that the card's latency timer register in5251 the PCI configuration space is set to a value much larger5252 than 0 by the computer's BIOS or the driver.5253 The windows driver always sets this 8 bit register [...]5254 to its maximum 255 to avoid problems with some computers."5255 */5256 pci_write_config_byte(hdsp->pci, PCI_LATENCY_TIMER, 0xFF);5257 5258 strcpy(card->driver, "H-DSP");5259 strcpy(card->mixername, "Xilinx FPGA");5260 5261 if (hdsp->firmware_rev < 0xa)5262 return -ENODEV;5263 else if (hdsp->firmware_rev < 0x64)5264 hdsp->card_name = "RME Hammerfall DSP";5265 else if (hdsp->firmware_rev < 0x96) {5266 hdsp->card_name = "RME HDSP 9652";5267 is_9652 = 1;5268 } else {5269 hdsp->card_name = "RME HDSP 9632";5270 hdsp->max_channels = 16;5271 is_9632 = 1;5272 }5273 5274 err = pcim_enable_device(pci);5275 if (err < 0)5276 return err;5277 5278 pci_set_master(hdsp->pci);5279 5280 err = pci_request_regions(pci, "hdsp");5281 if (err < 0)5282 return err;5283 hdsp->port = pci_resource_start(pci, 0);5284 hdsp->iobase = devm_ioremap(&pci->dev, hdsp->port, HDSP_IO_EXTENT);5285 if (!hdsp->iobase) {5286 dev_err(hdsp->card->dev, "unable to remap region 0x%lx-0x%lx\n",5287 hdsp->port, hdsp->port + HDSP_IO_EXTENT - 1);5288 return -EBUSY;5289 }5290 5291 if (devm_request_irq(&pci->dev, pci->irq, snd_hdsp_interrupt,5292 IRQF_SHARED, KBUILD_MODNAME, hdsp)) {5293 dev_err(hdsp->card->dev, "unable to use IRQ %d\n", pci->irq);5294 return -EBUSY;5295 }5296 5297 hdsp->irq = pci->irq;5298 card->sync_irq = hdsp->irq;5299 hdsp->precise_ptr = 0;5300 hdsp->use_midi_work = 1;5301 hdsp->dds_value = 0;5302 5303 err = snd_hdsp_initialize_memory(hdsp);5304 if (err < 0)5305 return err;5306 5307 if (!is_9652 && !is_9632) {5308 /* we wait a maximum of 10 seconds to let freshly5309 * inserted cardbus cards do their hardware init */5310 err = hdsp_wait_for_iobox(hdsp, 1000, 10);5311 5312 if (err < 0)5313 return err;5314 5315 if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {5316 err = hdsp_request_fw_loader(hdsp);5317 if (err < 0)5318 /* we don't fail as this can happen5319 if userspace is not ready for5320 firmware upload5321 */5322 dev_err(hdsp->card->dev,5323 "couldn't get firmware from userspace. try using hdsploader\n");5324 else5325 /* init is complete, we return */5326 return 0;5327 /* we defer initialization */5328 dev_info(hdsp->card->dev,5329 "card initialization pending : waiting for firmware\n");5330 err = snd_hdsp_create_hwdep(card, hdsp);5331 if (err < 0)5332 return err;5333 return 0;5334 } else {5335 dev_info(hdsp->card->dev,5336 "Firmware already present, initializing card.\n");5337 if (hdsp_read(hdsp, HDSP_status2Register) & HDSP_version2)5338 hdsp->io_type = RPM;5339 else if (hdsp_read(hdsp, HDSP_status2Register) & HDSP_version1)5340 hdsp->io_type = Multiface;5341 else5342 hdsp->io_type = Digiface;5343 }5344 }5345 5346 err = snd_hdsp_enable_io(hdsp);5347 if (err)5348 return err;5349 5350 if (is_9652)5351 hdsp->io_type = H9652;5352 5353 if (is_9632)5354 hdsp->io_type = H9632;5355 5356 err = snd_hdsp_create_hwdep(card, hdsp);5357 if (err < 0)5358 return err;5359 5360 snd_hdsp_initialize_channels(hdsp);5361 snd_hdsp_initialize_midi_flush(hdsp);5362 5363 hdsp->state |= HDSP_FirmwareLoaded;5364 5365 err = snd_hdsp_create_alsa_devices(card, hdsp);5366 if (err < 0)5367 return err;5368 5369 return 0;5370}5371 5372static void snd_hdsp_card_free(struct snd_card *card)5373{5374 struct hdsp *hdsp = card->private_data;5375 5376 if (hdsp->port) {5377 /* stop the audio, and cancel all interrupts */5378 cancel_work_sync(&hdsp->midi_work);5379 hdsp->control_register &= ~(HDSP_Start|HDSP_AudioInterruptEnable|HDSP_Midi0InterruptEnable|HDSP_Midi1InterruptEnable);5380 hdsp_write (hdsp, HDSP_controlRegister, hdsp->control_register);5381 }5382 5383 release_firmware(hdsp->firmware);5384 vfree(hdsp->fw_uploaded);5385}5386 5387static int snd_hdsp_probe(struct pci_dev *pci,5388 const struct pci_device_id *pci_id)5389{5390 static int dev;5391 struct hdsp *hdsp;5392 struct snd_card *card;5393 int err;5394 5395 if (dev >= SNDRV_CARDS)5396 return -ENODEV;5397 if (!enable[dev]) {5398 dev++;5399 return -ENOENT;5400 }5401 5402 err = snd_devm_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,5403 sizeof(struct hdsp), &card);5404 if (err < 0)5405 return err;5406 5407 hdsp = card->private_data;5408 card->private_free = snd_hdsp_card_free;5409 hdsp->dev = dev;5410 hdsp->pci = pci;5411 err = snd_hdsp_create(card, hdsp);5412 if (err)5413 goto error;5414 5415 strcpy(card->shortname, "Hammerfall DSP");5416 sprintf(card->longname, "%s at 0x%lx, irq %d", hdsp->card_name,5417 hdsp->port, hdsp->irq);5418 err = snd_card_register(card);5419 if (err)5420 goto error;5421 pci_set_drvdata(pci, card);5422 dev++;5423 return 0;5424 5425 error:5426 snd_card_free(card);5427 return err;5428}5429 5430static struct pci_driver hdsp_driver = {5431 .name = KBUILD_MODNAME,5432 .id_table = snd_hdsp_ids,5433 .probe = snd_hdsp_probe,5434};5435 5436module_pci_driver(hdsp_driver);5437