2566 lines · c
1// SPDX-License-Identifier: GPL-2.0-or-later2/*3 * ALSA driver for RME Digi9652 audio interfaces 4 *5 * Copyright (c) 1999 IEM - Winfried Ritsch6 * Copyright (c) 1999-2001 Paul Davis7 */8 9#include <linux/delay.h>10#include <linux/init.h>11#include <linux/interrupt.h>12#include <linux/pci.h>13#include <linux/module.h>14#include <linux/io.h>15#include <linux/nospec.h>16 17#include <sound/core.h>18#include <sound/control.h>19#include <sound/pcm.h>20#include <sound/info.h>21#include <sound/asoundef.h>22#include <sound/initval.h>23 24#include <asm/current.h>25 26static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */27static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */28static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */29static bool precise_ptr[SNDRV_CARDS]; /* Enable precise pointer */30 31module_param_array(index, int, NULL, 0444);32MODULE_PARM_DESC(index, "Index value for RME Digi9652 (Hammerfall) soundcard.");33module_param_array(id, charp, NULL, 0444);34MODULE_PARM_DESC(id, "ID string for RME Digi9652 (Hammerfall) soundcard.");35module_param_array(enable, bool, NULL, 0444);36MODULE_PARM_DESC(enable, "Enable/disable specific RME96{52,36} soundcards.");37module_param_array(precise_ptr, bool, NULL, 0444);38MODULE_PARM_DESC(precise_ptr, "Enable precise pointer (doesn't work reliably).");39MODULE_AUTHOR("Paul Davis <pbd@op.net>, Winfried Ritsch");40MODULE_DESCRIPTION("RME Digi9652/Digi9636");41MODULE_LICENSE("GPL");42 43/* The Hammerfall has two sets of 24 ADAT + 2 S/PDIF channels, one for44 capture, one for playback. Both the ADAT and S/PDIF channels appear45 to the host CPU in the same block of memory. There is no functional46 difference between them in terms of access.47 48 The Hammerfall Light is identical to the Hammerfall, except that it49 has 2 sets 18 channels (16 ADAT + 2 S/PDIF) for capture and playback.50*/51 52#define RME9652_NCHANNELS 2653#define RME9636_NCHANNELS 1854 55/* Preferred sync source choices - used by "sync_pref" control switch */56 57#define RME9652_SYNC_FROM_SPDIF 058#define RME9652_SYNC_FROM_ADAT1 159#define RME9652_SYNC_FROM_ADAT2 260#define RME9652_SYNC_FROM_ADAT3 361 62/* Possible sources of S/PDIF input */63 64#define RME9652_SPDIFIN_OPTICAL 0 /* optical (ADAT1) */65#define RME9652_SPDIFIN_COAXIAL 1 /* coaxial (RCA) */66#define RME9652_SPDIFIN_INTERN 2 /* internal (CDROM) */67 68/* ------------- Status-Register bits --------------------- */69 70#define RME9652_IRQ (1<<0) /* IRQ is High if not reset by irq_clear */71#define RME9652_lock_2 (1<<1) /* ADAT 3-PLL: 1=locked, 0=unlocked */72#define RME9652_lock_1 (1<<2) /* ADAT 2-PLL: 1=locked, 0=unlocked */73#define RME9652_lock_0 (1<<3) /* ADAT 1-PLL: 1=locked, 0=unlocked */74#define RME9652_fs48 (1<<4) /* sample rate is 0=44.1/88.2,1=48/96 Khz */75#define RME9652_wsel_rd (1<<5) /* if Word-Clock is used and valid then 1 */76 /* bits 6-15 encode h/w buffer pointer position */77#define RME9652_sync_2 (1<<16) /* if ADAT-IN 3 in sync to system clock */78#define RME9652_sync_1 (1<<17) /* if ADAT-IN 2 in sync to system clock */79#define RME9652_sync_0 (1<<18) /* if ADAT-IN 1 in sync to system clock */80#define RME9652_DS_rd (1<<19) /* 1=Double Speed Mode, 0=Normal Speed */81#define RME9652_tc_busy (1<<20) /* 1=time-code copy in progress (960ms) */82#define RME9652_tc_out (1<<21) /* time-code out bit */83#define RME9652_F_0 (1<<22) /* 000=64kHz, 100=88.2kHz, 011=96kHz */84#define RME9652_F_1 (1<<23) /* 111=32kHz, 110=44.1kHz, 101=48kHz, */85#define RME9652_F_2 (1<<24) /* external Crystal Chip if ERF=1 */86#define RME9652_ERF (1<<25) /* Error-Flag of SDPIF Receiver (1=No Lock) */87#define RME9652_buffer_id (1<<26) /* toggles by each interrupt on rec/play */88#define RME9652_tc_valid (1<<27) /* 1 = a signal is detected on time-code input */89#define RME9652_SPDIF_READ (1<<28) /* byte available from Rev 1.5+ S/PDIF interface */90 91#define RME9652_sync (RME9652_sync_0|RME9652_sync_1|RME9652_sync_2)92#define RME9652_lock (RME9652_lock_0|RME9652_lock_1|RME9652_lock_2)93#define RME9652_F (RME9652_F_0|RME9652_F_1|RME9652_F_2)94#define rme9652_decode_spdif_rate(x) ((x)>>22)95 96/* Bit 6..15 : h/w buffer pointer */97 98#define RME9652_buf_pos 0x000FFC099 100/* Bits 31,30,29 are bits 5,4,3 of h/w pointer position on later101 Rev G EEPROMS and Rev 1.5 cards or later.102*/ 103 104#define RME9652_REV15_buf_pos(x) ((((x)&0xE0000000)>>26)|((x)&RME9652_buf_pos))105 106/* amount of io space we remap for register access. i'm not sure we107 even need this much, but 1K is nice round number :)108*/109 110#define RME9652_IO_EXTENT 1024111 112#define RME9652_init_buffer 0113#define RME9652_play_buffer 32 /* holds ptr to 26x64kBit host RAM */114#define RME9652_rec_buffer 36 /* holds ptr to 26x64kBit host RAM */115#define RME9652_control_register 64116#define RME9652_irq_clear 96117#define RME9652_time_code 100 /* useful if used with alesis adat */118#define RME9652_thru_base 128 /* 132...228 Thru for 26 channels */119 120/* Read-only registers */121 122/* Writing to any of the register locations writes to the status123 register. We'll use the first location as our point of access.124*/125 126#define RME9652_status_register 0127 128/* --------- Control-Register Bits ---------------- */129 130 131#define RME9652_start_bit (1<<0) /* start record/play */132 /* bits 1-3 encode buffersize/latency */133#define RME9652_Master (1<<4) /* Clock Mode Master=1,Slave/Auto=0 */134#define RME9652_IE (1<<5) /* Interrupt Enable */135#define RME9652_freq (1<<6) /* samplerate 0=44.1/88.2, 1=48/96 kHz */136#define RME9652_freq1 (1<<7) /* if 0, 32kHz, else always 1 */137#define RME9652_DS (1<<8) /* Doule Speed 0=44.1/48, 1=88.2/96 Khz */138#define RME9652_PRO (1<<9) /* S/PDIF out: 0=consumer, 1=professional */139#define RME9652_EMP (1<<10) /* Emphasis 0=None, 1=ON */140#define RME9652_Dolby (1<<11) /* Non-audio bit 1=set, 0=unset */141#define RME9652_opt_out (1<<12) /* Use 1st optical OUT as SPDIF: 1=yes,0=no */142#define RME9652_wsel (1<<13) /* use Wordclock as sync (overwrites master) */143#define RME9652_inp_0 (1<<14) /* SPDIF-IN: 00=optical (ADAT1), */144#define RME9652_inp_1 (1<<15) /* 01=koaxial (Cinch), 10=Internal CDROM */145#define RME9652_SyncPref_ADAT2 (1<<16)146#define RME9652_SyncPref_ADAT3 (1<<17)147#define RME9652_SPDIF_RESET (1<<18) /* Rev 1.5+: h/w S/PDIF receiver */148#define RME9652_SPDIF_SELECT (1<<19)149#define RME9652_SPDIF_CLOCK (1<<20)150#define RME9652_SPDIF_WRITE (1<<21)151#define RME9652_ADAT1_INTERNAL (1<<22) /* Rev 1.5+: if set, internal CD connector carries ADAT */152 153/* buffersize = 512Bytes * 2^n, where n is made from Bit2 ... Bit0 */154 155#define RME9652_latency 0x0e156#define rme9652_encode_latency(x) (((x)&0x7)<<1)157#define rme9652_decode_latency(x) (((x)>>1)&0x7)158#define rme9652_running_double_speed(s) ((s)->control_register & RME9652_DS)159#define RME9652_inp (RME9652_inp_0|RME9652_inp_1)160#define rme9652_encode_spdif_in(x) (((x)&0x3)<<14)161#define rme9652_decode_spdif_in(x) (((x)>>14)&0x3)162 163#define RME9652_SyncPref_Mask (RME9652_SyncPref_ADAT2|RME9652_SyncPref_ADAT3)164#define RME9652_SyncPref_ADAT1 0165#define RME9652_SyncPref_SPDIF (RME9652_SyncPref_ADAT2|RME9652_SyncPref_ADAT3)166 167/* the size of a substream (1 mono data stream) */168 169#define RME9652_CHANNEL_BUFFER_SAMPLES (16*1024)170#define RME9652_CHANNEL_BUFFER_BYTES (4*RME9652_CHANNEL_BUFFER_SAMPLES)171 172/* the size of the area we need to allocate for DMA transfers. the173 size is the same regardless of the number of channels - the 174 9636 still uses the same memory area.175 176 Note that we allocate 1 more channel than is apparently needed177 because the h/w seems to write 1 byte beyond the end of the last178 page. Sigh.179*/180 181#define RME9652_DMA_AREA_BYTES ((RME9652_NCHANNELS+1) * RME9652_CHANNEL_BUFFER_BYTES)182#define RME9652_DMA_AREA_KILOBYTES (RME9652_DMA_AREA_BYTES/1024)183 184struct snd_rme9652 {185 int dev;186 187 spinlock_t lock;188 int irq;189 unsigned long port;190 void __iomem *iobase;191 192 int precise_ptr;193 194 u32 control_register; /* cached value */195 u32 thru_bits; /* thru 1=on, 0=off channel 1=Bit1... channel 26= Bit26 */196 197 u32 creg_spdif;198 u32 creg_spdif_stream;199 200 char *card_name; /* hammerfall or hammerfall light names */201 202 size_t hw_offsetmask; /* &-with status register to get real hw_offset */203 size_t prev_hw_offset; /* previous hw offset */204 size_t max_jitter; /* maximum jitter in frames for 205 hw pointer */206 size_t period_bytes; /* guess what this is */207 208 unsigned char ds_channels;209 unsigned char ss_channels; /* different for hammerfall/hammerfall-light */210 211 /* DMA buffers; those are copied instances from the original snd_dma_buf212 * objects (which are managed via devres) for the address alignments213 */214 struct snd_dma_buffer playback_dma_buf;215 struct snd_dma_buffer capture_dma_buf;216 217 unsigned char *capture_buffer; /* suitably aligned address */218 unsigned char *playback_buffer; /* suitably aligned address */219 220 pid_t capture_pid;221 pid_t playback_pid;222 223 struct snd_pcm_substream *capture_substream;224 struct snd_pcm_substream *playback_substream;225 int running;226 227 int passthru; /* non-zero if doing pass-thru */228 int hw_rev; /* h/w rev * 10 (i.e. 1.5 has hw_rev = 15) */229 230 int last_spdif_sample_rate; /* so that we can catch externally ... */231 int last_adat_sample_rate; /* ... induced rate changes */232 233 const signed char *channel_map;234 235 struct snd_card *card;236 struct snd_pcm *pcm;237 struct pci_dev *pci;238 struct snd_kcontrol *spdif_ctl;239 240};241 242/* These tables map the ALSA channels 1..N to the channels that we243 need to use in order to find the relevant channel buffer. RME244 refer to this kind of mapping as between "the ADAT channel and245 the DMA channel." We index it using the logical audio channel,246 and the value is the DMA channel (i.e. channel buffer number)247 where the data for that channel can be read/written from/to.248*/249 250static const signed char channel_map_9652_ss[26] = {251 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,252 18, 19, 20, 21, 22, 23, 24, 25253};254 255static const signed char channel_map_9636_ss[26] = {256 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 257 /* channels 16 and 17 are S/PDIF */258 24, 25,259 /* channels 18-25 don't exist */260 -1, -1, -1, -1, -1, -1, -1, -1261};262 263static const signed char channel_map_9652_ds[26] = {264 /* ADAT channels are remapped */265 1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23,266 /* channels 12 and 13 are S/PDIF */267 24, 25,268 /* others don't exist */269 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1270};271 272static const signed char channel_map_9636_ds[26] = {273 /* ADAT channels are remapped */274 1, 3, 5, 7, 9, 11, 13, 15,275 /* channels 8 and 9 are S/PDIF */276 24, 25,277 /* others don't exist */278 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1279};280 281static struct snd_dma_buffer *282snd_hammerfall_get_buffer(struct pci_dev *pci, size_t size)283{284 return snd_devm_alloc_pages(&pci->dev, SNDRV_DMA_TYPE_DEV, size);285}286 287static const struct pci_device_id snd_rme9652_ids[] = {288 {289 .vendor = 0x10ee,290 .device = 0x3fc4,291 .subvendor = PCI_ANY_ID,292 .subdevice = PCI_ANY_ID,293 }, /* RME Digi9652 */294 { 0, },295};296 297MODULE_DEVICE_TABLE(pci, snd_rme9652_ids);298 299static inline void rme9652_write(struct snd_rme9652 *rme9652, int reg, int val)300{301 writel(val, rme9652->iobase + reg);302}303 304static inline unsigned int rme9652_read(struct snd_rme9652 *rme9652, int reg)305{306 return readl(rme9652->iobase + reg);307}308 309static inline int snd_rme9652_use_is_exclusive(struct snd_rme9652 *rme9652)310{311 unsigned long flags;312 int ret = 1;313 314 spin_lock_irqsave(&rme9652->lock, flags);315 if ((rme9652->playback_pid != rme9652->capture_pid) &&316 (rme9652->playback_pid >= 0) && (rme9652->capture_pid >= 0)) {317 ret = 0;318 }319 spin_unlock_irqrestore(&rme9652->lock, flags);320 return ret;321}322 323static inline int rme9652_adat_sample_rate(struct snd_rme9652 *rme9652)324{325 if (rme9652_running_double_speed(rme9652)) {326 return (rme9652_read(rme9652, RME9652_status_register) &327 RME9652_fs48) ? 96000 : 88200;328 } else {329 return (rme9652_read(rme9652, RME9652_status_register) &330 RME9652_fs48) ? 48000 : 44100;331 }332}333 334static inline void rme9652_compute_period_size(struct snd_rme9652 *rme9652)335{336 unsigned int i;337 338 i = rme9652->control_register & RME9652_latency;339 rme9652->period_bytes = 1 << ((rme9652_decode_latency(i) + 8));340 rme9652->hw_offsetmask = 341 (rme9652->period_bytes * 2 - 1) & RME9652_buf_pos;342 rme9652->max_jitter = 80;343}344 345static snd_pcm_uframes_t rme9652_hw_pointer(struct snd_rme9652 *rme9652)346{347 int status;348 unsigned int offset, frag;349 snd_pcm_uframes_t period_size = rme9652->period_bytes / 4;350 snd_pcm_sframes_t delta;351 352 status = rme9652_read(rme9652, RME9652_status_register);353 if (!rme9652->precise_ptr)354 return (status & RME9652_buffer_id) ? period_size : 0;355 offset = status & RME9652_buf_pos;356 357 /* The hardware may give a backward movement for up to 80 frames358 Martin Kirst <martin.kirst@freenet.de> knows the details.359 */360 361 delta = rme9652->prev_hw_offset - offset;362 delta &= 0xffff;363 if (delta <= (snd_pcm_sframes_t)rme9652->max_jitter * 4)364 offset = rme9652->prev_hw_offset;365 else366 rme9652->prev_hw_offset = offset;367 offset &= rme9652->hw_offsetmask;368 offset /= 4;369 frag = status & RME9652_buffer_id;370 371 if (offset < period_size) {372 if (offset > rme9652->max_jitter) {373 if (frag)374 dev_err(rme9652->card->dev,375 "Unexpected hw_pointer position (bufid == 0): status: %x offset: %d\n",376 status, offset);377 } else if (!frag)378 return 0;379 offset -= rme9652->max_jitter;380 if ((int)offset < 0)381 offset += period_size * 2;382 } else {383 if (offset > period_size + rme9652->max_jitter) {384 if (!frag)385 dev_err(rme9652->card->dev,386 "Unexpected hw_pointer position (bufid == 1): status: %x offset: %d\n",387 status, offset);388 } else if (frag)389 return period_size;390 offset -= rme9652->max_jitter;391 }392 393 return offset;394}395 396static inline void rme9652_reset_hw_pointer(struct snd_rme9652 *rme9652)397{398 int i;399 400 /* reset the FIFO pointer to zero. We do this by writing to 8401 registers, each of which is a 32bit wide register, and set402 them all to zero. Note that s->iobase is a pointer to403 int32, not pointer to char. 404 */405 406 for (i = 0; i < 8; i++) {407 rme9652_write(rme9652, i * 4, 0);408 udelay(10);409 }410 rme9652->prev_hw_offset = 0;411}412 413static inline void rme9652_start(struct snd_rme9652 *s)414{415 s->control_register |= (RME9652_IE | RME9652_start_bit);416 rme9652_write(s, RME9652_control_register, s->control_register);417}418 419static inline void rme9652_stop(struct snd_rme9652 *s)420{421 s->control_register &= ~(RME9652_start_bit | RME9652_IE);422 rme9652_write(s, RME9652_control_register, s->control_register);423}424 425static int rme9652_set_interrupt_interval(struct snd_rme9652 *s,426 unsigned int frames)427{428 int restart = 0;429 int n;430 431 spin_lock_irq(&s->lock);432 433 restart = s->running;434 if (restart)435 rme9652_stop(s);436 437 frames >>= 7;438 n = 0;439 while (frames) {440 n++;441 frames >>= 1;442 }443 444 s->control_register &= ~RME9652_latency;445 s->control_register |= rme9652_encode_latency(n);446 447 rme9652_write(s, RME9652_control_register, s->control_register);448 449 rme9652_compute_period_size(s);450 451 if (restart)452 rme9652_start(s);453 454 spin_unlock_irq(&s->lock);455 456 return 0;457}458 459static int rme9652_set_rate(struct snd_rme9652 *rme9652, int rate)460{461 int restart;462 int reject_if_open = 0;463 int xrate;464 465 if (!snd_rme9652_use_is_exclusive (rme9652)) {466 return -EBUSY;467 }468 469 /* Changing from a "single speed" to a "double speed" rate is470 not allowed if any substreams are open. This is because471 such a change causes a shift in the location of 472 the DMA buffers and a reduction in the number of available473 buffers. 474 475 Note that a similar but essentially insoluble problem476 exists for externally-driven rate changes. All we can do477 is to flag rate changes in the read/write routines.478 */479 480 spin_lock_irq(&rme9652->lock);481 xrate = rme9652_adat_sample_rate(rme9652);482 483 switch (rate) {484 case 44100:485 if (xrate > 48000) {486 reject_if_open = 1;487 }488 rate = 0;489 break;490 case 48000:491 if (xrate > 48000) {492 reject_if_open = 1;493 }494 rate = RME9652_freq;495 break;496 case 88200:497 if (xrate < 48000) {498 reject_if_open = 1;499 }500 rate = RME9652_DS;501 break;502 case 96000:503 if (xrate < 48000) {504 reject_if_open = 1;505 }506 rate = RME9652_DS | RME9652_freq;507 break;508 default:509 spin_unlock_irq(&rme9652->lock);510 return -EINVAL;511 }512 513 if (reject_if_open && (rme9652->capture_pid >= 0 || rme9652->playback_pid >= 0)) {514 spin_unlock_irq(&rme9652->lock);515 return -EBUSY;516 }517 518 restart = rme9652->running;519 if (restart)520 rme9652_stop(rme9652);521 rme9652->control_register &= ~(RME9652_freq | RME9652_DS);522 rme9652->control_register |= rate;523 rme9652_write(rme9652, RME9652_control_register, rme9652->control_register);524 525 if (restart)526 rme9652_start(rme9652);527 528 if (rate & RME9652_DS) {529 if (rme9652->ss_channels == RME9652_NCHANNELS) {530 rme9652->channel_map = channel_map_9652_ds;531 } else {532 rme9652->channel_map = channel_map_9636_ds;533 }534 } else {535 if (rme9652->ss_channels == RME9652_NCHANNELS) {536 rme9652->channel_map = channel_map_9652_ss;537 } else {538 rme9652->channel_map = channel_map_9636_ss;539 }540 }541 542 spin_unlock_irq(&rme9652->lock);543 return 0;544}545 546static void rme9652_set_thru(struct snd_rme9652 *rme9652, int channel, int enable)547{548 int i;549 550 rme9652->passthru = 0;551 552 if (channel < 0) {553 554 /* set thru for all channels */555 556 if (enable) {557 for (i = 0; i < RME9652_NCHANNELS; i++) {558 rme9652->thru_bits |= (1 << i);559 rme9652_write(rme9652, RME9652_thru_base + i * 4, 1);560 }561 } else {562 for (i = 0; i < RME9652_NCHANNELS; i++) {563 rme9652->thru_bits &= ~(1 << i);564 rme9652_write(rme9652, RME9652_thru_base + i * 4, 0);565 }566 }567 568 } else {569 int mapped_channel;570 571 mapped_channel = rme9652->channel_map[channel];572 573 if (enable) {574 rme9652->thru_bits |= (1 << mapped_channel);575 } else {576 rme9652->thru_bits &= ~(1 << mapped_channel);577 }578 579 rme9652_write(rme9652,580 RME9652_thru_base + mapped_channel * 4,581 enable ? 1 : 0); 582 }583}584 585static int rme9652_set_passthru(struct snd_rme9652 *rme9652, int onoff)586{587 if (onoff) {588 rme9652_set_thru(rme9652, -1, 1);589 590 /* we don't want interrupts, so do a591 custom version of rme9652_start().592 */593 594 rme9652->control_register =595 RME9652_inp_0 | 596 rme9652_encode_latency(7) |597 RME9652_start_bit;598 599 rme9652_reset_hw_pointer(rme9652);600 601 rme9652_write(rme9652, RME9652_control_register,602 rme9652->control_register);603 rme9652->passthru = 1;604 } else {605 rme9652_set_thru(rme9652, -1, 0);606 rme9652_stop(rme9652); 607 rme9652->passthru = 0;608 }609 610 return 0;611}612 613static void rme9652_spdif_set_bit (struct snd_rme9652 *rme9652, int mask, int onoff)614{615 if (onoff) 616 rme9652->control_register |= mask;617 else 618 rme9652->control_register &= ~mask;619 620 rme9652_write(rme9652, RME9652_control_register, rme9652->control_register);621}622 623static void rme9652_spdif_write_byte (struct snd_rme9652 *rme9652, const int val)624{625 long mask;626 long i;627 628 for (i = 0, mask = 0x80; i < 8; i++, mask >>= 1) {629 if (val & mask)630 rme9652_spdif_set_bit (rme9652, RME9652_SPDIF_WRITE, 1);631 else 632 rme9652_spdif_set_bit (rme9652, RME9652_SPDIF_WRITE, 0);633 634 rme9652_spdif_set_bit (rme9652, RME9652_SPDIF_CLOCK, 1);635 rme9652_spdif_set_bit (rme9652, RME9652_SPDIF_CLOCK, 0);636 }637}638 639static int rme9652_spdif_read_byte (struct snd_rme9652 *rme9652)640{641 long mask;642 long val;643 long i;644 645 val = 0;646 647 for (i = 0, mask = 0x80; i < 8; i++, mask >>= 1) {648 rme9652_spdif_set_bit (rme9652, RME9652_SPDIF_CLOCK, 1);649 if (rme9652_read (rme9652, RME9652_status_register) & RME9652_SPDIF_READ)650 val |= mask;651 rme9652_spdif_set_bit (rme9652, RME9652_SPDIF_CLOCK, 0);652 }653 654 return val;655}656 657static void rme9652_write_spdif_codec (struct snd_rme9652 *rme9652, const int address, const int data)658{659 rme9652_spdif_set_bit (rme9652, RME9652_SPDIF_SELECT, 1);660 rme9652_spdif_write_byte (rme9652, 0x20);661 rme9652_spdif_write_byte (rme9652, address);662 rme9652_spdif_write_byte (rme9652, data);663 rme9652_spdif_set_bit (rme9652, RME9652_SPDIF_SELECT, 0);664}665 666 667static int rme9652_spdif_read_codec (struct snd_rme9652 *rme9652, const int address)668{669 int ret;670 671 rme9652_spdif_set_bit (rme9652, RME9652_SPDIF_SELECT, 1);672 rme9652_spdif_write_byte (rme9652, 0x20);673 rme9652_spdif_write_byte (rme9652, address);674 rme9652_spdif_set_bit (rme9652, RME9652_SPDIF_SELECT, 0);675 rme9652_spdif_set_bit (rme9652, RME9652_SPDIF_SELECT, 1);676 677 rme9652_spdif_write_byte (rme9652, 0x21);678 ret = rme9652_spdif_read_byte (rme9652);679 rme9652_spdif_set_bit (rme9652, RME9652_SPDIF_SELECT, 0);680 681 return ret;682}683 684static void rme9652_initialize_spdif_receiver (struct snd_rme9652 *rme9652)685{686 /* XXX what unsets this ? */687 688 rme9652->control_register |= RME9652_SPDIF_RESET;689 690 rme9652_write_spdif_codec (rme9652, 4, 0x40);691 rme9652_write_spdif_codec (rme9652, 17, 0x13);692 rme9652_write_spdif_codec (rme9652, 6, 0x02);693}694 695static inline int rme9652_spdif_sample_rate(struct snd_rme9652 *s)696{697 unsigned int rate_bits;698 699 if (rme9652_read(s, RME9652_status_register) & RME9652_ERF) {700 return -1; /* error condition */701 }702 703 if (s->hw_rev == 15) {704 705 int x, y, ret;706 707 x = rme9652_spdif_read_codec (s, 30);708 709 if (x != 0) 710 y = 48000 * 64 / x;711 else712 y = 0;713 714 if (y > 30400 && y < 33600) ret = 32000; 715 else if (y > 41900 && y < 46000) ret = 44100;716 else if (y > 46000 && y < 50400) ret = 48000;717 else if (y > 60800 && y < 67200) ret = 64000;718 else if (y > 83700 && y < 92000) ret = 88200;719 else if (y > 92000 && y < 100000) ret = 96000;720 else ret = 0;721 return ret;722 }723 724 rate_bits = rme9652_read(s, RME9652_status_register) & RME9652_F;725 726 switch (rme9652_decode_spdif_rate(rate_bits)) {727 case 0x7:728 return 32000;729 730 case 0x6:731 return 44100;732 733 case 0x5:734 return 48000;735 736 case 0x4:737 return 88200;738 739 case 0x3:740 return 96000;741 742 case 0x0:743 return 64000;744 745 default:746 dev_err(s->card->dev,747 "%s: unknown S/PDIF input rate (bits = 0x%x)\n",748 s->card_name, rate_bits);749 return 0;750 }751}752 753/*-----------------------------------------------------------------------------754 Control Interface755 ----------------------------------------------------------------------------*/756 757static u32 snd_rme9652_convert_from_aes(struct snd_aes_iec958 *aes)758{759 u32 val = 0;760 val |= (aes->status[0] & IEC958_AES0_PROFESSIONAL) ? RME9652_PRO : 0;761 val |= (aes->status[0] & IEC958_AES0_NONAUDIO) ? RME9652_Dolby : 0;762 if (val & RME9652_PRO)763 val |= (aes->status[0] & IEC958_AES0_PRO_EMPHASIS_5015) ? RME9652_EMP : 0;764 else765 val |= (aes->status[0] & IEC958_AES0_CON_EMPHASIS_5015) ? RME9652_EMP : 0;766 return val;767}768 769static void snd_rme9652_convert_to_aes(struct snd_aes_iec958 *aes, u32 val)770{771 aes->status[0] = ((val & RME9652_PRO) ? IEC958_AES0_PROFESSIONAL : 0) |772 ((val & RME9652_Dolby) ? IEC958_AES0_NONAUDIO : 0);773 if (val & RME9652_PRO)774 aes->status[0] |= (val & RME9652_EMP) ? IEC958_AES0_PRO_EMPHASIS_5015 : 0;775 else776 aes->status[0] |= (val & RME9652_EMP) ? IEC958_AES0_CON_EMPHASIS_5015 : 0;777}778 779static int snd_rme9652_control_spdif_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)780{781 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;782 uinfo->count = 1;783 return 0;784}785 786static int snd_rme9652_control_spdif_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)787{788 struct snd_rme9652 *rme9652 = snd_kcontrol_chip(kcontrol);789 790 snd_rme9652_convert_to_aes(&ucontrol->value.iec958, rme9652->creg_spdif);791 return 0;792}793 794static int snd_rme9652_control_spdif_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)795{796 struct snd_rme9652 *rme9652 = snd_kcontrol_chip(kcontrol);797 int change;798 u32 val;799 800 val = snd_rme9652_convert_from_aes(&ucontrol->value.iec958);801 spin_lock_irq(&rme9652->lock);802 change = val != rme9652->creg_spdif;803 rme9652->creg_spdif = val;804 spin_unlock_irq(&rme9652->lock);805 return change;806}807 808static int snd_rme9652_control_spdif_stream_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)809{810 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;811 uinfo->count = 1;812 return 0;813}814 815static int snd_rme9652_control_spdif_stream_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)816{817 struct snd_rme9652 *rme9652 = snd_kcontrol_chip(kcontrol);818 819 snd_rme9652_convert_to_aes(&ucontrol->value.iec958, rme9652->creg_spdif_stream);820 return 0;821}822 823static int snd_rme9652_control_spdif_stream_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)824{825 struct snd_rme9652 *rme9652 = snd_kcontrol_chip(kcontrol);826 int change;827 u32 val;828 829 val = snd_rme9652_convert_from_aes(&ucontrol->value.iec958);830 spin_lock_irq(&rme9652->lock);831 change = val != rme9652->creg_spdif_stream;832 rme9652->creg_spdif_stream = val;833 rme9652->control_register &= ~(RME9652_PRO | RME9652_Dolby | RME9652_EMP);834 rme9652_write(rme9652, RME9652_control_register, rme9652->control_register |= val);835 spin_unlock_irq(&rme9652->lock);836 return change;837}838 839static int snd_rme9652_control_spdif_mask_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)840{841 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;842 uinfo->count = 1;843 return 0;844}845 846static int snd_rme9652_control_spdif_mask_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)847{848 ucontrol->value.iec958.status[0] = kcontrol->private_value;849 return 0;850}851 852#define RME9652_ADAT1_IN(xname, xindex) \853{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \854 .info = snd_rme9652_info_adat1_in, \855 .get = snd_rme9652_get_adat1_in, \856 .put = snd_rme9652_put_adat1_in }857 858static unsigned int rme9652_adat1_in(struct snd_rme9652 *rme9652)859{860 if (rme9652->control_register & RME9652_ADAT1_INTERNAL)861 return 1; 862 return 0;863}864 865static int rme9652_set_adat1_input(struct snd_rme9652 *rme9652, int internal)866{867 int restart = 0;868 869 if (internal) {870 rme9652->control_register |= RME9652_ADAT1_INTERNAL;871 } else {872 rme9652->control_register &= ~RME9652_ADAT1_INTERNAL;873 }874 875 /* XXX do we actually need to stop the card when we do this ? */876 877 restart = rme9652->running;878 if (restart)879 rme9652_stop(rme9652);880 881 rme9652_write(rme9652, RME9652_control_register, rme9652->control_register);882 883 if (restart)884 rme9652_start(rme9652);885 886 return 0;887}888 889static int snd_rme9652_info_adat1_in(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)890{891 static const char * const texts[2] = {"ADAT1", "Internal"};892 893 return snd_ctl_enum_info(uinfo, 1, 2, texts);894}895 896static int snd_rme9652_get_adat1_in(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)897{898 struct snd_rme9652 *rme9652 = snd_kcontrol_chip(kcontrol);899 900 spin_lock_irq(&rme9652->lock);901 ucontrol->value.enumerated.item[0] = rme9652_adat1_in(rme9652);902 spin_unlock_irq(&rme9652->lock);903 return 0;904}905 906static int snd_rme9652_put_adat1_in(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)907{908 struct snd_rme9652 *rme9652 = snd_kcontrol_chip(kcontrol);909 int change;910 unsigned int val;911 912 if (!snd_rme9652_use_is_exclusive(rme9652))913 return -EBUSY;914 val = ucontrol->value.enumerated.item[0] % 2;915 spin_lock_irq(&rme9652->lock);916 change = val != rme9652_adat1_in(rme9652);917 if (change)918 rme9652_set_adat1_input(rme9652, val);919 spin_unlock_irq(&rme9652->lock);920 return change;921}922 923#define RME9652_SPDIF_IN(xname, xindex) \924{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \925 .info = snd_rme9652_info_spdif_in, \926 .get = snd_rme9652_get_spdif_in, .put = snd_rme9652_put_spdif_in }927 928static unsigned int rme9652_spdif_in(struct snd_rme9652 *rme9652)929{930 return rme9652_decode_spdif_in(rme9652->control_register &931 RME9652_inp);932}933 934static int rme9652_set_spdif_input(struct snd_rme9652 *rme9652, int in)935{936 int restart = 0;937 938 rme9652->control_register &= ~RME9652_inp;939 rme9652->control_register |= rme9652_encode_spdif_in(in);940 941 restart = rme9652->running;942 if (restart)943 rme9652_stop(rme9652);944 945 rme9652_write(rme9652, RME9652_control_register, rme9652->control_register);946 947 if (restart)948 rme9652_start(rme9652);949 950 return 0;951}952 953static int snd_rme9652_info_spdif_in(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)954{955 static const char * const texts[3] = {"ADAT1", "Coaxial", "Internal"};956 957 return snd_ctl_enum_info(uinfo, 1, 3, texts);958}959 960static int snd_rme9652_get_spdif_in(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)961{962 struct snd_rme9652 *rme9652 = snd_kcontrol_chip(kcontrol);963 964 spin_lock_irq(&rme9652->lock);965 ucontrol->value.enumerated.item[0] = rme9652_spdif_in(rme9652);966 spin_unlock_irq(&rme9652->lock);967 return 0;968}969 970static int snd_rme9652_put_spdif_in(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)971{972 struct snd_rme9652 *rme9652 = snd_kcontrol_chip(kcontrol);973 int change;974 unsigned int val;975 976 if (!snd_rme9652_use_is_exclusive(rme9652))977 return -EBUSY;978 val = ucontrol->value.enumerated.item[0] % 3;979 spin_lock_irq(&rme9652->lock);980 change = val != rme9652_spdif_in(rme9652);981 if (change)982 rme9652_set_spdif_input(rme9652, val);983 spin_unlock_irq(&rme9652->lock);984 return change;985}986 987#define RME9652_SPDIF_OUT(xname, xindex) \988{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \989 .info = snd_rme9652_info_spdif_out, \990 .get = snd_rme9652_get_spdif_out, .put = snd_rme9652_put_spdif_out }991 992static int rme9652_spdif_out(struct snd_rme9652 *rme9652)993{994 return (rme9652->control_register & RME9652_opt_out) ? 1 : 0;995}996 997static int rme9652_set_spdif_output(struct snd_rme9652 *rme9652, int out)998{999 int restart = 0;1000 1001 if (out) {1002 rme9652->control_register |= RME9652_opt_out;1003 } else {1004 rme9652->control_register &= ~RME9652_opt_out;1005 }1006 1007 restart = rme9652->running;1008 if (restart)1009 rme9652_stop(rme9652);1010 1011 rme9652_write(rme9652, RME9652_control_register, rme9652->control_register);1012 1013 if (restart)1014 rme9652_start(rme9652);1015 1016 return 0;1017}1018 1019#define snd_rme9652_info_spdif_out snd_ctl_boolean_mono_info1020 1021static int snd_rme9652_get_spdif_out(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)1022{1023 struct snd_rme9652 *rme9652 = snd_kcontrol_chip(kcontrol);1024 1025 spin_lock_irq(&rme9652->lock);1026 ucontrol->value.integer.value[0] = rme9652_spdif_out(rme9652);1027 spin_unlock_irq(&rme9652->lock);1028 return 0;1029}1030 1031static int snd_rme9652_put_spdif_out(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)1032{1033 struct snd_rme9652 *rme9652 = snd_kcontrol_chip(kcontrol);1034 int change;1035 unsigned int val;1036 1037 if (!snd_rme9652_use_is_exclusive(rme9652))1038 return -EBUSY;1039 val = ucontrol->value.integer.value[0] & 1;1040 spin_lock_irq(&rme9652->lock);1041 change = (int)val != rme9652_spdif_out(rme9652);1042 rme9652_set_spdif_output(rme9652, val);1043 spin_unlock_irq(&rme9652->lock);1044 return change;1045}1046 1047#define RME9652_SYNC_MODE(xname, xindex) \1048{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \1049 .info = snd_rme9652_info_sync_mode, \1050 .get = snd_rme9652_get_sync_mode, .put = snd_rme9652_put_sync_mode }1051 1052static int rme9652_sync_mode(struct snd_rme9652 *rme9652)1053{1054 if (rme9652->control_register & RME9652_wsel) {1055 return 2;1056 } else if (rme9652->control_register & RME9652_Master) {1057 return 1;1058 } else {1059 return 0;1060 }1061}1062 1063static int rme9652_set_sync_mode(struct snd_rme9652 *rme9652, int mode)1064{1065 int restart = 0;1066 1067 switch (mode) {1068 case 0:1069 rme9652->control_register &=1070 ~(RME9652_Master | RME9652_wsel);1071 break;1072 case 1:1073 rme9652->control_register =1074 (rme9652->control_register & ~RME9652_wsel) | RME9652_Master;1075 break;1076 case 2:1077 rme9652->control_register |=1078 (RME9652_Master | RME9652_wsel);1079 break;1080 }1081 1082 restart = rme9652->running;1083 if (restart)1084 rme9652_stop(rme9652);1085 1086 rme9652_write(rme9652, RME9652_control_register, rme9652->control_register);1087 1088 if (restart)1089 rme9652_start(rme9652);1090 1091 return 0;1092}1093 1094static int snd_rme9652_info_sync_mode(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)1095{1096 static const char * const texts[3] = {1097 "AutoSync", "Master", "Word Clock"1098 };1099 1100 return snd_ctl_enum_info(uinfo, 1, 3, texts);1101}1102 1103static int snd_rme9652_get_sync_mode(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)1104{1105 struct snd_rme9652 *rme9652 = snd_kcontrol_chip(kcontrol);1106 1107 spin_lock_irq(&rme9652->lock);1108 ucontrol->value.enumerated.item[0] = rme9652_sync_mode(rme9652);1109 spin_unlock_irq(&rme9652->lock);1110 return 0;1111}1112 1113static int snd_rme9652_put_sync_mode(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)1114{1115 struct snd_rme9652 *rme9652 = snd_kcontrol_chip(kcontrol);1116 int change;1117 unsigned int val;1118 1119 val = ucontrol->value.enumerated.item[0] % 3;1120 spin_lock_irq(&rme9652->lock);1121 change = (int)val != rme9652_sync_mode(rme9652);1122 rme9652_set_sync_mode(rme9652, val);1123 spin_unlock_irq(&rme9652->lock);1124 return change;1125}1126 1127#define RME9652_SYNC_PREF(xname, xindex) \1128{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \1129 .info = snd_rme9652_info_sync_pref, \1130 .get = snd_rme9652_get_sync_pref, .put = snd_rme9652_put_sync_pref }1131 1132static int rme9652_sync_pref(struct snd_rme9652 *rme9652)1133{1134 switch (rme9652->control_register & RME9652_SyncPref_Mask) {1135 case RME9652_SyncPref_ADAT1:1136 return RME9652_SYNC_FROM_ADAT1;1137 case RME9652_SyncPref_ADAT2:1138 return RME9652_SYNC_FROM_ADAT2;1139 case RME9652_SyncPref_ADAT3:1140 return RME9652_SYNC_FROM_ADAT3;1141 case RME9652_SyncPref_SPDIF:1142 return RME9652_SYNC_FROM_SPDIF;1143 }1144 /* Not reachable */1145 return 0;1146}1147 1148static int rme9652_set_sync_pref(struct snd_rme9652 *rme9652, int pref)1149{1150 int restart;1151 1152 rme9652->control_register &= ~RME9652_SyncPref_Mask;1153 switch (pref) {1154 case RME9652_SYNC_FROM_ADAT1:1155 rme9652->control_register |= RME9652_SyncPref_ADAT1;1156 break;1157 case RME9652_SYNC_FROM_ADAT2:1158 rme9652->control_register |= RME9652_SyncPref_ADAT2;1159 break;1160 case RME9652_SYNC_FROM_ADAT3:1161 rme9652->control_register |= RME9652_SyncPref_ADAT3;1162 break;1163 case RME9652_SYNC_FROM_SPDIF:1164 rme9652->control_register |= RME9652_SyncPref_SPDIF;1165 break;1166 }1167 1168 restart = rme9652->running;1169 if (restart)1170 rme9652_stop(rme9652);1171 1172 rme9652_write(rme9652, RME9652_control_register, rme9652->control_register);1173 1174 if (restart)1175 rme9652_start(rme9652);1176 1177 return 0;1178}1179 1180static int snd_rme9652_info_sync_pref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)1181{1182 static const char * const texts[4] = {1183 "IEC958 In", "ADAT1 In", "ADAT2 In", "ADAT3 In"1184 };1185 struct snd_rme9652 *rme9652 = snd_kcontrol_chip(kcontrol);1186 1187 return snd_ctl_enum_info(uinfo, 1,1188 rme9652->ss_channels == RME9652_NCHANNELS ? 4 : 3,1189 texts);1190}1191 1192static int snd_rme9652_get_sync_pref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)1193{1194 struct snd_rme9652 *rme9652 = snd_kcontrol_chip(kcontrol);1195 1196 spin_lock_irq(&rme9652->lock);1197 ucontrol->value.enumerated.item[0] = rme9652_sync_pref(rme9652);1198 spin_unlock_irq(&rme9652->lock);1199 return 0;1200}1201 1202static int snd_rme9652_put_sync_pref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)1203{1204 struct snd_rme9652 *rme9652 = snd_kcontrol_chip(kcontrol);1205 int change, max;1206 unsigned int val;1207 1208 if (!snd_rme9652_use_is_exclusive(rme9652))1209 return -EBUSY;1210 max = rme9652->ss_channels == RME9652_NCHANNELS ? 4 : 3;1211 val = ucontrol->value.enumerated.item[0] % max;1212 spin_lock_irq(&rme9652->lock);1213 change = (int)val != rme9652_sync_pref(rme9652);1214 rme9652_set_sync_pref(rme9652, val);1215 spin_unlock_irq(&rme9652->lock);1216 return change;1217}1218 1219static int snd_rme9652_info_thru(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)1220{1221 struct snd_rme9652 *rme9652 = snd_kcontrol_chip(kcontrol);1222 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;1223 uinfo->count = rme9652->ss_channels;1224 uinfo->value.integer.min = 0;1225 uinfo->value.integer.max = 1;1226 return 0;1227}1228 1229static int snd_rme9652_get_thru(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)1230{1231 struct snd_rme9652 *rme9652 = snd_kcontrol_chip(kcontrol);1232 unsigned int k;1233 u32 thru_bits = rme9652->thru_bits;1234 1235 for (k = 0; k < rme9652->ss_channels; ++k) {1236 ucontrol->value.integer.value[k] = !!(thru_bits & (1 << k));1237 }1238 return 0;1239}1240 1241static int snd_rme9652_put_thru(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)1242{1243 struct snd_rme9652 *rme9652 = snd_kcontrol_chip(kcontrol);1244 int change;1245 unsigned int chn;1246 u32 thru_bits = 0;1247 1248 if (!snd_rme9652_use_is_exclusive(rme9652))1249 return -EBUSY;1250 1251 for (chn = 0; chn < rme9652->ss_channels; ++chn) {1252 if (ucontrol->value.integer.value[chn])1253 thru_bits |= 1 << chn;1254 }1255 1256 spin_lock_irq(&rme9652->lock);1257 change = thru_bits ^ rme9652->thru_bits;1258 if (change) {1259 for (chn = 0; chn < rme9652->ss_channels; ++chn) {1260 if (!(change & (1 << chn)))1261 continue;1262 rme9652_set_thru(rme9652,chn,thru_bits&(1<<chn));1263 }1264 }1265 spin_unlock_irq(&rme9652->lock);1266 return !!change;1267}1268 1269#define RME9652_PASSTHRU(xname, xindex) \1270{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \1271 .info = snd_rme9652_info_passthru, \1272 .put = snd_rme9652_put_passthru, \1273 .get = snd_rme9652_get_passthru }1274 1275#define snd_rme9652_info_passthru snd_ctl_boolean_mono_info1276 1277static int snd_rme9652_get_passthru(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)1278{1279 struct snd_rme9652 *rme9652 = snd_kcontrol_chip(kcontrol);1280 1281 spin_lock_irq(&rme9652->lock);1282 ucontrol->value.integer.value[0] = rme9652->passthru;1283 spin_unlock_irq(&rme9652->lock);1284 return 0;1285}1286 1287static int snd_rme9652_put_passthru(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)1288{1289 struct snd_rme9652 *rme9652 = snd_kcontrol_chip(kcontrol);1290 int change;1291 unsigned int val;1292 int err = 0;1293 1294 if (!snd_rme9652_use_is_exclusive(rme9652))1295 return -EBUSY;1296 1297 val = ucontrol->value.integer.value[0] & 1;1298 spin_lock_irq(&rme9652->lock);1299 change = (ucontrol->value.integer.value[0] != rme9652->passthru);1300 if (change)1301 err = rme9652_set_passthru(rme9652, val);1302 spin_unlock_irq(&rme9652->lock);1303 return err ? err : change;1304}1305 1306/* Read-only switches */1307 1308#define RME9652_SPDIF_RATE(xname, xindex) \1309{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \1310 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \1311 .info = snd_rme9652_info_spdif_rate, \1312 .get = snd_rme9652_get_spdif_rate }1313 1314static int snd_rme9652_info_spdif_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)1315{1316 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;1317 uinfo->count = 1;1318 uinfo->value.integer.min = 0;1319 uinfo->value.integer.max = 96000;1320 return 0;1321}1322 1323static int snd_rme9652_get_spdif_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)1324{1325 struct snd_rme9652 *rme9652 = snd_kcontrol_chip(kcontrol);1326 1327 spin_lock_irq(&rme9652->lock);1328 ucontrol->value.integer.value[0] = rme9652_spdif_sample_rate(rme9652);1329 spin_unlock_irq(&rme9652->lock);1330 return 0;1331}1332 1333#define RME9652_ADAT_SYNC(xname, xindex, xidx) \1334{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \1335 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \1336 .info = snd_rme9652_info_adat_sync, \1337 .get = snd_rme9652_get_adat_sync, .private_value = xidx }1338 1339static int snd_rme9652_info_adat_sync(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)1340{1341 static const char * const texts[4] = {1342 "No Lock", "Lock", "No Lock Sync", "Lock Sync"1343 };1344 1345 return snd_ctl_enum_info(uinfo, 1, 4, texts);1346}1347 1348static int snd_rme9652_get_adat_sync(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)1349{1350 struct snd_rme9652 *rme9652 = snd_kcontrol_chip(kcontrol);1351 unsigned int mask1, mask2, val;1352 1353 switch (kcontrol->private_value) {1354 case 0: mask1 = RME9652_lock_0; mask2 = RME9652_sync_0; break; 1355 case 1: mask1 = RME9652_lock_1; mask2 = RME9652_sync_1; break; 1356 case 2: mask1 = RME9652_lock_2; mask2 = RME9652_sync_2; break; 1357 default: return -EINVAL;1358 }1359 val = rme9652_read(rme9652, RME9652_status_register);1360 ucontrol->value.enumerated.item[0] = (val & mask1) ? 1 : 0;1361 ucontrol->value.enumerated.item[0] |= (val & mask2) ? 2 : 0;1362 return 0;1363}1364 1365#define RME9652_TC_VALID(xname, xindex) \1366{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \1367 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \1368 .info = snd_rme9652_info_tc_valid, \1369 .get = snd_rme9652_get_tc_valid }1370 1371#define snd_rme9652_info_tc_valid snd_ctl_boolean_mono_info1372 1373static int snd_rme9652_get_tc_valid(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)1374{1375 struct snd_rme9652 *rme9652 = snd_kcontrol_chip(kcontrol);1376 1377 ucontrol->value.integer.value[0] = 1378 (rme9652_read(rme9652, RME9652_status_register) & RME9652_tc_valid) ? 1 : 0;1379 return 0;1380}1381 1382#ifdef ALSA_HAS_STANDARD_WAY_OF_RETURNING_TIMECODE1383 1384/* FIXME: this routine needs a port to the new control API --jk */1385 1386static int snd_rme9652_get_tc_value(void *private_data,1387 snd_kswitch_t *kswitch,1388 snd_switch_t *uswitch)1389{1390 struct snd_rme9652 *s = (struct snd_rme9652 *) private_data;1391 u32 value;1392 int i;1393 1394 uswitch->type = SNDRV_SW_TYPE_DWORD;1395 1396 if ((rme9652_read(s, RME9652_status_register) &1397 RME9652_tc_valid) == 0) {1398 uswitch->value.data32[0] = 0;1399 return 0;1400 }1401 1402 /* timecode request */1403 1404 rme9652_write(s, RME9652_time_code, 0);1405 1406 /* XXX bug alert: loop-based timing !!!! */1407 1408 for (i = 0; i < 50; i++) {1409 if (!(rme9652_read(s, i * 4) & RME9652_tc_busy))1410 break;1411 }1412 1413 if (!(rme9652_read(s, i * 4) & RME9652_tc_busy)) {1414 return -EIO;1415 }1416 1417 value = 0;1418 1419 for (i = 0; i < 32; i++) {1420 value >>= 1;1421 1422 if (rme9652_read(s, i * 4) & RME9652_tc_out)1423 value |= 0x80000000;1424 }1425 1426 if (value > 2 * 60 * 48000) {1427 value -= 2 * 60 * 48000;1428 } else {1429 value = 0;1430 }1431 1432 uswitch->value.data32[0] = value;1433 1434 return 0;1435}1436 1437#endif /* ALSA_HAS_STANDARD_WAY_OF_RETURNING_TIMECODE */1438 1439static const struct snd_kcontrol_new snd_rme9652_controls[] = {1440{1441 .iface = SNDRV_CTL_ELEM_IFACE_PCM,1442 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),1443 .info = snd_rme9652_control_spdif_info,1444 .get = snd_rme9652_control_spdif_get,1445 .put = snd_rme9652_control_spdif_put,1446},1447{1448 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE,1449 .iface = SNDRV_CTL_ELEM_IFACE_PCM,1450 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),1451 .info = snd_rme9652_control_spdif_stream_info,1452 .get = snd_rme9652_control_spdif_stream_get,1453 .put = snd_rme9652_control_spdif_stream_put,1454},1455{1456 .access = SNDRV_CTL_ELEM_ACCESS_READ,1457 .iface = SNDRV_CTL_ELEM_IFACE_PCM,1458 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,CON_MASK),1459 .info = snd_rme9652_control_spdif_mask_info,1460 .get = snd_rme9652_control_spdif_mask_get,1461 .private_value = IEC958_AES0_NONAUDIO |1462 IEC958_AES0_PROFESSIONAL |1463 IEC958_AES0_CON_EMPHASIS, 1464},1465{1466 .access = SNDRV_CTL_ELEM_ACCESS_READ,1467 .iface = SNDRV_CTL_ELEM_IFACE_PCM,1468 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PRO_MASK),1469 .info = snd_rme9652_control_spdif_mask_info,1470 .get = snd_rme9652_control_spdif_mask_get,1471 .private_value = IEC958_AES0_NONAUDIO |1472 IEC958_AES0_PROFESSIONAL |1473 IEC958_AES0_PRO_EMPHASIS,1474},1475RME9652_SPDIF_IN("IEC958 Input Connector", 0),1476RME9652_SPDIF_OUT("IEC958 Output also on ADAT1", 0),1477RME9652_SYNC_MODE("Sync Mode", 0),1478RME9652_SYNC_PREF("Preferred Sync Source", 0),1479{1480 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,1481 .name = "Channels Thru",1482 .index = 0,1483 .info = snd_rme9652_info_thru,1484 .get = snd_rme9652_get_thru,1485 .put = snd_rme9652_put_thru,1486},1487RME9652_SPDIF_RATE("IEC958 Sample Rate", 0),1488RME9652_ADAT_SYNC("ADAT1 Sync Check", 0, 0),1489RME9652_ADAT_SYNC("ADAT2 Sync Check", 0, 1),1490RME9652_TC_VALID("Timecode Valid", 0),1491RME9652_PASSTHRU("Passthru", 0)1492};1493 1494static const struct snd_kcontrol_new snd_rme9652_adat3_check =1495RME9652_ADAT_SYNC("ADAT3 Sync Check", 0, 2);1496 1497static const struct snd_kcontrol_new snd_rme9652_adat1_input =1498RME9652_ADAT1_IN("ADAT1 Input Source", 0);1499 1500static int snd_rme9652_create_controls(struct snd_card *card, struct snd_rme9652 *rme9652)1501{1502 unsigned int idx;1503 int err;1504 struct snd_kcontrol *kctl;1505 1506 for (idx = 0; idx < ARRAY_SIZE(snd_rme9652_controls); idx++) {1507 kctl = snd_ctl_new1(&snd_rme9652_controls[idx], rme9652);1508 err = snd_ctl_add(card, kctl);1509 if (err < 0)1510 return err;1511 if (idx == 1) /* IEC958 (S/PDIF) Stream */1512 rme9652->spdif_ctl = kctl;1513 }1514 1515 if (rme9652->ss_channels == RME9652_NCHANNELS) {1516 kctl = snd_ctl_new1(&snd_rme9652_adat3_check, rme9652);1517 err = snd_ctl_add(card, kctl);1518 if (err < 0)1519 return err;1520 }1521 1522 if (rme9652->hw_rev >= 15) {1523 kctl = snd_ctl_new1(&snd_rme9652_adat1_input, rme9652);1524 err = snd_ctl_add(card, kctl);1525 if (err < 0)1526 return err;1527 }1528 1529 return 0;1530}1531 1532/*------------------------------------------------------------1533 /proc interface 1534 ------------------------------------------------------------*/1535 1536static void1537snd_rme9652_proc_read(struct snd_info_entry *entry, struct snd_info_buffer *buffer)1538{1539 struct snd_rme9652 *rme9652 = (struct snd_rme9652 *) entry->private_data;1540 u32 thru_bits = rme9652->thru_bits;1541 int show_auto_sync_source = 0;1542 int i;1543 unsigned int status;1544 int x;1545 1546 status = rme9652_read(rme9652, RME9652_status_register);1547 1548 snd_iprintf(buffer, "%s (Card #%d)\n", rme9652->card_name, rme9652->card->number + 1);1549 snd_iprintf(buffer, "Buffers: capture %p playback %p\n",1550 rme9652->capture_buffer, rme9652->playback_buffer);1551 snd_iprintf(buffer, "IRQ: %d Registers bus: 0x%lx VM: 0x%lx\n",1552 rme9652->irq, rme9652->port, (unsigned long)rme9652->iobase);1553 snd_iprintf(buffer, "Control register: %x\n", rme9652->control_register);1554 1555 snd_iprintf(buffer, "\n");1556 1557 x = 1 << (6 + rme9652_decode_latency(rme9652->control_register & 1558 RME9652_latency));1559 1560 snd_iprintf(buffer, "Latency: %d samples (2 periods of %lu bytes)\n", 1561 x, (unsigned long) rme9652->period_bytes);1562 snd_iprintf(buffer, "Hardware pointer (frames): %ld\n",1563 rme9652_hw_pointer(rme9652));1564 snd_iprintf(buffer, "Passthru: %s\n",1565 rme9652->passthru ? "yes" : "no");1566 1567 if ((rme9652->control_register & (RME9652_Master | RME9652_wsel)) == 0) {1568 snd_iprintf(buffer, "Clock mode: autosync\n");1569 show_auto_sync_source = 1;1570 } else if (rme9652->control_register & RME9652_wsel) {1571 if (status & RME9652_wsel_rd) {1572 snd_iprintf(buffer, "Clock mode: word clock\n");1573 } else {1574 snd_iprintf(buffer, "Clock mode: word clock (no signal)\n");1575 }1576 } else {1577 snd_iprintf(buffer, "Clock mode: master\n");1578 }1579 1580 if (show_auto_sync_source) {1581 switch (rme9652->control_register & RME9652_SyncPref_Mask) {1582 case RME9652_SyncPref_ADAT1:1583 snd_iprintf(buffer, "Pref. sync source: ADAT1\n");1584 break;1585 case RME9652_SyncPref_ADAT2:1586 snd_iprintf(buffer, "Pref. sync source: ADAT2\n");1587 break;1588 case RME9652_SyncPref_ADAT3:1589 snd_iprintf(buffer, "Pref. sync source: ADAT3\n");1590 break;1591 case RME9652_SyncPref_SPDIF:1592 snd_iprintf(buffer, "Pref. sync source: IEC958\n");1593 break;1594 default:1595 snd_iprintf(buffer, "Pref. sync source: ???\n");1596 }1597 }1598 1599 if (rme9652->hw_rev >= 15)1600 snd_iprintf(buffer, "\nADAT1 Input source: %s\n",1601 (rme9652->control_register & RME9652_ADAT1_INTERNAL) ?1602 "Internal" : "ADAT1 optical");1603 1604 snd_iprintf(buffer, "\n");1605 1606 switch (rme9652_decode_spdif_in(rme9652->control_register & 1607 RME9652_inp)) {1608 case RME9652_SPDIFIN_OPTICAL:1609 snd_iprintf(buffer, "IEC958 input: ADAT1\n");1610 break;1611 case RME9652_SPDIFIN_COAXIAL:1612 snd_iprintf(buffer, "IEC958 input: Coaxial\n");1613 break;1614 case RME9652_SPDIFIN_INTERN:1615 snd_iprintf(buffer, "IEC958 input: Internal\n");1616 break;1617 default:1618 snd_iprintf(buffer, "IEC958 input: ???\n");1619 break;1620 }1621 1622 if (rme9652->control_register & RME9652_opt_out) {1623 snd_iprintf(buffer, "IEC958 output: Coaxial & ADAT1\n");1624 } else {1625 snd_iprintf(buffer, "IEC958 output: Coaxial only\n");1626 }1627 1628 if (rme9652->control_register & RME9652_PRO) {1629 snd_iprintf(buffer, "IEC958 quality: Professional\n");1630 } else {1631 snd_iprintf(buffer, "IEC958 quality: Consumer\n");1632 }1633 1634 if (rme9652->control_register & RME9652_EMP) {1635 snd_iprintf(buffer, "IEC958 emphasis: on\n");1636 } else {1637 snd_iprintf(buffer, "IEC958 emphasis: off\n");1638 }1639 1640 if (rme9652->control_register & RME9652_Dolby) {1641 snd_iprintf(buffer, "IEC958 Dolby: on\n");1642 } else {1643 snd_iprintf(buffer, "IEC958 Dolby: off\n");1644 }1645 1646 i = rme9652_spdif_sample_rate(rme9652);1647 1648 if (i < 0) {1649 snd_iprintf(buffer,1650 "IEC958 sample rate: error flag set\n");1651 } else if (i == 0) {1652 snd_iprintf(buffer, "IEC958 sample rate: undetermined\n");1653 } else {1654 snd_iprintf(buffer, "IEC958 sample rate: %d\n", i);1655 }1656 1657 snd_iprintf(buffer, "\n");1658 1659 snd_iprintf(buffer, "ADAT Sample rate: %dHz\n",1660 rme9652_adat_sample_rate(rme9652));1661 1662 /* Sync Check */1663 1664 x = status & RME9652_sync_0;1665 if (status & RME9652_lock_0) {1666 snd_iprintf(buffer, "ADAT1: %s\n", x ? "Sync" : "Lock");1667 } else {1668 snd_iprintf(buffer, "ADAT1: No Lock\n");1669 }1670 1671 x = status & RME9652_sync_1;1672 if (status & RME9652_lock_1) {1673 snd_iprintf(buffer, "ADAT2: %s\n", x ? "Sync" : "Lock");1674 } else {1675 snd_iprintf(buffer, "ADAT2: No Lock\n");1676 }1677 1678 x = status & RME9652_sync_2;1679 if (status & RME9652_lock_2) {1680 snd_iprintf(buffer, "ADAT3: %s\n", x ? "Sync" : "Lock");1681 } else {1682 snd_iprintf(buffer, "ADAT3: No Lock\n");1683 }1684 1685 snd_iprintf(buffer, "\n");1686 1687 snd_iprintf(buffer, "Timecode signal: %s\n",1688 (status & RME9652_tc_valid) ? "yes" : "no");1689 1690 /* thru modes */1691 1692 snd_iprintf(buffer, "Punch Status:\n\n");1693 1694 for (i = 0; i < rme9652->ss_channels; i++) {1695 if (thru_bits & (1 << i)) {1696 snd_iprintf(buffer, "%2d: on ", i + 1);1697 } else {1698 snd_iprintf(buffer, "%2d: off ", i + 1);1699 }1700 1701 if (((i + 1) % 8) == 0) {1702 snd_iprintf(buffer, "\n");1703 }1704 }1705 1706 snd_iprintf(buffer, "\n");1707}1708 1709static void snd_rme9652_proc_init(struct snd_rme9652 *rme9652)1710{1711 snd_card_ro_proc_new(rme9652->card, "rme9652", rme9652,1712 snd_rme9652_proc_read);1713}1714 1715static void snd_rme9652_card_free(struct snd_card *card)1716{1717 struct snd_rme9652 *rme9652 = (struct snd_rme9652 *) card->private_data;1718 1719 if (rme9652->irq >= 0)1720 rme9652_stop(rme9652);1721}1722 1723static int snd_rme9652_initialize_memory(struct snd_rme9652 *rme9652)1724{1725 struct snd_dma_buffer *capture_dma, *playback_dma;1726 1727 capture_dma = snd_hammerfall_get_buffer(rme9652->pci, RME9652_DMA_AREA_BYTES);1728 playback_dma = snd_hammerfall_get_buffer(rme9652->pci, RME9652_DMA_AREA_BYTES);1729 if (!capture_dma || !playback_dma) {1730 dev_err(rme9652->card->dev,1731 "%s: no buffers available\n", rme9652->card_name);1732 return -ENOMEM;1733 }1734 1735 /* copy to the own data for alignment */1736 rme9652->capture_dma_buf = *capture_dma;1737 rme9652->playback_dma_buf = *playback_dma;1738 1739 /* Align to bus-space 64K boundary */1740 rme9652->capture_dma_buf.addr = ALIGN(capture_dma->addr, 0x10000ul);1741 rme9652->playback_dma_buf.addr = ALIGN(playback_dma->addr, 0x10000ul);1742 1743 /* Tell the card where it is */1744 rme9652_write(rme9652, RME9652_rec_buffer, rme9652->capture_dma_buf.addr);1745 rme9652_write(rme9652, RME9652_play_buffer, rme9652->playback_dma_buf.addr);1746 1747 rme9652->capture_dma_buf.area += rme9652->capture_dma_buf.addr - capture_dma->addr;1748 rme9652->playback_dma_buf.area += rme9652->playback_dma_buf.addr - playback_dma->addr;1749 rme9652->capture_buffer = rme9652->capture_dma_buf.area;1750 rme9652->playback_buffer = rme9652->playback_dma_buf.area;1751 1752 return 0;1753}1754 1755static void snd_rme9652_set_defaults(struct snd_rme9652 *rme9652)1756{1757 unsigned int k;1758 1759 /* ASSUMPTION: rme9652->lock is either held, or1760 there is no need to hold it (e.g. during module1761 initialization).1762 */1763 1764 /* set defaults:1765 1766 SPDIF Input via Coax 1767 autosync clock mode1768 maximum latency (7 = 8192 samples, 64Kbyte buffer,1769 which implies 2 4096 sample, 32Kbyte periods).1770 1771 if rev 1.5, initialize the S/PDIF receiver.1772 1773 */1774 1775 rme9652->control_register =1776 RME9652_inp_0 | rme9652_encode_latency(7);1777 1778 rme9652_write(rme9652, RME9652_control_register, rme9652->control_register);1779 1780 rme9652_reset_hw_pointer(rme9652);1781 rme9652_compute_period_size(rme9652);1782 1783 /* default: thru off for all channels */1784 1785 for (k = 0; k < RME9652_NCHANNELS; ++k)1786 rme9652_write(rme9652, RME9652_thru_base + k * 4, 0);1787 1788 rme9652->thru_bits = 0;1789 rme9652->passthru = 0;1790 1791 /* set a default rate so that the channel map is set up */1792 1793 rme9652_set_rate(rme9652, 48000);1794}1795 1796static irqreturn_t snd_rme9652_interrupt(int irq, void *dev_id)1797{1798 struct snd_rme9652 *rme9652 = (struct snd_rme9652 *) dev_id;1799 1800 if (!(rme9652_read(rme9652, RME9652_status_register) & RME9652_IRQ)) {1801 return IRQ_NONE;1802 }1803 1804 rme9652_write(rme9652, RME9652_irq_clear, 0);1805 1806 if (rme9652->capture_substream) {1807 snd_pcm_period_elapsed(rme9652->pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream);1808 }1809 1810 if (rme9652->playback_substream) {1811 snd_pcm_period_elapsed(rme9652->pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream);1812 }1813 return IRQ_HANDLED;1814}1815 1816static snd_pcm_uframes_t snd_rme9652_hw_pointer(struct snd_pcm_substream *substream)1817{1818 struct snd_rme9652 *rme9652 = snd_pcm_substream_chip(substream);1819 return rme9652_hw_pointer(rme9652);1820}1821 1822static signed char *rme9652_channel_buffer_location(struct snd_rme9652 *rme9652,1823 int stream,1824 int channel)1825 1826{1827 int mapped_channel;1828 1829 if (snd_BUG_ON(channel < 0 || channel >= RME9652_NCHANNELS))1830 return NULL;1831 1832 mapped_channel = rme9652->channel_map[channel];1833 if (mapped_channel < 0)1834 return NULL;1835 1836 if (stream == SNDRV_PCM_STREAM_CAPTURE) {1837 return rme9652->capture_buffer +1838 (mapped_channel * RME9652_CHANNEL_BUFFER_BYTES);1839 } else {1840 return rme9652->playback_buffer +1841 (mapped_channel * RME9652_CHANNEL_BUFFER_BYTES);1842 }1843}1844 1845static int snd_rme9652_playback_copy(struct snd_pcm_substream *substream,1846 int channel, unsigned long pos,1847 struct iov_iter *src, unsigned long count)1848{1849 struct snd_rme9652 *rme9652 = snd_pcm_substream_chip(substream);1850 signed char *channel_buf;1851 1852 if (snd_BUG_ON(pos + count > RME9652_CHANNEL_BUFFER_BYTES))1853 return -EINVAL;1854 1855 channel_buf = rme9652_channel_buffer_location (rme9652,1856 substream->pstr->stream,1857 channel);1858 if (snd_BUG_ON(!channel_buf))1859 return -EIO;1860 if (copy_from_iter(channel_buf + pos, count, src) != count)1861 return -EFAULT;1862 return 0;1863}1864 1865static int snd_rme9652_capture_copy(struct snd_pcm_substream *substream,1866 int channel, unsigned long pos,1867 struct iov_iter *dst, unsigned long count)1868{1869 struct snd_rme9652 *rme9652 = snd_pcm_substream_chip(substream);1870 signed char *channel_buf;1871 1872 if (snd_BUG_ON(pos + count > RME9652_CHANNEL_BUFFER_BYTES))1873 return -EINVAL;1874 1875 channel_buf = rme9652_channel_buffer_location (rme9652,1876 substream->pstr->stream,1877 channel);1878 if (snd_BUG_ON(!channel_buf))1879 return -EIO;1880 if (copy_to_iter(channel_buf + pos, count, dst) != count)1881 return -EFAULT;1882 return 0;1883}1884 1885static int snd_rme9652_hw_silence(struct snd_pcm_substream *substream,1886 int channel, unsigned long pos,1887 unsigned long count)1888{1889 struct snd_rme9652 *rme9652 = snd_pcm_substream_chip(substream);1890 signed char *channel_buf;1891 1892 channel_buf = rme9652_channel_buffer_location (rme9652,1893 substream->pstr->stream,1894 channel);1895 if (snd_BUG_ON(!channel_buf))1896 return -EIO;1897 memset(channel_buf + pos, 0, count);1898 return 0;1899}1900 1901static int snd_rme9652_reset(struct snd_pcm_substream *substream)1902{1903 struct snd_pcm_runtime *runtime = substream->runtime;1904 struct snd_rme9652 *rme9652 = snd_pcm_substream_chip(substream);1905 struct snd_pcm_substream *other;1906 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)1907 other = rme9652->capture_substream;1908 else1909 other = rme9652->playback_substream;1910 if (rme9652->running)1911 runtime->status->hw_ptr = rme9652_hw_pointer(rme9652);1912 else1913 runtime->status->hw_ptr = 0;1914 if (other) {1915 struct snd_pcm_substream *s;1916 struct snd_pcm_runtime *oruntime = other->runtime;1917 snd_pcm_group_for_each_entry(s, substream) {1918 if (s == other) {1919 oruntime->status->hw_ptr = runtime->status->hw_ptr;1920 break;1921 }1922 }1923 }1924 return 0;1925}1926 1927static int snd_rme9652_hw_params(struct snd_pcm_substream *substream,1928 struct snd_pcm_hw_params *params)1929{1930 struct snd_rme9652 *rme9652 = snd_pcm_substream_chip(substream);1931 int err;1932 pid_t this_pid;1933 pid_t other_pid;1934 1935 spin_lock_irq(&rme9652->lock);1936 1937 if (substream->pstr->stream == SNDRV_PCM_STREAM_PLAYBACK) {1938 rme9652->control_register &= ~(RME9652_PRO | RME9652_Dolby | RME9652_EMP);1939 rme9652_write(rme9652, RME9652_control_register, rme9652->control_register |= rme9652->creg_spdif_stream);1940 this_pid = rme9652->playback_pid;1941 other_pid = rme9652->capture_pid;1942 } else {1943 this_pid = rme9652->capture_pid;1944 other_pid = rme9652->playback_pid;1945 }1946 1947 if ((other_pid > 0) && (this_pid != other_pid)) {1948 1949 /* The other stream is open, and not by the same1950 task as this one. Make sure that the parameters1951 that matter are the same.1952 */1953 1954 if ((int)params_rate(params) !=1955 rme9652_adat_sample_rate(rme9652)) {1956 spin_unlock_irq(&rme9652->lock);1957 _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_RATE);1958 return -EBUSY;1959 }1960 1961 if (params_period_size(params) != rme9652->period_bytes / 4) {1962 spin_unlock_irq(&rme9652->lock);1963 _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_PERIOD_SIZE);1964 return -EBUSY;1965 }1966 1967 /* We're fine. */1968 1969 spin_unlock_irq(&rme9652->lock);1970 return 0;1971 1972 } else {1973 spin_unlock_irq(&rme9652->lock);1974 }1975 1976 /* how to make sure that the rate matches an externally-set one ?1977 */1978 1979 err = rme9652_set_rate(rme9652, params_rate(params));1980 if (err < 0) {1981 _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_RATE);1982 return err;1983 }1984 1985 err = rme9652_set_interrupt_interval(rme9652, params_period_size(params));1986 if (err < 0) {1987 _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_PERIOD_SIZE);1988 return err;1989 }1990 1991 return 0;1992}1993 1994static int snd_rme9652_channel_info(struct snd_pcm_substream *substream,1995 struct snd_pcm_channel_info *info)1996{1997 struct snd_rme9652 *rme9652 = snd_pcm_substream_chip(substream);1998 int chn;1999 2000 if (snd_BUG_ON(info->channel >= RME9652_NCHANNELS))2001 return -EINVAL;2002 2003 chn = rme9652->channel_map[array_index_nospec(info->channel,2004 RME9652_NCHANNELS)];2005 if (chn < 0)2006 return -EINVAL;2007 2008 info->offset = chn * RME9652_CHANNEL_BUFFER_BYTES;2009 info->first = 0;2010 info->step = 32;2011 return 0;2012}2013 2014static int snd_rme9652_ioctl(struct snd_pcm_substream *substream,2015 unsigned int cmd, void *arg)2016{2017 switch (cmd) {2018 case SNDRV_PCM_IOCTL1_RESET:2019 {2020 return snd_rme9652_reset(substream);2021 }2022 case SNDRV_PCM_IOCTL1_CHANNEL_INFO:2023 {2024 struct snd_pcm_channel_info *info = arg;2025 return snd_rme9652_channel_info(substream, info);2026 }2027 default:2028 break;2029 }2030 2031 return snd_pcm_lib_ioctl(substream, cmd, arg);2032}2033 2034static void rme9652_silence_playback(struct snd_rme9652 *rme9652)2035{2036 memset(rme9652->playback_buffer, 0, RME9652_DMA_AREA_BYTES);2037}2038 2039static int snd_rme9652_trigger(struct snd_pcm_substream *substream,2040 int cmd)2041{2042 struct snd_rme9652 *rme9652 = snd_pcm_substream_chip(substream);2043 struct snd_pcm_substream *other;2044 int running;2045 spin_lock(&rme9652->lock);2046 running = rme9652->running;2047 switch (cmd) {2048 case SNDRV_PCM_TRIGGER_START:2049 running |= 1 << substream->stream;2050 break;2051 case SNDRV_PCM_TRIGGER_STOP:2052 running &= ~(1 << substream->stream);2053 break;2054 default:2055 snd_BUG();2056 spin_unlock(&rme9652->lock);2057 return -EINVAL;2058 }2059 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)2060 other = rme9652->capture_substream;2061 else2062 other = rme9652->playback_substream;2063 2064 if (other) {2065 struct snd_pcm_substream *s;2066 snd_pcm_group_for_each_entry(s, substream) {2067 if (s == other) {2068 snd_pcm_trigger_done(s, substream);2069 if (cmd == SNDRV_PCM_TRIGGER_START)2070 running |= 1 << s->stream;2071 else2072 running &= ~(1 << s->stream);2073 goto _ok;2074 }2075 }2076 if (cmd == SNDRV_PCM_TRIGGER_START) {2077 if (!(running & (1 << SNDRV_PCM_STREAM_PLAYBACK)) &&2078 substream->stream == SNDRV_PCM_STREAM_CAPTURE)2079 rme9652_silence_playback(rme9652);2080 } else {2081 if (running &&2082 substream->stream == SNDRV_PCM_STREAM_PLAYBACK)2083 rme9652_silence_playback(rme9652);2084 }2085 } else {2086 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) 2087 rme9652_silence_playback(rme9652);2088 }2089 _ok:2090 snd_pcm_trigger_done(substream, substream);2091 if (!rme9652->running && running)2092 rme9652_start(rme9652);2093 else if (rme9652->running && !running)2094 rme9652_stop(rme9652);2095 rme9652->running = running;2096 spin_unlock(&rme9652->lock);2097 2098 return 0;2099}2100 2101static int snd_rme9652_prepare(struct snd_pcm_substream *substream)2102{2103 struct snd_rme9652 *rme9652 = snd_pcm_substream_chip(substream);2104 unsigned long flags;2105 2106 spin_lock_irqsave(&rme9652->lock, flags);2107 if (!rme9652->running)2108 rme9652_reset_hw_pointer(rme9652);2109 spin_unlock_irqrestore(&rme9652->lock, flags);2110 return 0;2111}2112 2113static const struct snd_pcm_hardware snd_rme9652_playback_subinfo =2114{2115 .info = (SNDRV_PCM_INFO_MMAP |2116 SNDRV_PCM_INFO_MMAP_VALID |2117 SNDRV_PCM_INFO_NONINTERLEAVED |2118 SNDRV_PCM_INFO_SYNC_START |2119 SNDRV_PCM_INFO_DOUBLE),2120 .formats = SNDRV_PCM_FMTBIT_S32_LE,2121 .rates = (SNDRV_PCM_RATE_44100 | 2122 SNDRV_PCM_RATE_48000 | 2123 SNDRV_PCM_RATE_88200 | 2124 SNDRV_PCM_RATE_96000),2125 .rate_min = 44100,2126 .rate_max = 96000,2127 .channels_min = 10,2128 .channels_max = 26,2129 .buffer_bytes_max = RME9652_CHANNEL_BUFFER_BYTES * 26,2130 .period_bytes_min = (64 * 4) * 10,2131 .period_bytes_max = (8192 * 4) * 26,2132 .periods_min = 2,2133 .periods_max = 2,2134 .fifo_size = 0,2135};2136 2137static const struct snd_pcm_hardware snd_rme9652_capture_subinfo =2138{2139 .info = (SNDRV_PCM_INFO_MMAP |2140 SNDRV_PCM_INFO_MMAP_VALID |2141 SNDRV_PCM_INFO_NONINTERLEAVED |2142 SNDRV_PCM_INFO_SYNC_START),2143 .formats = SNDRV_PCM_FMTBIT_S32_LE,2144 .rates = (SNDRV_PCM_RATE_44100 | 2145 SNDRV_PCM_RATE_48000 | 2146 SNDRV_PCM_RATE_88200 | 2147 SNDRV_PCM_RATE_96000),2148 .rate_min = 44100,2149 .rate_max = 96000,2150 .channels_min = 10,2151 .channels_max = 26,2152 .buffer_bytes_max = RME9652_CHANNEL_BUFFER_BYTES *26,2153 .period_bytes_min = (64 * 4) * 10,2154 .period_bytes_max = (8192 * 4) * 26,2155 .periods_min = 2,2156 .periods_max = 2,2157 .fifo_size = 0,2158};2159 2160static const unsigned int period_sizes[] = { 64, 128, 256, 512, 1024, 2048, 4096, 8192 };2161 2162static const struct snd_pcm_hw_constraint_list hw_constraints_period_sizes = {2163 .count = ARRAY_SIZE(period_sizes),2164 .list = period_sizes,2165 .mask = 02166};2167 2168static int snd_rme9652_hw_rule_channels(struct snd_pcm_hw_params *params,2169 struct snd_pcm_hw_rule *rule)2170{2171 struct snd_rme9652 *rme9652 = rule->private;2172 struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);2173 unsigned int list[2] = { rme9652->ds_channels, rme9652->ss_channels };2174 return snd_interval_list(c, 2, list, 0);2175}2176 2177static int snd_rme9652_hw_rule_channels_rate(struct snd_pcm_hw_params *params,2178 struct snd_pcm_hw_rule *rule)2179{2180 struct snd_rme9652 *rme9652 = rule->private;2181 struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);2182 struct snd_interval *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);2183 if (r->min > 48000) {2184 struct snd_interval t = {2185 .min = rme9652->ds_channels,2186 .max = rme9652->ds_channels,2187 .integer = 1,2188 };2189 return snd_interval_refine(c, &t);2190 } else if (r->max < 88200) {2191 struct snd_interval t = {2192 .min = rme9652->ss_channels,2193 .max = rme9652->ss_channels,2194 .integer = 1,2195 };2196 return snd_interval_refine(c, &t);2197 }2198 return 0;2199}2200 2201static int snd_rme9652_hw_rule_rate_channels(struct snd_pcm_hw_params *params,2202 struct snd_pcm_hw_rule *rule)2203{2204 struct snd_rme9652 *rme9652 = rule->private;2205 struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);2206 struct snd_interval *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);2207 if (c->min >= rme9652->ss_channels) {2208 struct snd_interval t = {2209 .min = 44100,2210 .max = 48000,2211 .integer = 1,2212 };2213 return snd_interval_refine(r, &t);2214 } else if (c->max <= rme9652->ds_channels) {2215 struct snd_interval t = {2216 .min = 88200,2217 .max = 96000,2218 .integer = 1,2219 };2220 return snd_interval_refine(r, &t);2221 }2222 return 0;2223}2224 2225static int snd_rme9652_playback_open(struct snd_pcm_substream *substream)2226{2227 struct snd_rme9652 *rme9652 = snd_pcm_substream_chip(substream);2228 struct snd_pcm_runtime *runtime = substream->runtime;2229 2230 spin_lock_irq(&rme9652->lock);2231 2232 snd_pcm_set_sync(substream);2233 2234 runtime->hw = snd_rme9652_playback_subinfo;2235 snd_pcm_set_runtime_buffer(substream, &rme9652->playback_dma_buf);2236 2237 if (rme9652->capture_substream == NULL) {2238 rme9652_stop(rme9652);2239 rme9652_set_thru(rme9652, -1, 0);2240 }2241 2242 rme9652->playback_pid = current->pid;2243 rme9652->playback_substream = substream;2244 2245 spin_unlock_irq(&rme9652->lock);2246 2247 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);2248 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE, &hw_constraints_period_sizes);2249 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,2250 snd_rme9652_hw_rule_channels, rme9652,2251 SNDRV_PCM_HW_PARAM_CHANNELS, -1);2252 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,2253 snd_rme9652_hw_rule_channels_rate, rme9652,2254 SNDRV_PCM_HW_PARAM_RATE, -1);2255 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,2256 snd_rme9652_hw_rule_rate_channels, rme9652,2257 SNDRV_PCM_HW_PARAM_CHANNELS, -1);2258 2259 rme9652->creg_spdif_stream = rme9652->creg_spdif;2260 rme9652->spdif_ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;2261 snd_ctl_notify(rme9652->card, SNDRV_CTL_EVENT_MASK_VALUE |2262 SNDRV_CTL_EVENT_MASK_INFO, &rme9652->spdif_ctl->id);2263 return 0;2264}2265 2266static int snd_rme9652_playback_release(struct snd_pcm_substream *substream)2267{2268 struct snd_rme9652 *rme9652 = snd_pcm_substream_chip(substream);2269 2270 spin_lock_irq(&rme9652->lock);2271 2272 rme9652->playback_pid = -1;2273 rme9652->playback_substream = NULL;2274 2275 spin_unlock_irq(&rme9652->lock);2276 2277 rme9652->spdif_ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;2278 snd_ctl_notify(rme9652->card, SNDRV_CTL_EVENT_MASK_VALUE |2279 SNDRV_CTL_EVENT_MASK_INFO, &rme9652->spdif_ctl->id);2280 return 0;2281}2282 2283 2284static int snd_rme9652_capture_open(struct snd_pcm_substream *substream)2285{2286 struct snd_rme9652 *rme9652 = snd_pcm_substream_chip(substream);2287 struct snd_pcm_runtime *runtime = substream->runtime;2288 2289 spin_lock_irq(&rme9652->lock);2290 2291 snd_pcm_set_sync(substream);2292 2293 runtime->hw = snd_rme9652_capture_subinfo;2294 snd_pcm_set_runtime_buffer(substream, &rme9652->capture_dma_buf);2295 2296 if (rme9652->playback_substream == NULL) {2297 rme9652_stop(rme9652);2298 rme9652_set_thru(rme9652, -1, 0);2299 }2300 2301 rme9652->capture_pid = current->pid;2302 rme9652->capture_substream = substream;2303 2304 spin_unlock_irq(&rme9652->lock);2305 2306 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);2307 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE, &hw_constraints_period_sizes);2308 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,2309 snd_rme9652_hw_rule_channels, rme9652,2310 SNDRV_PCM_HW_PARAM_CHANNELS, -1);2311 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,2312 snd_rme9652_hw_rule_channels_rate, rme9652,2313 SNDRV_PCM_HW_PARAM_RATE, -1);2314 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,2315 snd_rme9652_hw_rule_rate_channels, rme9652,2316 SNDRV_PCM_HW_PARAM_CHANNELS, -1);2317 return 0;2318}2319 2320static int snd_rme9652_capture_release(struct snd_pcm_substream *substream)2321{2322 struct snd_rme9652 *rme9652 = snd_pcm_substream_chip(substream);2323 2324 spin_lock_irq(&rme9652->lock);2325 2326 rme9652->capture_pid = -1;2327 rme9652->capture_substream = NULL;2328 2329 spin_unlock_irq(&rme9652->lock);2330 return 0;2331}2332 2333static const struct snd_pcm_ops snd_rme9652_playback_ops = {2334 .open = snd_rme9652_playback_open,2335 .close = snd_rme9652_playback_release,2336 .ioctl = snd_rme9652_ioctl,2337 .hw_params = snd_rme9652_hw_params,2338 .prepare = snd_rme9652_prepare,2339 .trigger = snd_rme9652_trigger,2340 .pointer = snd_rme9652_hw_pointer,2341 .copy = snd_rme9652_playback_copy,2342 .fill_silence = snd_rme9652_hw_silence,2343};2344 2345static const struct snd_pcm_ops snd_rme9652_capture_ops = {2346 .open = snd_rme9652_capture_open,2347 .close = snd_rme9652_capture_release,2348 .ioctl = snd_rme9652_ioctl,2349 .hw_params = snd_rme9652_hw_params,2350 .prepare = snd_rme9652_prepare,2351 .trigger = snd_rme9652_trigger,2352 .pointer = snd_rme9652_hw_pointer,2353 .copy = snd_rme9652_capture_copy,2354};2355 2356static int snd_rme9652_create_pcm(struct snd_card *card,2357 struct snd_rme9652 *rme9652)2358{2359 struct snd_pcm *pcm;2360 int err;2361 2362 err = snd_pcm_new(card, rme9652->card_name, 0, 1, 1, &pcm);2363 if (err < 0)2364 return err;2365 2366 rme9652->pcm = pcm;2367 pcm->private_data = rme9652;2368 strcpy(pcm->name, rme9652->card_name);2369 2370 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_rme9652_playback_ops);2371 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_rme9652_capture_ops);2372 2373 pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX;2374 2375 return 0;2376}2377 2378static int snd_rme9652_create(struct snd_card *card,2379 struct snd_rme9652 *rme9652,2380 int precise_ptr)2381{2382 struct pci_dev *pci = rme9652->pci;2383 int err;2384 int status;2385 unsigned short rev;2386 2387 rme9652->irq = -1;2388 rme9652->card = card;2389 2390 pci_read_config_word(rme9652->pci, PCI_CLASS_REVISION, &rev);2391 2392 switch (rev & 0xff) {2393 case 3:2394 case 4:2395 case 8:2396 case 9:2397 break;2398 2399 default:2400 /* who knows? */2401 return -ENODEV;2402 }2403 2404 err = pcim_enable_device(pci);2405 if (err < 0)2406 return err;2407 2408 spin_lock_init(&rme9652->lock);2409 2410 err = pci_request_regions(pci, "rme9652");2411 if (err < 0)2412 return err;2413 rme9652->port = pci_resource_start(pci, 0);2414 rme9652->iobase = devm_ioremap(&pci->dev, rme9652->port, RME9652_IO_EXTENT);2415 if (rme9652->iobase == NULL) {2416 dev_err(card->dev, "unable to remap region 0x%lx-0x%lx\n",2417 rme9652->port, rme9652->port + RME9652_IO_EXTENT - 1);2418 return -EBUSY;2419 }2420 2421 if (devm_request_irq(&pci->dev, pci->irq, snd_rme9652_interrupt,2422 IRQF_SHARED, KBUILD_MODNAME, rme9652)) {2423 dev_err(card->dev, "unable to request IRQ %d\n", pci->irq);2424 return -EBUSY;2425 }2426 rme9652->irq = pci->irq;2427 card->sync_irq = rme9652->irq;2428 rme9652->precise_ptr = precise_ptr;2429 2430 /* Determine the h/w rev level of the card. This seems like2431 a particularly kludgy way to encode it, but its what RME2432 chose to do, so we follow them ...2433 */2434 2435 status = rme9652_read(rme9652, RME9652_status_register);2436 if (rme9652_decode_spdif_rate(status&RME9652_F) == 1) {2437 rme9652->hw_rev = 15;2438 } else {2439 rme9652->hw_rev = 11;2440 }2441 2442 /* Differentiate between the standard Hammerfall, and the2443 "Light", which does not have the expansion board. This2444 method comes from information received from Mathhias2445 Clausen at RME. Display the EEPROM and h/w revID where2446 relevant. 2447 */2448 2449 switch (rev) {2450 case 8: /* original eprom */2451 strcpy(card->driver, "RME9636");2452 if (rme9652->hw_rev == 15) {2453 rme9652->card_name = "RME Digi9636 (Rev 1.5)";2454 } else {2455 rme9652->card_name = "RME Digi9636";2456 }2457 rme9652->ss_channels = RME9636_NCHANNELS;2458 break;2459 case 9: /* W36_G EPROM */2460 strcpy(card->driver, "RME9636");2461 rme9652->card_name = "RME Digi9636 (Rev G)";2462 rme9652->ss_channels = RME9636_NCHANNELS;2463 break;2464 case 4: /* W52_G EPROM */2465 strcpy(card->driver, "RME9652");2466 rme9652->card_name = "RME Digi9652 (Rev G)";2467 rme9652->ss_channels = RME9652_NCHANNELS;2468 break;2469 case 3: /* original eprom */2470 strcpy(card->driver, "RME9652");2471 if (rme9652->hw_rev == 15) {2472 rme9652->card_name = "RME Digi9652 (Rev 1.5)";2473 } else {2474 rme9652->card_name = "RME Digi9652";2475 }2476 rme9652->ss_channels = RME9652_NCHANNELS;2477 break;2478 }2479 2480 rme9652->ds_channels = (rme9652->ss_channels - 2) / 2 + 2;2481 2482 pci_set_master(rme9652->pci);2483 2484 err = snd_rme9652_initialize_memory(rme9652);2485 if (err < 0)2486 return err;2487 2488 err = snd_rme9652_create_pcm(card, rme9652);2489 if (err < 0)2490 return err;2491 2492 err = snd_rme9652_create_controls(card, rme9652);2493 if (err < 0)2494 return err;2495 2496 snd_rme9652_proc_init(rme9652);2497 2498 rme9652->last_spdif_sample_rate = -1;2499 rme9652->last_adat_sample_rate = -1;2500 rme9652->playback_pid = -1;2501 rme9652->capture_pid = -1;2502 rme9652->capture_substream = NULL;2503 rme9652->playback_substream = NULL;2504 2505 snd_rme9652_set_defaults(rme9652);2506 2507 if (rme9652->hw_rev == 15) {2508 rme9652_initialize_spdif_receiver (rme9652);2509 }2510 2511 return 0;2512}2513 2514static int snd_rme9652_probe(struct pci_dev *pci,2515 const struct pci_device_id *pci_id)2516{2517 static int dev;2518 struct snd_rme9652 *rme9652;2519 struct snd_card *card;2520 int err;2521 2522 if (dev >= SNDRV_CARDS)2523 return -ENODEV;2524 if (!enable[dev]) {2525 dev++;2526 return -ENOENT;2527 }2528 2529 err = snd_devm_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,2530 sizeof(struct snd_rme9652), &card);2531 2532 if (err < 0)2533 return err;2534 2535 rme9652 = (struct snd_rme9652 *) card->private_data;2536 card->private_free = snd_rme9652_card_free;2537 rme9652->dev = dev;2538 rme9652->pci = pci;2539 err = snd_rme9652_create(card, rme9652, precise_ptr[dev]);2540 if (err)2541 goto error;2542 2543 strcpy(card->shortname, rme9652->card_name);2544 2545 sprintf(card->longname, "%s at 0x%lx, irq %d",2546 card->shortname, rme9652->port, rme9652->irq);2547 err = snd_card_register(card);2548 if (err)2549 goto error;2550 pci_set_drvdata(pci, card);2551 dev++;2552 return 0;2553 2554 error:2555 snd_card_free(card);2556 return err;2557}2558 2559static struct pci_driver rme9652_driver = {2560 .name = KBUILD_MODNAME,2561 .id_table = snd_rme9652_ids,2562 .probe = snd_rme9652_probe,2563};2564 2565module_pci_driver(rme9652_driver);2566