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1/* SPDX-License-Identifier: GPL-2.0-only */2#ifndef __sis7019_h__3#define __sis7019_h__4 5/*6 * Definitions for SiS7019 Audio Accelerator7 *8 * Copyright (C) 2004-2007, David Dillow9 * Written by David Dillow <dave@thedillows.org>10 * Inspired by the Trident 4D-WaveDX/NX driver.11 *12 * All rights reserved.13 */14 15 16/* General Control Register */17#define SIS_GCR 0x0018#define SIS_GCR_MACRO_POWER_DOWN 0x8000000019#define SIS_GCR_MODEM_ENABLE 0x0001000020#define SIS_GCR_SOFTWARE_RESET 0x0000000121 22/* General Interrupt Enable Register */23#define SIS_GIER 0x0424#define SIS_GIER_MODEM_TIMER_IRQ_ENABLE 0x0010000025#define SIS_GIER_MODEM_RX_DMA_IRQ_ENABLE 0x0008000026#define SIS_GIER_MODEM_TX_DMA_IRQ_ENABLE 0x0004000027#define SIS_GIER_AC97_GPIO1_IRQ_ENABLE 0x0002000028#define SIS_GIER_AC97_GPIO0_IRQ_ENABLE 0x0001000029#define SIS_GIER_AC97_SAMPLE_TIMER_IRQ_ENABLE 0x0000001030#define SIS_GIER_AUDIO_GLOBAL_TIMER_IRQ_ENABLE 0x0000000831#define SIS_GIER_AUDIO_RECORD_DMA_IRQ_ENABLE 0x0000000432#define SIS_GIER_AUDIO_PLAY_DMA_IRQ_ENABLE 0x0000000233#define SIS_GIER_AUDIO_WAVE_ENGINE_IRQ_ENABLE 0x0000000134 35/* General Interrupt Status Register */36#define SIS_GISR 0x0837#define SIS_GISR_MODEM_TIMER_IRQ_STATUS 0x0010000038#define SIS_GISR_MODEM_RX_DMA_IRQ_STATUS 0x0008000039#define SIS_GISR_MODEM_TX_DMA_IRQ_STATUS 0x0004000040#define SIS_GISR_AC97_GPIO1_IRQ_STATUS 0x0002000041#define SIS_GISR_AC97_GPIO0_IRQ_STATUS 0x0001000042#define SIS_GISR_AC97_SAMPLE_TIMER_IRQ_STATUS 0x0000001043#define SIS_GISR_AUDIO_GLOBAL_TIMER_IRQ_STATUS 0x0000000844#define SIS_GISR_AUDIO_RECORD_DMA_IRQ_STATUS 0x0000000445#define SIS_GISR_AUDIO_PLAY_DMA_IRQ_STATUS 0x0000000246#define SIS_GISR_AUDIO_WAVE_ENGINE_IRQ_STATUS 0x0000000147 48/* DMA Control Register */49#define SIS_DMA_CSR 0x1050#define SIS_DMA_CSR_PCI_SETTINGS 0x0000001d51#define SIS_DMA_CSR_CONCURRENT_ENABLE 0x0000020052#define SIS_DMA_CSR_PIPELINE_ENABLE 0x0000010053#define SIS_DMA_CSR_RX_DRAIN_ENABLE 0x0000001054#define SIS_DMA_CSR_RX_FILL_ENABLE 0x0000000855#define SIS_DMA_CSR_TX_DRAIN_ENABLE 0x0000000456#define SIS_DMA_CSR_TX_LOWPRI_FILL_ENABLE 0x0000000257#define SIS_DMA_CSR_TX_HIPRI_FILL_ENABLE 0x0000000158 59/* Playback Channel Start Registers */60#define SIS_PLAY_START_A_REG 0x1461#define SIS_PLAY_START_B_REG 0x1862 63/* Playback Channel Stop Registers */64#define SIS_PLAY_STOP_A_REG 0x1c65#define SIS_PLAY_STOP_B_REG 0x2066 67/* Recording Channel Start Register */68#define SIS_RECORD_START_REG 0x2469 70/* Recording Channel Stop Register */71#define SIS_RECORD_STOP_REG 0x2872 73/* Playback Interrupt Status Registers */74#define SIS_PISR_A 0x2c75#define SIS_PISR_B 0x3076 77/* Recording Interrupt Status Register */78#define SIS_RISR 0x3479 80/* AC97 AC-link Playback Source Register */81#define SIS_AC97_PSR 0x4082#define SIS_AC97_PSR_MODEM_HEADSET_SRC_MIXER 0x0f00000083#define SIS_AC97_PSR_MODEM_LINE2_SRC_MIXER 0x00f0000084#define SIS_AC97_PSR_MODEM_LINE1_SRC_MIXER 0x000f000085#define SIS_AC97_PSR_PCM_LFR_SRC_MIXER 0x0000f00086#define SIS_AC97_PSR_PCM_SURROUND_SRC_MIXER 0x00000f0087#define SIS_AC97_PSR_PCM_CENTER_SRC_MIXER 0x000000f088#define SIS_AC97_PSR_PCM_LR_SRC_MIXER 0x0000000f89 90/* AC97 AC-link Command Register */91#define SIS_AC97_CMD 0x5092#define SIS_AC97_CMD_DATA_MASK 0xffff000093#define SIS_AC97_CMD_REG_MASK 0x0000ff0094#define SIS_AC97_CMD_CODEC3_READ 0x0000000d95#define SIS_AC97_CMD_CODEC3_WRITE 0x0000000c96#define SIS_AC97_CMD_CODEC2_READ 0x0000000b97#define SIS_AC97_CMD_CODEC2_WRITE 0x0000000a98#define SIS_AC97_CMD_CODEC_READ 0x0000000999#define SIS_AC97_CMD_CODEC_WRITE 0x00000008100#define SIS_AC97_CMD_CODEC_WARM_RESET 0x00000005101#define SIS_AC97_CMD_CODEC_COLD_RESET 0x00000004102#define SIS_AC97_CMD_DONE 0x00000000103 104/* AC97 AC-link Semaphore Register */105#define SIS_AC97_SEMA 0x54106#define SIS_AC97_SEMA_BUSY 0x00000001107#define SIS_AC97_SEMA_RELEASE 0x00000000108 109/* AC97 AC-link Status Register */110#define SIS_AC97_STATUS 0x58111#define SIS_AC97_STATUS_AUDIO_D2_INACT_SECS 0x03f00000112#define SIS_AC97_STATUS_MODEM_ALIVE 0x00002000113#define SIS_AC97_STATUS_AUDIO_ALIVE 0x00001000114#define SIS_AC97_STATUS_CODEC3_READY 0x00000400115#define SIS_AC97_STATUS_CODEC2_READY 0x00000200116#define SIS_AC97_STATUS_CODEC_READY 0x00000100117#define SIS_AC97_STATUS_WARM_RESET 0x00000080118#define SIS_AC97_STATUS_COLD_RESET 0x00000040119#define SIS_AC97_STATUS_POWERED_DOWN 0x00000020120#define SIS_AC97_STATUS_NORMAL 0x00000010121#define SIS_AC97_STATUS_READ_EXPIRED 0x00000004122#define SIS_AC97_STATUS_SEMAPHORE 0x00000002123#define SIS_AC97_STATUS_BUSY 0x00000001124 125/* AC97 AC-link Audio Configuration Register */126#define SIS_AC97_CONF 0x5c127#define SIS_AC97_CONF_AUDIO_ALIVE 0x80000000128#define SIS_AC97_CONF_WARM_RESET_ENABLE 0x40000000129#define SIS_AC97_CONF_PR6_ENABLE 0x20000000130#define SIS_AC97_CONF_PR5_ENABLE 0x10000000131#define SIS_AC97_CONF_PR4_ENABLE 0x08000000132#define SIS_AC97_CONF_PR3_ENABLE 0x04000000133#define SIS_AC97_CONF_PR2_PR7_ENABLE 0x02000000134#define SIS_AC97_CONF_PR0_PR1_ENABLE 0x01000000135#define SIS_AC97_CONF_AUTO_PM_ENABLE 0x00800000136#define SIS_AC97_CONF_PCM_LFE_ENABLE 0x00080000137#define SIS_AC97_CONF_PCM_SURROUND_ENABLE 0x00040000138#define SIS_AC97_CONF_PCM_CENTER_ENABLE 0x00020000139#define SIS_AC97_CONF_PCM_LR_ENABLE 0x00010000140#define SIS_AC97_CONF_PCM_CAP_MIC_ENABLE 0x00002000141#define SIS_AC97_CONF_PCM_CAP_LR_ENABLE 0x00001000142#define SIS_AC97_CONF_PCM_CAP_MIC_FROM_CODEC3 0x00000200143#define SIS_AC97_CONF_PCM_CAP_LR_FROM_CODEC3 0x00000100144#define SIS_AC97_CONF_CODEC3_PM_VRM 0x00000080145#define SIS_AC97_CONF_CODEC_PM_VRM 0x00000040146#define SIS_AC97_CONF_CODEC3_VRA_ENABLE 0x00000020147#define SIS_AC97_CONF_CODEC_VRA_ENABLE 0x00000010148#define SIS_AC97_CONF_CODEC3_PM_EAC 0x00000008149#define SIS_AC97_CONF_CODEC_PM_EAC 0x00000004150#define SIS_AC97_CONF_CODEC3_EXISTS 0x00000002151#define SIS_AC97_CONF_CODEC_EXISTS 0x00000001152 153/* Playback Channel Sync Group registers */154#define SIS_PLAY_SYNC_GROUP_A 0x80155#define SIS_PLAY_SYNC_GROUP_B 0x84156#define SIS_PLAY_SYNC_GROUP_C 0x88157#define SIS_PLAY_SYNC_GROUP_D 0x8c158#define SIS_MIXER_SYNC_GROUP 0x90159 160/* Wave Engine Config and Control Register */161#define SIS_WECCR 0xa0162#define SIS_WECCR_TESTMODE_MASK 0x00300000163#define SIS_WECCR_TESTMODE_NORMAL 0x00000000164#define SIS_WECCR_TESTMODE_BYPASS_NSO_ALPHA 0x00100000165#define SIS_WECCR_TESTMODE_BYPASS_FC 0x00200000166#define SIS_WECCR_TESTMODE_BYPASS_WOL 0x00300000167#define SIS_WECCR_RESONANCE_DELAY_MASK 0x00060000168#define SIS_WECCR_RESONANCE_DELAY_NONE 0x00000000169#define SIS_WECCR_RESONANCE_DELAY_FC_1F00 0x00020000170#define SIS_WECCR_RESONANCE_DELAY_FC_1E00 0x00040000171#define SIS_WECCR_RESONANCE_DELAY_FC_1C00 0x00060000172#define SIS_WECCR_IGNORE_CHANNEL_PARMS 0x00010000173#define SIS_WECCR_COMMAND_CHANNEL_ID_MASK 0x0003ff00174#define SIS_WECCR_COMMAND_MASK 0x00000007175#define SIS_WECCR_COMMAND_NONE 0x00000000176#define SIS_WECCR_COMMAND_DONE 0x00000000177#define SIS_WECCR_COMMAND_PAUSE 0x00000001178#define SIS_WECCR_COMMAND_TOGGLE_VEG 0x00000002179#define SIS_WECCR_COMMAND_TOGGLE_MEG 0x00000003180#define SIS_WECCR_COMMAND_TOGGLE_VEG_MEG 0x00000004181 182/* Wave Engine Volume Control Register */183#define SIS_WEVCR 0xa4184#define SIS_WEVCR_LEFT_MUSIC_ATTENUATION_MASK 0xff000000185#define SIS_WEVCR_RIGHT_MUSIC_ATTENUATION_MASK 0x00ff0000186#define SIS_WEVCR_LEFT_WAVE_ATTENUATION_MASK 0x0000ff00187#define SIS_WEVCR_RIGHT_WAVE_ATTENUATION_MASK 0x000000ff188 189/* Wave Engine Interrupt Status Registers */190#define SIS_WEISR_A 0xa8191#define SIS_WEISR_B 0xac192 193 194/* Playback DMA parameters (parameter RAM) */195#define SIS_PLAY_DMA_OFFSET 0x0000196#define SIS_PLAY_DMA_SIZE 0x10197#define SIS_PLAY_DMA_ADDR(addr, num) \198 ((num * SIS_PLAY_DMA_SIZE) + (addr) + SIS_PLAY_DMA_OFFSET)199 200#define SIS_PLAY_DMA_FORMAT_CSO 0x00201#define SIS_PLAY_DMA_FORMAT_UNSIGNED 0x00080000202#define SIS_PLAY_DMA_FORMAT_8BIT 0x00040000203#define SIS_PLAY_DMA_FORMAT_MONO 0x00020000204#define SIS_PLAY_DMA_CSO_MASK 0x0000ffff205#define SIS_PLAY_DMA_BASE 0x04206#define SIS_PLAY_DMA_CONTROL 0x08207#define SIS_PLAY_DMA_STOP_AT_SSO 0x04000000208#define SIS_PLAY_DMA_RELEASE 0x02000000209#define SIS_PLAY_DMA_LOOP 0x01000000210#define SIS_PLAY_DMA_INTR_AT_SSO 0x00080000211#define SIS_PLAY_DMA_INTR_AT_ESO 0x00040000212#define SIS_PLAY_DMA_INTR_AT_LEO 0x00020000213#define SIS_PLAY_DMA_INTR_AT_MLP 0x00010000214#define SIS_PLAY_DMA_LEO_MASK 0x0000ffff215#define SIS_PLAY_DMA_SSO_ESO 0x0c216#define SIS_PLAY_DMA_SSO_MASK 0xffff0000217#define SIS_PLAY_DMA_ESO_MASK 0x0000ffff218 219/* Capture DMA parameters (parameter RAM) */220#define SIS_CAPTURE_DMA_OFFSET 0x0800221#define SIS_CAPTURE_DMA_SIZE 0x10222#define SIS_CAPTURE_DMA_ADDR(addr, num) \223 ((num * SIS_CAPTURE_DMA_SIZE) + (addr) + SIS_CAPTURE_DMA_OFFSET)224 225#define SIS_CAPTURE_CHAN_MIXER_ROUTE_BACK_0 0226#define SIS_CAPTURE_CHAN_MIXER_ROUTE_BACK_1 1227#define SIS_CAPTURE_CHAN_MIXER_ROUTE_BACK_2 2228#define SIS_CAPTURE_CHAN_MIXER_ROUTE_BACK_3 3229#define SIS_CAPTURE_CHAN_MIXER_ROUTE_BACK_4 4230#define SIS_CAPTURE_CHAN_MIXER_ROUTE_BACK_5 5231#define SIS_CAPTURE_CHAN_MIXER_ROUTE_BACK_6 6232#define SIS_CAPTURE_CHAN_MIXER_ROUTE_BACK_7 7233#define SIS_CAPTURE_CHAN_MIXER_ROUTE_BACK_8 8234#define SIS_CAPTURE_CHAN_MIXER_ROUTE_BACK_9 9235#define SIS_CAPTURE_CHAN_MIXER_ROUTE_BACK_10 10236#define SIS_CAPTURE_CHAN_MIXER_ROUTE_BACK_11 11237#define SIS_CAPTURE_CHAN_MIXER_ROUTE_BACK_12 12238#define SIS_CAPTURE_CHAN_MIXER_ROUTE_BACK_13 13239#define SIS_CAPTURE_CHAN_MIXER_ROUTE_BACK_14 14240#define SIS_CAPTURE_CHAN_MIXER_ROUTE_BACK_15 15241#define SIS_CAPTURE_CHAN_AC97_PCM_IN 16242#define SIS_CAPTURE_CHAN_AC97_MIC_IN 17243#define SIS_CAPTURE_CHAN_AC97_LINE1_IN 18244#define SIS_CAPTURE_CHAN_AC97_LINE2_IN 19245#define SIS_CAPTURE_CHAN_AC97_HANDSE_IN 20246 247#define SIS_CAPTURE_DMA_FORMAT_CSO 0x00248#define SIS_CAPTURE_DMA_MONO_MODE_MASK 0xc0000000249#define SIS_CAPTURE_DMA_MONO_MODE_AVG 0x00000000250#define SIS_CAPTURE_DMA_MONO_MODE_LEFT 0x40000000251#define SIS_CAPTURE_DMA_MONO_MODE_RIGHT 0x80000000252#define SIS_CAPTURE_DMA_FORMAT_UNSIGNED 0x00080000253#define SIS_CAPTURE_DMA_FORMAT_8BIT 0x00040000254#define SIS_CAPTURE_DMA_FORMAT_MONO 0x00020000255#define SIS_CAPTURE_DMA_CSO_MASK 0x0000ffff256#define SIS_CAPTURE_DMA_BASE 0x04257#define SIS_CAPTURE_DMA_CONTROL 0x08258#define SIS_CAPTURE_DMA_STOP_AT_SSO 0x04000000259#define SIS_CAPTURE_DMA_RELEASE 0x02000000260#define SIS_CAPTURE_DMA_LOOP 0x01000000261#define SIS_CAPTURE_DMA_INTR_AT_LEO 0x00020000262#define SIS_CAPTURE_DMA_INTR_AT_MLP 0x00010000263#define SIS_CAPTURE_DMA_LEO_MASK 0x0000ffff264#define SIS_CAPTURE_DMA_RESERVED 0x0c265 266 267/* Mixer routing list start pointer (parameter RAM) */268#define SIS_MIXER_START_OFFSET 0x1000269#define SIS_MIXER_START_SIZE 0x04270#define SIS_MIXER_START_ADDR(addr, num) \271 ((num * SIS_MIXER_START_SIZE) + (addr) + SIS_MIXER_START_OFFSET)272 273#define SIS_MIXER_START_MASK 0x0000007f274 275/* Mixer routing table (parameter RAM) */276#define SIS_MIXER_OFFSET 0x1400277#define SIS_MIXER_SIZE 0x04278#define SIS_MIXER_ADDR(addr, num) \279 ((num * SIS_MIXER_SIZE) + (addr) + SIS_MIXER_OFFSET)280 281#define SIS_MIXER_RIGHT_ATTENUTATION_MASK 0xff000000282#define SIS_MIXER_RIGHT_NO_ATTEN 0xff000000283#define SIS_MIXER_LEFT_ATTENUTATION_MASK 0x00ff0000284#define SIS_MIXER_LEFT_NO_ATTEN 0x00ff0000285#define SIS_MIXER_NEXT_ENTRY_MASK 0x00007f00286#define SIS_MIXER_NEXT_ENTRY_NONE 0x00000000287#define SIS_MIXER_DEST_MASK 0x0000007f288#define SIS_MIXER_DEST_0 0x00000020289#define SIS_MIXER_DEST_1 0x00000021290#define SIS_MIXER_DEST_2 0x00000022291#define SIS_MIXER_DEST_3 0x00000023292#define SIS_MIXER_DEST_4 0x00000024293#define SIS_MIXER_DEST_5 0x00000025294#define SIS_MIXER_DEST_6 0x00000026295#define SIS_MIXER_DEST_7 0x00000027296#define SIS_MIXER_DEST_8 0x00000028297#define SIS_MIXER_DEST_9 0x00000029298#define SIS_MIXER_DEST_10 0x0000002a299#define SIS_MIXER_DEST_11 0x0000002b300#define SIS_MIXER_DEST_12 0x0000002c301#define SIS_MIXER_DEST_13 0x0000002d302#define SIS_MIXER_DEST_14 0x0000002e303#define SIS_MIXER_DEST_15 0x0000002f304 305/* Wave Engine Control Parameters (parameter RAM) */306#define SIS_WAVE_OFFSET 0x2000307#define SIS_WAVE_SIZE 0x40308#define SIS_WAVE_ADDR(addr, num) \309 ((num * SIS_WAVE_SIZE) + (addr) + SIS_WAVE_OFFSET)310 311#define SIS_WAVE_GENERAL 0x00312#define SIS_WAVE_GENERAL_WAVE_VOLUME 0x80000000313#define SIS_WAVE_GENERAL_MUSIC_VOLUME 0x00000000314#define SIS_WAVE_GENERAL_VOLUME_MASK 0x7f000000315#define SIS_WAVE_GENERAL_ARTICULATION 0x04316#define SIS_WAVE_GENERAL_ARTICULATION_DELTA_MASK 0x3fff0000317#define SIS_WAVE_ARTICULATION 0x08318#define SIS_WAVE_TIMER 0x0c319#define SIS_WAVE_GENERATOR 0x10320#define SIS_WAVE_CHANNEL_CONTROL 0x14321#define SIS_WAVE_CHANNEL_CONTROL_FIRST_SAMPLE 0x80000000322#define SIS_WAVE_CHANNEL_CONTROL_AMP_ENABLE 0x40000000323#define SIS_WAVE_CHANNEL_CONTROL_FILTER_ENABLE 0x20000000324#define SIS_WAVE_CHANNEL_CONTROL_INTERPOLATE_ENABLE 0x10000000325#define SIS_WAVE_LFO_EG_CONTROL 0x18326#define SIS_WAVE_LFO_EG_CONTROL_2 0x1c327#define SIS_WAVE_LFO_EG_CONTROL_3 0x20328#define SIS_WAVE_LFO_EG_CONTROL_4 0x24329 330#endif /* __sis7019_h__ */331