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1// SPDX-License-Identifier: GPL-2.0-only2/*3 * AMD ALSA SoC PCM Driver for ACP 2.x4 *5 * Copyright 2014-2015 Advanced Micro Devices, Inc.6 */7 8#include <linux/module.h>9#include <linux/delay.h>10#include <linux/io.h>11#include <linux/iopoll.h>12#include <linux/sizes.h>13#include <linux/pm_runtime.h>14 15#include <sound/soc.h>16#include <drm/amd_asic_type.h>17#include "acp.h"18 19#define DRV_NAME "acp_audio_dma"20 21#define PLAYBACK_MIN_NUM_PERIODS 222#define PLAYBACK_MAX_NUM_PERIODS 223#define PLAYBACK_MAX_PERIOD_SIZE 1638424#define PLAYBACK_MIN_PERIOD_SIZE 102425#define CAPTURE_MIN_NUM_PERIODS 226#define CAPTURE_MAX_NUM_PERIODS 227#define CAPTURE_MAX_PERIOD_SIZE 1638428#define CAPTURE_MIN_PERIOD_SIZE 102429 30#define MAX_BUFFER (PLAYBACK_MAX_PERIOD_SIZE * PLAYBACK_MAX_NUM_PERIODS)31#define MIN_BUFFER MAX_BUFFER32 33#define ST_PLAYBACK_MAX_PERIOD_SIZE 409634#define ST_CAPTURE_MAX_PERIOD_SIZE ST_PLAYBACK_MAX_PERIOD_SIZE35#define ST_MAX_BUFFER (ST_PLAYBACK_MAX_PERIOD_SIZE * PLAYBACK_MAX_NUM_PERIODS)36#define ST_MIN_BUFFER ST_MAX_BUFFER37 38#define DRV_NAME "acp_audio_dma"39bool acp_bt_uart_enable = true;40EXPORT_SYMBOL(acp_bt_uart_enable);41 42static const struct snd_pcm_hardware acp_pcm_hardware_playback = {43 .info = SNDRV_PCM_INFO_INTERLEAVED |44 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_MMAP |45 SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_BATCH |46 SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME,47 .formats = SNDRV_PCM_FMTBIT_S16_LE |48 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE,49 .channels_min = 1,50 .channels_max = 8,51 .rates = SNDRV_PCM_RATE_8000_96000,52 .rate_min = 8000,53 .rate_max = 96000,54 .buffer_bytes_max = PLAYBACK_MAX_NUM_PERIODS * PLAYBACK_MAX_PERIOD_SIZE,55 .period_bytes_min = PLAYBACK_MIN_PERIOD_SIZE,56 .period_bytes_max = PLAYBACK_MAX_PERIOD_SIZE,57 .periods_min = PLAYBACK_MIN_NUM_PERIODS,58 .periods_max = PLAYBACK_MAX_NUM_PERIODS,59};60 61static const struct snd_pcm_hardware acp_pcm_hardware_capture = {62 .info = SNDRV_PCM_INFO_INTERLEAVED |63 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_MMAP |64 SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_BATCH |65 SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME,66 .formats = SNDRV_PCM_FMTBIT_S16_LE |67 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE,68 .channels_min = 1,69 .channels_max = 2,70 .rates = SNDRV_PCM_RATE_8000_48000,71 .rate_min = 8000,72 .rate_max = 48000,73 .buffer_bytes_max = CAPTURE_MAX_NUM_PERIODS * CAPTURE_MAX_PERIOD_SIZE,74 .period_bytes_min = CAPTURE_MIN_PERIOD_SIZE,75 .period_bytes_max = CAPTURE_MAX_PERIOD_SIZE,76 .periods_min = CAPTURE_MIN_NUM_PERIODS,77 .periods_max = CAPTURE_MAX_NUM_PERIODS,78};79 80static const struct snd_pcm_hardware acp_st_pcm_hardware_playback = {81 .info = SNDRV_PCM_INFO_INTERLEAVED |82 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_MMAP |83 SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_BATCH |84 SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME,85 .formats = SNDRV_PCM_FMTBIT_S16_LE |86 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE,87 .channels_min = 1,88 .channels_max = 8,89 .rates = SNDRV_PCM_RATE_8000_96000,90 .rate_min = 8000,91 .rate_max = 96000,92 .buffer_bytes_max = ST_MAX_BUFFER,93 .period_bytes_min = PLAYBACK_MIN_PERIOD_SIZE,94 .period_bytes_max = ST_PLAYBACK_MAX_PERIOD_SIZE,95 .periods_min = PLAYBACK_MIN_NUM_PERIODS,96 .periods_max = PLAYBACK_MAX_NUM_PERIODS,97};98 99static const struct snd_pcm_hardware acp_st_pcm_hardware_capture = {100 .info = SNDRV_PCM_INFO_INTERLEAVED |101 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_MMAP |102 SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_BATCH |103 SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME,104 .formats = SNDRV_PCM_FMTBIT_S16_LE |105 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE,106 .channels_min = 1,107 .channels_max = 2,108 .rates = SNDRV_PCM_RATE_8000_48000,109 .rate_min = 8000,110 .rate_max = 48000,111 .buffer_bytes_max = ST_MAX_BUFFER,112 .period_bytes_min = CAPTURE_MIN_PERIOD_SIZE,113 .period_bytes_max = ST_CAPTURE_MAX_PERIOD_SIZE,114 .periods_min = CAPTURE_MIN_NUM_PERIODS,115 .periods_max = CAPTURE_MAX_NUM_PERIODS,116};117 118static u32 acp_reg_read(void __iomem *acp_mmio, u32 reg)119{120 return readl(acp_mmio + (reg * 4));121}122 123static void acp_reg_write(u32 val, void __iomem *acp_mmio, u32 reg)124{125 writel(val, acp_mmio + (reg * 4));126}127 128/*129 * Configure a given dma channel parameters - enable/disable,130 * number of descriptors, priority131 */132static void config_acp_dma_channel(void __iomem *acp_mmio, u8 ch_num,133 u16 dscr_strt_idx, u16 num_dscrs,134 enum acp_dma_priority_level priority_level)135{136 u32 dma_ctrl;137 138 /* disable the channel run field */139 dma_ctrl = acp_reg_read(acp_mmio, mmACP_DMA_CNTL_0 + ch_num);140 dma_ctrl &= ~ACP_DMA_CNTL_0__DMAChRun_MASK;141 acp_reg_write(dma_ctrl, acp_mmio, mmACP_DMA_CNTL_0 + ch_num);142 143 /* program a DMA channel with first descriptor to be processed. */144 acp_reg_write((ACP_DMA_DSCR_STRT_IDX_0__DMAChDscrStrtIdx_MASK145 & dscr_strt_idx),146 acp_mmio, mmACP_DMA_DSCR_STRT_IDX_0 + ch_num);147 148 /*149 * program a DMA channel with the number of descriptors to be150 * processed in the transfer151 */152 acp_reg_write(ACP_DMA_DSCR_CNT_0__DMAChDscrCnt_MASK & num_dscrs,153 acp_mmio, mmACP_DMA_DSCR_CNT_0 + ch_num);154 155 /* set DMA channel priority */156 acp_reg_write(priority_level, acp_mmio, mmACP_DMA_PRIO_0 + ch_num);157}158 159/* Initialize a dma descriptor in SRAM based on descriptor information passed */160static void config_dma_descriptor_in_sram(void __iomem *acp_mmio,161 u16 descr_idx,162 acp_dma_dscr_transfer_t *descr_info)163{164 u32 sram_offset;165 166 sram_offset = (descr_idx * sizeof(acp_dma_dscr_transfer_t));167 168 /* program the source base address. */169 acp_reg_write(sram_offset, acp_mmio, mmACP_SRBM_Targ_Idx_Addr);170 acp_reg_write(descr_info->src, acp_mmio, mmACP_SRBM_Targ_Idx_Data);171 /* program the destination base address. */172 acp_reg_write(sram_offset + 4, acp_mmio, mmACP_SRBM_Targ_Idx_Addr);173 acp_reg_write(descr_info->dest, acp_mmio, mmACP_SRBM_Targ_Idx_Data);174 175 /* program the number of bytes to be transferred for this descriptor. */176 acp_reg_write(sram_offset + 8, acp_mmio, mmACP_SRBM_Targ_Idx_Addr);177 acp_reg_write(descr_info->xfer_val, acp_mmio, mmACP_SRBM_Targ_Idx_Data);178}179 180static void pre_config_reset(void __iomem *acp_mmio, u16 ch_num)181{182 u32 dma_ctrl;183 int ret;184 185 /* clear the reset bit */186 dma_ctrl = acp_reg_read(acp_mmio, mmACP_DMA_CNTL_0 + ch_num);187 dma_ctrl &= ~ACP_DMA_CNTL_0__DMAChRst_MASK;188 acp_reg_write(dma_ctrl, acp_mmio, mmACP_DMA_CNTL_0 + ch_num);189 /* check the reset bit before programming configuration registers */190 ret = readl_poll_timeout(acp_mmio + ((mmACP_DMA_CNTL_0 + ch_num) * 4),191 dma_ctrl,192 !(dma_ctrl & ACP_DMA_CNTL_0__DMAChRst_MASK),193 100, ACP_DMA_RESET_TIME);194 if (ret < 0)195 pr_err("Failed to clear reset of channel : %d\n", ch_num);196}197 198/*199 * Initialize the DMA descriptor information for transfer between200 * system memory <-> ACP SRAM201 */202static void set_acp_sysmem_dma_descriptors(void __iomem *acp_mmio,203 u32 size, int direction,204 u32 pte_offset, u16 ch,205 u32 sram_bank, u16 dma_dscr_idx,206 u32 asic_type)207{208 u16 i;209 acp_dma_dscr_transfer_t dmadscr[NUM_DSCRS_PER_CHANNEL];210 211 for (i = 0; i < NUM_DSCRS_PER_CHANNEL; i++) {212 dmadscr[i].xfer_val = 0;213 if (direction == SNDRV_PCM_STREAM_PLAYBACK) {214 dma_dscr_idx = dma_dscr_idx + i;215 dmadscr[i].dest = sram_bank + (i * (size / 2));216 dmadscr[i].src = ACP_INTERNAL_APERTURE_WINDOW_0_ADDRESS217 + (pte_offset * SZ_4K) + (i * (size / 2));218 switch (asic_type) {219 case CHIP_STONEY:220 dmadscr[i].xfer_val |=221 (ACP_DMA_ATTR_DAGB_GARLIC_TO_SHAREDMEM << 16) |222 (size / 2);223 break;224 default:225 dmadscr[i].xfer_val |=226 (ACP_DMA_ATTR_DAGB_ONION_TO_SHAREDMEM << 16) |227 (size / 2);228 }229 } else {230 dma_dscr_idx = dma_dscr_idx + i;231 dmadscr[i].src = sram_bank + (i * (size / 2));232 dmadscr[i].dest =233 ACP_INTERNAL_APERTURE_WINDOW_0_ADDRESS +234 (pte_offset * SZ_4K) + (i * (size / 2));235 switch (asic_type) {236 case CHIP_STONEY:237 dmadscr[i].xfer_val |=238 (ACP_DMA_ATTR_SHARED_MEM_TO_DAGB_GARLIC << 16) |239 (size / 2);240 break;241 default:242 dmadscr[i].xfer_val |=243 (ACP_DMA_ATTR_SHAREDMEM_TO_DAGB_ONION << 16) |244 (size / 2);245 }246 }247 config_dma_descriptor_in_sram(acp_mmio, dma_dscr_idx,248 &dmadscr[i]);249 }250 pre_config_reset(acp_mmio, ch);251 config_acp_dma_channel(acp_mmio, ch,252 dma_dscr_idx - 1,253 NUM_DSCRS_PER_CHANNEL,254 ACP_DMA_PRIORITY_LEVEL_NORMAL);255}256 257/*258 * Initialize the DMA descriptor information for transfer between259 * ACP SRAM <-> I2S260 */261static void set_acp_to_i2s_dma_descriptors(void __iomem *acp_mmio, u32 size,262 int direction, u32 sram_bank,263 u16 destination, u16 ch,264 u16 dma_dscr_idx, u32 asic_type)265{266 u16 i;267 acp_dma_dscr_transfer_t dmadscr[NUM_DSCRS_PER_CHANNEL];268 269 for (i = 0; i < NUM_DSCRS_PER_CHANNEL; i++) {270 dmadscr[i].xfer_val = 0;271 if (direction == SNDRV_PCM_STREAM_PLAYBACK) {272 dma_dscr_idx = dma_dscr_idx + i;273 dmadscr[i].src = sram_bank + (i * (size / 2));274 /* dmadscr[i].dest is unused by hardware. */275 dmadscr[i].dest = 0;276 dmadscr[i].xfer_val |= BIT(22) | (destination << 16) |277 (size / 2);278 } else {279 dma_dscr_idx = dma_dscr_idx + i;280 /* dmadscr[i].src is unused by hardware. */281 dmadscr[i].src = 0;282 dmadscr[i].dest =283 sram_bank + (i * (size / 2));284 dmadscr[i].xfer_val |= BIT(22) |285 (destination << 16) | (size / 2);286 }287 config_dma_descriptor_in_sram(acp_mmio, dma_dscr_idx,288 &dmadscr[i]);289 }290 pre_config_reset(acp_mmio, ch);291 /* Configure the DMA channel with the above descriptor */292 config_acp_dma_channel(acp_mmio, ch, dma_dscr_idx - 1,293 NUM_DSCRS_PER_CHANNEL,294 ACP_DMA_PRIORITY_LEVEL_NORMAL);295}296 297/* Create page table entries in ACP SRAM for the allocated memory */298static void acp_pte_config(void __iomem *acp_mmio, dma_addr_t addr,299 u16 num_of_pages, u32 pte_offset)300{301 u16 page_idx;302 u32 low;303 u32 high;304 u32 offset;305 306 offset = ACP_DAGB_GRP_SRBM_SRAM_BASE_OFFSET + (pte_offset * 8);307 for (page_idx = 0; page_idx < (num_of_pages); page_idx++) {308 /* Load the low address of page int ACP SRAM through SRBM */309 acp_reg_write((offset + (page_idx * 8)),310 acp_mmio, mmACP_SRBM_Targ_Idx_Addr);311 312 low = lower_32_bits(addr);313 high = upper_32_bits(addr);314 315 acp_reg_write(low, acp_mmio, mmACP_SRBM_Targ_Idx_Data);316 317 /* Load the High address of page int ACP SRAM through SRBM */318 acp_reg_write((offset + (page_idx * 8) + 4),319 acp_mmio, mmACP_SRBM_Targ_Idx_Addr);320 321 /* page enable in ACP */322 high |= BIT(31);323 acp_reg_write(high, acp_mmio, mmACP_SRBM_Targ_Idx_Data);324 325 /* Move to next physically contiguous page */326 addr += PAGE_SIZE;327 }328}329 330static void config_acp_dma(void __iomem *acp_mmio,331 struct audio_substream_data *rtd,332 u32 asic_type)333{334 u16 ch_acp_sysmem, ch_acp_i2s;335 336 acp_pte_config(acp_mmio, rtd->dma_addr, rtd->num_of_pages,337 rtd->pte_offset);338 339 if (rtd->direction == SNDRV_PCM_STREAM_PLAYBACK) {340 ch_acp_sysmem = rtd->ch1;341 ch_acp_i2s = rtd->ch2;342 } else {343 ch_acp_i2s = rtd->ch1;344 ch_acp_sysmem = rtd->ch2;345 }346 /* Configure System memory <-> ACP SRAM DMA descriptors */347 set_acp_sysmem_dma_descriptors(acp_mmio, rtd->size,348 rtd->direction, rtd->pte_offset,349 ch_acp_sysmem, rtd->sram_bank,350 rtd->dma_dscr_idx_1, asic_type);351 /* Configure ACP SRAM <-> I2S DMA descriptors */352 set_acp_to_i2s_dma_descriptors(acp_mmio, rtd->size,353 rtd->direction, rtd->sram_bank,354 rtd->destination, ch_acp_i2s,355 rtd->dma_dscr_idx_2, asic_type);356}357 358static void acp_dma_cap_channel_enable(void __iomem *acp_mmio,359 u16 cap_channel)360{361 u32 val, ch_reg, imr_reg, res_reg;362 363 switch (cap_channel) {364 case CAP_CHANNEL1:365 ch_reg = mmACP_I2SMICSP_RER1;366 res_reg = mmACP_I2SMICSP_RCR1;367 imr_reg = mmACP_I2SMICSP_IMR1;368 break;369 case CAP_CHANNEL0:370 default:371 ch_reg = mmACP_I2SMICSP_RER0;372 res_reg = mmACP_I2SMICSP_RCR0;373 imr_reg = mmACP_I2SMICSP_IMR0;374 break;375 }376 val = acp_reg_read(acp_mmio,377 mmACP_I2S_16BIT_RESOLUTION_EN);378 if (val & ACP_I2S_MIC_16BIT_RESOLUTION_EN) {379 acp_reg_write(0x0, acp_mmio, ch_reg);380 /* Set 16bit resolution on capture */381 acp_reg_write(0x2, acp_mmio, res_reg);382 }383 val = acp_reg_read(acp_mmio, imr_reg);384 val &= ~ACP_I2SMICSP_IMR1__I2SMICSP_RXDAM_MASK;385 val &= ~ACP_I2SMICSP_IMR1__I2SMICSP_RXFOM_MASK;386 acp_reg_write(val, acp_mmio, imr_reg);387 acp_reg_write(0x1, acp_mmio, ch_reg);388}389 390static void acp_dma_cap_channel_disable(void __iomem *acp_mmio,391 u16 cap_channel)392{393 u32 val, ch_reg, imr_reg;394 395 switch (cap_channel) {396 case CAP_CHANNEL1:397 imr_reg = mmACP_I2SMICSP_IMR1;398 ch_reg = mmACP_I2SMICSP_RER1;399 break;400 case CAP_CHANNEL0:401 default:402 imr_reg = mmACP_I2SMICSP_IMR0;403 ch_reg = mmACP_I2SMICSP_RER0;404 break;405 }406 val = acp_reg_read(acp_mmio, imr_reg);407 val |= ACP_I2SMICSP_IMR1__I2SMICSP_RXDAM_MASK;408 val |= ACP_I2SMICSP_IMR1__I2SMICSP_RXFOM_MASK;409 acp_reg_write(val, acp_mmio, imr_reg);410 acp_reg_write(0x0, acp_mmio, ch_reg);411}412 413/* Start a given DMA channel transfer */414static void acp_dma_start(void __iomem *acp_mmio, u16 ch_num, bool is_circular)415{416 u32 dma_ctrl;417 418 /* read the dma control register and disable the channel run field */419 dma_ctrl = acp_reg_read(acp_mmio, mmACP_DMA_CNTL_0 + ch_num);420 421 /* Invalidating the DAGB cache */422 acp_reg_write(1, acp_mmio, mmACP_DAGB_ATU_CTRL);423 424 /*425 * configure the DMA channel and start the DMA transfer426 * set dmachrun bit to start the transfer and enable the427 * interrupt on completion of the dma transfer428 */429 dma_ctrl |= ACP_DMA_CNTL_0__DMAChRun_MASK;430 431 switch (ch_num) {432 case ACP_TO_I2S_DMA_CH_NUM:433 case I2S_TO_ACP_DMA_CH_NUM:434 case ACP_TO_I2S_DMA_BT_INSTANCE_CH_NUM:435 case I2S_TO_ACP_DMA_BT_INSTANCE_CH_NUM:436 case ACP_TO_I2S_DMA_MICSP_INSTANCE_CH_NUM:437 dma_ctrl |= ACP_DMA_CNTL_0__DMAChIOCEn_MASK;438 break;439 default:440 dma_ctrl &= ~ACP_DMA_CNTL_0__DMAChIOCEn_MASK;441 break;442 }443 444 /* enable for ACP to SRAM DMA channel */445 if (is_circular == true)446 dma_ctrl |= ACP_DMA_CNTL_0__Circular_DMA_En_MASK;447 else448 dma_ctrl &= ~ACP_DMA_CNTL_0__Circular_DMA_En_MASK;449 450 acp_reg_write(dma_ctrl, acp_mmio, mmACP_DMA_CNTL_0 + ch_num);451}452 453/* Stop a given DMA channel transfer */454static int acp_dma_stop(void __iomem *acp_mmio, u8 ch_num)455{456 u32 dma_ctrl;457 u32 dma_ch_sts;458 u32 count = ACP_DMA_RESET_TIME;459 460 dma_ctrl = acp_reg_read(acp_mmio, mmACP_DMA_CNTL_0 + ch_num);461 462 /*463 * clear the dma control register fields before writing zero464 * in reset bit465 */466 dma_ctrl &= ~ACP_DMA_CNTL_0__DMAChRun_MASK;467 dma_ctrl &= ~ACP_DMA_CNTL_0__DMAChIOCEn_MASK;468 469 acp_reg_write(dma_ctrl, acp_mmio, mmACP_DMA_CNTL_0 + ch_num);470 dma_ch_sts = acp_reg_read(acp_mmio, mmACP_DMA_CH_STS);471 472 if (dma_ch_sts & BIT(ch_num)) {473 /*474 * set the reset bit for this channel to stop the dma475 * transfer476 */477 dma_ctrl |= ACP_DMA_CNTL_0__DMAChRst_MASK;478 acp_reg_write(dma_ctrl, acp_mmio, mmACP_DMA_CNTL_0 + ch_num);479 }480 481 /* check the channel status bit for some time and return the status */482 while (true) {483 dma_ch_sts = acp_reg_read(acp_mmio, mmACP_DMA_CH_STS);484 if (!(dma_ch_sts & BIT(ch_num))) {485 /*486 * clear the reset flag after successfully stopping487 * the dma transfer and break from the loop488 */489 dma_ctrl &= ~ACP_DMA_CNTL_0__DMAChRst_MASK;490 491 acp_reg_write(dma_ctrl, acp_mmio, mmACP_DMA_CNTL_0492 + ch_num);493 break;494 }495 if (--count == 0) {496 pr_err("Failed to stop ACP DMA channel : %d\n", ch_num);497 return -ETIMEDOUT;498 }499 udelay(100);500 }501 return 0;502}503 504static void acp_set_sram_bank_state(void __iomem *acp_mmio, u16 bank,505 bool power_on)506{507 u32 val, req_reg, sts_reg, sts_reg_mask;508 u32 loops = 1000;509 510 if (bank < 32) {511 req_reg = mmACP_MEM_SHUT_DOWN_REQ_LO;512 sts_reg = mmACP_MEM_SHUT_DOWN_STS_LO;513 sts_reg_mask = 0xFFFFFFFF;514 515 } else {516 bank -= 32;517 req_reg = mmACP_MEM_SHUT_DOWN_REQ_HI;518 sts_reg = mmACP_MEM_SHUT_DOWN_STS_HI;519 sts_reg_mask = 0x0000FFFF;520 }521 522 val = acp_reg_read(acp_mmio, req_reg);523 if (val & (1 << bank)) {524 /* bank is in off state */525 if (power_on == true)526 /* request to on */527 val &= ~(1 << bank);528 else529 /* request to off */530 return;531 } else {532 /* bank is in on state */533 if (power_on == false)534 /* request to off */535 val |= 1 << bank;536 else537 /* request to on */538 return;539 }540 acp_reg_write(val, acp_mmio, req_reg);541 542 while (acp_reg_read(acp_mmio, sts_reg) != sts_reg_mask) {543 if (!loops--) {544 pr_err("ACP SRAM bank %d state change failed\n", bank);545 break;546 }547 cpu_relax();548 }549}550 551/* Initialize and bring ACP hardware to default state. */552static int acp_init(void __iomem *acp_mmio, u32 asic_type)553{554 u16 bank;555 u32 val, count, sram_pte_offset;556 557 /* Assert Soft reset of ACP */558 val = acp_reg_read(acp_mmio, mmACP_SOFT_RESET);559 560 val |= ACP_SOFT_RESET__SoftResetAud_MASK;561 acp_reg_write(val, acp_mmio, mmACP_SOFT_RESET);562 563 count = ACP_SOFT_RESET_DONE_TIME_OUT_VALUE;564 while (true) {565 val = acp_reg_read(acp_mmio, mmACP_SOFT_RESET);566 if (ACP_SOFT_RESET__SoftResetAudDone_MASK ==567 (val & ACP_SOFT_RESET__SoftResetAudDone_MASK))568 break;569 if (--count == 0) {570 pr_err("Failed to reset ACP\n");571 return -ETIMEDOUT;572 }573 udelay(100);574 }575 576 /* Enable clock to ACP and wait until the clock is enabled */577 val = acp_reg_read(acp_mmio, mmACP_CONTROL);578 val = val | ACP_CONTROL__ClkEn_MASK;579 acp_reg_write(val, acp_mmio, mmACP_CONTROL);580 581 count = ACP_CLOCK_EN_TIME_OUT_VALUE;582 583 while (true) {584 val = acp_reg_read(acp_mmio, mmACP_STATUS);585 if (val & (u32)0x1)586 break;587 if (--count == 0) {588 pr_err("Failed to reset ACP\n");589 return -ETIMEDOUT;590 }591 udelay(100);592 }593 594 /* Deassert the SOFT RESET flags */595 val = acp_reg_read(acp_mmio, mmACP_SOFT_RESET);596 val &= ~ACP_SOFT_RESET__SoftResetAud_MASK;597 acp_reg_write(val, acp_mmio, mmACP_SOFT_RESET);598 599 /* For BT instance change pins from UART to BT */600 if (!acp_bt_uart_enable) {601 val = acp_reg_read(acp_mmio, mmACP_BT_UART_PAD_SEL);602 val |= ACP_BT_UART_PAD_SELECT_MASK;603 acp_reg_write(val, acp_mmio, mmACP_BT_UART_PAD_SEL);604 }605 606 /* initialize Onion control DAGB register */607 acp_reg_write(ACP_ONION_CNTL_DEFAULT, acp_mmio,608 mmACP_AXI2DAGB_ONION_CNTL);609 610 /* initialize Garlic control DAGB registers */611 acp_reg_write(ACP_GARLIC_CNTL_DEFAULT, acp_mmio,612 mmACP_AXI2DAGB_GARLIC_CNTL);613 614 sram_pte_offset = ACP_DAGB_GRP_SRAM_BASE_ADDRESS |615 ACP_DAGB_BASE_ADDR_GRP_1__AXI2DAGBSnoopSel_MASK |616 ACP_DAGB_BASE_ADDR_GRP_1__AXI2DAGBTargetMemSel_MASK |617 ACP_DAGB_BASE_ADDR_GRP_1__AXI2DAGBGrpEnable_MASK;618 acp_reg_write(sram_pte_offset, acp_mmio, mmACP_DAGB_BASE_ADDR_GRP_1);619 acp_reg_write(ACP_PAGE_SIZE_4K_ENABLE, acp_mmio,620 mmACP_DAGB_PAGE_SIZE_GRP_1);621 622 acp_reg_write(ACP_SRAM_BASE_ADDRESS, acp_mmio,623 mmACP_DMA_DESC_BASE_ADDR);624 625 /* Num of descriptors in SRAM 0x4, means 256 descriptors;(64 * 4) */626 acp_reg_write(0x4, acp_mmio, mmACP_DMA_DESC_MAX_NUM_DSCR);627 acp_reg_write(ACP_EXTERNAL_INTR_CNTL__DMAIOCMask_MASK,628 acp_mmio, mmACP_EXTERNAL_INTR_CNTL);629 630 /*631 * When ACP_TILE_P1 is turned on, all SRAM banks get turned on.632 * Now, turn off all of them. This can't be done in 'poweron' of633 * ACP pm domain, as this requires ACP to be initialized.634 * For Stoney, Memory gating is disabled,i.e SRAM Banks635 * won't be turned off. The default state for SRAM banks is ON.636 * Setting SRAM bank state code skipped for STONEY platform.637 */638 if (asic_type != CHIP_STONEY) {639 for (bank = 1; bank < 48; bank++)640 acp_set_sram_bank_state(acp_mmio, bank, false);641 }642 return 0;643}644 645/* Deinitialize ACP */646static int acp_deinit(void __iomem *acp_mmio)647{648 u32 val;649 u32 count;650 651 /* Assert Soft reset of ACP */652 val = acp_reg_read(acp_mmio, mmACP_SOFT_RESET);653 654 val |= ACP_SOFT_RESET__SoftResetAud_MASK;655 acp_reg_write(val, acp_mmio, mmACP_SOFT_RESET);656 657 count = ACP_SOFT_RESET_DONE_TIME_OUT_VALUE;658 while (true) {659 val = acp_reg_read(acp_mmio, mmACP_SOFT_RESET);660 if (ACP_SOFT_RESET__SoftResetAudDone_MASK ==661 (val & ACP_SOFT_RESET__SoftResetAudDone_MASK))662 break;663 if (--count == 0) {664 pr_err("Failed to reset ACP\n");665 return -ETIMEDOUT;666 }667 udelay(100);668 }669 /* Disable ACP clock */670 val = acp_reg_read(acp_mmio, mmACP_CONTROL);671 val &= ~ACP_CONTROL__ClkEn_MASK;672 acp_reg_write(val, acp_mmio, mmACP_CONTROL);673 674 count = ACP_CLOCK_EN_TIME_OUT_VALUE;675 676 while (true) {677 val = acp_reg_read(acp_mmio, mmACP_STATUS);678 if (!(val & (u32)0x1))679 break;680 if (--count == 0) {681 pr_err("Failed to reset ACP\n");682 return -ETIMEDOUT;683 }684 udelay(100);685 }686 return 0;687}688 689/* ACP DMA irq handler routine for playback, capture usecases */690static irqreturn_t dma_irq_handler(int irq, void *arg)691{692 u16 dscr_idx;693 u32 intr_flag, ext_intr_status;694 struct audio_drv_data *irq_data;695 void __iomem *acp_mmio;696 struct device *dev = arg;697 bool valid_irq = false;698 699 irq_data = dev_get_drvdata(dev);700 acp_mmio = irq_data->acp_mmio;701 702 ext_intr_status = acp_reg_read(acp_mmio, mmACP_EXTERNAL_INTR_STAT);703 intr_flag = (((ext_intr_status &704 ACP_EXTERNAL_INTR_STAT__DMAIOCStat_MASK) >>705 ACP_EXTERNAL_INTR_STAT__DMAIOCStat__SHIFT));706 707 if ((intr_flag & BIT(ACP_TO_I2S_DMA_CH_NUM)) != 0) {708 valid_irq = true;709 snd_pcm_period_elapsed(irq_data->play_i2ssp_stream);710 acp_reg_write((intr_flag & BIT(ACP_TO_I2S_DMA_CH_NUM)) << 16,711 acp_mmio, mmACP_EXTERNAL_INTR_STAT);712 }713 714 if ((intr_flag & BIT(ACP_TO_I2S_DMA_MICSP_INSTANCE_CH_NUM)) != 0) {715 valid_irq = true;716 snd_pcm_period_elapsed(irq_data->play_i2s_micsp_stream);717 acp_reg_write((intr_flag & BIT(ACP_TO_I2S_DMA_MICSP_INSTANCE_CH_NUM)) << 16,718 acp_mmio, mmACP_EXTERNAL_INTR_STAT);719 }720 721 if ((intr_flag & BIT(ACP_TO_I2S_DMA_BT_INSTANCE_CH_NUM)) != 0) {722 valid_irq = true;723 snd_pcm_period_elapsed(irq_data->play_i2sbt_stream);724 acp_reg_write((intr_flag &725 BIT(ACP_TO_I2S_DMA_BT_INSTANCE_CH_NUM)) << 16,726 acp_mmio, mmACP_EXTERNAL_INTR_STAT);727 }728 729 if ((intr_flag & BIT(I2S_TO_ACP_DMA_CH_NUM)) != 0) {730 valid_irq = true;731 if (acp_reg_read(acp_mmio, mmACP_DMA_CUR_DSCR_14) ==732 CAPTURE_START_DMA_DESCR_CH15)733 dscr_idx = CAPTURE_END_DMA_DESCR_CH14;734 else735 dscr_idx = CAPTURE_START_DMA_DESCR_CH14;736 config_acp_dma_channel(acp_mmio, ACP_TO_SYSRAM_CH_NUM, dscr_idx,737 1, 0);738 acp_dma_start(acp_mmio, ACP_TO_SYSRAM_CH_NUM, false);739 740 snd_pcm_period_elapsed(irq_data->capture_i2ssp_stream);741 acp_reg_write((intr_flag & BIT(I2S_TO_ACP_DMA_CH_NUM)) << 16,742 acp_mmio, mmACP_EXTERNAL_INTR_STAT);743 }744 745 if ((intr_flag & BIT(I2S_TO_ACP_DMA_BT_INSTANCE_CH_NUM)) != 0) {746 valid_irq = true;747 if (acp_reg_read(acp_mmio, mmACP_DMA_CUR_DSCR_10) ==748 CAPTURE_START_DMA_DESCR_CH11)749 dscr_idx = CAPTURE_END_DMA_DESCR_CH10;750 else751 dscr_idx = CAPTURE_START_DMA_DESCR_CH10;752 config_acp_dma_channel(acp_mmio,753 ACP_TO_SYSRAM_BT_INSTANCE_CH_NUM,754 dscr_idx, 1, 0);755 acp_dma_start(acp_mmio, ACP_TO_SYSRAM_BT_INSTANCE_CH_NUM,756 false);757 758 snd_pcm_period_elapsed(irq_data->capture_i2sbt_stream);759 acp_reg_write((intr_flag &760 BIT(I2S_TO_ACP_DMA_BT_INSTANCE_CH_NUM)) << 16,761 acp_mmio, mmACP_EXTERNAL_INTR_STAT);762 }763 764 if (valid_irq)765 return IRQ_HANDLED;766 else767 return IRQ_NONE;768}769 770static int acp_dma_open(struct snd_soc_component *component,771 struct snd_pcm_substream *substream)772{773 u16 bank;774 int ret = 0;775 struct snd_pcm_runtime *runtime = substream->runtime;776 struct audio_drv_data *intr_data = dev_get_drvdata(component->dev);777 struct audio_substream_data *adata =778 kzalloc(sizeof(struct audio_substream_data), GFP_KERNEL);779 if (!adata)780 return -ENOMEM;781 782 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {783 switch (intr_data->asic_type) {784 case CHIP_STONEY:785 runtime->hw = acp_st_pcm_hardware_playback;786 break;787 default:788 runtime->hw = acp_pcm_hardware_playback;789 }790 } else {791 switch (intr_data->asic_type) {792 case CHIP_STONEY:793 runtime->hw = acp_st_pcm_hardware_capture;794 break;795 default:796 runtime->hw = acp_pcm_hardware_capture;797 }798 }799 800 ret = snd_pcm_hw_constraint_integer(runtime,801 SNDRV_PCM_HW_PARAM_PERIODS);802 if (ret < 0) {803 dev_err(component->dev, "set integer constraint failed\n");804 kfree(adata);805 return ret;806 }807 808 adata->acp_mmio = intr_data->acp_mmio;809 runtime->private_data = adata;810 811 /*812 * Enable ACP irq, when neither playback or capture streams are813 * active by the time when a new stream is being opened.814 * This enablement is not required for another stream, if current815 * stream is not closed816 */817 if (!intr_data->play_i2ssp_stream && !intr_data->capture_i2ssp_stream &&818 !intr_data->play_i2sbt_stream && !intr_data->capture_i2sbt_stream &&819 !intr_data->play_i2s_micsp_stream)820 acp_reg_write(1, adata->acp_mmio, mmACP_EXTERNAL_INTR_ENB);821 822 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {823 /*824 * For Stoney, Memory gating is disabled,i.e SRAM Banks825 * won't be turned off. The default state for SRAM banks is ON.826 * Setting SRAM bank state code skipped for STONEY platform.827 */828 if (intr_data->asic_type != CHIP_STONEY) {829 for (bank = 1; bank <= 4; bank++)830 acp_set_sram_bank_state(intr_data->acp_mmio,831 bank, true);832 }833 } else {834 if (intr_data->asic_type != CHIP_STONEY) {835 for (bank = 5; bank <= 8; bank++)836 acp_set_sram_bank_state(intr_data->acp_mmio,837 bank, true);838 }839 }840 841 return 0;842}843 844static int acp_dma_hw_params(struct snd_soc_component *component,845 struct snd_pcm_substream *substream,846 struct snd_pcm_hw_params *params)847{848 uint64_t size;849 u32 val = 0;850 struct snd_pcm_runtime *runtime;851 struct audio_substream_data *rtd;852 struct snd_soc_pcm_runtime *prtd = snd_soc_substream_to_rtd(substream);853 struct audio_drv_data *adata = dev_get_drvdata(component->dev);854 struct snd_soc_card *card = prtd->card;855 struct acp_platform_info *pinfo = snd_soc_card_get_drvdata(card);856 857 runtime = substream->runtime;858 rtd = runtime->private_data;859 860 if (WARN_ON(!rtd))861 return -EINVAL;862 863 if (pinfo) {864 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {865 rtd->i2s_instance = pinfo->play_i2s_instance;866 } else {867 rtd->i2s_instance = pinfo->cap_i2s_instance;868 rtd->capture_channel = pinfo->capture_channel;869 }870 }871 if (adata->asic_type == CHIP_STONEY) {872 val = acp_reg_read(adata->acp_mmio,873 mmACP_I2S_16BIT_RESOLUTION_EN);874 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {875 switch (rtd->i2s_instance) {876 case I2S_BT_INSTANCE:877 val |= ACP_I2S_BT_16BIT_RESOLUTION_EN;878 break;879 case I2S_MICSP_INSTANCE:880 val |= ACP_I2S_MICSP_16BIT_RESOLUTION_EN;881 break;882 case I2S_SP_INSTANCE:883 default:884 val |= ACP_I2S_SP_16BIT_RESOLUTION_EN;885 }886 } else {887 switch (rtd->i2s_instance) {888 case I2S_BT_INSTANCE:889 val |= ACP_I2S_BT_16BIT_RESOLUTION_EN;890 break;891 case I2S_MICSP_INSTANCE:892 case I2S_SP_INSTANCE:893 default:894 val |= ACP_I2S_MIC_16BIT_RESOLUTION_EN;895 }896 }897 acp_reg_write(val, adata->acp_mmio,898 mmACP_I2S_16BIT_RESOLUTION_EN);899 }900 901 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {902 switch (rtd->i2s_instance) {903 case I2S_BT_INSTANCE:904 rtd->pte_offset = ACP_ST_BT_PLAYBACK_PTE_OFFSET;905 rtd->ch1 = SYSRAM_TO_ACP_BT_INSTANCE_CH_NUM;906 rtd->ch2 = ACP_TO_I2S_DMA_BT_INSTANCE_CH_NUM;907 rtd->sram_bank = ACP_SRAM_BANK_3_ADDRESS;908 rtd->destination = TO_BLUETOOTH;909 rtd->dma_dscr_idx_1 = PLAYBACK_START_DMA_DESCR_CH8;910 rtd->dma_dscr_idx_2 = PLAYBACK_START_DMA_DESCR_CH9;911 rtd->byte_cnt_high_reg_offset =912 mmACP_I2S_BT_TRANSMIT_BYTE_CNT_HIGH;913 rtd->byte_cnt_low_reg_offset =914 mmACP_I2S_BT_TRANSMIT_BYTE_CNT_LOW;915 adata->play_i2sbt_stream = substream;916 break;917 case I2S_MICSP_INSTANCE:918 switch (adata->asic_type) {919 case CHIP_STONEY:920 rtd->pte_offset = ACP_ST_PLAYBACK_PTE_OFFSET;921 break;922 default:923 rtd->pte_offset = ACP_PLAYBACK_PTE_OFFSET;924 }925 rtd->ch1 = SYSRAM_TO_ACP_MICSP_INSTANCE_CH_NUM;926 rtd->ch2 = ACP_TO_I2S_DMA_MICSP_INSTANCE_CH_NUM;927 rtd->sram_bank = ACP_SRAM_BANK_1_ADDRESS;928 rtd->destination = TO_ACP_I2S_2;929 rtd->dma_dscr_idx_1 = PLAYBACK_START_DMA_DESCR_CH4;930 rtd->dma_dscr_idx_2 = PLAYBACK_START_DMA_DESCR_CH5;931 rtd->byte_cnt_high_reg_offset =932 mmACP_I2S_MICSP_TRANSMIT_BYTE_CNT_HIGH;933 rtd->byte_cnt_low_reg_offset =934 mmACP_I2S_MICSP_TRANSMIT_BYTE_CNT_LOW;935 936 adata->play_i2s_micsp_stream = substream;937 break;938 case I2S_SP_INSTANCE:939 default:940 switch (adata->asic_type) {941 case CHIP_STONEY:942 rtd->pte_offset = ACP_ST_PLAYBACK_PTE_OFFSET;943 break;944 default:945 rtd->pte_offset = ACP_PLAYBACK_PTE_OFFSET;946 }947 rtd->ch1 = SYSRAM_TO_ACP_CH_NUM;948 rtd->ch2 = ACP_TO_I2S_DMA_CH_NUM;949 rtd->sram_bank = ACP_SRAM_BANK_1_ADDRESS;950 rtd->destination = TO_ACP_I2S_1;951 rtd->dma_dscr_idx_1 = PLAYBACK_START_DMA_DESCR_CH12;952 rtd->dma_dscr_idx_2 = PLAYBACK_START_DMA_DESCR_CH13;953 rtd->byte_cnt_high_reg_offset =954 mmACP_I2S_TRANSMIT_BYTE_CNT_HIGH;955 rtd->byte_cnt_low_reg_offset =956 mmACP_I2S_TRANSMIT_BYTE_CNT_LOW;957 adata->play_i2ssp_stream = substream;958 }959 } else {960 switch (rtd->i2s_instance) {961 case I2S_BT_INSTANCE:962 rtd->pte_offset = ACP_ST_BT_CAPTURE_PTE_OFFSET;963 rtd->ch1 = I2S_TO_ACP_DMA_BT_INSTANCE_CH_NUM;964 rtd->ch2 = ACP_TO_SYSRAM_BT_INSTANCE_CH_NUM;965 rtd->sram_bank = ACP_SRAM_BANK_4_ADDRESS;966 rtd->destination = FROM_BLUETOOTH;967 rtd->dma_dscr_idx_1 = CAPTURE_START_DMA_DESCR_CH10;968 rtd->dma_dscr_idx_2 = CAPTURE_START_DMA_DESCR_CH11;969 rtd->byte_cnt_high_reg_offset =970 mmACP_I2S_BT_RECEIVE_BYTE_CNT_HIGH;971 rtd->byte_cnt_low_reg_offset =972 mmACP_I2S_BT_RECEIVE_BYTE_CNT_LOW;973 rtd->dma_curr_dscr = mmACP_DMA_CUR_DSCR_11;974 adata->capture_i2sbt_stream = substream;975 break;976 case I2S_MICSP_INSTANCE:977 case I2S_SP_INSTANCE:978 default:979 rtd->pte_offset = ACP_CAPTURE_PTE_OFFSET;980 rtd->ch1 = I2S_TO_ACP_DMA_CH_NUM;981 rtd->ch2 = ACP_TO_SYSRAM_CH_NUM;982 switch (adata->asic_type) {983 case CHIP_STONEY:984 rtd->pte_offset = ACP_ST_CAPTURE_PTE_OFFSET;985 rtd->sram_bank = ACP_SRAM_BANK_2_ADDRESS;986 break;987 default:988 rtd->pte_offset = ACP_CAPTURE_PTE_OFFSET;989 rtd->sram_bank = ACP_SRAM_BANK_5_ADDRESS;990 }991 rtd->destination = FROM_ACP_I2S_1;992 rtd->dma_dscr_idx_1 = CAPTURE_START_DMA_DESCR_CH14;993 rtd->dma_dscr_idx_2 = CAPTURE_START_DMA_DESCR_CH15;994 rtd->byte_cnt_high_reg_offset =995 mmACP_I2S_RECEIVED_BYTE_CNT_HIGH;996 rtd->byte_cnt_low_reg_offset =997 mmACP_I2S_RECEIVED_BYTE_CNT_LOW;998 rtd->dma_curr_dscr = mmACP_DMA_CUR_DSCR_15;999 adata->capture_i2ssp_stream = substream;1000 }1001 }1002 1003 size = params_buffer_bytes(params);1004 1005 acp_set_sram_bank_state(rtd->acp_mmio, 0, true);1006 /* Save for runtime private data */1007 rtd->dma_addr = runtime->dma_addr;1008 rtd->order = get_order(size);1009 1010 /* Fill the page table entries in ACP SRAM */1011 rtd->size = size;1012 rtd->num_of_pages = PAGE_ALIGN(size) >> PAGE_SHIFT;1013 rtd->direction = substream->stream;1014 1015 config_acp_dma(rtd->acp_mmio, rtd, adata->asic_type);1016 return 0;1017}1018 1019static u64 acp_get_byte_count(struct audio_substream_data *rtd)1020{1021 union acp_dma_count byte_count;1022 1023 byte_count.bcount.high = acp_reg_read(rtd->acp_mmio,1024 rtd->byte_cnt_high_reg_offset);1025 byte_count.bcount.low = acp_reg_read(rtd->acp_mmio,1026 rtd->byte_cnt_low_reg_offset);1027 return byte_count.bytescount;1028}1029 1030static snd_pcm_uframes_t acp_dma_pointer(struct snd_soc_component *component,1031 struct snd_pcm_substream *substream)1032{1033 u32 buffersize;1034 u32 pos = 0;1035 u64 bytescount = 0;1036 u16 dscr;1037 u32 period_bytes, delay;1038 1039 struct snd_pcm_runtime *runtime = substream->runtime;1040 struct audio_substream_data *rtd = runtime->private_data;1041 struct audio_drv_data *adata = dev_get_drvdata(component->dev);1042 1043 if (!rtd)1044 return -EINVAL;1045 1046 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {1047 period_bytes = frames_to_bytes(runtime, runtime->period_size);1048 bytescount = acp_get_byte_count(rtd);1049 if (bytescount >= rtd->bytescount)1050 bytescount -= rtd->bytescount;1051 if (bytescount < period_bytes) {1052 pos = 0;1053 } else {1054 dscr = acp_reg_read(rtd->acp_mmio, rtd->dma_curr_dscr);1055 if (dscr == rtd->dma_dscr_idx_1)1056 pos = period_bytes;1057 else1058 pos = 0;1059 }1060 if (bytescount > 0) {1061 delay = do_div(bytescount, period_bytes);1062 adata->delay += bytes_to_frames(runtime, delay);1063 }1064 } else {1065 buffersize = frames_to_bytes(runtime, runtime->buffer_size);1066 bytescount = acp_get_byte_count(rtd);1067 if (bytescount > rtd->bytescount)1068 bytescount -= rtd->bytescount;1069 pos = do_div(bytescount, buffersize);1070 }1071 return bytes_to_frames(runtime, pos);1072}1073 1074static snd_pcm_sframes_t acp_dma_delay(struct snd_soc_component *component,1075 struct snd_pcm_substream *substream)1076{1077 struct audio_drv_data *adata = dev_get_drvdata(component->dev);1078 snd_pcm_sframes_t delay = adata->delay;1079 1080 adata->delay = 0;1081 1082 return delay;1083}1084 1085static int acp_dma_prepare(struct snd_soc_component *component,1086 struct snd_pcm_substream *substream)1087{1088 struct snd_pcm_runtime *runtime = substream->runtime;1089 struct audio_substream_data *rtd = runtime->private_data;1090 u16 ch_acp_sysmem, ch_acp_i2s;1091 1092 if (!rtd)1093 return -EINVAL;1094 1095 if (rtd->direction == SNDRV_PCM_STREAM_PLAYBACK) {1096 ch_acp_sysmem = rtd->ch1;1097 ch_acp_i2s = rtd->ch2;1098 } else {1099 ch_acp_i2s = rtd->ch1;1100 ch_acp_sysmem = rtd->ch2;1101 }1102 config_acp_dma_channel(rtd->acp_mmio,1103 ch_acp_sysmem,1104 rtd->dma_dscr_idx_1,1105 NUM_DSCRS_PER_CHANNEL, 0);1106 config_acp_dma_channel(rtd->acp_mmio,1107 ch_acp_i2s,1108 rtd->dma_dscr_idx_2,1109 NUM_DSCRS_PER_CHANNEL, 0);1110 return 0;1111}1112 1113static int acp_dma_trigger(struct snd_soc_component *component,1114 struct snd_pcm_substream *substream, int cmd)1115{1116 int ret;1117 1118 struct snd_pcm_runtime *runtime = substream->runtime;1119 struct audio_substream_data *rtd = runtime->private_data;1120 1121 if (!rtd)1122 return -EINVAL;1123 switch (cmd) {1124 case SNDRV_PCM_TRIGGER_START:1125 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:1126 case SNDRV_PCM_TRIGGER_RESUME:1127 rtd->bytescount = acp_get_byte_count(rtd);1128 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {1129 if (rtd->capture_channel == CAP_CHANNEL0) {1130 acp_dma_cap_channel_disable(rtd->acp_mmio,1131 CAP_CHANNEL1);1132 acp_dma_cap_channel_enable(rtd->acp_mmio,1133 CAP_CHANNEL0);1134 }1135 if (rtd->capture_channel == CAP_CHANNEL1) {1136 acp_dma_cap_channel_disable(rtd->acp_mmio,1137 CAP_CHANNEL0);1138 acp_dma_cap_channel_enable(rtd->acp_mmio,1139 CAP_CHANNEL1);1140 }1141 acp_dma_start(rtd->acp_mmio, rtd->ch1, true);1142 } else {1143 acp_dma_start(rtd->acp_mmio, rtd->ch1, true);1144 acp_dma_start(rtd->acp_mmio, rtd->ch2, true);1145 }1146 ret = 0;1147 break;1148 case SNDRV_PCM_TRIGGER_STOP:1149 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:1150 case SNDRV_PCM_TRIGGER_SUSPEND:1151 acp_dma_stop(rtd->acp_mmio, rtd->ch2);1152 ret = acp_dma_stop(rtd->acp_mmio, rtd->ch1);1153 break;1154 default:1155 ret = -EINVAL;1156 }1157 return ret;1158}1159 1160static int acp_dma_new(struct snd_soc_component *component,1161 struct snd_soc_pcm_runtime *rtd)1162{1163 struct audio_drv_data *adata = dev_get_drvdata(component->dev);1164 struct device *parent = component->dev->parent;1165 1166 switch (adata->asic_type) {1167 case CHIP_STONEY:1168 snd_pcm_set_managed_buffer_all(rtd->pcm,1169 SNDRV_DMA_TYPE_DEV,1170 parent,1171 ST_MIN_BUFFER,1172 ST_MAX_BUFFER);1173 break;1174 default:1175 snd_pcm_set_managed_buffer_all(rtd->pcm,1176 SNDRV_DMA_TYPE_DEV,1177 parent,1178 MIN_BUFFER,1179 MAX_BUFFER);1180 break;1181 }1182 return 0;1183}1184 1185static int acp_dma_close(struct snd_soc_component *component,1186 struct snd_pcm_substream *substream)1187{1188 u16 bank;1189 struct snd_pcm_runtime *runtime = substream->runtime;1190 struct audio_substream_data *rtd = runtime->private_data;1191 struct audio_drv_data *adata = dev_get_drvdata(component->dev);1192 1193 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {1194 switch (rtd->i2s_instance) {1195 case I2S_BT_INSTANCE:1196 adata->play_i2sbt_stream = NULL;1197 break;1198 case I2S_MICSP_INSTANCE:1199 adata->play_i2s_micsp_stream = NULL;1200 break;1201 case I2S_SP_INSTANCE:1202 default:1203 adata->play_i2ssp_stream = NULL;1204 /*1205 * For Stoney, Memory gating is disabled,i.e SRAM Banks1206 * won't be turned off. The default state for SRAM banks1207 * is ON.Setting SRAM bank state code skipped for STONEY1208 * platform. Added condition checks for Carrizo platform1209 * only.1210 */1211 if (adata->asic_type != CHIP_STONEY) {1212 for (bank = 1; bank <= 4; bank++)1213 acp_set_sram_bank_state(adata->acp_mmio,1214 bank, false);1215 }1216 }1217 } else {1218 switch (rtd->i2s_instance) {1219 case I2S_BT_INSTANCE:1220 adata->capture_i2sbt_stream = NULL;1221 break;1222 case I2S_MICSP_INSTANCE:1223 case I2S_SP_INSTANCE:1224 default:1225 adata->capture_i2ssp_stream = NULL;1226 if (adata->asic_type != CHIP_STONEY) {1227 for (bank = 5; bank <= 8; bank++)1228 acp_set_sram_bank_state(adata->acp_mmio,1229 bank, false);1230 }1231 }1232 }1233 1234 /*1235 * Disable ACP irq, when the current stream is being closed and1236 * another stream is also not active.1237 */1238 if (!adata->play_i2ssp_stream && !adata->capture_i2ssp_stream &&1239 !adata->play_i2sbt_stream && !adata->capture_i2sbt_stream &&1240 !adata->play_i2s_micsp_stream)1241 acp_reg_write(0, adata->acp_mmio, mmACP_EXTERNAL_INTR_ENB);1242 kfree(rtd);1243 return 0;1244}1245 1246static const struct snd_soc_component_driver acp_asoc_platform = {1247 .name = DRV_NAME,1248 .open = acp_dma_open,1249 .close = acp_dma_close,1250 .hw_params = acp_dma_hw_params,1251 .trigger = acp_dma_trigger,1252 .pointer = acp_dma_pointer,1253 .delay = acp_dma_delay,1254 .prepare = acp_dma_prepare,1255 .pcm_construct = acp_dma_new,1256};1257 1258static int acp_audio_probe(struct platform_device *pdev)1259{1260 int status, irq;1261 struct audio_drv_data *audio_drv_data;1262 const u32 *pdata = pdev->dev.platform_data;1263 1264 if (!pdata) {1265 dev_err(&pdev->dev, "Missing platform data\n");1266 return -ENODEV;1267 }1268 1269 audio_drv_data = devm_kzalloc(&pdev->dev, sizeof(struct audio_drv_data),1270 GFP_KERNEL);1271 if (!audio_drv_data)1272 return -ENOMEM;1273 1274 audio_drv_data->acp_mmio = devm_platform_ioremap_resource(pdev, 0);1275 if (IS_ERR(audio_drv_data->acp_mmio))1276 return PTR_ERR(audio_drv_data->acp_mmio);1277 1278 /*1279 * The following members gets populated in device 'open'1280 * function. Till then interrupts are disabled in 'acp_init'1281 * and device doesn't generate any interrupts.1282 */1283 1284 audio_drv_data->play_i2ssp_stream = NULL;1285 audio_drv_data->capture_i2ssp_stream = NULL;1286 audio_drv_data->play_i2sbt_stream = NULL;1287 audio_drv_data->capture_i2sbt_stream = NULL;1288 audio_drv_data->play_i2s_micsp_stream = NULL;1289 1290 audio_drv_data->asic_type = *pdata;1291 1292 irq = platform_get_irq(pdev, 0);1293 if (irq < 0)1294 return -ENODEV;1295 1296 status = devm_request_irq(&pdev->dev, irq, dma_irq_handler,1297 0, "ACP_IRQ", &pdev->dev);1298 if (status) {1299 dev_err(&pdev->dev, "ACP IRQ request failed\n");1300 return status;1301 }1302 1303 dev_set_drvdata(&pdev->dev, audio_drv_data);1304 1305 /* Initialize the ACP */1306 status = acp_init(audio_drv_data->acp_mmio, audio_drv_data->asic_type);1307 if (status) {1308 dev_err(&pdev->dev, "ACP Init failed status:%d\n", status);1309 return status;1310 }1311 1312 status = devm_snd_soc_register_component(&pdev->dev,1313 &acp_asoc_platform, NULL, 0);1314 if (status != 0) {1315 dev_err(&pdev->dev, "Fail to register ALSA platform device\n");1316 return status;1317 }1318 1319 pm_runtime_set_autosuspend_delay(&pdev->dev, 10000);1320 pm_runtime_use_autosuspend(&pdev->dev);1321 pm_runtime_enable(&pdev->dev);1322 1323 return status;1324}1325 1326static void acp_audio_remove(struct platform_device *pdev)1327{1328 int status;1329 struct audio_drv_data *adata = dev_get_drvdata(&pdev->dev);1330 1331 status = acp_deinit(adata->acp_mmio);1332 if (status)1333 dev_err(&pdev->dev, "ACP Deinit failed status:%d\n", status);1334 pm_runtime_disable(&pdev->dev);1335}1336 1337static int acp_pcm_resume(struct device *dev)1338{1339 u16 bank;1340 int status;1341 struct audio_substream_data *rtd;1342 struct audio_drv_data *adata = dev_get_drvdata(dev);1343 1344 status = acp_init(adata->acp_mmio, adata->asic_type);1345 if (status) {1346 dev_err(dev, "ACP Init failed status:%d\n", status);1347 return status;1348 }1349 1350 if (adata->play_i2ssp_stream && adata->play_i2ssp_stream->runtime) {1351 /*1352 * For Stoney, Memory gating is disabled,i.e SRAM Banks1353 * won't be turned off. The default state for SRAM banks is ON.1354 * Setting SRAM bank state code skipped for STONEY platform.1355 */1356 if (adata->asic_type != CHIP_STONEY) {1357 for (bank = 1; bank <= 4; bank++)1358 acp_set_sram_bank_state(adata->acp_mmio, bank,1359 true);1360 }1361 rtd = adata->play_i2ssp_stream->runtime->private_data;1362 config_acp_dma(adata->acp_mmio, rtd, adata->asic_type);1363 }1364 if (adata->capture_i2ssp_stream &&1365 adata->capture_i2ssp_stream->runtime) {1366 if (adata->asic_type != CHIP_STONEY) {1367 for (bank = 5; bank <= 8; bank++)1368 acp_set_sram_bank_state(adata->acp_mmio, bank,1369 true);1370 }1371 rtd = adata->capture_i2ssp_stream->runtime->private_data;1372 config_acp_dma(adata->acp_mmio, rtd, adata->asic_type);1373 }1374 if (adata->asic_type != CHIP_CARRIZO) {1375 if (adata->play_i2s_micsp_stream &&1376 adata->play_i2s_micsp_stream->runtime) {1377 rtd = adata->play_i2s_micsp_stream->runtime->private_data;1378 config_acp_dma(adata->acp_mmio, rtd, adata->asic_type);1379 }1380 if (adata->play_i2sbt_stream &&1381 adata->play_i2sbt_stream->runtime) {1382 rtd = adata->play_i2sbt_stream->runtime->private_data;1383 config_acp_dma(adata->acp_mmio, rtd, adata->asic_type);1384 }1385 if (adata->capture_i2sbt_stream &&1386 adata->capture_i2sbt_stream->runtime) {1387 rtd = adata->capture_i2sbt_stream->runtime->private_data;1388 config_acp_dma(adata->acp_mmio, rtd, adata->asic_type);1389 }1390 }1391 acp_reg_write(1, adata->acp_mmio, mmACP_EXTERNAL_INTR_ENB);1392 return 0;1393}1394 1395static int acp_pcm_runtime_suspend(struct device *dev)1396{1397 int status;1398 struct audio_drv_data *adata = dev_get_drvdata(dev);1399 1400 status = acp_deinit(adata->acp_mmio);1401 if (status)1402 dev_err(dev, "ACP Deinit failed status:%d\n", status);1403 acp_reg_write(0, adata->acp_mmio, mmACP_EXTERNAL_INTR_ENB);1404 return 0;1405}1406 1407static int acp_pcm_runtime_resume(struct device *dev)1408{1409 int status;1410 struct audio_drv_data *adata = dev_get_drvdata(dev);1411 1412 status = acp_init(adata->acp_mmio, adata->asic_type);1413 if (status) {1414 dev_err(dev, "ACP Init failed status:%d\n", status);1415 return status;1416 }1417 acp_reg_write(1, adata->acp_mmio, mmACP_EXTERNAL_INTR_ENB);1418 return 0;1419}1420 1421static const struct dev_pm_ops acp_pm_ops = {1422 .resume = acp_pcm_resume,1423 .runtime_suspend = acp_pcm_runtime_suspend,1424 .runtime_resume = acp_pcm_runtime_resume,1425};1426 1427static struct platform_driver acp_dma_driver = {1428 .probe = acp_audio_probe,1429 .remove = acp_audio_remove,1430 .driver = {1431 .name = DRV_NAME,1432 .pm = &acp_pm_ops,1433 },1434};1435 1436module_platform_driver(acp_dma_driver);1437 1438MODULE_AUTHOR("Vijendar.Mukunda@amd.com");1439MODULE_AUTHOR("Maruthi.Bayyavarapu@amd.com");1440MODULE_DESCRIPTION("AMD ACP PCM Driver");1441MODULE_LICENSE("GPL v2");1442MODULE_ALIAS("platform:"DRV_NAME);1443