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1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)2//3// This file is provided under a dual BSD/GPLv2 license. When using or4// redistributing this file, you may do so under either license.5//6// Copyright(c) 2022 Advanced Micro Devices, Inc.7//8// Authors: Ajit Kumar Pandey <AjitKumar.Pandey@amd.com>9// Vijendar Mukunda <Vijendar.Mukunda@amd.com>10//11 12/*13 * Generic Hardware interface for ACP Audio PDM controller14 */15 16#include <linux/err.h>17#include <linux/io.h>18#include <linux/module.h>19#include <linux/platform_device.h>20#include <sound/pcm_params.h>21#include <sound/soc.h>22#include <sound/soc-dai.h>23 24#include "amd.h"25 26#define DRV_NAME "acp-pdm"27 28static int acp_dmic_prepare(struct snd_pcm_substream *substream,29 struct snd_soc_dai *dai)30{31 struct acp_stream *stream = substream->runtime->private_data;32 struct device *dev = dai->component->dev;33 struct acp_dev_data *adata = dev_get_drvdata(dev);34 struct acp_chip_info *chip;35 u32 physical_addr, size_dmic, period_bytes;36 unsigned int dmic_ctrl;37 38 chip = dev_get_platdata(dev);39 /* Enable default DMIC clk */40 writel(PDM_CLK_FREQ_MASK, adata->acp_base + ACP_WOV_CLK_CTRL);41 dmic_ctrl = readl(adata->acp_base + ACP_WOV_MISC_CTRL);42 dmic_ctrl |= PDM_MISC_CTRL_MASK;43 writel(dmic_ctrl, adata->acp_base + ACP_WOV_MISC_CTRL);44 45 period_bytes = frames_to_bytes(substream->runtime,46 substream->runtime->period_size);47 size_dmic = frames_to_bytes(substream->runtime,48 substream->runtime->buffer_size);49 50 if (chip->acp_rev >= ACP70_DEV)51 physical_addr = ACP7x_DMIC_MEM_WINDOW_START;52 else53 physical_addr = stream->reg_offset + MEM_WINDOW_START;54 55 /* Init DMIC Ring buffer */56 writel(physical_addr, adata->acp_base + ACP_WOV_RX_RINGBUFADDR);57 writel(size_dmic, adata->acp_base + ACP_WOV_RX_RINGBUFSIZE);58 writel(period_bytes, adata->acp_base + ACP_WOV_RX_INTR_WATERMARK_SIZE);59 writel(0x01, adata->acp_base + ACPAXI2AXI_ATU_CTRL);60 61 return 0;62}63 64static int acp_dmic_dai_trigger(struct snd_pcm_substream *substream,65 int cmd, struct snd_soc_dai *dai)66{67 struct device *dev = dai->component->dev;68 struct acp_dev_data *adata = dev_get_drvdata(dev);69 unsigned int dma_enable;70 int ret = 0;71 72 switch (cmd) {73 case SNDRV_PCM_TRIGGER_START:74 case SNDRV_PCM_TRIGGER_RESUME:75 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:76 dma_enable = readl(adata->acp_base + ACP_WOV_PDM_DMA_ENABLE);77 if (!(dma_enable & DMA_EN_MASK)) {78 writel(PDM_ENABLE, adata->acp_base + ACP_WOV_PDM_ENABLE);79 writel(PDM_ENABLE, adata->acp_base + ACP_WOV_PDM_DMA_ENABLE);80 }81 82 ret = readl_poll_timeout_atomic(adata->acp_base + ACP_WOV_PDM_DMA_ENABLE,83 dma_enable, (dma_enable & DMA_EN_MASK),84 DELAY_US, PDM_TIMEOUT);85 break;86 case SNDRV_PCM_TRIGGER_STOP:87 case SNDRV_PCM_TRIGGER_SUSPEND:88 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:89 dma_enable = readl(adata->acp_base + ACP_WOV_PDM_DMA_ENABLE);90 if ((dma_enable & DMA_EN_MASK)) {91 writel(PDM_DISABLE, adata->acp_base + ACP_WOV_PDM_ENABLE);92 writel(PDM_DISABLE, adata->acp_base + ACP_WOV_PDM_DMA_ENABLE);93 94 }95 96 ret = readl_poll_timeout_atomic(adata->acp_base + ACP_WOV_PDM_DMA_ENABLE,97 dma_enable, !(dma_enable & DMA_EN_MASK),98 DELAY_US, PDM_TIMEOUT);99 break;100 default:101 ret = -EINVAL;102 break;103 }104 105 return ret;106}107 108static int acp_dmic_hwparams(struct snd_pcm_substream *substream,109 struct snd_pcm_hw_params *hwparams, struct snd_soc_dai *dai)110{111 struct device *dev = dai->component->dev;112 struct acp_dev_data *adata = dev_get_drvdata(dev);113 unsigned int channels, ch_mask;114 115 channels = params_channels(hwparams);116 switch (channels) {117 case 2:118 ch_mask = 0;119 break;120 case 4:121 ch_mask = 1;122 break;123 case 6:124 ch_mask = 2;125 break;126 default:127 dev_err(dev, "Invalid channels %d\n", channels);128 return -EINVAL;129 }130 131 adata->ch_mask = ch_mask;132 if (params_format(hwparams) != SNDRV_PCM_FORMAT_S32_LE) {133 dev_err(dai->dev, "Invalid format:%d\n", params_format(hwparams));134 return -EINVAL;135 }136 137 writel(ch_mask, adata->acp_base + ACP_WOV_PDM_NO_OF_CHANNELS);138 writel(PDM_DEC_64, adata->acp_base + ACP_WOV_PDM_DECIMATION_FACTOR);139 140 return 0;141}142 143static int acp_dmic_dai_startup(struct snd_pcm_substream *substream,144 struct snd_soc_dai *dai)145{146 struct acp_stream *stream = substream->runtime->private_data;147 struct device *dev = dai->component->dev;148 struct acp_dev_data *adata = dev_get_drvdata(dev);149 u32 ext_int_ctrl;150 151 stream->dai_id = DMIC_INSTANCE;152 stream->irq_bit = BIT(PDM_DMA_STAT);153 stream->pte_offset = ACP_SRAM_PDM_PTE_OFFSET;154 stream->reg_offset = ACP_REGION2_OFFSET;155 156 /* Enable DMIC Interrupts */157 ext_int_ctrl = readl(ACP_EXTERNAL_INTR_CNTL(adata, 0));158 ext_int_ctrl |= PDM_DMA_INTR_MASK;159 writel(ext_int_ctrl, ACP_EXTERNAL_INTR_CNTL(adata, 0));160 161 return 0;162}163 164static void acp_dmic_dai_shutdown(struct snd_pcm_substream *substream,165 struct snd_soc_dai *dai)166{167 struct device *dev = dai->component->dev;168 struct acp_dev_data *adata = dev_get_drvdata(dev);169 u32 ext_int_ctrl;170 171 /* Disable DMIC interrupts */172 ext_int_ctrl = readl(ACP_EXTERNAL_INTR_CNTL(adata, 0));173 ext_int_ctrl &= ~PDM_DMA_INTR_MASK;174 writel(ext_int_ctrl, ACP_EXTERNAL_INTR_CNTL(adata, 0));175}176 177const struct snd_soc_dai_ops acp_dmic_dai_ops = {178 .prepare = acp_dmic_prepare,179 .hw_params = acp_dmic_hwparams,180 .trigger = acp_dmic_dai_trigger,181 .startup = acp_dmic_dai_startup,182 .shutdown = acp_dmic_dai_shutdown,183};184EXPORT_SYMBOL_NS_GPL(acp_dmic_dai_ops, SND_SOC_ACP_COMMON);185 186MODULE_DESCRIPTION("AMD ACP Audio PDM controller");187MODULE_LICENSE("Dual BSD/GPL");188MODULE_ALIAS(DRV_NAME);189