2293 lines · c
1/*2 * ACP_2_2 Register documentation3 *4 * Copyright (C) 2014 Advanced Micro Devices, Inc.5 *6 * Permission is hereby granted, free of charge, to any person obtaining a7 * copy of this software and associated documentation files (the "Software"),8 * to deal in the Software without restriction, including without limitation9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,10 * and/or sell copies of the Software, and to permit persons to whom the11 * Software is furnished to do so, subject to the following conditions:12 *13 * The above copyright notice and this permission notice shall be included14 * in all copies or substantial portions of the Software.15 *16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL19 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN20 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.22 */23 24#ifndef ACP_2_2_SH_MASK_H25#define ACP_2_2_SH_MASK_H26 27#define ACP_DMA_CNTL_0__DMAChRst_MASK 0x128#define ACP_DMA_CNTL_0__DMAChRst__SHIFT 0x029#define ACP_DMA_CNTL_0__DMAChRun_MASK 0x230#define ACP_DMA_CNTL_0__DMAChRun__SHIFT 0x131#define ACP_DMA_CNTL_0__DMAChIOCEn_MASK 0x432#define ACP_DMA_CNTL_0__DMAChIOCEn__SHIFT 0x233#define ACP_DMA_CNTL_0__Circular_DMA_En_MASK 0x834#define ACP_DMA_CNTL_0__Circular_DMA_En__SHIFT 0x335#define ACP_DMA_CNTL_0__DMAChGracefulRstEn_MASK 0x1036#define ACP_DMA_CNTL_0__DMAChGracefulRstEn__SHIFT 0x437#define ACP_DMA_CNTL_1__DMAChRst_MASK 0x138#define ACP_DMA_CNTL_1__DMAChRst__SHIFT 0x039#define ACP_DMA_CNTL_1__DMAChRun_MASK 0x240#define ACP_DMA_CNTL_1__DMAChRun__SHIFT 0x141#define ACP_DMA_CNTL_1__DMAChIOCEn_MASK 0x442#define ACP_DMA_CNTL_1__DMAChIOCEn__SHIFT 0x243#define ACP_DMA_CNTL_1__Circular_DMA_En_MASK 0x844#define ACP_DMA_CNTL_1__Circular_DMA_En__SHIFT 0x345#define ACP_DMA_CNTL_1__DMAChGracefulRstEn_MASK 0x1046#define ACP_DMA_CNTL_1__DMAChGracefulRstEn__SHIFT 0x447#define ACP_DMA_CNTL_2__DMAChRst_MASK 0x148#define ACP_DMA_CNTL_2__DMAChRst__SHIFT 0x049#define ACP_DMA_CNTL_2__DMAChRun_MASK 0x250#define ACP_DMA_CNTL_2__DMAChRun__SHIFT 0x151#define ACP_DMA_CNTL_2__DMAChIOCEn_MASK 0x452#define ACP_DMA_CNTL_2__DMAChIOCEn__SHIFT 0x253#define ACP_DMA_CNTL_2__Circular_DMA_En_MASK 0x854#define ACP_DMA_CNTL_2__Circular_DMA_En__SHIFT 0x355#define ACP_DMA_CNTL_2__DMAChGracefulRstEn_MASK 0x1056#define ACP_DMA_CNTL_2__DMAChGracefulRstEn__SHIFT 0x457#define ACP_DMA_CNTL_3__DMAChRst_MASK 0x158#define ACP_DMA_CNTL_3__DMAChRst__SHIFT 0x059#define ACP_DMA_CNTL_3__DMAChRun_MASK 0x260#define ACP_DMA_CNTL_3__DMAChRun__SHIFT 0x161#define ACP_DMA_CNTL_3__DMAChIOCEn_MASK 0x462#define ACP_DMA_CNTL_3__DMAChIOCEn__SHIFT 0x263#define ACP_DMA_CNTL_3__Circular_DMA_En_MASK 0x864#define ACP_DMA_CNTL_3__Circular_DMA_En__SHIFT 0x365#define ACP_DMA_CNTL_3__DMAChGracefulRstEn_MASK 0x1066#define ACP_DMA_CNTL_3__DMAChGracefulRstEn__SHIFT 0x467#define ACP_DMA_CNTL_4__DMAChRst_MASK 0x168#define ACP_DMA_CNTL_4__DMAChRst__SHIFT 0x069#define ACP_DMA_CNTL_4__DMAChRun_MASK 0x270#define ACP_DMA_CNTL_4__DMAChRun__SHIFT 0x171#define ACP_DMA_CNTL_4__DMAChIOCEn_MASK 0x472#define ACP_DMA_CNTL_4__DMAChIOCEn__SHIFT 0x273#define ACP_DMA_CNTL_4__Circular_DMA_En_MASK 0x874#define ACP_DMA_CNTL_4__Circular_DMA_En__SHIFT 0x375#define ACP_DMA_CNTL_4__DMAChGracefulRstEn_MASK 0x1076#define ACP_DMA_CNTL_4__DMAChGracefulRstEn__SHIFT 0x477#define ACP_DMA_CNTL_5__DMAChRst_MASK 0x178#define ACP_DMA_CNTL_5__DMAChRst__SHIFT 0x079#define ACP_DMA_CNTL_5__DMAChRun_MASK 0x280#define ACP_DMA_CNTL_5__DMAChRun__SHIFT 0x181#define ACP_DMA_CNTL_5__DMAChIOCEn_MASK 0x482#define ACP_DMA_CNTL_5__DMAChIOCEn__SHIFT 0x283#define ACP_DMA_CNTL_5__Circular_DMA_En_MASK 0x884#define ACP_DMA_CNTL_5__Circular_DMA_En__SHIFT 0x385#define ACP_DMA_CNTL_5__DMAChGracefulRstEn_MASK 0x1086#define ACP_DMA_CNTL_5__DMAChGracefulRstEn__SHIFT 0x487#define ACP_DMA_CNTL_6__DMAChRst_MASK 0x188#define ACP_DMA_CNTL_6__DMAChRst__SHIFT 0x089#define ACP_DMA_CNTL_6__DMAChRun_MASK 0x290#define ACP_DMA_CNTL_6__DMAChRun__SHIFT 0x191#define ACP_DMA_CNTL_6__DMAChIOCEn_MASK 0x492#define ACP_DMA_CNTL_6__DMAChIOCEn__SHIFT 0x293#define ACP_DMA_CNTL_6__Circular_DMA_En_MASK 0x894#define ACP_DMA_CNTL_6__Circular_DMA_En__SHIFT 0x395#define ACP_DMA_CNTL_6__DMAChGracefulRstEn_MASK 0x1096#define ACP_DMA_CNTL_6__DMAChGracefulRstEn__SHIFT 0x497#define ACP_DMA_CNTL_7__DMAChRst_MASK 0x198#define ACP_DMA_CNTL_7__DMAChRst__SHIFT 0x099#define ACP_DMA_CNTL_7__DMAChRun_MASK 0x2100#define ACP_DMA_CNTL_7__DMAChRun__SHIFT 0x1101#define ACP_DMA_CNTL_7__DMAChIOCEn_MASK 0x4102#define ACP_DMA_CNTL_7__DMAChIOCEn__SHIFT 0x2103#define ACP_DMA_CNTL_7__Circular_DMA_En_MASK 0x8104#define ACP_DMA_CNTL_7__Circular_DMA_En__SHIFT 0x3105#define ACP_DMA_CNTL_7__DMAChGracefulRstEn_MASK 0x10106#define ACP_DMA_CNTL_7__DMAChGracefulRstEn__SHIFT 0x4107#define ACP_DMA_CNTL_8__DMAChRst_MASK 0x1108#define ACP_DMA_CNTL_8__DMAChRst__SHIFT 0x0109#define ACP_DMA_CNTL_8__DMAChRun_MASK 0x2110#define ACP_DMA_CNTL_8__DMAChRun__SHIFT 0x1111#define ACP_DMA_CNTL_8__DMAChIOCEn_MASK 0x4112#define ACP_DMA_CNTL_8__DMAChIOCEn__SHIFT 0x2113#define ACP_DMA_CNTL_8__Circular_DMA_En_MASK 0x8114#define ACP_DMA_CNTL_8__Circular_DMA_En__SHIFT 0x3115#define ACP_DMA_CNTL_8__DMAChGracefulRstEn_MASK 0x10116#define ACP_DMA_CNTL_8__DMAChGracefulRstEn__SHIFT 0x4117#define ACP_DMA_CNTL_9__DMAChRst_MASK 0x1118#define ACP_DMA_CNTL_9__DMAChRst__SHIFT 0x0119#define ACP_DMA_CNTL_9__DMAChRun_MASK 0x2120#define ACP_DMA_CNTL_9__DMAChRun__SHIFT 0x1121#define ACP_DMA_CNTL_9__DMAChIOCEn_MASK 0x4122#define ACP_DMA_CNTL_9__DMAChIOCEn__SHIFT 0x2123#define ACP_DMA_CNTL_9__Circular_DMA_En_MASK 0x8124#define ACP_DMA_CNTL_9__Circular_DMA_En__SHIFT 0x3125#define ACP_DMA_CNTL_9__DMAChGracefulRstEn_MASK 0x10126#define ACP_DMA_CNTL_9__DMAChGracefulRstEn__SHIFT 0x4127#define ACP_DMA_CNTL_10__DMAChRst_MASK 0x1128#define ACP_DMA_CNTL_10__DMAChRst__SHIFT 0x0129#define ACP_DMA_CNTL_10__DMAChRun_MASK 0x2130#define ACP_DMA_CNTL_10__DMAChRun__SHIFT 0x1131#define ACP_DMA_CNTL_10__DMAChIOCEn_MASK 0x4132#define ACP_DMA_CNTL_10__DMAChIOCEn__SHIFT 0x2133#define ACP_DMA_CNTL_10__Circular_DMA_En_MASK 0x8134#define ACP_DMA_CNTL_10__Circular_DMA_En__SHIFT 0x3135#define ACP_DMA_CNTL_10__DMAChGracefulRstEn_MASK 0x10136#define ACP_DMA_CNTL_10__DMAChGracefulRstEn__SHIFT 0x4137#define ACP_DMA_CNTL_11__DMAChRst_MASK 0x1138#define ACP_DMA_CNTL_11__DMAChRst__SHIFT 0x0139#define ACP_DMA_CNTL_11__DMAChRun_MASK 0x2140#define ACP_DMA_CNTL_11__DMAChRun__SHIFT 0x1141#define ACP_DMA_CNTL_11__DMAChIOCEn_MASK 0x4142#define ACP_DMA_CNTL_11__DMAChIOCEn__SHIFT 0x2143#define ACP_DMA_CNTL_11__Circular_DMA_En_MASK 0x8144#define ACP_DMA_CNTL_11__Circular_DMA_En__SHIFT 0x3145#define ACP_DMA_CNTL_11__DMAChGracefulRstEn_MASK 0x10146#define ACP_DMA_CNTL_11__DMAChGracefulRstEn__SHIFT 0x4147#define ACP_DMA_CNTL_12__DMAChRst_MASK 0x1148#define ACP_DMA_CNTL_12__DMAChRst__SHIFT 0x0149#define ACP_DMA_CNTL_12__DMAChRun_MASK 0x2150#define ACP_DMA_CNTL_12__DMAChRun__SHIFT 0x1151#define ACP_DMA_CNTL_12__DMAChIOCEn_MASK 0x4152#define ACP_DMA_CNTL_12__DMAChIOCEn__SHIFT 0x2153#define ACP_DMA_CNTL_12__Circular_DMA_En_MASK 0x8154#define ACP_DMA_CNTL_12__Circular_DMA_En__SHIFT 0x3155#define ACP_DMA_CNTL_12__DMAChGracefulRstEn_MASK 0x10156#define ACP_DMA_CNTL_12__DMAChGracefulRstEn__SHIFT 0x4157#define ACP_DMA_CNTL_13__DMAChRst_MASK 0x1158#define ACP_DMA_CNTL_13__DMAChRst__SHIFT 0x0159#define ACP_DMA_CNTL_13__DMAChRun_MASK 0x2160#define ACP_DMA_CNTL_13__DMAChRun__SHIFT 0x1161#define ACP_DMA_CNTL_13__DMAChIOCEn_MASK 0x4162#define ACP_DMA_CNTL_13__DMAChIOCEn__SHIFT 0x2163#define ACP_DMA_CNTL_13__Circular_DMA_En_MASK 0x8164#define ACP_DMA_CNTL_13__Circular_DMA_En__SHIFT 0x3165#define ACP_DMA_CNTL_13__DMAChGracefulRstEn_MASK 0x10166#define ACP_DMA_CNTL_13__DMAChGracefulRstEn__SHIFT 0x4167#define ACP_DMA_CNTL_14__DMAChRst_MASK 0x1168#define ACP_DMA_CNTL_14__DMAChRst__SHIFT 0x0169#define ACP_DMA_CNTL_14__DMAChRun_MASK 0x2170#define ACP_DMA_CNTL_14__DMAChRun__SHIFT 0x1171#define ACP_DMA_CNTL_14__DMAChIOCEn_MASK 0x4172#define ACP_DMA_CNTL_14__DMAChIOCEn__SHIFT 0x2173#define ACP_DMA_CNTL_14__Circular_DMA_En_MASK 0x8174#define ACP_DMA_CNTL_14__Circular_DMA_En__SHIFT 0x3175#define ACP_DMA_CNTL_14__DMAChGracefulRstEn_MASK 0x10176#define ACP_DMA_CNTL_14__DMAChGracefulRstEn__SHIFT 0x4177#define ACP_DMA_CNTL_15__DMAChRst_MASK 0x1178#define ACP_DMA_CNTL_15__DMAChRst__SHIFT 0x0179#define ACP_DMA_CNTL_15__DMAChRun_MASK 0x2180#define ACP_DMA_CNTL_15__DMAChRun__SHIFT 0x1181#define ACP_DMA_CNTL_15__DMAChIOCEn_MASK 0x4182#define ACP_DMA_CNTL_15__DMAChIOCEn__SHIFT 0x2183#define ACP_DMA_CNTL_15__Circular_DMA_En_MASK 0x8184#define ACP_DMA_CNTL_15__Circular_DMA_En__SHIFT 0x3185#define ACP_DMA_CNTL_15__DMAChGracefulRstEn_MASK 0x10186#define ACP_DMA_CNTL_15__DMAChGracefulRstEn__SHIFT 0x4187#define ACP_DMA_DSCR_STRT_IDX_0__DMAChDscrStrtIdx_MASK 0x3ff188#define ACP_DMA_DSCR_STRT_IDX_0__DMAChDscrStrtIdx__SHIFT 0x0189#define ACP_DMA_DSCR_STRT_IDX_1__DMAChDscrStrtIdx_MASK 0x3ff190#define ACP_DMA_DSCR_STRT_IDX_1__DMAChDscrStrtIdx__SHIFT 0x0191#define ACP_DMA_DSCR_STRT_IDX_2__DMAChDscrStrtIdx_MASK 0x3ff192#define ACP_DMA_DSCR_STRT_IDX_2__DMAChDscrStrtIdx__SHIFT 0x0193#define ACP_DMA_DSCR_STRT_IDX_3__DMAChDscrStrtIdx_MASK 0x3ff194#define ACP_DMA_DSCR_STRT_IDX_3__DMAChDscrStrtIdx__SHIFT 0x0195#define ACP_DMA_DSCR_STRT_IDX_4__DMAChDscrStrtIdx_MASK 0x3ff196#define ACP_DMA_DSCR_STRT_IDX_4__DMAChDscrStrtIdx__SHIFT 0x0197#define ACP_DMA_DSCR_STRT_IDX_5__DMAChDscrStrtIdx_MASK 0x3ff198#define ACP_DMA_DSCR_STRT_IDX_5__DMAChDscrStrtIdx__SHIFT 0x0199#define ACP_DMA_DSCR_STRT_IDX_6__DMAChDscrStrtIdx_MASK 0x3ff200#define ACP_DMA_DSCR_STRT_IDX_6__DMAChDscrStrtIdx__SHIFT 0x0201#define ACP_DMA_DSCR_STRT_IDX_7__DMAChDscrStrtIdx_MASK 0x3ff202#define ACP_DMA_DSCR_STRT_IDX_7__DMAChDscrStrtIdx__SHIFT 0x0203#define ACP_DMA_DSCR_STRT_IDX_8__DMAChDscrStrtIdx_MASK 0x3ff204#define ACP_DMA_DSCR_STRT_IDX_8__DMAChDscrStrtIdx__SHIFT 0x0205#define ACP_DMA_DSCR_STRT_IDX_9__DMAChDscrStrtIdx_MASK 0x3ff206#define ACP_DMA_DSCR_STRT_IDX_9__DMAChDscrStrtIdx__SHIFT 0x0207#define ACP_DMA_DSCR_STRT_IDX_10__DMAChDscrStrtIdx_MASK 0x3ff208#define ACP_DMA_DSCR_STRT_IDX_10__DMAChDscrStrtIdx__SHIFT 0x0209#define ACP_DMA_DSCR_STRT_IDX_11__DMAChDscrStrtIdx_MASK 0x3ff210#define ACP_DMA_DSCR_STRT_IDX_11__DMAChDscrStrtIdx__SHIFT 0x0211#define ACP_DMA_DSCR_STRT_IDX_12__DMAChDscrStrtIdx_MASK 0x3ff212#define ACP_DMA_DSCR_STRT_IDX_12__DMAChDscrStrtIdx__SHIFT 0x0213#define ACP_DMA_DSCR_STRT_IDX_13__DMAChDscrStrtIdx_MASK 0x3ff214#define ACP_DMA_DSCR_STRT_IDX_13__DMAChDscrStrtIdx__SHIFT 0x0215#define ACP_DMA_DSCR_STRT_IDX_14__DMAChDscrStrtIdx_MASK 0x3ff216#define ACP_DMA_DSCR_STRT_IDX_14__DMAChDscrStrtIdx__SHIFT 0x0217#define ACP_DMA_DSCR_STRT_IDX_15__DMAChDscrStrtIdx_MASK 0x3ff218#define ACP_DMA_DSCR_STRT_IDX_15__DMAChDscrStrtIdx__SHIFT 0x0219#define ACP_DMA_DSCR_CNT_0__DMAChDscrCnt_MASK 0x3ff220#define ACP_DMA_DSCR_CNT_0__DMAChDscrCnt__SHIFT 0x0221#define ACP_DMA_DSCR_CNT_1__DMAChDscrCnt_MASK 0x3ff222#define ACP_DMA_DSCR_CNT_1__DMAChDscrCnt__SHIFT 0x0223#define ACP_DMA_DSCR_CNT_2__DMAChDscrCnt_MASK 0x3ff224#define ACP_DMA_DSCR_CNT_2__DMAChDscrCnt__SHIFT 0x0225#define ACP_DMA_DSCR_CNT_3__DMAChDscrCnt_MASK 0x3ff226#define ACP_DMA_DSCR_CNT_3__DMAChDscrCnt__SHIFT 0x0227#define ACP_DMA_DSCR_CNT_4__DMAChDscrCnt_MASK 0x3ff228#define ACP_DMA_DSCR_CNT_4__DMAChDscrCnt__SHIFT 0x0229#define ACP_DMA_DSCR_CNT_5__DMAChDscrCnt_MASK 0x3ff230#define ACP_DMA_DSCR_CNT_5__DMAChDscrCnt__SHIFT 0x0231#define ACP_DMA_DSCR_CNT_6__DMAChDscrCnt_MASK 0x3ff232#define ACP_DMA_DSCR_CNT_6__DMAChDscrCnt__SHIFT 0x0233#define ACP_DMA_DSCR_CNT_7__DMAChDscrCnt_MASK 0x3ff234#define ACP_DMA_DSCR_CNT_7__DMAChDscrCnt__SHIFT 0x0235#define ACP_DMA_DSCR_CNT_8__DMAChDscrCnt_MASK 0x3ff236#define ACP_DMA_DSCR_CNT_8__DMAChDscrCnt__SHIFT 0x0237#define ACP_DMA_DSCR_CNT_9__DMAChDscrCnt_MASK 0x3ff238#define ACP_DMA_DSCR_CNT_9__DMAChDscrCnt__SHIFT 0x0239#define ACP_DMA_DSCR_CNT_10__DMAChDscrCnt_MASK 0x3ff240#define ACP_DMA_DSCR_CNT_10__DMAChDscrCnt__SHIFT 0x0241#define ACP_DMA_DSCR_CNT_11__DMAChDscrCnt_MASK 0x3ff242#define ACP_DMA_DSCR_CNT_11__DMAChDscrCnt__SHIFT 0x0243#define ACP_DMA_DSCR_CNT_12__DMAChDscrCnt_MASK 0x3ff244#define ACP_DMA_DSCR_CNT_12__DMAChDscrCnt__SHIFT 0x0245#define ACP_DMA_DSCR_CNT_13__DMAChDscrCnt_MASK 0x3ff246#define ACP_DMA_DSCR_CNT_13__DMAChDscrCnt__SHIFT 0x0247#define ACP_DMA_DSCR_CNT_14__DMAChDscrCnt_MASK 0x3ff248#define ACP_DMA_DSCR_CNT_14__DMAChDscrCnt__SHIFT 0x0249#define ACP_DMA_DSCR_CNT_15__DMAChDscrCnt_MASK 0x3ff250#define ACP_DMA_DSCR_CNT_15__DMAChDscrCnt__SHIFT 0x0251#define ACP_DMA_PRIO_0__DMAChPrioLvl_MASK 0x1252#define ACP_DMA_PRIO_0__DMAChPrioLvl__SHIFT 0x0253#define ACP_DMA_PRIO_1__DMAChPrioLvl_MASK 0x1254#define ACP_DMA_PRIO_1__DMAChPrioLvl__SHIFT 0x0255#define ACP_DMA_PRIO_2__DMAChPrioLvl_MASK 0x1256#define ACP_DMA_PRIO_2__DMAChPrioLvl__SHIFT 0x0257#define ACP_DMA_PRIO_3__DMAChPrioLvl_MASK 0x1258#define ACP_DMA_PRIO_3__DMAChPrioLvl__SHIFT 0x0259#define ACP_DMA_PRIO_4__DMAChPrioLvl_MASK 0x1260#define ACP_DMA_PRIO_4__DMAChPrioLvl__SHIFT 0x0261#define ACP_DMA_PRIO_5__DMAChPrioLvl_MASK 0x1262#define ACP_DMA_PRIO_5__DMAChPrioLvl__SHIFT 0x0263#define ACP_DMA_PRIO_6__DMAChPrioLvl_MASK 0x1264#define ACP_DMA_PRIO_6__DMAChPrioLvl__SHIFT 0x0265#define ACP_DMA_PRIO_7__DMAChPrioLvl_MASK 0x1266#define ACP_DMA_PRIO_7__DMAChPrioLvl__SHIFT 0x0267#define ACP_DMA_PRIO_8__DMAChPrioLvl_MASK 0x1268#define ACP_DMA_PRIO_8__DMAChPrioLvl__SHIFT 0x0269#define ACP_DMA_PRIO_9__DMAChPrioLvl_MASK 0x1270#define ACP_DMA_PRIO_9__DMAChPrioLvl__SHIFT 0x0271#define ACP_DMA_PRIO_10__DMAChPrioLvl_MASK 0x1272#define ACP_DMA_PRIO_10__DMAChPrioLvl__SHIFT 0x0273#define ACP_DMA_PRIO_11__DMAChPrioLvl_MASK 0x1274#define ACP_DMA_PRIO_11__DMAChPrioLvl__SHIFT 0x0275#define ACP_DMA_PRIO_12__DMAChPrioLvl_MASK 0x1276#define ACP_DMA_PRIO_12__DMAChPrioLvl__SHIFT 0x0277#define ACP_DMA_PRIO_13__DMAChPrioLvl_MASK 0x1278#define ACP_DMA_PRIO_13__DMAChPrioLvl__SHIFT 0x0279#define ACP_DMA_PRIO_14__DMAChPrioLvl_MASK 0x1280#define ACP_DMA_PRIO_14__DMAChPrioLvl__SHIFT 0x0281#define ACP_DMA_PRIO_15__DMAChPrioLvl_MASK 0x1282#define ACP_DMA_PRIO_15__DMAChPrioLvl__SHIFT 0x0283#define ACP_DMA_CUR_DSCR_0__DMAChCurDscrIdx_MASK 0x3ff284#define ACP_DMA_CUR_DSCR_0__DMAChCurDscrIdx__SHIFT 0x0285#define ACP_DMA_CUR_DSCR_1__DMAChCurDscrIdx_MASK 0x3ff286#define ACP_DMA_CUR_DSCR_1__DMAChCurDscrIdx__SHIFT 0x0287#define ACP_DMA_CUR_DSCR_2__DMAChCurDscrIdx_MASK 0x3ff288#define ACP_DMA_CUR_DSCR_2__DMAChCurDscrIdx__SHIFT 0x0289#define ACP_DMA_CUR_DSCR_3__DMAChCurDscrIdx_MASK 0x3ff290#define ACP_DMA_CUR_DSCR_3__DMAChCurDscrIdx__SHIFT 0x0291#define ACP_DMA_CUR_DSCR_4__DMAChCurDscrIdx_MASK 0x3ff292#define ACP_DMA_CUR_DSCR_4__DMAChCurDscrIdx__SHIFT 0x0293#define ACP_DMA_CUR_DSCR_5__DMAChCurDscrIdx_MASK 0x3ff294#define ACP_DMA_CUR_DSCR_5__DMAChCurDscrIdx__SHIFT 0x0295#define ACP_DMA_CUR_DSCR_6__DMAChCurDscrIdx_MASK 0x3ff296#define ACP_DMA_CUR_DSCR_6__DMAChCurDscrIdx__SHIFT 0x0297#define ACP_DMA_CUR_DSCR_7__DMAChCurDscrIdx_MASK 0x3ff298#define ACP_DMA_CUR_DSCR_7__DMAChCurDscrIdx__SHIFT 0x0299#define ACP_DMA_CUR_DSCR_8__DMAChCurDscrIdx_MASK 0x3ff300#define ACP_DMA_CUR_DSCR_8__DMAChCurDscrIdx__SHIFT 0x0301#define ACP_DMA_CUR_DSCR_9__DMAChCurDscrIdx_MASK 0x3ff302#define ACP_DMA_CUR_DSCR_9__DMAChCurDscrIdx__SHIFT 0x0303#define ACP_DMA_CUR_DSCR_10__DMAChCurDscrIdx_MASK 0x3ff304#define ACP_DMA_CUR_DSCR_10__DMAChCurDscrIdx__SHIFT 0x0305#define ACP_DMA_CUR_DSCR_11__DMAChCurDscrIdx_MASK 0x3ff306#define ACP_DMA_CUR_DSCR_11__DMAChCurDscrIdx__SHIFT 0x0307#define ACP_DMA_CUR_DSCR_12__DMAChCurDscrIdx_MASK 0x3ff308#define ACP_DMA_CUR_DSCR_12__DMAChCurDscrIdx__SHIFT 0x0309#define ACP_DMA_CUR_DSCR_13__DMAChCurDscrIdx_MASK 0x3ff310#define ACP_DMA_CUR_DSCR_13__DMAChCurDscrIdx__SHIFT 0x0311#define ACP_DMA_CUR_DSCR_14__DMAChCurDscrIdx_MASK 0x3ff312#define ACP_DMA_CUR_DSCR_14__DMAChCurDscrIdx__SHIFT 0x0313#define ACP_DMA_CUR_DSCR_15__DMAChCurDscrIdx_MASK 0x3ff314#define ACP_DMA_CUR_DSCR_15__DMAChCurDscrIdx__SHIFT 0x0315#define ACP_DMA_CUR_TRANS_CNT_0__DMAChCurTransCnt_MASK 0x1ffff316#define ACP_DMA_CUR_TRANS_CNT_0__DMAChCurTransCnt__SHIFT 0x0317#define ACP_DMA_CUR_TRANS_CNT_1__DMAChCurTransCnt_MASK 0x1ffff318#define ACP_DMA_CUR_TRANS_CNT_1__DMAChCurTransCnt__SHIFT 0x0319#define ACP_DMA_CUR_TRANS_CNT_2__DMAChCurTransCnt_MASK 0x1ffff320#define ACP_DMA_CUR_TRANS_CNT_2__DMAChCurTransCnt__SHIFT 0x0321#define ACP_DMA_CUR_TRANS_CNT_3__DMAChCurTransCnt_MASK 0x1ffff322#define ACP_DMA_CUR_TRANS_CNT_3__DMAChCurTransCnt__SHIFT 0x0323#define ACP_DMA_CUR_TRANS_CNT_4__DMAChCurTransCnt_MASK 0x1ffff324#define ACP_DMA_CUR_TRANS_CNT_4__DMAChCurTransCnt__SHIFT 0x0325#define ACP_DMA_CUR_TRANS_CNT_5__DMAChCurTransCnt_MASK 0x1ffff326#define ACP_DMA_CUR_TRANS_CNT_5__DMAChCurTransCnt__SHIFT 0x0327#define ACP_DMA_CUR_TRANS_CNT_6__DMAChCurTransCnt_MASK 0x1ffff328#define ACP_DMA_CUR_TRANS_CNT_6__DMAChCurTransCnt__SHIFT 0x0329#define ACP_DMA_CUR_TRANS_CNT_7__DMAChCurTransCnt_MASK 0x1ffff330#define ACP_DMA_CUR_TRANS_CNT_7__DMAChCurTransCnt__SHIFT 0x0331#define ACP_DMA_CUR_TRANS_CNT_8__DMAChCurTransCnt_MASK 0x1ffff332#define ACP_DMA_CUR_TRANS_CNT_8__DMAChCurTransCnt__SHIFT 0x0333#define ACP_DMA_CUR_TRANS_CNT_9__DMAChCurTransCnt_MASK 0x1ffff334#define ACP_DMA_CUR_TRANS_CNT_9__DMAChCurTransCnt__SHIFT 0x0335#define ACP_DMA_CUR_TRANS_CNT_10__DMAChCurTransCnt_MASK 0x1ffff336#define ACP_DMA_CUR_TRANS_CNT_10__DMAChCurTransCnt__SHIFT 0x0337#define ACP_DMA_CUR_TRANS_CNT_11__DMAChCurTransCnt_MASK 0x1ffff338#define ACP_DMA_CUR_TRANS_CNT_11__DMAChCurTransCnt__SHIFT 0x0339#define ACP_DMA_CUR_TRANS_CNT_12__DMAChCurTransCnt_MASK 0x1ffff340#define ACP_DMA_CUR_TRANS_CNT_12__DMAChCurTransCnt__SHIFT 0x0341#define ACP_DMA_CUR_TRANS_CNT_13__DMAChCurTransCnt_MASK 0x1ffff342#define ACP_DMA_CUR_TRANS_CNT_13__DMAChCurTransCnt__SHIFT 0x0343#define ACP_DMA_CUR_TRANS_CNT_14__DMAChCurTransCnt_MASK 0x1ffff344#define ACP_DMA_CUR_TRANS_CNT_14__DMAChCurTransCnt__SHIFT 0x0345#define ACP_DMA_CUR_TRANS_CNT_15__DMAChCurTransCnt_MASK 0x1ffff346#define ACP_DMA_CUR_TRANS_CNT_15__DMAChCurTransCnt__SHIFT 0x0347#define ACP_DMA_ERR_STS_0__DMAChTermErr_MASK 0x1348#define ACP_DMA_ERR_STS_0__DMAChTermErr__SHIFT 0x0349#define ACP_DMA_ERR_STS_0__DMAChErrCode_MASK 0x1e350#define ACP_DMA_ERR_STS_0__DMAChErrCode__SHIFT 0x1351#define ACP_DMA_ERR_STS_1__DMAChTermErr_MASK 0x1352#define ACP_DMA_ERR_STS_1__DMAChTermErr__SHIFT 0x0353#define ACP_DMA_ERR_STS_1__DMAChErrCode_MASK 0x1e354#define ACP_DMA_ERR_STS_1__DMAChErrCode__SHIFT 0x1355#define ACP_DMA_ERR_STS_2__DMAChTermErr_MASK 0x1356#define ACP_DMA_ERR_STS_2__DMAChTermErr__SHIFT 0x0357#define ACP_DMA_ERR_STS_2__DMAChErrCode_MASK 0x1e358#define ACP_DMA_ERR_STS_2__DMAChErrCode__SHIFT 0x1359#define ACP_DMA_ERR_STS_3__DMAChTermErr_MASK 0x1360#define ACP_DMA_ERR_STS_3__DMAChTermErr__SHIFT 0x0361#define ACP_DMA_ERR_STS_3__DMAChErrCode_MASK 0x1e362#define ACP_DMA_ERR_STS_3__DMAChErrCode__SHIFT 0x1363#define ACP_DMA_ERR_STS_4__DMAChTermErr_MASK 0x1364#define ACP_DMA_ERR_STS_4__DMAChTermErr__SHIFT 0x0365#define ACP_DMA_ERR_STS_4__DMAChErrCode_MASK 0x1e366#define ACP_DMA_ERR_STS_4__DMAChErrCode__SHIFT 0x1367#define ACP_DMA_ERR_STS_5__DMAChTermErr_MASK 0x1368#define ACP_DMA_ERR_STS_5__DMAChTermErr__SHIFT 0x0369#define ACP_DMA_ERR_STS_5__DMAChErrCode_MASK 0x1e370#define ACP_DMA_ERR_STS_5__DMAChErrCode__SHIFT 0x1371#define ACP_DMA_ERR_STS_6__DMAChTermErr_MASK 0x1372#define ACP_DMA_ERR_STS_6__DMAChTermErr__SHIFT 0x0373#define ACP_DMA_ERR_STS_6__DMAChErrCode_MASK 0x1e374#define ACP_DMA_ERR_STS_6__DMAChErrCode__SHIFT 0x1375#define ACP_DMA_ERR_STS_7__DMAChTermErr_MASK 0x1376#define ACP_DMA_ERR_STS_7__DMAChTermErr__SHIFT 0x0377#define ACP_DMA_ERR_STS_7__DMAChErrCode_MASK 0x1e378#define ACP_DMA_ERR_STS_7__DMAChErrCode__SHIFT 0x1379#define ACP_DMA_ERR_STS_8__DMAChTermErr_MASK 0x1380#define ACP_DMA_ERR_STS_8__DMAChTermErr__SHIFT 0x0381#define ACP_DMA_ERR_STS_8__DMAChErrCode_MASK 0x1e382#define ACP_DMA_ERR_STS_8__DMAChErrCode__SHIFT 0x1383#define ACP_DMA_ERR_STS_9__DMAChTermErr_MASK 0x1384#define ACP_DMA_ERR_STS_9__DMAChTermErr__SHIFT 0x0385#define ACP_DMA_ERR_STS_9__DMAChErrCode_MASK 0x1e386#define ACP_DMA_ERR_STS_9__DMAChErrCode__SHIFT 0x1387#define ACP_DMA_ERR_STS_10__DMAChTermErr_MASK 0x1388#define ACP_DMA_ERR_STS_10__DMAChTermErr__SHIFT 0x0389#define ACP_DMA_ERR_STS_10__DMAChErrCode_MASK 0x1e390#define ACP_DMA_ERR_STS_10__DMAChErrCode__SHIFT 0x1391#define ACP_DMA_ERR_STS_11__DMAChTermErr_MASK 0x1392#define ACP_DMA_ERR_STS_11__DMAChTermErr__SHIFT 0x0393#define ACP_DMA_ERR_STS_11__DMAChErrCode_MASK 0x1e394#define ACP_DMA_ERR_STS_11__DMAChErrCode__SHIFT 0x1395#define ACP_DMA_ERR_STS_12__DMAChTermErr_MASK 0x1396#define ACP_DMA_ERR_STS_12__DMAChTermErr__SHIFT 0x0397#define ACP_DMA_ERR_STS_12__DMAChErrCode_MASK 0x1e398#define ACP_DMA_ERR_STS_12__DMAChErrCode__SHIFT 0x1399#define ACP_DMA_ERR_STS_13__DMAChTermErr_MASK 0x1400#define ACP_DMA_ERR_STS_13__DMAChTermErr__SHIFT 0x0401#define ACP_DMA_ERR_STS_13__DMAChErrCode_MASK 0x1e402#define ACP_DMA_ERR_STS_13__DMAChErrCode__SHIFT 0x1403#define ACP_DMA_ERR_STS_14__DMAChTermErr_MASK 0x1404#define ACP_DMA_ERR_STS_14__DMAChTermErr__SHIFT 0x0405#define ACP_DMA_ERR_STS_14__DMAChErrCode_MASK 0x1e406#define ACP_DMA_ERR_STS_14__DMAChErrCode__SHIFT 0x1407#define ACP_DMA_ERR_STS_15__DMAChTermErr_MASK 0x1408#define ACP_DMA_ERR_STS_15__DMAChTermErr__SHIFT 0x0409#define ACP_DMA_ERR_STS_15__DMAChErrCode_MASK 0x1e410#define ACP_DMA_ERR_STS_15__DMAChErrCode__SHIFT 0x1411#define ACP_DMA_DESC_BASE_ADDR__DescriptorBaseAddr_MASK 0xffffffff412#define ACP_DMA_DESC_BASE_ADDR__DescriptorBaseAddr__SHIFT 0x0413#define ACP_DMA_DESC_MAX_NUM_DSCR__MaximumNumberDescr_MASK 0xf414#define ACP_DMA_DESC_MAX_NUM_DSCR__MaximumNumberDescr__SHIFT 0x0415#define ACP_DMA_CH_STS__DMAChSts_MASK 0xffff416#define ACP_DMA_CH_STS__DMAChSts__SHIFT 0x0417#define ACP_DMA_CH_GROUP__DMAChanelGrouping_MASK 0x1418#define ACP_DMA_CH_GROUP__DMAChanelGrouping__SHIFT 0x0419#define ACP_DSP0_CACHE_OFFSET0__Offset_MASK 0xfffffff420#define ACP_DSP0_CACHE_OFFSET0__Offset__SHIFT 0x0421#define ACP_DSP0_CACHE_OFFSET0__OnionGarlicSel_MASK 0x80000000422#define ACP_DSP0_CACHE_OFFSET0__OnionGarlicSel__SHIFT 0x1f423#define ACP_DSP0_CACHE_SIZE0__Size_MASK 0xffffff424#define ACP_DSP0_CACHE_SIZE0__Size__SHIFT 0x0425#define ACP_DSP0_CACHE_SIZE0__PageEnable_MASK 0x80000000426#define ACP_DSP0_CACHE_SIZE0__PageEnable__SHIFT 0x1f427#define ACP_DSP0_CACHE_OFFSET1__Offset_MASK 0xfffffff428#define ACP_DSP0_CACHE_OFFSET1__Offset__SHIFT 0x0429#define ACP_DSP0_CACHE_OFFSET1__OnionGarlicSel_MASK 0x80000000430#define ACP_DSP0_CACHE_OFFSET1__OnionGarlicSel__SHIFT 0x1f431#define ACP_DSP0_CACHE_SIZE1__Size_MASK 0xffffff432#define ACP_DSP0_CACHE_SIZE1__Size__SHIFT 0x0433#define ACP_DSP0_CACHE_SIZE1__PageEnable_MASK 0x80000000434#define ACP_DSP0_CACHE_SIZE1__PageEnable__SHIFT 0x1f435#define ACP_DSP0_CACHE_OFFSET2__Offset_MASK 0xfffffff436#define ACP_DSP0_CACHE_OFFSET2__Offset__SHIFT 0x0437#define ACP_DSP0_CACHE_OFFSET2__OnionGarlicSel_MASK 0x80000000438#define ACP_DSP0_CACHE_OFFSET2__OnionGarlicSel__SHIFT 0x1f439#define ACP_DSP0_CACHE_SIZE2__Size_MASK 0xffffff440#define ACP_DSP0_CACHE_SIZE2__Size__SHIFT 0x0441#define ACP_DSP0_CACHE_SIZE2__PageEnable_MASK 0x80000000442#define ACP_DSP0_CACHE_SIZE2__PageEnable__SHIFT 0x1f443#define ACP_DSP0_CACHE_OFFSET3__Offset_MASK 0xfffffff444#define ACP_DSP0_CACHE_OFFSET3__Offset__SHIFT 0x0445#define ACP_DSP0_CACHE_OFFSET3__OnionGarlicSel_MASK 0x80000000446#define ACP_DSP0_CACHE_OFFSET3__OnionGarlicSel__SHIFT 0x1f447#define ACP_DSP0_CACHE_SIZE3__Size_MASK 0xffffff448#define ACP_DSP0_CACHE_SIZE3__Size__SHIFT 0x0449#define ACP_DSP0_CACHE_SIZE3__PageEnable_MASK 0x80000000450#define ACP_DSP0_CACHE_SIZE3__PageEnable__SHIFT 0x1f451#define ACP_DSP0_CACHE_OFFSET4__Offset_MASK 0xfffffff452#define ACP_DSP0_CACHE_OFFSET4__Offset__SHIFT 0x0453#define ACP_DSP0_CACHE_OFFSET4__OnionGarlicSel_MASK 0x80000000454#define ACP_DSP0_CACHE_OFFSET4__OnionGarlicSel__SHIFT 0x1f455#define ACP_DSP0_CACHE_SIZE4__Size_MASK 0xffffff456#define ACP_DSP0_CACHE_SIZE4__Size__SHIFT 0x0457#define ACP_DSP0_CACHE_SIZE4__PageEnable_MASK 0x80000000458#define ACP_DSP0_CACHE_SIZE4__PageEnable__SHIFT 0x1f459#define ACP_DSP0_CACHE_OFFSET5__Offset_MASK 0xfffffff460#define ACP_DSP0_CACHE_OFFSET5__Offset__SHIFT 0x0461#define ACP_DSP0_CACHE_OFFSET5__OnionGarlicSel_MASK 0x80000000462#define ACP_DSP0_CACHE_OFFSET5__OnionGarlicSel__SHIFT 0x1f463#define ACP_DSP0_CACHE_SIZE5__Size_MASK 0xffffff464#define ACP_DSP0_CACHE_SIZE5__Size__SHIFT 0x0465#define ACP_DSP0_CACHE_SIZE5__PageEnable_MASK 0x80000000466#define ACP_DSP0_CACHE_SIZE5__PageEnable__SHIFT 0x1f467#define ACP_DSP0_CACHE_OFFSET6__Offset_MASK 0xfffffff468#define ACP_DSP0_CACHE_OFFSET6__Offset__SHIFT 0x0469#define ACP_DSP0_CACHE_OFFSET6__OnionGarlicSel_MASK 0x80000000470#define ACP_DSP0_CACHE_OFFSET6__OnionGarlicSel__SHIFT 0x1f471#define ACP_DSP0_CACHE_SIZE6__Size_MASK 0xffffff472#define ACP_DSP0_CACHE_SIZE6__Size__SHIFT 0x0473#define ACP_DSP0_CACHE_SIZE6__PageEnable_MASK 0x80000000474#define ACP_DSP0_CACHE_SIZE6__PageEnable__SHIFT 0x1f475#define ACP_DSP0_CACHE_OFFSET7__Offset_MASK 0xfffffff476#define ACP_DSP0_CACHE_OFFSET7__Offset__SHIFT 0x0477#define ACP_DSP0_CACHE_OFFSET7__OnionGarlicSel_MASK 0x80000000478#define ACP_DSP0_CACHE_OFFSET7__OnionGarlicSel__SHIFT 0x1f479#define ACP_DSP0_CACHE_SIZE7__Size_MASK 0xffffff480#define ACP_DSP0_CACHE_SIZE7__Size__SHIFT 0x0481#define ACP_DSP0_CACHE_SIZE7__PageEnable_MASK 0x80000000482#define ACP_DSP0_CACHE_SIZE7__PageEnable__SHIFT 0x1f483#define ACP_DSP0_CACHE_OFFSET8__Offset_MASK 0xfffffff484#define ACP_DSP0_CACHE_OFFSET8__Offset__SHIFT 0x0485#define ACP_DSP0_CACHE_OFFSET8__OnionGarlicSel_MASK 0x80000000486#define ACP_DSP0_CACHE_OFFSET8__OnionGarlicSel__SHIFT 0x1f487#define ACP_DSP0_CACHE_SIZE8__Size_MASK 0xffffff488#define ACP_DSP0_CACHE_SIZE8__Size__SHIFT 0x0489#define ACP_DSP0_CACHE_SIZE8__PageEnable_MASK 0x80000000490#define ACP_DSP0_CACHE_SIZE8__PageEnable__SHIFT 0x1f491#define ACP_DSP0_NONCACHE_OFFSET0__Offset_MASK 0xfffffff492#define ACP_DSP0_NONCACHE_OFFSET0__Offset__SHIFT 0x0493#define ACP_DSP0_NONCACHE_OFFSET0__OnionGarlicSel_MASK 0x80000000494#define ACP_DSP0_NONCACHE_OFFSET0__OnionGarlicSel__SHIFT 0x1f495#define ACP_DSP0_NONCACHE_SIZE0__Size_MASK 0xffffff496#define ACP_DSP0_NONCACHE_SIZE0__Size__SHIFT 0x0497#define ACP_DSP0_NONCACHE_SIZE0__PageEnable_MASK 0x80000000498#define ACP_DSP0_NONCACHE_SIZE0__PageEnable__SHIFT 0x1f499#define ACP_DSP0_NONCACHE_OFFSET1__Offset_MASK 0xfffffff500#define ACP_DSP0_NONCACHE_OFFSET1__Offset__SHIFT 0x0501#define ACP_DSP0_NONCACHE_OFFSET1__OnionGarlicSel_MASK 0x80000000502#define ACP_DSP0_NONCACHE_OFFSET1__OnionGarlicSel__SHIFT 0x1f503#define ACP_DSP0_NONCACHE_SIZE1__Size_MASK 0xffffff504#define ACP_DSP0_NONCACHE_SIZE1__Size__SHIFT 0x0505#define ACP_DSP0_NONCACHE_SIZE1__PageEnable_MASK 0x80000000506#define ACP_DSP0_NONCACHE_SIZE1__PageEnable__SHIFT 0x1f507#define ACP_DSP0_DEBUG_PC__DebugPC_MASK 0xffffffff508#define ACP_DSP0_DEBUG_PC__DebugPC__SHIFT 0x0509#define ACP_DSP0_NMI_SEL__NMISel_MASK 0x1510#define ACP_DSP0_NMI_SEL__NMISel__SHIFT 0x0511#define ACP_DSP0_CLKRST_CNTL__ClkEn_MASK 0x1512#define ACP_DSP0_CLKRST_CNTL__ClkEn__SHIFT 0x0513#define ACP_DSP0_CLKRST_CNTL__SoftResetDSP_MASK 0x2514#define ACP_DSP0_CLKRST_CNTL__SoftResetDSP__SHIFT 0x1515#define ACP_DSP0_CLKRST_CNTL__InternalSoftResetMode_MASK 0x4516#define ACP_DSP0_CLKRST_CNTL__InternalSoftResetMode__SHIFT 0x2517#define ACP_DSP0_CLKRST_CNTL__ExternalSoftResetMode_MASK 0x8518#define ACP_DSP0_CLKRST_CNTL__ExternalSoftResetMode__SHIFT 0x3519#define ACP_DSP0_CLKRST_CNTL__SoftResetDSPDone_MASK 0x10520#define ACP_DSP0_CLKRST_CNTL__SoftResetDSPDone__SHIFT 0x4521#define ACP_DSP0_CLKRST_CNTL__Clk_ON_Status_MASK 0x20522#define ACP_DSP0_CLKRST_CNTL__Clk_ON_Status__SHIFT 0x5523#define ACP_DSP0_RUNSTALL__RunStallCntl_MASK 0x1524#define ACP_DSP0_RUNSTALL__RunStallCntl__SHIFT 0x0525#define ACP_DSP0_OCD_HALT_ON_RST__OCD_HALT_ON_RST_MASK 0x1526#define ACP_DSP0_OCD_HALT_ON_RST__OCD_HALT_ON_RST__SHIFT 0x0527#define ACP_DSP0_WAIT_MODE__WaitMode_MASK 0x1528#define ACP_DSP0_WAIT_MODE__WaitMode__SHIFT 0x0529#define ACP_DSP0_VECT_SEL__StaticVectorSel_MASK 0x1530#define ACP_DSP0_VECT_SEL__StaticVectorSel__SHIFT 0x0531#define ACP_DSP0_DEBUG_REG1__ACP_DSP_DEBUG_REG1_MASK 0xffffffff532#define ACP_DSP0_DEBUG_REG1__ACP_DSP_DEBUG_REG1__SHIFT 0x0533#define ACP_DSP0_DEBUG_REG2__ACP_DSP_DEBUG_REG2_MASK 0xffffffff534#define ACP_DSP0_DEBUG_REG2__ACP_DSP_DEBUG_REG2__SHIFT 0x0535#define ACP_DSP0_DEBUG_REG3__ACP_DSP_DEBUG_REG3_MASK 0xffffffff536#define ACP_DSP0_DEBUG_REG3__ACP_DSP_DEBUG_REG3__SHIFT 0x0537#define ACP_DSP1_CACHE_OFFSET0__Offset_MASK 0xfffffff538#define ACP_DSP1_CACHE_OFFSET0__Offset__SHIFT 0x0539#define ACP_DSP1_CACHE_OFFSET0__OnionGarlicSel_MASK 0x80000000540#define ACP_DSP1_CACHE_OFFSET0__OnionGarlicSel__SHIFT 0x1f541#define ACP_DSP1_CACHE_SIZE0__Size_MASK 0xffffff542#define ACP_DSP1_CACHE_SIZE0__Size__SHIFT 0x0543#define ACP_DSP1_CACHE_SIZE0__PageEnable_MASK 0x80000000544#define ACP_DSP1_CACHE_SIZE0__PageEnable__SHIFT 0x1f545#define ACP_DSP1_CACHE_OFFSET1__Offset_MASK 0xfffffff546#define ACP_DSP1_CACHE_OFFSET1__Offset__SHIFT 0x0547#define ACP_DSP1_CACHE_OFFSET1__OnionGarlicSel_MASK 0x80000000548#define ACP_DSP1_CACHE_OFFSET1__OnionGarlicSel__SHIFT 0x1f549#define ACP_DSP1_CACHE_SIZE1__Size_MASK 0xffffff550#define ACP_DSP1_CACHE_SIZE1__Size__SHIFT 0x0551#define ACP_DSP1_CACHE_SIZE1__PageEnable_MASK 0x80000000552#define ACP_DSP1_CACHE_SIZE1__PageEnable__SHIFT 0x1f553#define ACP_DSP1_CACHE_OFFSET2__Offset_MASK 0xfffffff554#define ACP_DSP1_CACHE_OFFSET2__Offset__SHIFT 0x0555#define ACP_DSP1_CACHE_OFFSET2__OnionGarlicSel_MASK 0x80000000556#define ACP_DSP1_CACHE_OFFSET2__OnionGarlicSel__SHIFT 0x1f557#define ACP_DSP1_CACHE_SIZE2__Size_MASK 0xffffff558#define ACP_DSP1_CACHE_SIZE2__Size__SHIFT 0x0559#define ACP_DSP1_CACHE_SIZE2__PageEnable_MASK 0x80000000560#define ACP_DSP1_CACHE_SIZE2__PageEnable__SHIFT 0x1f561#define ACP_DSP1_CACHE_OFFSET3__Offset_MASK 0xfffffff562#define ACP_DSP1_CACHE_OFFSET3__Offset__SHIFT 0x0563#define ACP_DSP1_CACHE_OFFSET3__OnionGarlicSel_MASK 0x80000000564#define ACP_DSP1_CACHE_OFFSET3__OnionGarlicSel__SHIFT 0x1f565#define ACP_DSP1_CACHE_SIZE3__Size_MASK 0xffffff566#define ACP_DSP1_CACHE_SIZE3__Size__SHIFT 0x0567#define ACP_DSP1_CACHE_SIZE3__PageEnable_MASK 0x80000000568#define ACP_DSP1_CACHE_SIZE3__PageEnable__SHIFT 0x1f569#define ACP_DSP1_CACHE_OFFSET4__Offset_MASK 0xfffffff570#define ACP_DSP1_CACHE_OFFSET4__Offset__SHIFT 0x0571#define ACP_DSP1_CACHE_OFFSET4__OnionGarlicSel_MASK 0x80000000572#define ACP_DSP1_CACHE_OFFSET4__OnionGarlicSel__SHIFT 0x1f573#define ACP_DSP1_CACHE_SIZE4__Size_MASK 0xffffff574#define ACP_DSP1_CACHE_SIZE4__Size__SHIFT 0x0575#define ACP_DSP1_CACHE_SIZE4__PageEnable_MASK 0x80000000576#define ACP_DSP1_CACHE_SIZE4__PageEnable__SHIFT 0x1f577#define ACP_DSP1_CACHE_OFFSET5__Offset_MASK 0xfffffff578#define ACP_DSP1_CACHE_OFFSET5__Offset__SHIFT 0x0579#define ACP_DSP1_CACHE_OFFSET5__OnionGarlicSel_MASK 0x80000000580#define ACP_DSP1_CACHE_OFFSET5__OnionGarlicSel__SHIFT 0x1f581#define ACP_DSP1_CACHE_SIZE5__Size_MASK 0xffffff582#define ACP_DSP1_CACHE_SIZE5__Size__SHIFT 0x0583#define ACP_DSP1_CACHE_SIZE5__PageEnable_MASK 0x80000000584#define ACP_DSP1_CACHE_SIZE5__PageEnable__SHIFT 0x1f585#define ACP_DSP1_CACHE_OFFSET6__Offset_MASK 0xfffffff586#define ACP_DSP1_CACHE_OFFSET6__Offset__SHIFT 0x0587#define ACP_DSP1_CACHE_OFFSET6__OnionGarlicSel_MASK 0x80000000588#define ACP_DSP1_CACHE_OFFSET6__OnionGarlicSel__SHIFT 0x1f589#define ACP_DSP1_CACHE_SIZE6__Size_MASK 0xffffff590#define ACP_DSP1_CACHE_SIZE6__Size__SHIFT 0x0591#define ACP_DSP1_CACHE_SIZE6__PageEnable_MASK 0x80000000592#define ACP_DSP1_CACHE_SIZE6__PageEnable__SHIFT 0x1f593#define ACP_DSP1_CACHE_OFFSET7__Offset_MASK 0xfffffff594#define ACP_DSP1_CACHE_OFFSET7__Offset__SHIFT 0x0595#define ACP_DSP1_CACHE_OFFSET7__OnionGarlicSel_MASK 0x80000000596#define ACP_DSP1_CACHE_OFFSET7__OnionGarlicSel__SHIFT 0x1f597#define ACP_DSP1_CACHE_SIZE7__Size_MASK 0xffffff598#define ACP_DSP1_CACHE_SIZE7__Size__SHIFT 0x0599#define ACP_DSP1_CACHE_SIZE7__PageEnable_MASK 0x80000000600#define ACP_DSP1_CACHE_SIZE7__PageEnable__SHIFT 0x1f601#define ACP_DSP1_CACHE_OFFSET8__Offset_MASK 0xfffffff602#define ACP_DSP1_CACHE_OFFSET8__Offset__SHIFT 0x0603#define ACP_DSP1_CACHE_OFFSET8__OnionGarlicSel_MASK 0x80000000604#define ACP_DSP1_CACHE_OFFSET8__OnionGarlicSel__SHIFT 0x1f605#define ACP_DSP1_CACHE_SIZE8__Size_MASK 0xffffff606#define ACP_DSP1_CACHE_SIZE8__Size__SHIFT 0x0607#define ACP_DSP1_CACHE_SIZE8__PageEnable_MASK 0x80000000608#define ACP_DSP1_CACHE_SIZE8__PageEnable__SHIFT 0x1f609#define ACP_DSP1_NONCACHE_OFFSET0__Offset_MASK 0xfffffff610#define ACP_DSP1_NONCACHE_OFFSET0__Offset__SHIFT 0x0611#define ACP_DSP1_NONCACHE_OFFSET0__OnionGarlicSel_MASK 0x80000000612#define ACP_DSP1_NONCACHE_OFFSET0__OnionGarlicSel__SHIFT 0x1f613#define ACP_DSP1_NONCACHE_SIZE0__Size_MASK 0xffffff614#define ACP_DSP1_NONCACHE_SIZE0__Size__SHIFT 0x0615#define ACP_DSP1_NONCACHE_SIZE0__PageEnable_MASK 0x80000000616#define ACP_DSP1_NONCACHE_SIZE0__PageEnable__SHIFT 0x1f617#define ACP_DSP1_NONCACHE_OFFSET1__Offset_MASK 0xfffffff618#define ACP_DSP1_NONCACHE_OFFSET1__Offset__SHIFT 0x0619#define ACP_DSP1_NONCACHE_OFFSET1__OnionGarlicSel_MASK 0x80000000620#define ACP_DSP1_NONCACHE_OFFSET1__OnionGarlicSel__SHIFT 0x1f621#define ACP_DSP1_NONCACHE_SIZE1__Size_MASK 0xffffff622#define ACP_DSP1_NONCACHE_SIZE1__Size__SHIFT 0x0623#define ACP_DSP1_NONCACHE_SIZE1__PageEnable_MASK 0x80000000624#define ACP_DSP1_NONCACHE_SIZE1__PageEnable__SHIFT 0x1f625#define ACP_DSP1_DEBUG_PC__DebugPC_MASK 0xffffffff626#define ACP_DSP1_DEBUG_PC__DebugPC__SHIFT 0x0627#define ACP_DSP1_NMI_SEL__NMISel_MASK 0x1628#define ACP_DSP1_NMI_SEL__NMISel__SHIFT 0x0629#define ACP_DSP1_CLKRST_CNTL__ClkEn_MASK 0x1630#define ACP_DSP1_CLKRST_CNTL__ClkEn__SHIFT 0x0631#define ACP_DSP1_CLKRST_CNTL__SoftResetDSP_MASK 0x2632#define ACP_DSP1_CLKRST_CNTL__SoftResetDSP__SHIFT 0x1633#define ACP_DSP1_CLKRST_CNTL__InternalSoftResetMode_MASK 0x4634#define ACP_DSP1_CLKRST_CNTL__InternalSoftResetMode__SHIFT 0x2635#define ACP_DSP1_CLKRST_CNTL__ExternalSoftResetMode_MASK 0x8636#define ACP_DSP1_CLKRST_CNTL__ExternalSoftResetMode__SHIFT 0x3637#define ACP_DSP1_CLKRST_CNTL__SoftResetDSPDone_MASK 0x10638#define ACP_DSP1_CLKRST_CNTL__SoftResetDSPDone__SHIFT 0x4639#define ACP_DSP1_CLKRST_CNTL__Clk_ON_Status_MASK 0x20640#define ACP_DSP1_CLKRST_CNTL__Clk_ON_Status__SHIFT 0x5641#define ACP_DSP1_RUNSTALL__RunStallCntl_MASK 0x1642#define ACP_DSP1_RUNSTALL__RunStallCntl__SHIFT 0x0643#define ACP_DSP1_OCD_HALT_ON_RST__OCD_HALT_ON_RST_MASK 0x1644#define ACP_DSP1_OCD_HALT_ON_RST__OCD_HALT_ON_RST__SHIFT 0x0645#define ACP_DSP1_WAIT_MODE__WaitMode_MASK 0x1646#define ACP_DSP1_WAIT_MODE__WaitMode__SHIFT 0x0647#define ACP_DSP1_VECT_SEL__StaticVectorSel_MASK 0x1648#define ACP_DSP1_VECT_SEL__StaticVectorSel__SHIFT 0x0649#define ACP_DSP1_DEBUG_REG1__ACP_DSP_DEBUG_REG1_MASK 0xffffffff650#define ACP_DSP1_DEBUG_REG1__ACP_DSP_DEBUG_REG1__SHIFT 0x0651#define ACP_DSP1_DEBUG_REG2__ACP_DSP_DEBUG_REG2_MASK 0xffffffff652#define ACP_DSP1_DEBUG_REG2__ACP_DSP_DEBUG_REG2__SHIFT 0x0653#define ACP_DSP1_DEBUG_REG3__ACP_DSP_DEBUG_REG3_MASK 0xffffffff654#define ACP_DSP1_DEBUG_REG3__ACP_DSP_DEBUG_REG3__SHIFT 0x0655#define ACP_DSP2_CACHE_OFFSET0__Offset_MASK 0xfffffff656#define ACP_DSP2_CACHE_OFFSET0__Offset__SHIFT 0x0657#define ACP_DSP2_CACHE_OFFSET0__OnionGarlicSel_MASK 0x80000000658#define ACP_DSP2_CACHE_OFFSET0__OnionGarlicSel__SHIFT 0x1f659#define ACP_DSP2_CACHE_SIZE0__Size_MASK 0xffffff660#define ACP_DSP2_CACHE_SIZE0__Size__SHIFT 0x0661#define ACP_DSP2_CACHE_SIZE0__PageEnable_MASK 0x80000000662#define ACP_DSP2_CACHE_SIZE0__PageEnable__SHIFT 0x1f663#define ACP_DSP2_CACHE_OFFSET1__Offset_MASK 0xfffffff664#define ACP_DSP2_CACHE_OFFSET1__Offset__SHIFT 0x0665#define ACP_DSP2_CACHE_OFFSET1__OnionGarlicSel_MASK 0x80000000666#define ACP_DSP2_CACHE_OFFSET1__OnionGarlicSel__SHIFT 0x1f667#define ACP_DSP2_CACHE_SIZE1__Size_MASK 0xffffff668#define ACP_DSP2_CACHE_SIZE1__Size__SHIFT 0x0669#define ACP_DSP2_CACHE_SIZE1__PageEnable_MASK 0x80000000670#define ACP_DSP2_CACHE_SIZE1__PageEnable__SHIFT 0x1f671#define ACP_DSP2_CACHE_OFFSET2__Offset_MASK 0xfffffff672#define ACP_DSP2_CACHE_OFFSET2__Offset__SHIFT 0x0673#define ACP_DSP2_CACHE_OFFSET2__OnionGarlicSel_MASK 0x80000000674#define ACP_DSP2_CACHE_OFFSET2__OnionGarlicSel__SHIFT 0x1f675#define ACP_DSP2_CACHE_SIZE2__Size_MASK 0xffffff676#define ACP_DSP2_CACHE_SIZE2__Size__SHIFT 0x0677#define ACP_DSP2_CACHE_SIZE2__PageEnable_MASK 0x80000000678#define ACP_DSP2_CACHE_SIZE2__PageEnable__SHIFT 0x1f679#define ACP_DSP2_CACHE_OFFSET3__Offset_MASK 0xfffffff680#define ACP_DSP2_CACHE_OFFSET3__Offset__SHIFT 0x0681#define ACP_DSP2_CACHE_OFFSET3__OnionGarlicSel_MASK 0x80000000682#define ACP_DSP2_CACHE_OFFSET3__OnionGarlicSel__SHIFT 0x1f683#define ACP_DSP2_CACHE_SIZE3__Size_MASK 0xffffff684#define ACP_DSP2_CACHE_SIZE3__Size__SHIFT 0x0685#define ACP_DSP2_CACHE_SIZE3__PageEnable_MASK 0x80000000686#define ACP_DSP2_CACHE_SIZE3__PageEnable__SHIFT 0x1f687#define ACP_DSP2_CACHE_OFFSET4__Offset_MASK 0xfffffff688#define ACP_DSP2_CACHE_OFFSET4__Offset__SHIFT 0x0689#define ACP_DSP2_CACHE_OFFSET4__OnionGarlicSel_MASK 0x80000000690#define ACP_DSP2_CACHE_OFFSET4__OnionGarlicSel__SHIFT 0x1f691#define ACP_DSP2_CACHE_SIZE4__Size_MASK 0xffffff692#define ACP_DSP2_CACHE_SIZE4__Size__SHIFT 0x0693#define ACP_DSP2_CACHE_SIZE4__PageEnable_MASK 0x80000000694#define ACP_DSP2_CACHE_SIZE4__PageEnable__SHIFT 0x1f695#define ACP_DSP2_CACHE_OFFSET5__Offset_MASK 0xfffffff696#define ACP_DSP2_CACHE_OFFSET5__Offset__SHIFT 0x0697#define ACP_DSP2_CACHE_OFFSET5__OnionGarlicSel_MASK 0x80000000698#define ACP_DSP2_CACHE_OFFSET5__OnionGarlicSel__SHIFT 0x1f699#define ACP_DSP2_CACHE_SIZE5__Size_MASK 0xffffff700#define ACP_DSP2_CACHE_SIZE5__Size__SHIFT 0x0701#define ACP_DSP2_CACHE_SIZE5__PageEnable_MASK 0x80000000702#define ACP_DSP2_CACHE_SIZE5__PageEnable__SHIFT 0x1f703#define ACP_DSP2_CACHE_OFFSET6__Offset_MASK 0xfffffff704#define ACP_DSP2_CACHE_OFFSET6__Offset__SHIFT 0x0705#define ACP_DSP2_CACHE_OFFSET6__OnionGarlicSel_MASK 0x80000000706#define ACP_DSP2_CACHE_OFFSET6__OnionGarlicSel__SHIFT 0x1f707#define ACP_DSP2_CACHE_SIZE6__Size_MASK 0xffffff708#define ACP_DSP2_CACHE_SIZE6__Size__SHIFT 0x0709#define ACP_DSP2_CACHE_SIZE6__PageEnable_MASK 0x80000000710#define ACP_DSP2_CACHE_SIZE6__PageEnable__SHIFT 0x1f711#define ACP_DSP2_CACHE_OFFSET7__Offset_MASK 0xfffffff712#define ACP_DSP2_CACHE_OFFSET7__Offset__SHIFT 0x0713#define ACP_DSP2_CACHE_OFFSET7__OnionGarlicSel_MASK 0x80000000714#define ACP_DSP2_CACHE_OFFSET7__OnionGarlicSel__SHIFT 0x1f715#define ACP_DSP2_CACHE_SIZE7__Size_MASK 0xffffff716#define ACP_DSP2_CACHE_SIZE7__Size__SHIFT 0x0717#define ACP_DSP2_CACHE_SIZE7__PageEnable_MASK 0x80000000718#define ACP_DSP2_CACHE_SIZE7__PageEnable__SHIFT 0x1f719#define ACP_DSP2_CACHE_OFFSET8__Offset_MASK 0xfffffff720#define ACP_DSP2_CACHE_OFFSET8__Offset__SHIFT 0x0721#define ACP_DSP2_CACHE_OFFSET8__OnionGarlicSel_MASK 0x80000000722#define ACP_DSP2_CACHE_OFFSET8__OnionGarlicSel__SHIFT 0x1f723#define ACP_DSP2_CACHE_SIZE8__Size_MASK 0xffffff724#define ACP_DSP2_CACHE_SIZE8__Size__SHIFT 0x0725#define ACP_DSP2_CACHE_SIZE8__PageEnable_MASK 0x80000000726#define ACP_DSP2_CACHE_SIZE8__PageEnable__SHIFT 0x1f727#define ACP_DSP2_NONCACHE_OFFSET0__Offset_MASK 0xfffffff728#define ACP_DSP2_NONCACHE_OFFSET0__Offset__SHIFT 0x0729#define ACP_DSP2_NONCACHE_OFFSET0__OnionGarlicSel_MASK 0x80000000730#define ACP_DSP2_NONCACHE_OFFSET0__OnionGarlicSel__SHIFT 0x1f731#define ACP_DSP2_NONCACHE_SIZE0__Size_MASK 0xffffff732#define ACP_DSP2_NONCACHE_SIZE0__Size__SHIFT 0x0733#define ACP_DSP2_NONCACHE_SIZE0__PageEnable_MASK 0x80000000734#define ACP_DSP2_NONCACHE_SIZE0__PageEnable__SHIFT 0x1f735#define ACP_DSP2_NONCACHE_OFFSET1__Offset_MASK 0xfffffff736#define ACP_DSP2_NONCACHE_OFFSET1__Offset__SHIFT 0x0737#define ACP_DSP2_NONCACHE_OFFSET1__OnionGarlicSel_MASK 0x80000000738#define ACP_DSP2_NONCACHE_OFFSET1__OnionGarlicSel__SHIFT 0x1f739#define ACP_DSP2_NONCACHE_SIZE1__Size_MASK 0xffffff740#define ACP_DSP2_NONCACHE_SIZE1__Size__SHIFT 0x0741#define ACP_DSP2_NONCACHE_SIZE1__PageEnable_MASK 0x80000000742#define ACP_DSP2_NONCACHE_SIZE1__PageEnable__SHIFT 0x1f743#define ACP_DSP2_DEBUG_PC__DebugPC_MASK 0xffffffff744#define ACP_DSP2_DEBUG_PC__DebugPC__SHIFT 0x0745#define ACP_DSP2_NMI_SEL__NMISel_MASK 0x1746#define ACP_DSP2_NMI_SEL__NMISel__SHIFT 0x0747#define ACP_DSP2_CLKRST_CNTL__ClkEn_MASK 0x1748#define ACP_DSP2_CLKRST_CNTL__ClkEn__SHIFT 0x0749#define ACP_DSP2_CLKRST_CNTL__SoftResetDSP_MASK 0x2750#define ACP_DSP2_CLKRST_CNTL__SoftResetDSP__SHIFT 0x1751#define ACP_DSP2_CLKRST_CNTL__InternalSoftResetMode_MASK 0x4752#define ACP_DSP2_CLKRST_CNTL__InternalSoftResetMode__SHIFT 0x2753#define ACP_DSP2_CLKRST_CNTL__ExternalSoftResetMode_MASK 0x8754#define ACP_DSP2_CLKRST_CNTL__ExternalSoftResetMode__SHIFT 0x3755#define ACP_DSP2_CLKRST_CNTL__SoftResetDSPDone_MASK 0x10756#define ACP_DSP2_CLKRST_CNTL__SoftResetDSPDone__SHIFT 0x4757#define ACP_DSP2_CLKRST_CNTL__Clk_ON_Status_MASK 0x20758#define ACP_DSP2_CLKRST_CNTL__Clk_ON_Status__SHIFT 0x5759#define ACP_DSP2_RUNSTALL__RunStallCntl_MASK 0x1760#define ACP_DSP2_RUNSTALL__RunStallCntl__SHIFT 0x0761#define ACP_DSP2_OCD_HALT_ON_RST__OCD_HALT_ON_RST_MASK 0x1762#define ACP_DSP2_OCD_HALT_ON_RST__OCD_HALT_ON_RST__SHIFT 0x0763#define ACP_DSP2_WAIT_MODE__WaitMode_MASK 0x1764#define ACP_DSP2_WAIT_MODE__WaitMode__SHIFT 0x0765#define ACP_DSP2_VECT_SEL__StaticVectorSel_MASK 0x1766#define ACP_DSP2_VECT_SEL__StaticVectorSel__SHIFT 0x0767#define ACP_DSP2_DEBUG_REG1__ACP_DSP_DEBUG_REG1_MASK 0xffffffff768#define ACP_DSP2_DEBUG_REG1__ACP_DSP_DEBUG_REG1__SHIFT 0x0769#define ACP_DSP2_DEBUG_REG2__ACP_DSP_DEBUG_REG2_MASK 0xffffffff770#define ACP_DSP2_DEBUG_REG2__ACP_DSP_DEBUG_REG2__SHIFT 0x0771#define ACP_DSP2_DEBUG_REG3__ACP_DSP_DEBUG_REG3_MASK 0xffffffff772#define ACP_DSP2_DEBUG_REG3__ACP_DSP_DEBUG_REG3__SHIFT 0x0773#define ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBDataSwap_MASK 0x3774#define ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBDataSwap__SHIFT 0x0775#define ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBEnbMultRdReq_MASK 0x4776#define ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBEnbMultRdReq__SHIFT 0x2777#define ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBEnbMultWrReq_MASK 0x18778#define ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBEnbMultWrReq__SHIFT 0x3779#define ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBMaxReadBurst_MASK 0x60780#define ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBMaxReadBurst__SHIFT 0x5781#define ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBStallEnb_MASK 0x80782#define ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBStallEnb__SHIFT 0x7783#define ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBNackChkEnb_MASK 0x100784#define ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBNackChkEnb__SHIFT 0x8785#define ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBAdrWinViolChkEnb_MASK 0x200786#define ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBAdrWinViolChkEnb__SHIFT 0x9787#define ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBUrgEnb_MASK 0x400788#define ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBUrgEnb__SHIFT 0xa789#define ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBUrgCntMult_MASK 0x1800790#define ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBUrgCntMult__SHIFT 0xb791#define ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBStallMode_MASK 0x2000792#define ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBStallMode__SHIFT 0xd793#define ACP_AXI2DAGB_ONION_ERR_STATUS_WR__AXI2DAGBAdrWinViolOver_MASK 0x2000000794#define ACP_AXI2DAGB_ONION_ERR_STATUS_WR__AXI2DAGBAdrWinViolOver__SHIFT 0x19795#define ACP_AXI2DAGB_ONION_ERR_STATUS_WR__AXI2DAGBAdrWinViolSource_MASK 0x1c000000796#define ACP_AXI2DAGB_ONION_ERR_STATUS_WR__AXI2DAGBAdrWinViolSource__SHIFT 0x1a797#define ACP_AXI2DAGB_ONION_ERR_STATUS_WR__AXI2DAGBAdrWinViol_MASK 0x20000000798#define ACP_AXI2DAGB_ONION_ERR_STATUS_WR__AXI2DAGBAdrWinViol__SHIFT 0x1d799#define ACP_AXI2DAGB_ONION_ERR_STATUS_WR__AXI2DAGBNackOver_MASK 0x40000000800#define ACP_AXI2DAGB_ONION_ERR_STATUS_WR__AXI2DAGBNackOver__SHIFT 0x1e801#define ACP_AXI2DAGB_ONION_ERR_STATUS_WR__AXI2DAGBNackVal_MASK 0x80000000802#define ACP_AXI2DAGB_ONION_ERR_STATUS_WR__AXI2DAGBNackVal__SHIFT 0x1f803#define ACP_AXI2DAGB_ONION_ERR_STATUS_RD__AXI2DAGBAdrWinViolOver_MASK 0x2000000804#define ACP_AXI2DAGB_ONION_ERR_STATUS_RD__AXI2DAGBAdrWinViolOver__SHIFT 0x19805#define ACP_AXI2DAGB_ONION_ERR_STATUS_RD__AXI2DAGBAdrWinViolSource_MASK 0x1c000000806#define ACP_AXI2DAGB_ONION_ERR_STATUS_RD__AXI2DAGBAdrWinViolSource__SHIFT 0x1a807#define ACP_AXI2DAGB_ONION_ERR_STATUS_RD__AXI2DAGBAdrWinViol_MASK 0x20000000808#define ACP_AXI2DAGB_ONION_ERR_STATUS_RD__AXI2DAGBAdrWinViol__SHIFT 0x1d809#define ACP_AXI2DAGB_ONION_ERR_STATUS_RD__AXI2DAGBNackOver_MASK 0x40000000810#define ACP_AXI2DAGB_ONION_ERR_STATUS_RD__AXI2DAGBNackOver__SHIFT 0x1e811#define ACP_AXI2DAGB_ONION_ERR_STATUS_RD__AXI2DAGBNackVal_MASK 0x80000000812#define ACP_AXI2DAGB_ONION_ERR_STATUS_RD__AXI2DAGBNackVal__SHIFT 0x1f813#define ACP_DAGB_Onion_TransPerf_Counter_Control__EnbDAGBTransPerfCntr_MASK 0x1814#define ACP_DAGB_Onion_TransPerf_Counter_Control__EnbDAGBTransPerfCntr__SHIFT 0x0815#define ACP_DAGB_Onion_Wr_TransPerf_Counter_Current__CurDAGBTransPerfCntrTime_MASK 0x1ffff816#define ACP_DAGB_Onion_Wr_TransPerf_Counter_Current__CurDAGBTransPerfCntrTime__SHIFT 0x0817#define ACP_DAGB_Onion_Wr_TransPerf_Counter_Current__ClrCurDAGBTransPerfCntr_MASK 0x80000000818#define ACP_DAGB_Onion_Wr_TransPerf_Counter_Current__ClrCurDAGBTransPerfCntr__SHIFT 0x1f819#define ACP_DAGB_Onion_Wr_TransPerf_Counter_Peak__PeakDAGBTransPerfCntrTime_MASK 0x1ffff820#define ACP_DAGB_Onion_Wr_TransPerf_Counter_Peak__PeakDAGBTransPerfCntrTime__SHIFT 0x0821#define ACP_DAGB_Onion_Wr_TransPerf_Counter_Peak__ClrPeakDAGBTransPerfCntr_MASK 0x80000000822#define ACP_DAGB_Onion_Wr_TransPerf_Counter_Peak__ClrPeakDAGBTransPerfCntr__SHIFT 0x1f823#define ACP_DAGB_Onion_Rd_TransPerf_Counter_Current__CurDAGBTransPerfCntrTime_MASK 0x1ffff824#define ACP_DAGB_Onion_Rd_TransPerf_Counter_Current__CurDAGBTransPerfCntrTime__SHIFT 0x0825#define ACP_DAGB_Onion_Rd_TransPerf_Counter_Current__ClrCurDAGBTransPerfCntr_MASK 0x80000000826#define ACP_DAGB_Onion_Rd_TransPerf_Counter_Current__ClrCurDAGBTransPerfCntr__SHIFT 0x1f827#define ACP_DAGB_Onion_Rd_TransPerf_Counter_Peak__PeakDAGBTransPerfCntrTime_MASK 0x1ffff828#define ACP_DAGB_Onion_Rd_TransPerf_Counter_Peak__PeakDAGBTransPerfCntrTime__SHIFT 0x0829#define ACP_DAGB_Onion_Rd_TransPerf_Counter_Peak__ClrPeakDAGBTransPerfCntr_MASK 0x80000000830#define ACP_DAGB_Onion_Rd_TransPerf_Counter_Peak__ClrPeakDAGBTransPerfCntr__SHIFT 0x1f831#define ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBDataSwap_MASK 0x3832#define ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBDataSwap__SHIFT 0x0833#define ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBEnbMultRdReq_MASK 0x4834#define ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBEnbMultRdReq__SHIFT 0x2835#define ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBEnbMultWrReq_MASK 0x18836#define ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBEnbMultWrReq__SHIFT 0x3837#define ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBMaxReadBurst_MASK 0x60838#define ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBMaxReadBurst__SHIFT 0x5839#define ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBStallEnb_MASK 0x80840#define ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBStallEnb__SHIFT 0x7841#define ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBNackChkEnb_MASK 0x100842#define ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBNackChkEnb__SHIFT 0x8843#define ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBAdrWinViolChkEnb_MASK 0x200844#define ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBAdrWinViolChkEnb__SHIFT 0x9845#define ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBUrgEnb_MASK 0x400846#define ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBUrgEnb__SHIFT 0xa847#define ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBUrgCntMult_MASK 0x1800848#define ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBUrgCntMult__SHIFT 0xb849#define ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBStallMode_MASK 0x2000850#define ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBStallMode__SHIFT 0xd851#define ACP_AXI2DAGB_GARLIC_ERR_STATUS_WR__AXI2DAGBAdrWinViolOver_MASK 0x2000000852#define ACP_AXI2DAGB_GARLIC_ERR_STATUS_WR__AXI2DAGBAdrWinViolOver__SHIFT 0x19853#define ACP_AXI2DAGB_GARLIC_ERR_STATUS_WR__AXI2DAGBAdrWinViolSource_MASK 0x1c000000854#define ACP_AXI2DAGB_GARLIC_ERR_STATUS_WR__AXI2DAGBAdrWinViolSource__SHIFT 0x1a855#define ACP_AXI2DAGB_GARLIC_ERR_STATUS_WR__AXI2DAGBAdrWinViol_MASK 0x20000000856#define ACP_AXI2DAGB_GARLIC_ERR_STATUS_WR__AXI2DAGBAdrWinViol__SHIFT 0x1d857#define ACP_AXI2DAGB_GARLIC_ERR_STATUS_WR__AXI2DAGBNackOver_MASK 0x40000000858#define ACP_AXI2DAGB_GARLIC_ERR_STATUS_WR__AXI2DAGBNackOver__SHIFT 0x1e859#define ACP_AXI2DAGB_GARLIC_ERR_STATUS_WR__AXI2DAGBNackVal_MASK 0x80000000860#define ACP_AXI2DAGB_GARLIC_ERR_STATUS_WR__AXI2DAGBNackVal__SHIFT 0x1f861#define ACP_AXI2DAGB_GARLIC_ERR_STATUS_RD__AXI2DAGBAdrWinViolOver_MASK 0x2000000862#define ACP_AXI2DAGB_GARLIC_ERR_STATUS_RD__AXI2DAGBAdrWinViolOver__SHIFT 0x19863#define ACP_AXI2DAGB_GARLIC_ERR_STATUS_RD__AXI2DAGBAdrWinViolSource_MASK 0x1c000000864#define ACP_AXI2DAGB_GARLIC_ERR_STATUS_RD__AXI2DAGBAdrWinViolSource__SHIFT 0x1a865#define ACP_AXI2DAGB_GARLIC_ERR_STATUS_RD__AXI2DAGBAdrWinViol_MASK 0x20000000866#define ACP_AXI2DAGB_GARLIC_ERR_STATUS_RD__AXI2DAGBAdrWinViol__SHIFT 0x1d867#define ACP_AXI2DAGB_GARLIC_ERR_STATUS_RD__AXI2DAGBNackOver_MASK 0x40000000868#define ACP_AXI2DAGB_GARLIC_ERR_STATUS_RD__AXI2DAGBNackOver__SHIFT 0x1e869#define ACP_AXI2DAGB_GARLIC_ERR_STATUS_RD__AXI2DAGBNackVal_MASK 0x80000000870#define ACP_AXI2DAGB_GARLIC_ERR_STATUS_RD__AXI2DAGBNackVal__SHIFT 0x1f871#define ACP_DAGB_Garlic_TransPerf_Counter_Control__EnbDAGBTransPerfCntr_MASK 0x1872#define ACP_DAGB_Garlic_TransPerf_Counter_Control__EnbDAGBTransPerfCntr__SHIFT 0x0873#define ACP_DAGB_Garlic_Wr_TransPerf_Counter_Current__CurDAGBTransPerfCntrTime_MASK 0x1ffff874#define ACP_DAGB_Garlic_Wr_TransPerf_Counter_Current__CurDAGBTransPerfCntrTime__SHIFT 0x0875#define ACP_DAGB_Garlic_Wr_TransPerf_Counter_Current__ClrCurDAGBTransPerfCntr_MASK 0x80000000876#define ACP_DAGB_Garlic_Wr_TransPerf_Counter_Current__ClrCurDAGBTransPerfCntr__SHIFT 0x1f877#define ACP_DAGB_Garlic_Wr_TransPerf_Counter_Peak__PeakDAGBTransPerfCntrTime_MASK 0x1ffff878#define ACP_DAGB_Garlic_Wr_TransPerf_Counter_Peak__PeakDAGBTransPerfCntrTime__SHIFT 0x0879#define ACP_DAGB_Garlic_Wr_TransPerf_Counter_Peak__ClrPeakDAGBTransPerfCntr_MASK 0x80000000880#define ACP_DAGB_Garlic_Wr_TransPerf_Counter_Peak__ClrPeakDAGBTransPerfCntr__SHIFT 0x1f881#define ACP_DAGB_Garlic_Rd_TransPerf_Counter_Current__CurDAGBTransPerfCntrTime_MASK 0x1ffff882#define ACP_DAGB_Garlic_Rd_TransPerf_Counter_Current__CurDAGBTransPerfCntrTime__SHIFT 0x0883#define ACP_DAGB_Garlic_Rd_TransPerf_Counter_Current__ClrCurDAGBTransPerfCntr_MASK 0x80000000884#define ACP_DAGB_Garlic_Rd_TransPerf_Counter_Current__ClrCurDAGBTransPerfCntr__SHIFT 0x1f885#define ACP_DAGB_Garlic_Rd_TransPerf_Counter_Peak__PeakDAGBTransPerfCntrTime_MASK 0x1ffff886#define ACP_DAGB_Garlic_Rd_TransPerf_Counter_Peak__PeakDAGBTransPerfCntrTime__SHIFT 0x0887#define ACP_DAGB_Garlic_Rd_TransPerf_Counter_Peak__ClrPeakDAGBTransPerfCntr_MASK 0x80000000888#define ACP_DAGB_Garlic_Rd_TransPerf_Counter_Peak__ClrPeakDAGBTransPerfCntr__SHIFT 0x1f889#define ACP_DAGB_PAGE_SIZE_GRP_1__AXI2DAGBPageSize_MASK 0x3890#define ACP_DAGB_PAGE_SIZE_GRP_1__AXI2DAGBPageSize__SHIFT 0x0891#define ACP_DAGB_BASE_ADDR_GRP_1__AXI2DAGBBaseAddr_MASK 0xfffffff892#define ACP_DAGB_BASE_ADDR_GRP_1__AXI2DAGBBaseAddr__SHIFT 0x0893#define ACP_DAGB_BASE_ADDR_GRP_1__AXI2DAGBSnoopSel_MASK 0x20000000894#define ACP_DAGB_BASE_ADDR_GRP_1__AXI2DAGBSnoopSel__SHIFT 0x1d895#define ACP_DAGB_BASE_ADDR_GRP_1__AXI2DAGBTargetMemSel_MASK 0x40000000896#define ACP_DAGB_BASE_ADDR_GRP_1__AXI2DAGBTargetMemSel__SHIFT 0x1e897#define ACP_DAGB_BASE_ADDR_GRP_1__AXI2DAGBGrpEnable_MASK 0x80000000898#define ACP_DAGB_BASE_ADDR_GRP_1__AXI2DAGBGrpEnable__SHIFT 0x1f899#define ACP_DAGB_PAGE_SIZE_GRP_2__AXI2DAGBPageSize_MASK 0x3900#define ACP_DAGB_PAGE_SIZE_GRP_2__AXI2DAGBPageSize__SHIFT 0x0901#define ACP_DAGB_BASE_ADDR_GRP_2__AXI2DAGBBaseAddr_MASK 0xfffffff902#define ACP_DAGB_BASE_ADDR_GRP_2__AXI2DAGBBaseAddr__SHIFT 0x0903#define ACP_DAGB_BASE_ADDR_GRP_2__AXI2DAGBSnoopSel_MASK 0x20000000904#define ACP_DAGB_BASE_ADDR_GRP_2__AXI2DAGBSnoopSel__SHIFT 0x1d905#define ACP_DAGB_BASE_ADDR_GRP_2__AXI2DAGBTargetMemSel_MASK 0x40000000906#define ACP_DAGB_BASE_ADDR_GRP_2__AXI2DAGBTargetMemSel__SHIFT 0x1e907#define ACP_DAGB_BASE_ADDR_GRP_2__AXI2DAGBGrpEnable_MASK 0x80000000908#define ACP_DAGB_BASE_ADDR_GRP_2__AXI2DAGBGrpEnable__SHIFT 0x1f909#define ACP_DAGB_PAGE_SIZE_GRP_3__AXI2DAGBPageSize_MASK 0x3910#define ACP_DAGB_PAGE_SIZE_GRP_3__AXI2DAGBPageSize__SHIFT 0x0911#define ACP_DAGB_BASE_ADDR_GRP_3__AXI2DAGBBaseAddr_MASK 0xfffffff912#define ACP_DAGB_BASE_ADDR_GRP_3__AXI2DAGBBaseAddr__SHIFT 0x0913#define ACP_DAGB_BASE_ADDR_GRP_3__AXI2DAGBSnoopSel_MASK 0x20000000914#define ACP_DAGB_BASE_ADDR_GRP_3__AXI2DAGBSnoopSel__SHIFT 0x1d915#define ACP_DAGB_BASE_ADDR_GRP_3__AXI2DAGBTargetMemSel_MASK 0x40000000916#define ACP_DAGB_BASE_ADDR_GRP_3__AXI2DAGBTargetMemSel__SHIFT 0x1e917#define ACP_DAGB_BASE_ADDR_GRP_3__AXI2DAGBGrpEnable_MASK 0x80000000918#define ACP_DAGB_BASE_ADDR_GRP_3__AXI2DAGBGrpEnable__SHIFT 0x1f919#define ACP_DAGB_PAGE_SIZE_GRP_4__AXI2DAGBPageSize_MASK 0x3920#define ACP_DAGB_PAGE_SIZE_GRP_4__AXI2DAGBPageSize__SHIFT 0x0921#define ACP_DAGB_BASE_ADDR_GRP_4__AXI2DAGBBaseAddr_MASK 0xfffffff922#define ACP_DAGB_BASE_ADDR_GRP_4__AXI2DAGBBaseAddr__SHIFT 0x0923#define ACP_DAGB_BASE_ADDR_GRP_4__AXI2DAGBSnoopSel_MASK 0x20000000924#define ACP_DAGB_BASE_ADDR_GRP_4__AXI2DAGBSnoopSel__SHIFT 0x1d925#define ACP_DAGB_BASE_ADDR_GRP_4__AXI2DAGBTargetMemSel_MASK 0x40000000926#define ACP_DAGB_BASE_ADDR_GRP_4__AXI2DAGBTargetMemSel__SHIFT 0x1e927#define ACP_DAGB_BASE_ADDR_GRP_4__AXI2DAGBGrpEnable_MASK 0x80000000928#define ACP_DAGB_BASE_ADDR_GRP_4__AXI2DAGBGrpEnable__SHIFT 0x1f929#define ACP_DAGB_PAGE_SIZE_GRP_5__AXI2DAGBPageSize_MASK 0x3930#define ACP_DAGB_PAGE_SIZE_GRP_5__AXI2DAGBPageSize__SHIFT 0x0931#define ACP_DAGB_BASE_ADDR_GRP_5__AXI2DAGBBaseAddr_MASK 0xfffffff932#define ACP_DAGB_BASE_ADDR_GRP_5__AXI2DAGBBaseAddr__SHIFT 0x0933#define ACP_DAGB_BASE_ADDR_GRP_5__AXI2DAGBSnoopSel_MASK 0x20000000934#define ACP_DAGB_BASE_ADDR_GRP_5__AXI2DAGBSnoopSel__SHIFT 0x1d935#define ACP_DAGB_BASE_ADDR_GRP_5__AXI2DAGBTargetMemSel_MASK 0x40000000936#define ACP_DAGB_BASE_ADDR_GRP_5__AXI2DAGBTargetMemSel__SHIFT 0x1e937#define ACP_DAGB_BASE_ADDR_GRP_5__AXI2DAGBGrpEnable_MASK 0x80000000938#define ACP_DAGB_BASE_ADDR_GRP_5__AXI2DAGBGrpEnable__SHIFT 0x1f939#define ACP_DAGB_PAGE_SIZE_GRP_6__AXI2DAGBPageSize_MASK 0x3940#define ACP_DAGB_PAGE_SIZE_GRP_6__AXI2DAGBPageSize__SHIFT 0x0941#define ACP_DAGB_BASE_ADDR_GRP_6__AXI2DAGBBaseAddr_MASK 0xfffffff942#define ACP_DAGB_BASE_ADDR_GRP_6__AXI2DAGBBaseAddr__SHIFT 0x0943#define ACP_DAGB_BASE_ADDR_GRP_6__AXI2DAGBSnoopSel_MASK 0x20000000944#define ACP_DAGB_BASE_ADDR_GRP_6__AXI2DAGBSnoopSel__SHIFT 0x1d945#define ACP_DAGB_BASE_ADDR_GRP_6__AXI2DAGBTargetMemSel_MASK 0x40000000946#define ACP_DAGB_BASE_ADDR_GRP_6__AXI2DAGBTargetMemSel__SHIFT 0x1e947#define ACP_DAGB_BASE_ADDR_GRP_6__AXI2DAGBGrpEnable_MASK 0x80000000948#define ACP_DAGB_BASE_ADDR_GRP_6__AXI2DAGBGrpEnable__SHIFT 0x1f949#define ACP_DAGB_PAGE_SIZE_GRP_7__AXI2DAGBPageSize_MASK 0x3950#define ACP_DAGB_PAGE_SIZE_GRP_7__AXI2DAGBPageSize__SHIFT 0x0951#define ACP_DAGB_BASE_ADDR_GRP_7__AXI2DAGBBaseAddr_MASK 0xfffffff952#define ACP_DAGB_BASE_ADDR_GRP_7__AXI2DAGBBaseAddr__SHIFT 0x0953#define ACP_DAGB_BASE_ADDR_GRP_7__AXI2DAGBSnoopSel_MASK 0x20000000954#define ACP_DAGB_BASE_ADDR_GRP_7__AXI2DAGBSnoopSel__SHIFT 0x1d955#define ACP_DAGB_BASE_ADDR_GRP_7__AXI2DAGBTargetMemSel_MASK 0x40000000956#define ACP_DAGB_BASE_ADDR_GRP_7__AXI2DAGBTargetMemSel__SHIFT 0x1e957#define ACP_DAGB_BASE_ADDR_GRP_7__AXI2DAGBGrpEnable_MASK 0x80000000958#define ACP_DAGB_BASE_ADDR_GRP_7__AXI2DAGBGrpEnable__SHIFT 0x1f959#define ACP_DAGB_PAGE_SIZE_GRP_8__AXI2DAGBPageSize_MASK 0x3960#define ACP_DAGB_PAGE_SIZE_GRP_8__AXI2DAGBPageSize__SHIFT 0x0961#define ACP_DAGB_BASE_ADDR_GRP_8__AXI2DAGBBaseAddr_MASK 0xfffffff962#define ACP_DAGB_BASE_ADDR_GRP_8__AXI2DAGBBaseAddr__SHIFT 0x0963#define ACP_DAGB_BASE_ADDR_GRP_8__AXI2DAGBSnoopSel_MASK 0x20000000964#define ACP_DAGB_BASE_ADDR_GRP_8__AXI2DAGBSnoopSel__SHIFT 0x1d965#define ACP_DAGB_BASE_ADDR_GRP_8__AXI2DAGBTargetMemSel_MASK 0x40000000966#define ACP_DAGB_BASE_ADDR_GRP_8__AXI2DAGBTargetMemSel__SHIFT 0x1e967#define ACP_DAGB_BASE_ADDR_GRP_8__AXI2DAGBGrpEnable_MASK 0x80000000968#define ACP_DAGB_BASE_ADDR_GRP_8__AXI2DAGBGrpEnable__SHIFT 0x1f969#define ACP_DAGB_ATU_CTRL__AXI2DAGBCacheInvalidate_MASK 0x1970#define ACP_DAGB_ATU_CTRL__AXI2DAGBCacheInvalidate__SHIFT 0x0971#define ACP_CONTROL__ClkEn_MASK 0x1972#define ACP_CONTROL__ClkEn__SHIFT 0x0973#define ACP_CONTROL__JtagEn_MASK 0x400974#define ACP_CONTROL__JtagEn__SHIFT 0xa975#define ACP_STATUS__ClkOn_MASK 0x1976#define ACP_STATUS__ClkOn__SHIFT 0x0977#define ACP_STATUS__ACPRefClkSpd_MASK 0x2978#define ACP_STATUS__ACPRefClkSpd__SHIFT 0x1979#define ACP_STATUS__SMUStutterLastEdge_MASK 0x4980#define ACP_STATUS__SMUStutterLastEdge__SHIFT 0x2981#define ACP_STATUS__MCStutterLastEdge_MASK 0x8982#define ACP_STATUS__MCStutterLastEdge__SHIFT 0x3983#define ACP_SOFT_RESET__SoftResetAud_MASK 0x100984#define ACP_SOFT_RESET__SoftResetAud__SHIFT 0x8985#define ACP_SOFT_RESET__SoftResetDMA_MASK 0x200986#define ACP_SOFT_RESET__SoftResetDMA__SHIFT 0x9987#define ACP_SOFT_RESET__InternalSoftResetMode_MASK 0x4000988#define ACP_SOFT_RESET__InternalSoftResetMode__SHIFT 0xe989#define ACP_SOFT_RESET__ExternalSoftResetMode_MASK 0x8000990#define ACP_SOFT_RESET__ExternalSoftResetMode__SHIFT 0xf991#define ACP_SOFT_RESET__SoftResetAudDone_MASK 0x1000000992#define ACP_SOFT_RESET__SoftResetAudDone__SHIFT 0x18993#define ACP_SOFT_RESET__SoftResetDMADone_MASK 0x2000000994#define ACP_SOFT_RESET__SoftResetDMADone__SHIFT 0x19995#define ACP_PwrMgmt_CNTL__SCLKSleepCntl_MASK 0x3996#define ACP_PwrMgmt_CNTL__SCLKSleepCntl__SHIFT 0x0997#define ACP_CAC_INDICATOR_CONTROL__ACP_Cac_Indicator_Counter_MASK 0xffff998#define ACP_CAC_INDICATOR_CONTROL__ACP_Cac_Indicator_Counter__SHIFT 0x0999#define ACP_SMU_MAILBOX__ACP_SMU_Mailbox_MASK 0xffffffff1000#define ACP_SMU_MAILBOX__ACP_SMU_Mailbox__SHIFT 0x01001#define ACP_FUTURE_REG_SCLK_0__ACPFutureReg_MASK 0xffffffff1002#define ACP_FUTURE_REG_SCLK_0__ACPFutureReg__SHIFT 0x01003#define ACP_FUTURE_REG_SCLK_1__ACPFutureReg_MASK 0xffffffff1004#define ACP_FUTURE_REG_SCLK_1__ACPFutureReg__SHIFT 0x01005#define ACP_FUTURE_REG_SCLK_2__ACPFutureReg_MASK 0xffffffff1006#define ACP_FUTURE_REG_SCLK_2__ACPFutureReg__SHIFT 0x01007#define ACP_FUTURE_REG_SCLK_3__ACPFutureReg_MASK 0xffffffff1008#define ACP_FUTURE_REG_SCLK_3__ACPFutureReg__SHIFT 0x01009#define ACP_FUTURE_REG_SCLK_4__ACPFutureReg_MASK 0xffffffff1010#define ACP_FUTURE_REG_SCLK_4__ACPFutureReg__SHIFT 0x01011#define ACP_DAGB_DEBUG_CNT_ENABLE__garlic_wr_ask_cnt_enable_MASK 0x11012#define ACP_DAGB_DEBUG_CNT_ENABLE__garlic_wr_ask_cnt_enable__SHIFT 0x01013#define ACP_DAGB_DEBUG_CNT_ENABLE__garlic_wr_go_cnt_enable_MASK 0x21014#define ACP_DAGB_DEBUG_CNT_ENABLE__garlic_wr_go_cnt_enable__SHIFT 0x11015#define ACP_DAGB_DEBUG_CNT_ENABLE__garlic_wr_exp_respcnt_enable_MASK 0x41016#define ACP_DAGB_DEBUG_CNT_ENABLE__garlic_wr_exp_respcnt_enable__SHIFT 0x21017#define ACP_DAGB_DEBUG_CNT_ENABLE__garlic_wr_actual_respcnt_enable_MASK 0x81018#define ACP_DAGB_DEBUG_CNT_ENABLE__garlic_wr_actual_respcnt_enable__SHIFT 0x31019#define ACP_DAGB_DEBUG_CNT_ENABLE__garlic_rd_ask_cnt_enable_MASK 0x101020#define ACP_DAGB_DEBUG_CNT_ENABLE__garlic_rd_ask_cnt_enable__SHIFT 0x41021#define ACP_DAGB_DEBUG_CNT_ENABLE__garlic_rd_go_cnt_enable_MASK 0x201022#define ACP_DAGB_DEBUG_CNT_ENABLE__garlic_rd_go_cnt_enable__SHIFT 0x51023#define ACP_DAGB_DEBUG_CNT_ENABLE__garlic_rd_exp_respcnt_enable_MASK 0x401024#define ACP_DAGB_DEBUG_CNT_ENABLE__garlic_rd_exp_respcnt_enable__SHIFT 0x61025#define ACP_DAGB_DEBUG_CNT_ENABLE__garlic_rd_actual_respcnt_enable_MASK 0x801026#define ACP_DAGB_DEBUG_CNT_ENABLE__garlic_rd_actual_respcnt_enable__SHIFT 0x71027#define ACP_DAGB_DEBUG_CNT_ENABLE__onion_wr_ask_cnt_enable_MASK 0x1001028#define ACP_DAGB_DEBUG_CNT_ENABLE__onion_wr_ask_cnt_enable__SHIFT 0x81029#define ACP_DAGB_DEBUG_CNT_ENABLE__onion_wr_go_cnt_enable_MASK 0x2001030#define ACP_DAGB_DEBUG_CNT_ENABLE__onion_wr_go_cnt_enable__SHIFT 0x91031#define ACP_DAGB_DEBUG_CNT_ENABLE__onion_wr_exp_respcnt_enable_MASK 0x4001032#define ACP_DAGB_DEBUG_CNT_ENABLE__onion_wr_exp_respcnt_enable__SHIFT 0xa1033#define ACP_DAGB_DEBUG_CNT_ENABLE__onion_wr_actual_respcnt_enable_MASK 0x8001034#define ACP_DAGB_DEBUG_CNT_ENABLE__onion_wr_actual_respcnt_enable__SHIFT 0xb1035#define ACP_DAGB_DEBUG_CNT_ENABLE__onion_rd_ask_cnt_enable_MASK 0x10001036#define ACP_DAGB_DEBUG_CNT_ENABLE__onion_rd_ask_cnt_enable__SHIFT 0xc1037#define ACP_DAGB_DEBUG_CNT_ENABLE__onion_rd_go_cnt_enable_MASK 0x20001038#define ACP_DAGB_DEBUG_CNT_ENABLE__onion_rd_go_cnt_enable__SHIFT 0xd1039#define ACP_DAGB_DEBUG_CNT_ENABLE__onion_rd_exp_respcnt_enable_MASK 0x40001040#define ACP_DAGB_DEBUG_CNT_ENABLE__onion_rd_exp_respcnt_enable__SHIFT 0xe1041#define ACP_DAGB_DEBUG_CNT_ENABLE__onion_rd_actual_respcnt_enable_MASK 0x80001042#define ACP_DAGB_DEBUG_CNT_ENABLE__onion_rd_actual_respcnt_enable__SHIFT 0xf1043#define ACP_DAGBG_WR_ASK_CNT__garlic_wr_only_ask_cnt_MASK 0xffff1044#define ACP_DAGBG_WR_ASK_CNT__garlic_wr_only_ask_cnt__SHIFT 0x01045#define ACP_DAGBG_WR_GO_CNT__garlic_wr_only_go_cnt_MASK 0xffff1046#define ACP_DAGBG_WR_GO_CNT__garlic_wr_only_go_cnt__SHIFT 0x01047#define ACP_DAGBG_WR_EXP_RESP_CNT__garlic_wr_exp_resp_cnt_MASK 0xffff1048#define ACP_DAGBG_WR_EXP_RESP_CNT__garlic_wr_exp_resp_cnt__SHIFT 0x01049#define ACP_DAGBG_WR_ACTUAL_RESP_CNT__garlic_wr_actual_resp_cnt_MASK 0xffff1050#define ACP_DAGBG_WR_ACTUAL_RESP_CNT__garlic_wr_actual_resp_cnt__SHIFT 0x01051#define ACP_DAGBG_RD_ASK_CNT__garlic_rd_only_ask_cnt_MASK 0xffff1052#define ACP_DAGBG_RD_ASK_CNT__garlic_rd_only_ask_cnt__SHIFT 0x01053#define ACP_DAGBG_RD_GO_CNT__garlic_rd_only_go_cnt_MASK 0xffff1054#define ACP_DAGBG_RD_GO_CNT__garlic_rd_only_go_cnt__SHIFT 0x01055#define ACP_DAGBG_RD_EXP_RESP_CNT__garlic_rd_exp_resp_cnt_MASK 0xffff1056#define ACP_DAGBG_RD_EXP_RESP_CNT__garlic_rd_exp_resp_cnt__SHIFT 0x01057#define ACP_DAGBG_RD_ACTUAL_RESP_CNT__garlic_rd_actual_resp_cnt_MASK 0xffff1058#define ACP_DAGBG_RD_ACTUAL_RESP_CNT__garlic_rd_actual_resp_cnt__SHIFT 0x01059#define ACP_DAGBO_WR_ASK_CNT__onion_wr_only_ask_cnt_MASK 0xffff1060#define ACP_DAGBO_WR_ASK_CNT__onion_wr_only_ask_cnt__SHIFT 0x01061#define ACP_DAGBO_WR_GO_CNT__onion_wr_only_go_cnt_MASK 0xffff1062#define ACP_DAGBO_WR_GO_CNT__onion_wr_only_go_cnt__SHIFT 0x01063#define ACP_DAGBO_WR_EXP_RESP_CNT__onion_wr_exp_resp_cnt_MASK 0xffff1064#define ACP_DAGBO_WR_EXP_RESP_CNT__onion_wr_exp_resp_cnt__SHIFT 0x01065#define ACP_DAGBO_WR_ACTUAL_RESP_CNT__onion_wr_actual_resp_cnt_MASK 0xffff1066#define ACP_DAGBO_WR_ACTUAL_RESP_CNT__onion_wr_actual_resp_cnt__SHIFT 0x01067#define ACP_DAGBO_RD_ASK_CNT__onion_rd_only_ask_cnt_MASK 0xffff1068#define ACP_DAGBO_RD_ASK_CNT__onion_rd_only_ask_cnt__SHIFT 0x01069#define ACP_DAGBO_RD_GO_CNT__onion_rd_only_go_cnt_MASK 0xffff1070#define ACP_DAGBO_RD_GO_CNT__onion_rd_only_go_cnt__SHIFT 0x01071#define ACP_DAGBO_RD_EXP_RESP_CNT__onion_rd_exp_resp_cnt_MASK 0xffff1072#define ACP_DAGBO_RD_EXP_RESP_CNT__onion_rd_exp_resp_cnt__SHIFT 0x01073#define ACP_DAGBO_RD_ACTUAL_RESP_CNT__onion_rd_actual_resp_cnt_MASK 0xffff1074#define ACP_DAGBO_RD_ACTUAL_RESP_CNT__onion_rd_actual_resp_cnt__SHIFT 0x01075#define ACP_BRB_CONTROL__BRB_BlockSharedRAMArbCntrl_MASK 0xf1076#define ACP_BRB_CONTROL__BRB_BlockSharedRAMArbCntrl__SHIFT 0x01077#define ACP_EXTERNAL_INTR_ENB__ACPExtIntrEnb_MASK 0x11078#define ACP_EXTERNAL_INTR_ENB__ACPExtIntrEnb__SHIFT 0x01079#define ACP_EXTERNAL_INTR_CNTL__ACPErrMask_MASK 0x11080#define ACP_EXTERNAL_INTR_CNTL__ACPErrMask__SHIFT 0x01081#define ACP_EXTERNAL_INTR_CNTL__I2SMicDataAvMask_MASK 0x21082#define ACP_EXTERNAL_INTR_CNTL__I2SMicDataAvMask__SHIFT 0x11083#define ACP_EXTERNAL_INTR_CNTL__I2SSpkr0DataEmptyMask_MASK 0x41084#define ACP_EXTERNAL_INTR_CNTL__I2SSpkr0DataEmptyMask__SHIFT 0x21085#define ACP_EXTERNAL_INTR_CNTL__I2SSpkr1DataEmptyMask_MASK 0x81086#define ACP_EXTERNAL_INTR_CNTL__I2SSpkr1DataEmptyMask__SHIFT 0x31087#define ACP_EXTERNAL_INTR_CNTL__I2SBTDataAvMask_MASK 0x101088#define ACP_EXTERNAL_INTR_CNTL__I2SBTDataAvMask__SHIFT 0x41089#define ACP_EXTERNAL_INTR_CNTL__AzaliaIntrMask_MASK 0x401090#define ACP_EXTERNAL_INTR_CNTL__AzaliaIntrMask__SHIFT 0x61091#define ACP_EXTERNAL_INTR_CNTL__DSP0TimeoutMask_MASK 0x1001092#define ACP_EXTERNAL_INTR_CNTL__DSP0TimeoutMask__SHIFT 0x81093#define ACP_EXTERNAL_INTR_CNTL__DSP1TimeoutMask_MASK 0x2001094#define ACP_EXTERNAL_INTR_CNTL__DSP1TimeoutMask__SHIFT 0x91095#define ACP_EXTERNAL_INTR_CNTL__DSP2TimeoutMask_MASK 0x4001096#define ACP_EXTERNAL_INTR_CNTL__DSP2TimeoutMask__SHIFT 0xa1097#define ACP_EXTERNAL_INTR_CNTL__I2SBTDataEmptyMask_MASK 0x8001098#define ACP_EXTERNAL_INTR_CNTL__I2SBTDataEmptyMask__SHIFT 0xb1099#define ACP_EXTERNAL_INTR_CNTL__DMAIOCMask_MASK 0xffff00001100#define ACP_EXTERNAL_INTR_CNTL__DMAIOCMask__SHIFT 0x101101#define ACP_ERROR_SOURCE_STS__ACPRegUdefADDRErr_MASK 0x11102#define ACP_ERROR_SOURCE_STS__ACPRegUdefADDRErr__SHIFT 0x01103#define ACP_ERROR_SOURCE_STS__ACPRegUdefADDRErrSource_MASK 0xe1104#define ACP_ERROR_SOURCE_STS__ACPRegUdefADDRErrSource__SHIFT 0x11105#define ACP_ERROR_SOURCE_STS__ACPRegUdefADDRErrSourceOver_MASK 0x101106#define ACP_ERROR_SOURCE_STS__ACPRegUdefADDRErrSourceOver__SHIFT 0x41107#define ACP_ERROR_SOURCE_STS__BRBAddrErr_MASK 0x201108#define ACP_ERROR_SOURCE_STS__BRBAddrErr__SHIFT 0x51109#define ACP_ERROR_SOURCE_STS__BRBAddrErrSource_MASK 0x3c01110#define ACP_ERROR_SOURCE_STS__BRBAddrErrSource__SHIFT 0x61111#define ACP_ERROR_SOURCE_STS__BRBAddrErrSourceOver_MASK 0x4001112#define ACP_ERROR_SOURCE_STS__BRBAddrErrSourceOver__SHIFT 0xa1113#define ACP_ERROR_SOURCE_STS__I2SMicOverFlowErr_MASK 0x8001114#define ACP_ERROR_SOURCE_STS__I2SMicOverFlowErr__SHIFT 0xb1115#define ACP_ERROR_SOURCE_STS__I2SSpeaker0OverFlowErr_MASK 0x10001116#define ACP_ERROR_SOURCE_STS__I2SSpeaker0OverFlowErr__SHIFT 0xc1117#define ACP_ERROR_SOURCE_STS__I2SSpeaker1OverFlowErr_MASK 0x20001118#define ACP_ERROR_SOURCE_STS__I2SSpeaker1OverFlowErr__SHIFT 0xd1119#define ACP_ERROR_SOURCE_STS__I2SBTRxFifoOverFlowErr_MASK 0x40001120#define ACP_ERROR_SOURCE_STS__I2SBTRxFifoOverFlowErr__SHIFT 0xe1121#define ACP_ERROR_SOURCE_STS__DSPAdrTransRangeErr_MASK 0x80001122#define ACP_ERROR_SOURCE_STS__DSPAdrTransRangeErr__SHIFT 0xf1123#define ACP_ERROR_SOURCE_STS__DSPAdrTransRangeErrSource_MASK 0x700001124#define ACP_ERROR_SOURCE_STS__DSPAdrTransRangeErrSource__SHIFT 0x101125#define ACP_ERROR_SOURCE_STS__DSPAdrTransRangeErrSourceOver_MASK 0x800001126#define ACP_ERROR_SOURCE_STS__DSPAdrTransRangeErrSourceOver__SHIFT 0x131127#define ACP_ERROR_SOURCE_STS__DAGBErr_MASK 0x1000001128#define ACP_ERROR_SOURCE_STS__DAGBErr__SHIFT 0x141129#define ACP_ERROR_SOURCE_STS__DAGBErrSource_MASK 0x1e000001130#define ACP_ERROR_SOURCE_STS__DAGBErrSource__SHIFT 0x151131#define ACP_ERROR_SOURCE_STS__DAGBErrSourceOver_MASK 0x20000001132#define ACP_ERROR_SOURCE_STS__DAGBErrSourceOver__SHIFT 0x191133#define ACP_ERROR_SOURCE_STS__DMATermOnErr_MASK 0x40000001134#define ACP_ERROR_SOURCE_STS__DMATermOnErr__SHIFT 0x1a1135#define ACP_ERROR_SOURCE_STS__I2SBTTxFifoOverFlowErr_MASK 0x100000001136#define ACP_ERROR_SOURCE_STS__I2SBTTxFifoOverFlowErr__SHIFT 0x1c1137#define ACP_DSP_SW_INTR_TRIG__TrigSWIntHostDSP0_MASK 0x11138#define ACP_DSP_SW_INTR_TRIG__TrigSWIntHostDSP0__SHIFT 0x01139#define ACP_DSP_SW_INTR_TRIG__TrigSWIntHostDSP1_MASK 0x21140#define ACP_DSP_SW_INTR_TRIG__TrigSWIntHostDSP1__SHIFT 0x11141#define ACP_DSP_SW_INTR_TRIG__TrigSWIntHostDSP2_MASK 0x41142#define ACP_DSP_SW_INTR_TRIG__TrigSWIntHostDSP2__SHIFT 0x21143#define ACP_DSP_SW_INTR_TRIG__TrigSWIntDSPnDSP0_MASK 0x1001144#define ACP_DSP_SW_INTR_TRIG__TrigSWIntDSPnDSP0__SHIFT 0x81145#define ACP_DSP_SW_INTR_TRIG__TrigSWIntDSPnDSP1_MASK 0x2001146#define ACP_DSP_SW_INTR_TRIG__TrigSWIntDSPnDSP1__SHIFT 0x91147#define ACP_DSP_SW_INTR_TRIG__TrigSWIntDSPnDSP2_MASK 0x4001148#define ACP_DSP_SW_INTR_TRIG__TrigSWIntDSPnDSP2__SHIFT 0xa1149#define ACP_DSP_SW_INTR_TRIG__TrigSWIntDSP0Host_MASK 0x100001150#define ACP_DSP_SW_INTR_TRIG__TrigSWIntDSP0Host__SHIFT 0x101151#define ACP_DSP_SW_INTR_TRIG__TrigSWIntDSP1Host_MASK 0x200001152#define ACP_DSP_SW_INTR_TRIG__TrigSWIntDSP1Host__SHIFT 0x111153#define ACP_DSP_SW_INTR_TRIG__TrigSWIntDSP2Host_MASK 0x400001154#define ACP_DSP_SW_INTR_TRIG__TrigSWIntDSP2Host__SHIFT 0x121155#define ACP_DSP_SW_INTR_CNTL__EnbSWIntHostDSP0_MASK 0x11156#define ACP_DSP_SW_INTR_CNTL__EnbSWIntHostDSP0__SHIFT 0x01157#define ACP_DSP_SW_INTR_CNTL__EnbSWIntHostDSP1_MASK 0x21158#define ACP_DSP_SW_INTR_CNTL__EnbSWIntHostDSP1__SHIFT 0x11159#define ACP_DSP_SW_INTR_CNTL__EnbSWIntHostDSP2_MASK 0x41160#define ACP_DSP_SW_INTR_CNTL__EnbSWIntHostDSP2__SHIFT 0x21161#define ACP_DSP_SW_INTR_CNTL__EnbSWIntDSPnDSP0_MASK 0x1001162#define ACP_DSP_SW_INTR_CNTL__EnbSWIntDSPnDSP0__SHIFT 0x81163#define ACP_DSP_SW_INTR_CNTL__EnbSWIntDSPnDSP1_MASK 0x2001164#define ACP_DSP_SW_INTR_CNTL__EnbSWIntDSPnDSP1__SHIFT 0x91165#define ACP_DSP_SW_INTR_CNTL__EnbSWIntDSPnDSP2_MASK 0x4001166#define ACP_DSP_SW_INTR_CNTL__EnbSWIntDSPnDSP2__SHIFT 0xa1167#define ACP_DSP_SW_INTR_CNTL__EnbKernelIntrDSP0Mask_MASK 0x100001168#define ACP_DSP_SW_INTR_CNTL__EnbKernelIntrDSP0Mask__SHIFT 0x101169#define ACP_DSP_SW_INTR_CNTL__EmbKernelIntrDSP1Mask_MASK 0x200001170#define ACP_DSP_SW_INTR_CNTL__EmbKernelIntrDSP1Mask__SHIFT 0x111171#define ACP_DSP_SW_INTR_CNTL__EmbKernelIntrDSP2Mask_MASK 0x400001172#define ACP_DSP_SW_INTR_CNTL__EmbKernelIntrDSP2Mask__SHIFT 0x121173#define ACP_DAGBG_TIMEOUT_CNTL__DAGBGTimeoutValue_MASK 0x3ffff1174#define ACP_DAGBG_TIMEOUT_CNTL__DAGBGTimeoutValue__SHIFT 0x01175#define ACP_DAGBG_TIMEOUT_CNTL__CntEn_MASK 0x800000001176#define ACP_DAGBG_TIMEOUT_CNTL__CntEn__SHIFT 0x1f1177#define ACP_DAGBO_TIMEOUT_CNTL__DAGBOTimeoutValue_MASK 0x3ffff1178#define ACP_DAGBO_TIMEOUT_CNTL__DAGBOTimeoutValue__SHIFT 0x01179#define ACP_DAGBO_TIMEOUT_CNTL__CntEn_MASK 0x800000001180#define ACP_DAGBO_TIMEOUT_CNTL__CntEn__SHIFT 0x1f1181#define ACP_EXTERNAL_INTR_STAT__ACPErrStat_MASK 0x11182#define ACP_EXTERNAL_INTR_STAT__ACPErrStat__SHIFT 0x01183#define ACP_EXTERNAL_INTR_STAT__ACPErrAck_MASK 0x11184#define ACP_EXTERNAL_INTR_STAT__ACPErrAck__SHIFT 0x01185#define ACP_EXTERNAL_INTR_STAT__I2SMicDataAvStat_MASK 0x21186#define ACP_EXTERNAL_INTR_STAT__I2SMicDataAvStat__SHIFT 0x11187#define ACP_EXTERNAL_INTR_STAT__I2SMicDataAvAck_MASK 0x21188#define ACP_EXTERNAL_INTR_STAT__I2SMicDataAvAck__SHIFT 0x11189#define ACP_EXTERNAL_INTR_STAT__I2SSpkr0DataEmptyStat_MASK 0x41190#define ACP_EXTERNAL_INTR_STAT__I2SSpkr0DataEmptyStat__SHIFT 0x21191#define ACP_EXTERNAL_INTR_STAT__I2SSpkr0DataEmptyAck_MASK 0x41192#define ACP_EXTERNAL_INTR_STAT__I2SSpkr0DataEmptyAck__SHIFT 0x21193#define ACP_EXTERNAL_INTR_STAT__I2SSpkr1DataEmptyStat_MASK 0x81194#define ACP_EXTERNAL_INTR_STAT__I2SSpkr1DataEmptyStat__SHIFT 0x31195#define ACP_EXTERNAL_INTR_STAT__I2SSpkr1DataEmptyAck_MASK 0x81196#define ACP_EXTERNAL_INTR_STAT__I2SSpkr1DataEmptyAck__SHIFT 0x31197#define ACP_EXTERNAL_INTR_STAT__I2SBTDataAvStat_MASK 0x101198#define ACP_EXTERNAL_INTR_STAT__I2SBTDataAvStat__SHIFT 0x41199#define ACP_EXTERNAL_INTR_STAT__I2SBTDataAvAck_MASK 0x101200#define ACP_EXTERNAL_INTR_STAT__I2SBTDataAvAck__SHIFT 0x41201#define ACP_EXTERNAL_INTR_STAT__AzaliaIntrStat_MASK 0x401202#define ACP_EXTERNAL_INTR_STAT__AzaliaIntrStat__SHIFT 0x61203#define ACP_EXTERNAL_INTR_STAT__AzaliaIntrAck_MASK 0x401204#define ACP_EXTERNAL_INTR_STAT__AzaliaIntrAck__SHIFT 0x61205#define ACP_EXTERNAL_INTR_STAT__DSP0TimeoutStat_MASK 0x1001206#define ACP_EXTERNAL_INTR_STAT__DSP0TimeoutStat__SHIFT 0x81207#define ACP_EXTERNAL_INTR_STAT__DSP0TimeoutAck_MASK 0x1001208#define ACP_EXTERNAL_INTR_STAT__DSP0TimeoutAck__SHIFT 0x81209#define ACP_EXTERNAL_INTR_STAT__DSP1TimeoutStat_MASK 0x2001210#define ACP_EXTERNAL_INTR_STAT__DSP1TimeoutStat__SHIFT 0x91211#define ACP_EXTERNAL_INTR_STAT__DSP1TimeoutAck_MASK 0x2001212#define ACP_EXTERNAL_INTR_STAT__DSP1TimeoutAck__SHIFT 0x91213#define ACP_EXTERNAL_INTR_STAT__DSP2TimeoutStat_MASK 0x4001214#define ACP_EXTERNAL_INTR_STAT__DSP2TimeoutStat__SHIFT 0xa1215#define ACP_EXTERNAL_INTR_STAT__DSP2TimeoutAck_MASK 0x4001216#define ACP_EXTERNAL_INTR_STAT__DSP2TimeoutAck__SHIFT 0xa1217#define ACP_EXTERNAL_INTR_STAT__I2SBTDataEmptyStat_MASK 0x8001218#define ACP_EXTERNAL_INTR_STAT__I2SBTDataEmptyStat__SHIFT 0xb1219#define ACP_EXTERNAL_INTR_STAT__I2SBTDataEmptyAck_MASK 0x8001220#define ACP_EXTERNAL_INTR_STAT__I2SBTDataEmptyAck__SHIFT 0xb1221#define ACP_EXTERNAL_INTR_STAT__DMAIOCStat_MASK 0xffff00001222#define ACP_EXTERNAL_INTR_STAT__DMAIOCStat__SHIFT 0x101223#define ACP_EXTERNAL_INTR_STAT__DMAIOCAck_MASK 0xffff00001224#define ACP_EXTERNAL_INTR_STAT__DMAIOCAck__SHIFT 0x101225#define ACP_DSP_SW_INTR_STAT__SWIntHostDSP0Stat_MASK 0x11226#define ACP_DSP_SW_INTR_STAT__SWIntHostDSP0Stat__SHIFT 0x01227#define ACP_DSP_SW_INTR_STAT__SWIntHostDSP0Ack_MASK 0x11228#define ACP_DSP_SW_INTR_STAT__SWIntHostDSP0Ack__SHIFT 0x01229#define ACP_DSP_SW_INTR_STAT__SWIntHostDSP1Stat_MASK 0x21230#define ACP_DSP_SW_INTR_STAT__SWIntHostDSP1Stat__SHIFT 0x11231#define ACP_DSP_SW_INTR_STAT__SWIntHostDSP1Ack_MASK 0x21232#define ACP_DSP_SW_INTR_STAT__SWIntHostDSP1Ack__SHIFT 0x11233#define ACP_DSP_SW_INTR_STAT__SWIntHostDSP2Stat_MASK 0x41234#define ACP_DSP_SW_INTR_STAT__SWIntHostDSP2Stat__SHIFT 0x21235#define ACP_DSP_SW_INTR_STAT__SWIntHostDSP2Ack_MASK 0x41236#define ACP_DSP_SW_INTR_STAT__SWIntHostDSP2Ack__SHIFT 0x21237#define ACP_DSP_SW_INTR_STAT__SWIntDSPnDSP0Stat_MASK 0x1001238#define ACP_DSP_SW_INTR_STAT__SWIntDSPnDSP0Stat__SHIFT 0x81239#define ACP_DSP_SW_INTR_STAT__SWIntDSPnDSP0Ack_MASK 0x1001240#define ACP_DSP_SW_INTR_STAT__SWIntDSPnDSP0Ack__SHIFT 0x81241#define ACP_DSP_SW_INTR_STAT__SWIntDSPnDSP1Stat_MASK 0x2001242#define ACP_DSP_SW_INTR_STAT__SWIntDSPnDSP1Stat__SHIFT 0x91243#define ACP_DSP_SW_INTR_STAT__SWIntDSPnDSP1Ack_MASK 0x2001244#define ACP_DSP_SW_INTR_STAT__SWIntDSPnDSP1Ack__SHIFT 0x91245#define ACP_DSP_SW_INTR_STAT__SWIntDSPnDSP2Stat_MASK 0x4001246#define ACP_DSP_SW_INTR_STAT__SWIntDSPnDSP2Stat__SHIFT 0xa1247#define ACP_DSP_SW_INTR_STAT__SWIntDSPnDSP2Ack_MASK 0x4001248#define ACP_DSP_SW_INTR_STAT__SWIntDSPnDSP2Ack__SHIFT 0xa1249#define ACP_DSP_SW_INTR_STAT__SWKernelIntrDSP0Stat_MASK 0x100001250#define ACP_DSP_SW_INTR_STAT__SWKernelIntrDSP0Stat__SHIFT 0x101251#define ACP_DSP_SW_INTR_STAT__SWKernelIntrDSP0Ack_MASK 0x100001252#define ACP_DSP_SW_INTR_STAT__SWKernelIntrDSP0Ack__SHIFT 0x101253#define ACP_DSP_SW_INTR_STAT__SWKernelIntrDSP1Stat_MASK 0x200001254#define ACP_DSP_SW_INTR_STAT__SWKernelIntrDSP1Stat__SHIFT 0x111255#define ACP_DSP_SW_INTR_STAT__SWKernelIntrDSP1Ack_MASK 0x200001256#define ACP_DSP_SW_INTR_STAT__SWKernelIntrDSP1Ack__SHIFT 0x111257#define ACP_DSP_SW_INTR_STAT__SWKernelIntrDSP2Stat_MASK 0x400001258#define ACP_DSP_SW_INTR_STAT__SWKernelIntrDSP2Stat__SHIFT 0x121259#define ACP_DSP_SW_INTR_STAT__SWKernelIntrDSP2Ack_MASK 0x400001260#define ACP_DSP_SW_INTR_STAT__SWKernelIntrDSP2Ack__SHIFT 0x121261#define ACP_DSP0_INTR_CNTL__ACPErrMask_MASK 0x11262#define ACP_DSP0_INTR_CNTL__ACPErrMask__SHIFT 0x01263#define ACP_DSP0_INTR_CNTL__I2SMicDataAvMask_MASK 0x21264#define ACP_DSP0_INTR_CNTL__I2SMicDataAvMask__SHIFT 0x11265#define ACP_DSP0_INTR_CNTL__I2SSpkr0DataEmptyMask_MASK 0x41266#define ACP_DSP0_INTR_CNTL__I2SSpkr0DataEmptyMask__SHIFT 0x21267#define ACP_DSP0_INTR_CNTL__I2SSpkr1DataEmptyMask_MASK 0x81268#define ACP_DSP0_INTR_CNTL__I2SSpkr1DataEmptyMask__SHIFT 0x31269#define ACP_DSP0_INTR_CNTL__I2SBTDataAvMask_MASK 0x101270#define ACP_DSP0_INTR_CNTL__I2SBTDataAvMask__SHIFT 0x41271#define ACP_DSP0_INTR_CNTL__AzaliaIntrMask_MASK 0x401272#define ACP_DSP0_INTR_CNTL__AzaliaIntrMask__SHIFT 0x61273#define ACP_DSP0_INTR_CNTL__SMUMailboxWriteMask_MASK 0x1001274#define ACP_DSP0_INTR_CNTL__SMUMailboxWriteMask__SHIFT 0x81275#define ACP_DSP0_INTR_CNTL__SMUStutterStatusMask_MASK 0x2001276#define ACP_DSP0_INTR_CNTL__SMUStutterStatusMask__SHIFT 0x91277#define ACP_DSP0_INTR_CNTL__MCStutterStatusMask_MASK 0x4001278#define ACP_DSP0_INTR_CNTL__MCStutterStatusMask__SHIFT 0xa1279#define ACP_DSP0_INTR_CNTL__DSPExtTimerMask_MASK 0x8001280#define ACP_DSP0_INTR_CNTL__DSPExtTimerMask__SHIFT 0xb1281#define ACP_DSP0_INTR_CNTL__DSPSemRespMask_MASK 0x10001282#define ACP_DSP0_INTR_CNTL__DSPSemRespMask__SHIFT 0xc1283#define ACP_DSP0_INTR_CNTL__I2SBTDataEmptyMask_MASK 0x20001284#define ACP_DSP0_INTR_CNTL__I2SBTDataEmptyMask__SHIFT 0xd1285#define ACP_DSP0_INTR_CNTL__DMAIOCMask_MASK 0xffff00001286#define ACP_DSP0_INTR_CNTL__DMAIOCMask__SHIFT 0x101287#define ACP_DSP0_INTR_STAT__ACPErrStat_MASK 0x11288#define ACP_DSP0_INTR_STAT__ACPErrStat__SHIFT 0x01289#define ACP_DSP0_INTR_STAT__ACPErrAck_MASK 0x11290#define ACP_DSP0_INTR_STAT__ACPErrAck__SHIFT 0x01291#define ACP_DSP0_INTR_STAT__I2SMicDataAvStat_MASK 0x21292#define ACP_DSP0_INTR_STAT__I2SMicDataAvStat__SHIFT 0x11293#define ACP_DSP0_INTR_STAT__I2SMicDataAvAck_MASK 0x21294#define ACP_DSP0_INTR_STAT__I2SMicDataAvAck__SHIFT 0x11295#define ACP_DSP0_INTR_STAT__I2SSpkr0DataEmptyStat_MASK 0x41296#define ACP_DSP0_INTR_STAT__I2SSpkr0DataEmptyStat__SHIFT 0x21297#define ACP_DSP0_INTR_STAT__I2SSpkr0DataEmptyAck_MASK 0x41298#define ACP_DSP0_INTR_STAT__I2SSpkr0DataEmptyAck__SHIFT 0x21299#define ACP_DSP0_INTR_STAT__I2SSpkr1DataEmptyStat_MASK 0x81300#define ACP_DSP0_INTR_STAT__I2SSpkr1DataEmptyStat__SHIFT 0x31301#define ACP_DSP0_INTR_STAT__I2SSpkr1DataEmptyAck_MASK 0x81302#define ACP_DSP0_INTR_STAT__I2SSpkr1DataEmptyAck__SHIFT 0x31303#define ACP_DSP0_INTR_STAT__I2SBTDataAvStat_MASK 0x101304#define ACP_DSP0_INTR_STAT__I2SBTDataAvStat__SHIFT 0x41305#define ACP_DSP0_INTR_STAT__I2SBTDataAvAck_MASK 0x101306#define ACP_DSP0_INTR_STAT__I2SBTDataAvAck__SHIFT 0x41307#define ACP_DSP0_INTR_STAT__AzaliaIntrStat_MASK 0x401308#define ACP_DSP0_INTR_STAT__AzaliaIntrStat__SHIFT 0x61309#define ACP_DSP0_INTR_STAT__AzaliaIntrAck_MASK 0x401310#define ACP_DSP0_INTR_STAT__AzaliaIntrAck__SHIFT 0x61311#define ACP_DSP0_INTR_STAT__SMUMailboxWriteStat_MASK 0x1001312#define ACP_DSP0_INTR_STAT__SMUMailboxWriteStat__SHIFT 0x81313#define ACP_DSP0_INTR_STAT__SMUMailboxWriteAck_MASK 0x1001314#define ACP_DSP0_INTR_STAT__SMUMailboxWriteAck__SHIFT 0x81315#define ACP_DSP0_INTR_STAT__SMUStutterStatusStat_MASK 0x2001316#define ACP_DSP0_INTR_STAT__SMUStutterStatusStat__SHIFT 0x91317#define ACP_DSP0_INTR_STAT__SMUStutterStatusAck_MASK 0x2001318#define ACP_DSP0_INTR_STAT__SMUStutterStatusAck__SHIFT 0x91319#define ACP_DSP0_INTR_STAT__MCStutterStatusStat_MASK 0x4001320#define ACP_DSP0_INTR_STAT__MCStutterStatusStat__SHIFT 0xa1321#define ACP_DSP0_INTR_STAT__MCStutterStatusAck_MASK 0x4001322#define ACP_DSP0_INTR_STAT__MCStutterStatusAck__SHIFT 0xa1323#define ACP_DSP0_INTR_STAT__DSPExtTimerStat_MASK 0x8001324#define ACP_DSP0_INTR_STAT__DSPExtTimerStat__SHIFT 0xb1325#define ACP_DSP0_INTR_STAT__DSPExtTimerAck_MASK 0x8001326#define ACP_DSP0_INTR_STAT__DSPExtTimerAck__SHIFT 0xb1327#define ACP_DSP0_INTR_STAT__DSPSemRespStat_MASK 0x10001328#define ACP_DSP0_INTR_STAT__DSPSemRespStat__SHIFT 0xc1329#define ACP_DSP0_INTR_STAT__DSPSemRespAck_MASK 0x10001330#define ACP_DSP0_INTR_STAT__DSPSemRespAck__SHIFT 0xc1331#define ACP_DSP0_INTR_STAT__I2SBTDataEmptyStat_MASK 0x20001332#define ACP_DSP0_INTR_STAT__I2SBTDataEmptyStat__SHIFT 0xd1333#define ACP_DSP0_INTR_STAT__I2SBTDataEmptyAck_MASK 0x20001334#define ACP_DSP0_INTR_STAT__I2SBTDataEmptyAck__SHIFT 0xd1335#define ACP_DSP0_INTR_STAT__DMAIOCStat_MASK 0xffff00001336#define ACP_DSP0_INTR_STAT__DMAIOCStat__SHIFT 0x101337#define ACP_DSP0_INTR_STAT__DMAIOCAck_MASK 0xffff00001338#define ACP_DSP0_INTR_STAT__DMAIOCAck__SHIFT 0x101339#define ACP_DSP0_TIMEOUT_CNTL__DSP0TimeoutValue_MASK 0x3ffff1340#define ACP_DSP0_TIMEOUT_CNTL__DSP0TimeoutValue__SHIFT 0x01341#define ACP_DSP0_TIMEOUT_CNTL__CntEn_MASK 0x800000001342#define ACP_DSP0_TIMEOUT_CNTL__CntEn__SHIFT 0x1f1343#define ACP_DSP1_INTR_CNTL__ACPErrMask_MASK 0x11344#define ACP_DSP1_INTR_CNTL__ACPErrMask__SHIFT 0x01345#define ACP_DSP1_INTR_CNTL__I2SMicDataAvMask_MASK 0x21346#define ACP_DSP1_INTR_CNTL__I2SMicDataAvMask__SHIFT 0x11347#define ACP_DSP1_INTR_CNTL__I2SSpkr0DataEmptyMask_MASK 0x41348#define ACP_DSP1_INTR_CNTL__I2SSpkr0DataEmptyMask__SHIFT 0x21349#define ACP_DSP1_INTR_CNTL__I2SSpkr1DataEmptyMask_MASK 0x81350#define ACP_DSP1_INTR_CNTL__I2SSpkr1DataEmptyMask__SHIFT 0x31351#define ACP_DSP1_INTR_CNTL__I2SBTDataAvMask_MASK 0x101352#define ACP_DSP1_INTR_CNTL__I2SBTDataAvMask__SHIFT 0x41353#define ACP_DSP1_INTR_CNTL__AzaliaIntrMask_MASK 0x401354#define ACP_DSP1_INTR_CNTL__AzaliaIntrMask__SHIFT 0x61355#define ACP_DSP1_INTR_CNTL__SMUMailboxWriteMask_MASK 0x1001356#define ACP_DSP1_INTR_CNTL__SMUMailboxWriteMask__SHIFT 0x81357#define ACP_DSP1_INTR_CNTL__SMUStutterStatusMask_MASK 0x2001358#define ACP_DSP1_INTR_CNTL__SMUStutterStatusMask__SHIFT 0x91359#define ACP_DSP1_INTR_CNTL__MCStutterStatusMask_MASK 0x4001360#define ACP_DSP1_INTR_CNTL__MCStutterStatusMask__SHIFT 0xa1361#define ACP_DSP1_INTR_CNTL__DSPExtTimerMask_MASK 0x8001362#define ACP_DSP1_INTR_CNTL__DSPExtTimerMask__SHIFT 0xb1363#define ACP_DSP1_INTR_CNTL__DSPSemRespMask_MASK 0x10001364#define ACP_DSP1_INTR_CNTL__DSPSemRespMask__SHIFT 0xc1365#define ACP_DSP1_INTR_CNTL__I2SBTDataEmptyMask_MASK 0x20001366#define ACP_DSP1_INTR_CNTL__I2SBTDataEmptyMask__SHIFT 0xd1367#define ACP_DSP1_INTR_CNTL__DMAIOCMask_MASK 0xffff00001368#define ACP_DSP1_INTR_CNTL__DMAIOCMask__SHIFT 0x101369#define ACP_DSP1_INTR_STAT__ACPErrStat_MASK 0x11370#define ACP_DSP1_INTR_STAT__ACPErrStat__SHIFT 0x01371#define ACP_DSP1_INTR_STAT__ACPErrAck_MASK 0x11372#define ACP_DSP1_INTR_STAT__ACPErrAck__SHIFT 0x01373#define ACP_DSP1_INTR_STAT__I2SMicDataAvStat_MASK 0x21374#define ACP_DSP1_INTR_STAT__I2SMicDataAvStat__SHIFT 0x11375#define ACP_DSP1_INTR_STAT__I2SMicDataAvAck_MASK 0x21376#define ACP_DSP1_INTR_STAT__I2SMicDataAvAck__SHIFT 0x11377#define ACP_DSP1_INTR_STAT__I2SSpkr0DataEmptyStat_MASK 0x41378#define ACP_DSP1_INTR_STAT__I2SSpkr0DataEmptyStat__SHIFT 0x21379#define ACP_DSP1_INTR_STAT__I2SSpkr0DataEmptyAck_MASK 0x41380#define ACP_DSP1_INTR_STAT__I2SSpkr0DataEmptyAck__SHIFT 0x21381#define ACP_DSP1_INTR_STAT__I2SSpkr1DataEmptyStat_MASK 0x81382#define ACP_DSP1_INTR_STAT__I2SSpkr1DataEmptyStat__SHIFT 0x31383#define ACP_DSP1_INTR_STAT__I2SSpkr1DataEmptyAck_MASK 0x81384#define ACP_DSP1_INTR_STAT__I2SSpkr1DataEmptyAck__SHIFT 0x31385#define ACP_DSP1_INTR_STAT__I2SBTDataAvStat_MASK 0x101386#define ACP_DSP1_INTR_STAT__I2SBTDataAvStat__SHIFT 0x41387#define ACP_DSP1_INTR_STAT__I2SBTDataAvAck_MASK 0x101388#define ACP_DSP1_INTR_STAT__I2SBTDataAvAck__SHIFT 0x41389#define ACP_DSP1_INTR_STAT__AzaliaIntrStat_MASK 0x401390#define ACP_DSP1_INTR_STAT__AzaliaIntrStat__SHIFT 0x61391#define ACP_DSP1_INTR_STAT__AzaliaIntrAck_MASK 0x401392#define ACP_DSP1_INTR_STAT__AzaliaIntrAck__SHIFT 0x61393#define ACP_DSP1_INTR_STAT__SMUMailboxWriteStat_MASK 0x1001394#define ACP_DSP1_INTR_STAT__SMUMailboxWriteStat__SHIFT 0x81395#define ACP_DSP1_INTR_STAT__SMUMailboxWriteAck_MASK 0x1001396#define ACP_DSP1_INTR_STAT__SMUMailboxWriteAck__SHIFT 0x81397#define ACP_DSP1_INTR_STAT__SMUStutterStatusStat_MASK 0x2001398#define ACP_DSP1_INTR_STAT__SMUStutterStatusStat__SHIFT 0x91399#define ACP_DSP1_INTR_STAT__SMUStutterStatusAck_MASK 0x2001400#define ACP_DSP1_INTR_STAT__SMUStutterStatusAck__SHIFT 0x91401#define ACP_DSP1_INTR_STAT__MCStutterStatusStat_MASK 0x4001402#define ACP_DSP1_INTR_STAT__MCStutterStatusStat__SHIFT 0xa1403#define ACP_DSP1_INTR_STAT__MCStutterStatusAck_MASK 0x4001404#define ACP_DSP1_INTR_STAT__MCStutterStatusAck__SHIFT 0xa1405#define ACP_DSP1_INTR_STAT__DSPExtTimerStat_MASK 0x8001406#define ACP_DSP1_INTR_STAT__DSPExtTimerStat__SHIFT 0xb1407#define ACP_DSP1_INTR_STAT__DSPExtTimerAck_MASK 0x8001408#define ACP_DSP1_INTR_STAT__DSPExtTimerAck__SHIFT 0xb1409#define ACP_DSP1_INTR_STAT__DSPSemRespStat_MASK 0x10001410#define ACP_DSP1_INTR_STAT__DSPSemRespStat__SHIFT 0xc1411#define ACP_DSP1_INTR_STAT__DSPSemRespAck_MASK 0x10001412#define ACP_DSP1_INTR_STAT__DSPSemRespAck__SHIFT 0xc1413#define ACP_DSP1_INTR_STAT__I2SBTDataEmptyStat_MASK 0x20001414#define ACP_DSP1_INTR_STAT__I2SBTDataEmptyStat__SHIFT 0xd1415#define ACP_DSP1_INTR_STAT__I2SBTDataEmptyAck_MASK 0x20001416#define ACP_DSP1_INTR_STAT__I2SBTDataEmptyAck__SHIFT 0xd1417#define ACP_DSP1_INTR_STAT__DMAIOCStat_MASK 0xffff00001418#define ACP_DSP1_INTR_STAT__DMAIOCStat__SHIFT 0x101419#define ACP_DSP1_INTR_STAT__DMAIOCAck_MASK 0xffff00001420#define ACP_DSP1_INTR_STAT__DMAIOCAck__SHIFT 0x101421#define ACP_DSP1_TIMEOUT_CNTL__DSP1TimeoutValue_MASK 0x3ffff1422#define ACP_DSP1_TIMEOUT_CNTL__DSP1TimeoutValue__SHIFT 0x01423#define ACP_DSP1_TIMEOUT_CNTL__CntEn_MASK 0x800000001424#define ACP_DSP1_TIMEOUT_CNTL__CntEn__SHIFT 0x1f1425#define ACP_DSP2_INTR_CNTL__ACPErrMask_MASK 0x11426#define ACP_DSP2_INTR_CNTL__ACPErrMask__SHIFT 0x01427#define ACP_DSP2_INTR_CNTL__I2SMicDataAvMask_MASK 0x21428#define ACP_DSP2_INTR_CNTL__I2SMicDataAvMask__SHIFT 0x11429#define ACP_DSP2_INTR_CNTL__I2SSpkr0DataEmptyMask_MASK 0x41430#define ACP_DSP2_INTR_CNTL__I2SSpkr0DataEmptyMask__SHIFT 0x21431#define ACP_DSP2_INTR_CNTL__I2SSpkr1DataEmptyMask_MASK 0x81432#define ACP_DSP2_INTR_CNTL__I2SSpkr1DataEmptyMask__SHIFT 0x31433#define ACP_DSP2_INTR_CNTL__I2SBTDataAvMask_MASK 0x101434#define ACP_DSP2_INTR_CNTL__I2SBTDataAvMask__SHIFT 0x41435#define ACP_DSP2_INTR_CNTL__AzaliaIntrMask_MASK 0x401436#define ACP_DSP2_INTR_CNTL__AzaliaIntrMask__SHIFT 0x61437#define ACP_DSP2_INTR_CNTL__SMUMailboxWriteMask_MASK 0x1001438#define ACP_DSP2_INTR_CNTL__SMUMailboxWriteMask__SHIFT 0x81439#define ACP_DSP2_INTR_CNTL__SMUStutterStatusMask_MASK 0x2001440#define ACP_DSP2_INTR_CNTL__SMUStutterStatusMask__SHIFT 0x91441#define ACP_DSP2_INTR_CNTL__MCStutterStatusMask_MASK 0x4001442#define ACP_DSP2_INTR_CNTL__MCStutterStatusMask__SHIFT 0xa1443#define ACP_DSP2_INTR_CNTL__DSPExtTimerMask_MASK 0x8001444#define ACP_DSP2_INTR_CNTL__DSPExtTimerMask__SHIFT 0xb1445#define ACP_DSP2_INTR_CNTL__DSPSemRespMask_MASK 0x10001446#define ACP_DSP2_INTR_CNTL__DSPSemRespMask__SHIFT 0xc1447#define ACP_DSP2_INTR_CNTL__I2SBTDataEmptyMask_MASK 0x20001448#define ACP_DSP2_INTR_CNTL__I2SBTDataEmptyMask__SHIFT 0xd1449#define ACP_DSP2_INTR_CNTL__DMAIOCMask_MASK 0xffff00001450#define ACP_DSP2_INTR_CNTL__DMAIOCMask__SHIFT 0x101451#define ACP_DSP2_INTR_STAT__ACPErrStat_MASK 0x11452#define ACP_DSP2_INTR_STAT__ACPErrStat__SHIFT 0x01453#define ACP_DSP2_INTR_STAT__ACPErrAck_MASK 0x11454#define ACP_DSP2_INTR_STAT__ACPErrAck__SHIFT 0x01455#define ACP_DSP2_INTR_STAT__I2SMicDataAvStat_MASK 0x21456#define ACP_DSP2_INTR_STAT__I2SMicDataAvStat__SHIFT 0x11457#define ACP_DSP2_INTR_STAT__I2SMicDataAvAck_MASK 0x21458#define ACP_DSP2_INTR_STAT__I2SMicDataAvAck__SHIFT 0x11459#define ACP_DSP2_INTR_STAT__I2SSpkr0DataEmptyStat_MASK 0x41460#define ACP_DSP2_INTR_STAT__I2SSpkr0DataEmptyStat__SHIFT 0x21461#define ACP_DSP2_INTR_STAT__I2SSpkr0DataEmptyAck_MASK 0x41462#define ACP_DSP2_INTR_STAT__I2SSpkr0DataEmptyAck__SHIFT 0x21463#define ACP_DSP2_INTR_STAT__I2SSpkr1DataEmptyStat_MASK 0x81464#define ACP_DSP2_INTR_STAT__I2SSpkr1DataEmptyStat__SHIFT 0x31465#define ACP_DSP2_INTR_STAT__I2SSpkr1DataEmptyAck_MASK 0x81466#define ACP_DSP2_INTR_STAT__I2SSpkr1DataEmptyAck__SHIFT 0x31467#define ACP_DSP2_INTR_STAT__I2SBTDataAvStat_MASK 0x101468#define ACP_DSP2_INTR_STAT__I2SBTDataAvStat__SHIFT 0x41469#define ACP_DSP2_INTR_STAT__I2SBTDataAvAck_MASK 0x101470#define ACP_DSP2_INTR_STAT__I2SBTDataAvAck__SHIFT 0x41471#define ACP_DSP2_INTR_STAT__AzaliaIntrStat_MASK 0x401472#define ACP_DSP2_INTR_STAT__AzaliaIntrStat__SHIFT 0x61473#define ACP_DSP2_INTR_STAT__AzaliaIntrAck_MASK 0x401474#define ACP_DSP2_INTR_STAT__AzaliaIntrAck__SHIFT 0x61475#define ACP_DSP2_INTR_STAT__SMUMailboxWriteStat_MASK 0x1001476#define ACP_DSP2_INTR_STAT__SMUMailboxWriteStat__SHIFT 0x81477#define ACP_DSP2_INTR_STAT__SMUMailboxWriteAck_MASK 0x1001478#define ACP_DSP2_INTR_STAT__SMUMailboxWriteAck__SHIFT 0x81479#define ACP_DSP2_INTR_STAT__SMUStutterStatusStat_MASK 0x2001480#define ACP_DSP2_INTR_STAT__SMUStutterStatusStat__SHIFT 0x91481#define ACP_DSP2_INTR_STAT__SMUStutterStatusAck_MASK 0x2001482#define ACP_DSP2_INTR_STAT__SMUStutterStatusAck__SHIFT 0x91483#define ACP_DSP2_INTR_STAT__MCStutterStatusStat_MASK 0x4001484#define ACP_DSP2_INTR_STAT__MCStutterStatusStat__SHIFT 0xa1485#define ACP_DSP2_INTR_STAT__MCStutterStatusAck_MASK 0x4001486#define ACP_DSP2_INTR_STAT__MCStutterStatusAck__SHIFT 0xa1487#define ACP_DSP2_INTR_STAT__DSPExtTimerStat_MASK 0x8001488#define ACP_DSP2_INTR_STAT__DSPExtTimerStat__SHIFT 0xb1489#define ACP_DSP2_INTR_STAT__DSPExtTimerAck_MASK 0x8001490#define ACP_DSP2_INTR_STAT__DSPExtTimerAck__SHIFT 0xb1491#define ACP_DSP2_INTR_STAT__DSPSemRespStat_MASK 0x10001492#define ACP_DSP2_INTR_STAT__DSPSemRespStat__SHIFT 0xc1493#define ACP_DSP2_INTR_STAT__DSPSemRespAck_MASK 0x10001494#define ACP_DSP2_INTR_STAT__DSPSemRespAck__SHIFT 0xc1495#define ACP_DSP2_INTR_STAT__I2SBTDataEmptyStat_MASK 0x20001496#define ACP_DSP2_INTR_STAT__I2SBTDataEmptyStat__SHIFT 0xd1497#define ACP_DSP2_INTR_STAT__I2SBTDataEmptyAck_MASK 0x20001498#define ACP_DSP2_INTR_STAT__I2SBTDataEmptyAck__SHIFT 0xd1499#define ACP_DSP2_INTR_STAT__DMAIOCStat_MASK 0xffff00001500#define ACP_DSP2_INTR_STAT__DMAIOCStat__SHIFT 0x101501#define ACP_DSP2_INTR_STAT__DMAIOCAck_MASK 0xffff00001502#define ACP_DSP2_INTR_STAT__DMAIOCAck__SHIFT 0x101503#define ACP_DSP2_TIMEOUT_CNTL__DSP2TimeoutValue_MASK 0x3ffff1504#define ACP_DSP2_TIMEOUT_CNTL__DSP2TimeoutValue__SHIFT 0x01505#define ACP_DSP2_TIMEOUT_CNTL__CntEn_MASK 0x800000001506#define ACP_DSP2_TIMEOUT_CNTL__CntEn__SHIFT 0x1f1507#define ACP_DSP0_EXT_TIMER_CNTL__TimerCount_MASK 0xffffff1508#define ACP_DSP0_EXT_TIMER_CNTL__TimerCount__SHIFT 0x01509#define ACP_DSP0_EXT_TIMER_CNTL__TimerCntl_MASK 0xc00000001510#define ACP_DSP0_EXT_TIMER_CNTL__TimerCntl__SHIFT 0x1e1511#define ACP_DSP1_EXT_TIMER_CNTL__TimerCount_MASK 0xffffff1512#define ACP_DSP1_EXT_TIMER_CNTL__TimerCount__SHIFT 0x01513#define ACP_DSP1_EXT_TIMER_CNTL__TimerCntl_MASK 0xc00000001514#define ACP_DSP1_EXT_TIMER_CNTL__TimerCntl__SHIFT 0x1e1515#define ACP_DSP2_EXT_TIMER_CNTL__TimerCount_MASK 0xffffff1516#define ACP_DSP2_EXT_TIMER_CNTL__TimerCount__SHIFT 0x01517#define ACP_DSP2_EXT_TIMER_CNTL__TimerCntl_MASK 0xc00000001518#define ACP_DSP2_EXT_TIMER_CNTL__TimerCntl__SHIFT 0x1e1519#define ACP_AXI2DAGB_SEM_0__AXI2DAGBGblSemReg_MASK 0x11520#define ACP_AXI2DAGB_SEM_0__AXI2DAGBGblSemReg__SHIFT 0x01521#define ACP_AXI2DAGB_SEM_1__AXI2DAGBGblSemReg_MASK 0x11522#define ACP_AXI2DAGB_SEM_1__AXI2DAGBGblSemReg__SHIFT 0x01523#define ACP_AXI2DAGB_SEM_2__AXI2DAGBGblSemReg_MASK 0x11524#define ACP_AXI2DAGB_SEM_2__AXI2DAGBGblSemReg__SHIFT 0x01525#define ACP_AXI2DAGB_SEM_3__AXI2DAGBGblSemReg_MASK 0x11526#define ACP_AXI2DAGB_SEM_3__AXI2DAGBGblSemReg__SHIFT 0x01527#define ACP_AXI2DAGB_SEM_4__AXI2DAGBGblSemReg_MASK 0x11528#define ACP_AXI2DAGB_SEM_4__AXI2DAGBGblSemReg__SHIFT 0x01529#define ACP_AXI2DAGB_SEM_5__AXI2DAGBGblSemReg_MASK 0x11530#define ACP_AXI2DAGB_SEM_5__AXI2DAGBGblSemReg__SHIFT 0x01531#define ACP_AXI2DAGB_SEM_6__AXI2DAGBGblSemReg_MASK 0x11532#define ACP_AXI2DAGB_SEM_6__AXI2DAGBGblSemReg__SHIFT 0x01533#define ACP_AXI2DAGB_SEM_7__AXI2DAGBGblSemReg_MASK 0x11534#define ACP_AXI2DAGB_SEM_7__AXI2DAGBGblSemReg__SHIFT 0x01535#define ACP_AXI2DAGB_SEM_8__AXI2DAGBGblSemReg_MASK 0x11536#define ACP_AXI2DAGB_SEM_8__AXI2DAGBGblSemReg__SHIFT 0x01537#define ACP_AXI2DAGB_SEM_9__AXI2DAGBGblSemReg_MASK 0x11538#define ACP_AXI2DAGB_SEM_9__AXI2DAGBGblSemReg__SHIFT 0x01539#define ACP_AXI2DAGB_SEM_10__AXI2DAGBGblSemReg_MASK 0x11540#define ACP_AXI2DAGB_SEM_10__AXI2DAGBGblSemReg__SHIFT 0x01541#define ACP_AXI2DAGB_SEM_11__AXI2DAGBGblSemReg_MASK 0x11542#define ACP_AXI2DAGB_SEM_11__AXI2DAGBGblSemReg__SHIFT 0x01543#define ACP_AXI2DAGB_SEM_12__AXI2DAGBGblSemReg_MASK 0x11544#define ACP_AXI2DAGB_SEM_12__AXI2DAGBGblSemReg__SHIFT 0x01545#define ACP_AXI2DAGB_SEM_13__AXI2DAGBGblSemReg_MASK 0x11546#define ACP_AXI2DAGB_SEM_13__AXI2DAGBGblSemReg__SHIFT 0x01547#define ACP_AXI2DAGB_SEM_14__AXI2DAGBGblSemReg_MASK 0x11548#define ACP_AXI2DAGB_SEM_14__AXI2DAGBGblSemReg__SHIFT 0x01549#define ACP_AXI2DAGB_SEM_15__AXI2DAGBGblSemReg_MASK 0x11550#define ACP_AXI2DAGB_SEM_15__AXI2DAGBGblSemReg__SHIFT 0x01551#define ACP_AXI2DAGB_SEM_16__AXI2DAGBGblSemReg_MASK 0x11552#define ACP_AXI2DAGB_SEM_16__AXI2DAGBGblSemReg__SHIFT 0x01553#define ACP_AXI2DAGB_SEM_17__AXI2DAGBGblSemReg_MASK 0x11554#define ACP_AXI2DAGB_SEM_17__AXI2DAGBGblSemReg__SHIFT 0x01555#define ACP_AXI2DAGB_SEM_18__AXI2DAGBGblSemReg_MASK 0x11556#define ACP_AXI2DAGB_SEM_18__AXI2DAGBGblSemReg__SHIFT 0x01557#define ACP_AXI2DAGB_SEM_19__AXI2DAGBGblSemReg_MASK 0x11558#define ACP_AXI2DAGB_SEM_19__AXI2DAGBGblSemReg__SHIFT 0x01559#define ACP_AXI2DAGB_SEM_20__AXI2DAGBGblSemReg_MASK 0x11560#define ACP_AXI2DAGB_SEM_20__AXI2DAGBGblSemReg__SHIFT 0x01561#define ACP_AXI2DAGB_SEM_21__AXI2DAGBGblSemReg_MASK 0x11562#define ACP_AXI2DAGB_SEM_21__AXI2DAGBGblSemReg__SHIFT 0x01563#define ACP_AXI2DAGB_SEM_22__AXI2DAGBGblSemReg_MASK 0x11564#define ACP_AXI2DAGB_SEM_22__AXI2DAGBGblSemReg__SHIFT 0x01565#define ACP_AXI2DAGB_SEM_23__AXI2DAGBGblSemReg_MASK 0x11566#define ACP_AXI2DAGB_SEM_23__AXI2DAGBGblSemReg__SHIFT 0x01567#define ACP_AXI2DAGB_SEM_24__AXI2DAGBGblSemReg_MASK 0x11568#define ACP_AXI2DAGB_SEM_24__AXI2DAGBGblSemReg__SHIFT 0x01569#define ACP_AXI2DAGB_SEM_25__AXI2DAGBGblSemReg_MASK 0x11570#define ACP_AXI2DAGB_SEM_25__AXI2DAGBGblSemReg__SHIFT 0x01571#define ACP_AXI2DAGB_SEM_26__AXI2DAGBGblSemReg_MASK 0x11572#define ACP_AXI2DAGB_SEM_26__AXI2DAGBGblSemReg__SHIFT 0x01573#define ACP_AXI2DAGB_SEM_27__AXI2DAGBGblSemReg_MASK 0x11574#define ACP_AXI2DAGB_SEM_27__AXI2DAGBGblSemReg__SHIFT 0x01575#define ACP_AXI2DAGB_SEM_28__AXI2DAGBGblSemReg_MASK 0x11576#define ACP_AXI2DAGB_SEM_28__AXI2DAGBGblSemReg__SHIFT 0x01577#define ACP_AXI2DAGB_SEM_29__AXI2DAGBGblSemReg_MASK 0x11578#define ACP_AXI2DAGB_SEM_29__AXI2DAGBGblSemReg__SHIFT 0x01579#define ACP_AXI2DAGB_SEM_30__AXI2DAGBGblSemReg_MASK 0x11580#define ACP_AXI2DAGB_SEM_30__AXI2DAGBGblSemReg__SHIFT 0x01581#define ACP_AXI2DAGB_SEM_31__AXI2DAGBGblSemReg_MASK 0x11582#define ACP_AXI2DAGB_SEM_31__AXI2DAGBGblSemReg__SHIFT 0x01583#define ACP_AXI2DAGB_SEM_32__AXI2DAGBGblSemReg_MASK 0x11584#define ACP_AXI2DAGB_SEM_32__AXI2DAGBGblSemReg__SHIFT 0x01585#define ACP_AXI2DAGB_SEM_33__AXI2DAGBGblSemReg_MASK 0x11586#define ACP_AXI2DAGB_SEM_33__AXI2DAGBGblSemReg__SHIFT 0x01587#define ACP_AXI2DAGB_SEM_34__AXI2DAGBGblSemReg_MASK 0x11588#define ACP_AXI2DAGB_SEM_34__AXI2DAGBGblSemReg__SHIFT 0x01589#define ACP_AXI2DAGB_SEM_35__AXI2DAGBGblSemReg_MASK 0x11590#define ACP_AXI2DAGB_SEM_35__AXI2DAGBGblSemReg__SHIFT 0x01591#define ACP_AXI2DAGB_SEM_36__AXI2DAGBGblSemReg_MASK 0x11592#define ACP_AXI2DAGB_SEM_36__AXI2DAGBGblSemReg__SHIFT 0x01593#define ACP_AXI2DAGB_SEM_37__AXI2DAGBGblSemReg_MASK 0x11594#define ACP_AXI2DAGB_SEM_37__AXI2DAGBGblSemReg__SHIFT 0x01595#define ACP_AXI2DAGB_SEM_38__AXI2DAGBGblSemReg_MASK 0x11596#define ACP_AXI2DAGB_SEM_38__AXI2DAGBGblSemReg__SHIFT 0x01597#define ACP_AXI2DAGB_SEM_39__AXI2DAGBGblSemReg_MASK 0x11598#define ACP_AXI2DAGB_SEM_39__AXI2DAGBGblSemReg__SHIFT 0x01599#define ACP_AXI2DAGB_SEM_40__AXI2DAGBGblSemReg_MASK 0x11600#define ACP_AXI2DAGB_SEM_40__AXI2DAGBGblSemReg__SHIFT 0x01601#define ACP_AXI2DAGB_SEM_41__AXI2DAGBGblSemReg_MASK 0x11602#define ACP_AXI2DAGB_SEM_41__AXI2DAGBGblSemReg__SHIFT 0x01603#define ACP_AXI2DAGB_SEM_42__AXI2DAGBGblSemReg_MASK 0x11604#define ACP_AXI2DAGB_SEM_42__AXI2DAGBGblSemReg__SHIFT 0x01605#define ACP_AXI2DAGB_SEM_43__AXI2DAGBGblSemReg_MASK 0x11606#define ACP_AXI2DAGB_SEM_43__AXI2DAGBGblSemReg__SHIFT 0x01607#define ACP_AXI2DAGB_SEM_44__AXI2DAGBGblSemReg_MASK 0x11608#define ACP_AXI2DAGB_SEM_44__AXI2DAGBGblSemReg__SHIFT 0x01609#define ACP_AXI2DAGB_SEM_45__AXI2DAGBGblSemReg_MASK 0x11610#define ACP_AXI2DAGB_SEM_45__AXI2DAGBGblSemReg__SHIFT 0x01611#define ACP_AXI2DAGB_SEM_46__AXI2DAGBGblSemReg_MASK 0x11612#define ACP_AXI2DAGB_SEM_46__AXI2DAGBGblSemReg__SHIFT 0x01613#define ACP_AXI2DAGB_SEM_47__AXI2DAGBGblSemReg_MASK 0x11614#define ACP_AXI2DAGB_SEM_47__AXI2DAGBGblSemReg__SHIFT 0x01615#define ACP_SRBM_Client_Base_Addr__SRBM_Client_base_addr_MASK 0xff1616#define ACP_SRBM_Client_Base_Addr__SRBM_Client_base_addr__SHIFT 0x01617#define ACP_SRBM_Client_RDDATA__ReadData_MASK 0xffffffff1618#define ACP_SRBM_Client_RDDATA__ReadData__SHIFT 0x01619#define ACP_SRBM_Cycle_Sts__SRBM_Client_Sts_MASK 0x11620#define ACP_SRBM_Cycle_Sts__SRBM_Client_Sts__SHIFT 0x01621#define ACP_SRBM_Targ_Idx_Addr__SRBM_Targ_Idx_addr_MASK 0x7ffffff1622#define ACP_SRBM_Targ_Idx_Addr__SRBM_Targ_Idx_addr__SHIFT 0x01623#define ACP_SRBM_Targ_Idx_Data__SRBM_Targ_Idx_Data_MASK 0xffffffff1624#define ACP_SRBM_Targ_Idx_Data__SRBM_Targ_Idx_Data__SHIFT 0x01625#define ACP_SEMA_ADDR_LOW__ADDR_9_3_MASK 0x7f1626#define ACP_SEMA_ADDR_LOW__ADDR_9_3__SHIFT 0x01627#define ACP_SEMA_ADDR_HIGH__ADDR_39_10_MASK 0x3fffffff1628#define ACP_SEMA_ADDR_HIGH__ADDR_39_10__SHIFT 0x01629#define ACP_SEMA_CMD__REQ_CMD_MASK 0xf1630#define ACP_SEMA_CMD__REQ_CMD__SHIFT 0x01631#define ACP_SEMA_CMD__WR_PHASE_MASK 0x301632#define ACP_SEMA_CMD__WR_PHASE__SHIFT 0x41633#define ACP_SEMA_CMD__VMID_EN_MASK 0x801634#define ACP_SEMA_CMD__VMID_EN__SHIFT 0x71635#define ACP_SEMA_CMD__VMID_MASK 0xf001636#define ACP_SEMA_CMD__VMID__SHIFT 0x81637#define ACP_SEMA_CMD__ATC_MASK 0x10001638#define ACP_SEMA_CMD__ATC__SHIFT 0xc1639#define ACP_SEMA_STS__REQ_STS_MASK 0x31640#define ACP_SEMA_STS__REQ_STS__SHIFT 0x01641#define ACP_SEMA_STS__REQ_RESP_AVAIL_MASK 0x1001642#define ACP_SEMA_STS__REQ_RESP_AVAIL__SHIFT 0x81643#define ACP_SEMA_REQ__ISSUE_POLL_REQ_MASK 0x11644#define ACP_SEMA_REQ__ISSUE_POLL_REQ__SHIFT 0x01645#define ACP_FW_STATUS__RUN_MASK 0x11646#define ACP_FW_STATUS__RUN__SHIFT 0x01647#define ACP_FUTURE_REG_ACLK_0__ACPFutureReg_MASK 0xffffffff1648#define ACP_FUTURE_REG_ACLK_0__ACPFutureReg__SHIFT 0x01649#define ACP_FUTURE_REG_ACLK_1__ACPFutureReg_MASK 0xffffffff1650#define ACP_FUTURE_REG_ACLK_1__ACPFutureReg__SHIFT 0x01651#define ACP_FUTURE_REG_ACLK_2__ACPFutureReg_MASK 0xffffffff1652#define ACP_FUTURE_REG_ACLK_2__ACPFutureReg__SHIFT 0x01653#define ACP_FUTURE_REG_ACLK_3__ACPFutureReg_MASK 0xffffffff1654#define ACP_FUTURE_REG_ACLK_3__ACPFutureReg__SHIFT 0x01655#define ACP_FUTURE_REG_ACLK_4__ACPFutureReg_MASK 0xffffffff1656#define ACP_FUTURE_REG_ACLK_4__ACPFutureReg__SHIFT 0x01657#define ACP_TIMER__ACP_Timer_count_MASK 0xffffffff1658#define ACP_TIMER__ACP_Timer_count__SHIFT 0x01659#define ACP_TIMER_CNTL__ACP_Timer_control_MASK 0x11660#define ACP_TIMER_CNTL__ACP_Timer_control__SHIFT 0x01661#define ACP_DSP0_TIMER__ACP_DSP0_timer_MASK 0xffffff1662#define ACP_DSP0_TIMER__ACP_DSP0_timer__SHIFT 0x01663#define ACP_DSP1_TIMER__ACP_DSP1_timer_MASK 0xffffff1664#define ACP_DSP1_TIMER__ACP_DSP1_timer__SHIFT 0x01665#define ACP_DSP2_TIMER__ACP_DSP2_timer_MASK 0xffffff1666#define ACP_DSP2_TIMER__ACP_DSP2_timer__SHIFT 0x01667#define ACP_I2S_TRANSMIT_BYTE_CNT_HIGH__i2s_sp_tx_byte_cnt_high_MASK 0xffffffff1668#define ACP_I2S_TRANSMIT_BYTE_CNT_HIGH__i2s_sp_tx_byte_cnt_high__SHIFT 0x01669#define ACP_I2S_TRANSMIT_BYTE_CNT_LOW__i2s_sp_tx_byte_cnt_low_MASK 0xffffffff1670#define ACP_I2S_TRANSMIT_BYTE_CNT_LOW__i2s_sp_tx_byte_cnt_low__SHIFT 0x01671#define ACP_I2S_BT_TRANSMIT_BYTE_CNT_HIGH__i2s_bt_tx_byte_cnt_high_MASK 0xffffffff1672#define ACP_I2S_BT_TRANSMIT_BYTE_CNT_HIGH__i2s_bt_tx_byte_cnt_high__SHIFT 0x01673#define ACP_I2S_BT_TRANSMIT_BYTE_CNT_LOW__i2s_bt_tx_byte_cnt_low_MASK 0xffffffff1674#define ACP_I2S_BT_TRANSMIT_BYTE_CNT_LOW__i2s_bt_tx_byte_cnt_low__SHIFT 0x01675#define ACP_I2S_BT_RECEIVE_BYTE_CNT_HIGH__i2s_bt_rx_byte_cnt_high_MASK 0xffffffff1676#define ACP_I2S_BT_RECEIVE_BYTE_CNT_HIGH__i2s_bt_rx_byte_cnt_high__SHIFT 0x01677#define ACP_I2S_BT_RECEIVE_BYTE_CNT_LOW__i2s_bt_rx_byte_cnt_low_MASK 0xffffffff1678#define ACP_I2S_BT_RECEIVE_BYTE_CNT_LOW__i2s_bt_rx_byte_cnt_low__SHIFT 0x01679#define ACP_DSP0_CS_STATE__DSP0_CS_state_MASK 0x11680#define ACP_DSP0_CS_STATE__DSP0_CS_state__SHIFT 0x01681#define ACP_DSP1_CS_STATE__DSP1_CS_state_MASK 0x11682#define ACP_DSP1_CS_STATE__DSP1_CS_state__SHIFT 0x01683#define ACP_DSP2_CS_STATE__DSP2_CS_state_MASK 0x11684#define ACP_DSP2_CS_STATE__DSP2_CS_state__SHIFT 0x01685#define ACP_SCRATCH_REG_BASE_ADDR__SCRATCH_REG_BASE_ADDR_MASK 0x7ffff1686#define ACP_SCRATCH_REG_BASE_ADDR__SCRATCH_REG_BASE_ADDR__SHIFT 0x01687#define CC_ACP_EFUSE__DSP0_DISABLE_MASK 0x21688#define CC_ACP_EFUSE__DSP0_DISABLE__SHIFT 0x11689#define CC_ACP_EFUSE__DSP1_DISABLE_MASK 0x41690#define CC_ACP_EFUSE__DSP1_DISABLE__SHIFT 0x21691#define CC_ACP_EFUSE__DSP2_DISABLE_MASK 0x81692#define CC_ACP_EFUSE__DSP2_DISABLE__SHIFT 0x31693#define CC_ACP_EFUSE__ACP_DISABLE_MASK 0x101694#define CC_ACP_EFUSE__ACP_DISABLE__SHIFT 0x41695#define ACP_PGFSM_RETAIN_REG__ACP_P1_ON_OFF_MASK 0x11696#define ACP_PGFSM_RETAIN_REG__ACP_P1_ON_OFF__SHIFT 0x01697#define ACP_PGFSM_RETAIN_REG__ACP_P2_ON_OFF_MASK 0x21698#define ACP_PGFSM_RETAIN_REG__ACP_P2_ON_OFF__SHIFT 0x11699#define ACP_PGFSM_RETAIN_REG__ACP_DSP0_ON_OFF_MASK 0x41700#define ACP_PGFSM_RETAIN_REG__ACP_DSP0_ON_OFF__SHIFT 0x21701#define ACP_PGFSM_RETAIN_REG__ACP_DSP1_ON_OFF_MASK 0x81702#define ACP_PGFSM_RETAIN_REG__ACP_DSP1_ON_OFF__SHIFT 0x31703#define ACP_PGFSM_RETAIN_REG__ACP_DSP2_ON_OFF_MASK 0x101704#define ACP_PGFSM_RETAIN_REG__ACP_DSP2_ON_OFF__SHIFT 0x41705#define ACP_PGFSM_RETAIN_REG__ACP_AZ_ON_OFF_MASK 0x201706#define ACP_PGFSM_RETAIN_REG__ACP_AZ_ON_OFF__SHIFT 0x51707#define ACP_PGFSM_CONFIG_REG__FSM_ADDR_MASK 0xff1708#define ACP_PGFSM_CONFIG_REG__FSM_ADDR__SHIFT 0x01709#define ACP_PGFSM_CONFIG_REG__Power_Down_MASK 0x1001710#define ACP_PGFSM_CONFIG_REG__Power_Down__SHIFT 0x81711#define ACP_PGFSM_CONFIG_REG__Power_Up_MASK 0x2001712#define ACP_PGFSM_CONFIG_REG__Power_Up__SHIFT 0x91713#define ACP_PGFSM_CONFIG_REG__P1_Select_MASK 0x4001714#define ACP_PGFSM_CONFIG_REG__P1_Select__SHIFT 0xa1715#define ACP_PGFSM_CONFIG_REG__P2_Select_MASK 0x8001716#define ACP_PGFSM_CONFIG_REG__P2_Select__SHIFT 0xb1717#define ACP_PGFSM_CONFIG_REG__Wr_MASK 0x10001718#define ACP_PGFSM_CONFIG_REG__Wr__SHIFT 0xc1719#define ACP_PGFSM_CONFIG_REG__Rd_MASK 0x20001720#define ACP_PGFSM_CONFIG_REG__Rd__SHIFT 0xd1721#define ACP_PGFSM_CONFIG_REG__RdData_Reset_MASK 0x40001722#define ACP_PGFSM_CONFIG_REG__RdData_Reset__SHIFT 0xe1723#define ACP_PGFSM_CONFIG_REG__Short_Format_MASK 0x80001724#define ACP_PGFSM_CONFIG_REG__Short_Format__SHIFT 0xf1725#define ACP_PGFSM_CONFIG_REG__BPM_CG_MG_FGCG_MASK 0x3ff00001726#define ACP_PGFSM_CONFIG_REG__BPM_CG_MG_FGCG__SHIFT 0x101727#define ACP_PGFSM_CONFIG_REG__SRBM_override_MASK 0x40000001728#define ACP_PGFSM_CONFIG_REG__SRBM_override__SHIFT 0x1a1729#define ACP_PGFSM_CONFIG_REG__Rsvd_BPM_Addr_MASK 0x80000001730#define ACP_PGFSM_CONFIG_REG__Rsvd_BPM_Addr__SHIFT 0x1b1731#define ACP_PGFSM_CONFIG_REG__REG_ADDR_MASK 0xf00000001732#define ACP_PGFSM_CONFIG_REG__REG_ADDR__SHIFT 0x1c1733#define ACP_PGFSM_WRITE_REG__Write_value_MASK 0xffffffff1734#define ACP_PGFSM_WRITE_REG__Write_value__SHIFT 0x01735#define ACP_PGFSM_READ_REG_0__Read_value_MASK 0xffffff1736#define ACP_PGFSM_READ_REG_0__Read_value__SHIFT 0x01737#define ACP_PGFSM_READ_REG_1__Read_value_MASK 0xffffff1738#define ACP_PGFSM_READ_REG_1__Read_value__SHIFT 0x01739#define ACP_PGFSM_READ_REG_2__Read_value_MASK 0xffffff1740#define ACP_PGFSM_READ_REG_2__Read_value__SHIFT 0x01741#define ACP_PGFSM_READ_REG_3__Read_value_MASK 0xffffff1742#define ACP_PGFSM_READ_REG_3__Read_value__SHIFT 0x01743#define ACP_PGFSM_READ_REG_4__Read_value_MASK 0xffffff1744#define ACP_PGFSM_READ_REG_4__Read_value__SHIFT 0x01745#define ACP_PGFSM_READ_REG_5__Read_value_MASK 0xffffff1746#define ACP_PGFSM_READ_REG_5__Read_value__SHIFT 0x01747#define ACP_IP_PGFSM_ENABLE__ACP_IP_ACCESS_MASK 0x11748#define ACP_IP_PGFSM_ENABLE__ACP_IP_ACCESS__SHIFT 0x01749#define ACP_I2S_PIN_CONFIG__ACP_I2S_PIN_CONFIG_MASK 0x31750#define ACP_I2S_PIN_CONFIG__ACP_I2S_PIN_CONFIG__SHIFT 0x01751#define ACP_AZALIA_I2S_SELECT__AZ_I2S_SELECT_MASK 0x11752#define ACP_AZALIA_I2S_SELECT__AZ_I2S_SELECT__SHIFT 0x01753#define ACP_CHIP_PKG_FOR_PAD_ISOLATION__external_fch_package_MASK 0x11754#define ACP_CHIP_PKG_FOR_PAD_ISOLATION__external_fch_package__SHIFT 0x01755#define ACP_AUDIO_PAD_PULLUP_PULLDOWN_CTRL__ACP_AUDIO_PAD_pullup_disable_MASK 0x7ff1756#define ACP_AUDIO_PAD_PULLUP_PULLDOWN_CTRL__ACP_AUDIO_PAD_pullup_disable__SHIFT 0x01757#define ACP_AUDIO_PAD_PULLUP_PULLDOWN_CTRL__ACP_AUDIO_PAD_pulldown_enable_MASK 0x7ff00001758#define ACP_AUDIO_PAD_PULLUP_PULLDOWN_CTRL__ACP_AUDIO_PAD_pulldown_enable__SHIFT 0x101759#define ACP_BT_UART_PAD_SEL__ACP_BT_UART_PAD_SEL_MASK 0x11760#define ACP_BT_UART_PAD_SEL__ACP_BT_UART_PAD_SEL__SHIFT 0x01761#define ACP_SCRATCH_REG_0__ACP_SCRATCH_REG_MASK 0xffffffff1762#define ACP_SCRATCH_REG_0__ACP_SCRATCH_REG__SHIFT 0x01763#define ACP_SCRATCH_REG_1__ACP_SCRATCH_REG_MASK 0xffffffff1764#define ACP_SCRATCH_REG_1__ACP_SCRATCH_REG__SHIFT 0x01765#define ACP_SCRATCH_REG_2__ACP_SCRATCH_REG_MASK 0xffffffff1766#define ACP_SCRATCH_REG_2__ACP_SCRATCH_REG__SHIFT 0x01767#define ACP_SCRATCH_REG_3__ACP_SCRATCH_REG_MASK 0xffffffff1768#define ACP_SCRATCH_REG_3__ACP_SCRATCH_REG__SHIFT 0x01769#define ACP_SCRATCH_REG_4__ACP_SCRATCH_REG_MASK 0xffffffff1770#define ACP_SCRATCH_REG_4__ACP_SCRATCH_REG__SHIFT 0x01771#define ACP_SCRATCH_REG_5__ACP_SCRATCH_REG_MASK 0xffffffff1772#define ACP_SCRATCH_REG_5__ACP_SCRATCH_REG__SHIFT 0x01773#define ACP_SCRATCH_REG_6__ACP_SCRATCH_REG_MASK 0xffffffff1774#define ACP_SCRATCH_REG_6__ACP_SCRATCH_REG__SHIFT 0x01775#define ACP_SCRATCH_REG_7__ACP_SCRATCH_REG_MASK 0xffffffff1776#define ACP_SCRATCH_REG_7__ACP_SCRATCH_REG__SHIFT 0x01777#define ACP_SCRATCH_REG_8__ACP_SCRATCH_REG_MASK 0xffffffff1778#define ACP_SCRATCH_REG_8__ACP_SCRATCH_REG__SHIFT 0x01779#define ACP_SCRATCH_REG_9__ACP_SCRATCH_REG_MASK 0xffffffff1780#define ACP_SCRATCH_REG_9__ACP_SCRATCH_REG__SHIFT 0x01781#define ACP_SCRATCH_REG_10__ACP_SCRATCH_REG_MASK 0xffffffff1782#define ACP_SCRATCH_REG_10__ACP_SCRATCH_REG__SHIFT 0x01783#define ACP_SCRATCH_REG_11__ACP_SCRATCH_REG_MASK 0xffffffff1784#define ACP_SCRATCH_REG_11__ACP_SCRATCH_REG__SHIFT 0x01785#define ACP_SCRATCH_REG_12__ACP_SCRATCH_REG_MASK 0xffffffff1786#define ACP_SCRATCH_REG_12__ACP_SCRATCH_REG__SHIFT 0x01787#define ACP_SCRATCH_REG_13__ACP_SCRATCH_REG_MASK 0xffffffff1788#define ACP_SCRATCH_REG_13__ACP_SCRATCH_REG__SHIFT 0x01789#define ACP_SCRATCH_REG_14__ACP_SCRATCH_REG_MASK 0xffffffff1790#define ACP_SCRATCH_REG_14__ACP_SCRATCH_REG__SHIFT 0x01791#define ACP_SCRATCH_REG_15__ACP_SCRATCH_REG_MASK 0xffffffff1792#define ACP_SCRATCH_REG_15__ACP_SCRATCH_REG__SHIFT 0x01793#define ACP_SCRATCH_REG_16__ACP_SCRATCH_REG_MASK 0xffffffff1794#define ACP_SCRATCH_REG_16__ACP_SCRATCH_REG__SHIFT 0x01795#define ACP_SCRATCH_REG_17__ACP_SCRATCH_REG_MASK 0xffffffff1796#define ACP_SCRATCH_REG_17__ACP_SCRATCH_REG__SHIFT 0x01797#define ACP_SCRATCH_REG_18__ACP_SCRATCH_REG_MASK 0xffffffff1798#define ACP_SCRATCH_REG_18__ACP_SCRATCH_REG__SHIFT 0x01799#define ACP_SCRATCH_REG_19__ACP_SCRATCH_REG_MASK 0xffffffff1800#define ACP_SCRATCH_REG_19__ACP_SCRATCH_REG__SHIFT 0x01801#define ACP_SCRATCH_REG_20__ACP_SCRATCH_REG_MASK 0xffffffff1802#define ACP_SCRATCH_REG_20__ACP_SCRATCH_REG__SHIFT 0x01803#define ACP_SCRATCH_REG_21__ACP_SCRATCH_REG_MASK 0xffffffff1804#define ACP_SCRATCH_REG_21__ACP_SCRATCH_REG__SHIFT 0x01805#define ACP_SCRATCH_REG_22__ACP_SCRATCH_REG_MASK 0xffffffff1806#define ACP_SCRATCH_REG_22__ACP_SCRATCH_REG__SHIFT 0x01807#define ACP_SCRATCH_REG_23__ACP_SCRATCH_REG_MASK 0xffffffff1808#define ACP_SCRATCH_REG_23__ACP_SCRATCH_REG__SHIFT 0x01809#define ACP_SCRATCH_REG_24__ACP_SCRATCH_REG_MASK 0xffffffff1810#define ACP_SCRATCH_REG_24__ACP_SCRATCH_REG__SHIFT 0x01811#define ACP_SCRATCH_REG_25__ACP_SCRATCH_REG_MASK 0xffffffff1812#define ACP_SCRATCH_REG_25__ACP_SCRATCH_REG__SHIFT 0x01813#define ACP_SCRATCH_REG_26__ACP_SCRATCH_REG_MASK 0xffffffff1814#define ACP_SCRATCH_REG_26__ACP_SCRATCH_REG__SHIFT 0x01815#define ACP_SCRATCH_REG_27__ACP_SCRATCH_REG_MASK 0xffffffff1816#define ACP_SCRATCH_REG_27__ACP_SCRATCH_REG__SHIFT 0x01817#define ACP_SCRATCH_REG_28__ACP_SCRATCH_REG_MASK 0xffffffff1818#define ACP_SCRATCH_REG_28__ACP_SCRATCH_REG__SHIFT 0x01819#define ACP_SCRATCH_REG_29__ACP_SCRATCH_REG_MASK 0xffffffff1820#define ACP_SCRATCH_REG_29__ACP_SCRATCH_REG__SHIFT 0x01821#define ACP_SCRATCH_REG_30__ACP_SCRATCH_REG_MASK 0xffffffff1822#define ACP_SCRATCH_REG_30__ACP_SCRATCH_REG__SHIFT 0x01823#define ACP_SCRATCH_REG_31__ACP_SCRATCH_REG_MASK 0xffffffff1824#define ACP_SCRATCH_REG_31__ACP_SCRATCH_REG__SHIFT 0x01825#define ACP_SCRATCH_REG_32__ACP_SCRATCH_REG_MASK 0xffffffff1826#define ACP_SCRATCH_REG_32__ACP_SCRATCH_REG__SHIFT 0x01827#define ACP_SCRATCH_REG_33__ACP_SCRATCH_REG_MASK 0xffffffff1828#define ACP_SCRATCH_REG_33__ACP_SCRATCH_REG__SHIFT 0x01829#define ACP_SCRATCH_REG_34__ACP_SCRATCH_REG_MASK 0xffffffff1830#define ACP_SCRATCH_REG_34__ACP_SCRATCH_REG__SHIFT 0x01831#define ACP_SCRATCH_REG_35__ACP_SCRATCH_REG_MASK 0xffffffff1832#define ACP_SCRATCH_REG_35__ACP_SCRATCH_REG__SHIFT 0x01833#define ACP_SCRATCH_REG_36__ACP_SCRATCH_REG_MASK 0xffffffff1834#define ACP_SCRATCH_REG_36__ACP_SCRATCH_REG__SHIFT 0x01835#define ACP_SCRATCH_REG_37__ACP_SCRATCH_REG_MASK 0xffffffff1836#define ACP_SCRATCH_REG_37__ACP_SCRATCH_REG__SHIFT 0x01837#define ACP_SCRATCH_REG_38__ACP_SCRATCH_REG_MASK 0xffffffff1838#define ACP_SCRATCH_REG_38__ACP_SCRATCH_REG__SHIFT 0x01839#define ACP_SCRATCH_REG_39__ACP_SCRATCH_REG_MASK 0xffffffff1840#define ACP_SCRATCH_REG_39__ACP_SCRATCH_REG__SHIFT 0x01841#define ACP_SCRATCH_REG_40__ACP_SCRATCH_REG_MASK 0xffffffff1842#define ACP_SCRATCH_REG_40__ACP_SCRATCH_REG__SHIFT 0x01843#define ACP_SCRATCH_REG_41__ACP_SCRATCH_REG_MASK 0xffffffff1844#define ACP_SCRATCH_REG_41__ACP_SCRATCH_REG__SHIFT 0x01845#define ACP_SCRATCH_REG_42__ACP_SCRATCH_REG_MASK 0xffffffff1846#define ACP_SCRATCH_REG_42__ACP_SCRATCH_REG__SHIFT 0x01847#define ACP_SCRATCH_REG_43__ACP_SCRATCH_REG_MASK 0xffffffff1848#define ACP_SCRATCH_REG_43__ACP_SCRATCH_REG__SHIFT 0x01849#define ACP_SCRATCH_REG_44__ACP_SCRATCH_REG_MASK 0xffffffff1850#define ACP_SCRATCH_REG_44__ACP_SCRATCH_REG__SHIFT 0x01851#define ACP_SCRATCH_REG_45__ACP_SCRATCH_REG_MASK 0xffffffff1852#define ACP_SCRATCH_REG_45__ACP_SCRATCH_REG__SHIFT 0x01853#define ACP_SCRATCH_REG_46__ACP_SCRATCH_REG_MASK 0xffffffff1854#define ACP_SCRATCH_REG_46__ACP_SCRATCH_REG__SHIFT 0x01855#define ACP_SCRATCH_REG_47__ACP_SCRATCH_REG_MASK 0xffffffff1856#define ACP_SCRATCH_REG_47__ACP_SCRATCH_REG__SHIFT 0x01857#define ACP_VOICE_WAKEUP_ENABLE__voice_wakeup_enable_MASK 0x11858#define ACP_VOICE_WAKEUP_ENABLE__voice_wakeup_enable__SHIFT 0x01859#define ACP_VOICE_WAKEUP_STATUS__voice_wakeup_status_MASK 0x11860#define ACP_VOICE_WAKEUP_STATUS__voice_wakeup_status__SHIFT 0x01861#define I2S_VOICE_WAKEUP_LOWER_THRESHOLD__i2s_voice_wakeup_lower_threshold_MASK 0xffffffff1862#define I2S_VOICE_WAKEUP_LOWER_THRESHOLD__i2s_voice_wakeup_lower_threshold__SHIFT 0x01863#define I2S_VOICE_WAKEUP_HIGHER_THRESHOLD__i2s_voice_wakeup_higher_threshold_MASK 0xffffffff1864#define I2S_VOICE_WAKEUP_HIGHER_THRESHOLD__i2s_voice_wakeup_higher_threshold__SHIFT 0x01865#define I2S_VOICE_WAKEUP_NO_OF_SAMPLES__i2s_voice_wakeup_no_of_samples_MASK 0xffff1866#define I2S_VOICE_WAKEUP_NO_OF_SAMPLES__i2s_voice_wakeup_no_of_samples__SHIFT 0x01867#define I2S_VOICE_WAKEUP_NO_OF_PEAKS__i2s_voice_wakeup_no_of_peaks_MASK 0xffff1868#define I2S_VOICE_WAKEUP_NO_OF_PEAKS__i2s_voice_wakeup_no_of_peaks__SHIFT 0x01869#define I2S_VOICE_WAKEUP_DURATION_OF_N_PEAKS__i2s_voice_wakeup_duration_of_n_peaks_MASK 0xffffffff1870#define I2S_VOICE_WAKEUP_DURATION_OF_N_PEAKS__i2s_voice_wakeup_duration_of_n_peaks__SHIFT 0x01871#define I2S_VOICE_WAKEUP_BITCLK_TOGGLE_DETECTION__i2s_voice_wakeup_bitclk_toggle_wakeup_en_MASK 0x11872#define I2S_VOICE_WAKEUP_BITCLK_TOGGLE_DETECTION__i2s_voice_wakeup_bitclk_toggle_wakeup_en__SHIFT 0x01873#define I2S_VOICE_WAKEUP_DATA_PATH_SWITCH__i2s_voice_wakeup_data_path_switch_req_MASK 0x11874#define I2S_VOICE_WAKEUP_DATA_PATH_SWITCH__i2s_voice_wakeup_data_path_switch_req__SHIFT 0x01875#define I2S_VOICE_WAKEUP_DATA_PATH_SWITCH__i2s_voice_wakeup_data_path_switch_ack_MASK 0x21876#define I2S_VOICE_WAKEUP_DATA_PATH_SWITCH__i2s_voice_wakeup_data_path_switch_ack__SHIFT 0x11877#define I2S_VOICE_WAKEUP_DATA_POINTER__i2s_voice_wakeup_data_pointer_MASK 0xffffffff1878#define I2S_VOICE_WAKEUP_DATA_POINTER__i2s_voice_wakeup_data_pointer__SHIFT 0x01879#define I2S_VOICE_WAKEUP_AUTH_MATCH__i2s_voice_wakeup_authentication_valid_MASK 0x11880#define I2S_VOICE_WAKEUP_AUTH_MATCH__i2s_voice_wakeup_authentication_valid__SHIFT 0x01881#define I2S_VOICE_WAKEUP_AUTH_MATCH__i2s_voice_wakeup_authentication_match_MASK 0x21882#define I2S_VOICE_WAKEUP_AUTH_MATCH__i2s_voice_wakeup_authentication_match__SHIFT 0x11883#define I2S_VOICE_WAKEUP_8KB_WRAP__i2s_voice_wakeup_8kb_wrap_MASK 0x11884#define I2S_VOICE_WAKEUP_8KB_WRAP__i2s_voice_wakeup_8kb_wrap__SHIFT 0x01885#define ACP_I2S_RECEIVED_BYTE_CNT_HIGH__i2s_mic_rx_byte_cnt_high_MASK 0xffffffff1886#define ACP_I2S_RECEIVED_BYTE_CNT_HIGH__i2s_mic_rx_byte_cnt_high__SHIFT 0x01887#define ACP_I2S_RECEIVED_BYTE_CNT_LOW__i2s_mic_rx_byte_cnt_low_MASK 0xffffffff1888#define ACP_I2S_RECEIVED_BYTE_CNT_LOW__i2s_mic_rx_byte_cnt_low__SHIFT 0x01889#define ACP_I2S_MICSP_TRANSMIT_BYTE_CNT_HIGH__i2s_micsp_tx_byte_cnt_high_MASK 0xffffffff1890#define ACP_I2S_MICSP_TRANSMIT_BYTE_CNT_HIGH__i2s_micsp_tx_byte_cnt_high__SHIFT 0x01891#define ACP_I2S_MICSP_TRANSMIT_BYTE_CNT_LOW__i2s_micsp_tx_byte_cnt_low_MASK 0xffffffff1892#define ACP_I2S_MICSP_TRANSMIT_BYTE_CNT_LOW__i2s_micsp_tx_byte_cnt_low__SHIFT 0x01893#define ACP_MEM_SHUT_DOWN_REQ_LO__ACP_ShutDownReq_RAML_MASK 0xffffffff1894#define ACP_MEM_SHUT_DOWN_REQ_LO__ACP_ShutDownReq_RAML__SHIFT 0x01895#define ACP_MEM_SHUT_DOWN_REQ_HI__ACP_ShutDownReq_RAMH_MASK 0xffff1896#define ACP_MEM_SHUT_DOWN_REQ_HI__ACP_ShutDownReq_RAMH__SHIFT 0x01897#define ACP_MEM_SHUT_DOWN_STS_LO__ACP_ShutDownSts_RAML_MASK 0xffffffff1898#define ACP_MEM_SHUT_DOWN_STS_LO__ACP_ShutDownSts_RAML__SHIFT 0x01899#define ACP_MEM_SHUT_DOWN_STS_HI__ACP_ShutDownSts_RAMH_MASK 0xffff1900#define ACP_MEM_SHUT_DOWN_STS_HI__ACP_ShutDownSts_RAMH__SHIFT 0x01901#define ACP_MEM_DEEP_SLEEP_REQ_LO__ACP_DeepSleepReq_RAML_MASK 0xffffffff1902#define ACP_MEM_DEEP_SLEEP_REQ_LO__ACP_DeepSleepReq_RAML__SHIFT 0x01903#define ACP_MEM_DEEP_SLEEP_REQ_HI__ACP_DeepSleepReq_RAMH_MASK 0xffff1904#define ACP_MEM_DEEP_SLEEP_REQ_HI__ACP_DeepSleepReq_RAMH__SHIFT 0x01905#define ACP_MEM_DEEP_SLEEP_STS_LO__ACP_DeepSleepSts_RAML_MASK 0xffffffff1906#define ACP_MEM_DEEP_SLEEP_STS_LO__ACP_DeepSleepSts_RAML__SHIFT 0x01907#define ACP_MEM_DEEP_SLEEP_STS_HI__ACP_DeepSleepSts_RAMH_MASK 0xffff1908#define ACP_MEM_DEEP_SLEEP_STS_HI__ACP_DeepSleepSts_RAMH__SHIFT 0x01909#define ACP_MEM_WAKEUP_FROM_SHUT_DOWN_LO__acp_mem_wakeup_from_shut_down_lo_MASK 0xffffffff1910#define ACP_MEM_WAKEUP_FROM_SHUT_DOWN_LO__acp_mem_wakeup_from_shut_down_lo__SHIFT 0x01911#define ACP_MEM_WAKEUP_FROM_SHUT_DOWN_HI__acp_mem_wakeup_from_shut_down_hi_MASK 0xffff1912#define ACP_MEM_WAKEUP_FROM_SHUT_DOWN_HI__acp_mem_wakeup_from_shut_down_hi__SHIFT 0x01913#define ACP_MEM_WAKEUP_FROM_SLEEP_LO__acp_mem_wakeup_from_sleep_lo_MASK 0xffffffff1914#define ACP_MEM_WAKEUP_FROM_SLEEP_LO__acp_mem_wakeup_from_sleep_lo__SHIFT 0x01915#define ACP_MEM_WAKEUP_FROM_SLEEP_HI__acp_mem_wakeup_from_sleep_hi_MASK 0xffff1916#define ACP_MEM_WAKEUP_FROM_SLEEP_HI__acp_mem_wakeup_from_sleep_hi__SHIFT 0x01917#define ACP_I2SSP_IER__I2SSP_IEN_MASK 0x11918#define ACP_I2SSP_IER__I2SSP_IEN__SHIFT 0x01919#define ACP_I2SSP_IRER__I2SSP_RXEN_MASK 0x11920#define ACP_I2SSP_IRER__I2SSP_RXEN__SHIFT 0x01921#define ACP_I2SSP_ITER__I2SSP_TXEN_MASK 0x11922#define ACP_I2SSP_ITER__I2SSP_TXEN__SHIFT 0x01923#define ACP_I2SSP_CER__I2SSP_CLKEN_MASK 0x11924#define ACP_I2SSP_CER__I2SSP_CLKEN__SHIFT 0x01925#define ACP_I2SSP_CCR__I2SSP_SCLKG_MASK 0x71926#define ACP_I2SSP_CCR__I2SSP_SCLKG__SHIFT 0x01927#define ACP_I2SSP_CCR__I2SSP_WSS_MASK 0x181928#define ACP_I2SSP_CCR__I2SSP_WSS__SHIFT 0x31929#define ACP_I2SSP_RXFFR__I2SSP_RXFFR_MASK 0x11930#define ACP_I2SSP_RXFFR__I2SSP_RXFFR__SHIFT 0x01931#define ACP_I2SSP_TXFFR__I2SSP_TXFFR_MASK 0x11932#define ACP_I2SSP_TXFFR__I2SSP_TXFFR__SHIFT 0x01933#define ACP_I2SSP_LRBR0__I2SSP_LRBR0_MASK 0xffffffff1934#define ACP_I2SSP_LRBR0__I2SSP_LRBR0__SHIFT 0x01935#define ACP_I2SSP_RRBR0__I2SSP_RRBR0_MASK 0xffffffff1936#define ACP_I2SSP_RRBR0__I2SSP_RRBR0__SHIFT 0x01937#define ACP_I2SSP_RER0__I2SSP_RXCHEN0_MASK 0x11938#define ACP_I2SSP_RER0__I2SSP_RXCHEN0__SHIFT 0x01939#define ACP_I2SSP_TER0__I2SSP_TXCHEN0_MASK 0x11940#define ACP_I2SSP_TER0__I2SSP_TXCHEN0__SHIFT 0x01941#define ACP_I2SSP_RCR0__I2SSP_WLEN_MASK 0x71942#define ACP_I2SSP_RCR0__I2SSP_WLEN__SHIFT 0x01943#define ACP_I2SSP_TCR0__I2SSP_WLEN_MASK 0x71944#define ACP_I2SSP_TCR0__I2SSP_WLEN__SHIFT 0x01945#define ACP_I2SSP_ISR0__I2SSP_RXDA_MASK 0x11946#define ACP_I2SSP_ISR0__I2SSP_RXDA__SHIFT 0x01947#define ACP_I2SSP_ISR0__I2SSP_RXFO_MASK 0x21948#define ACP_I2SSP_ISR0__I2SSP_RXFO__SHIFT 0x11949#define ACP_I2SSP_ISR0__I2SSP_TXFE_MASK 0x101950#define ACP_I2SSP_ISR0__I2SSP_TXFE__SHIFT 0x41951#define ACP_I2SSP_ISR0__I2SSP_TXFO_MASK 0x201952#define ACP_I2SSP_ISR0__I2SSP_TXFO__SHIFT 0x51953#define ACP_I2SSP_IMR0__I2SSP_RXDAM_MASK 0x11954#define ACP_I2SSP_IMR0__I2SSP_RXDAM__SHIFT 0x01955#define ACP_I2SSP_IMR0__I2SSP_RXFOM_MASK 0x21956#define ACP_I2SSP_IMR0__I2SSP_RXFOM__SHIFT 0x11957#define ACP_I2SSP_IMR0__I2SSP_TXFEM_MASK 0x101958#define ACP_I2SSP_IMR0__I2SSP_TXFEM__SHIFT 0x41959#define ACP_I2SSP_IMR0__I2SSP_TXFOM_MASK 0x201960#define ACP_I2SSP_IMR0__I2SSP_TXFOM__SHIFT 0x51961#define ACP_I2SSP_ROR0__I2SSP_RXCHO_MASK 0x11962#define ACP_I2SSP_ROR0__I2SSP_RXCHO__SHIFT 0x01963#define ACP_I2SSP_TOR0__I2SSP_TXCHO_MASK 0x11964#define ACP_I2SSP_TOR0__I2SSP_TXCHO__SHIFT 0x01965#define ACP_I2SSP_RFCR0__I2SSP_RXCHDT_MASK 0xf1966#define ACP_I2SSP_RFCR0__I2SSP_RXCHDT__SHIFT 0x01967#define ACP_I2SSP_TFCR0__I2SSP_TXCHET_MASK 0xf1968#define ACP_I2SSP_TFCR0__I2SSP_TXCHET__SHIFT 0x01969#define ACP_I2SSP_RFF0__I2SSP_RXCHFR_MASK 0x11970#define ACP_I2SSP_RFF0__I2SSP_RXCHFR__SHIFT 0x01971#define ACP_I2SSP_TFF0__I2SSP_TXCHFR_MASK 0x11972#define ACP_I2SSP_TFF0__I2SSP_TXCHFR__SHIFT 0x01973#define ACP_I2SSP_RXDMA__I2SSP_RXDMA_MASK 0xffffffff1974#define ACP_I2SSP_RXDMA__I2SSP_RXDMA__SHIFT 0x01975#define ACP_I2SSP_RRXDMA__I2SSP_RRXDMA_MASK 0x11976#define ACP_I2SSP_RRXDMA__I2SSP_RRXDMA__SHIFT 0x01977#define ACP_I2SSP_TXDMA__I2SSP_TXDMA_MASK 0xffffffff1978#define ACP_I2SSP_TXDMA__I2SSP_TXDMA__SHIFT 0x01979#define ACP_I2SSP_RTXDMA__I2SSP_RTXDMA_MASK 0x11980#define ACP_I2SSP_RTXDMA__I2SSP_RTXDMA__SHIFT 0x01981#define ACP_I2SSP_COMP_PARAM_2__I2SSP_RX_WPRDSIZE_0_MASK 0x71982#define ACP_I2SSP_COMP_PARAM_2__I2SSP_RX_WPRDSIZE_0__SHIFT 0x01983#define ACP_I2SSP_COMP_PARAM_2__I2SSP_RX_WPRDSIZE_1_MASK 0x381984#define ACP_I2SSP_COMP_PARAM_2__I2SSP_RX_WPRDSIZE_1__SHIFT 0x31985#define ACP_I2SSP_COMP_PARAM_2__I2SSP_RX_WPRDSIZE_2_MASK 0x3801986#define ACP_I2SSP_COMP_PARAM_2__I2SSP_RX_WPRDSIZE_2__SHIFT 0x71987#define ACP_I2SSP_COMP_PARAM_2__I2SSP_RX_WPRDSIZE_3_MASK 0x1c001988#define ACP_I2SSP_COMP_PARAM_2__I2SSP_RX_WPRDSIZE_3__SHIFT 0xa1989#define ACP_I2SSP_COMP_PARAM_1__I2SSP_APB_DATA_WIDTH_MASK 0x31990#define ACP_I2SSP_COMP_PARAM_1__I2SSP_APB_DATA_WIDTH__SHIFT 0x01991#define ACP_I2SSP_COMP_PARAM_1__I2SSP_FIFO_DEPTH_GLOBAL_MASK 0xc1992#define ACP_I2SSP_COMP_PARAM_1__I2SSP_FIFO_DEPTH_GLOBAL__SHIFT 0x21993#define ACP_I2SSP_COMP_PARAM_1__I2SSP_MODE_EN_MASK 0x101994#define ACP_I2SSP_COMP_PARAM_1__I2SSP_MODE_EN__SHIFT 0x41995#define ACP_I2SSP_COMP_PARAM_1__I2SSP_TRANSMITTER_BLOCK_MASK 0x201996#define ACP_I2SSP_COMP_PARAM_1__I2SSP_TRANSMITTER_BLOCK__SHIFT 0x51997#define ACP_I2SSP_COMP_PARAM_1__I2SSP_RECEIVER_BLOCK_MASK 0x401998#define ACP_I2SSP_COMP_PARAM_1__I2SSP_RECEIVER_BLOCK__SHIFT 0x61999#define ACP_I2SSP_COMP_PARAM_1__I2SSP_RX_CHANNLES_MASK 0x1802000#define ACP_I2SSP_COMP_PARAM_1__I2SSP_RX_CHANNLES__SHIFT 0x72001#define ACP_I2SSP_COMP_PARAM_1__I2SSP_TX_CHANNLES_MASK 0x6002002#define ACP_I2SSP_COMP_PARAM_1__I2SSP_TX_CHANNLES__SHIFT 0x92003#define ACP_I2SSP_COMP_PARAM_1__I2SSP_TX_WORDSIZE_0_MASK 0x700002004#define ACP_I2SSP_COMP_PARAM_1__I2SSP_TX_WORDSIZE_0__SHIFT 0x102005#define ACP_I2SSP_COMP_PARAM_1__I2SSP_TX_WORDSIZE_1_MASK 0x3800002006#define ACP_I2SSP_COMP_PARAM_1__I2SSP_TX_WORDSIZE_1__SHIFT 0x132007#define ACP_I2SSP_COMP_PARAM_1__I2SSP_TX_WORDSIZE_2_MASK 0x1c000002008#define ACP_I2SSP_COMP_PARAM_1__I2SSP_TX_WORDSIZE_2__SHIFT 0x162009#define ACP_I2SSP_COMP_PARAM_1__I2SSP_TX_WORDSIZE_3_MASK 0xe0000002010#define ACP_I2SSP_COMP_PARAM_1__I2SSP_TX_WORDSIZE_3__SHIFT 0x192011#define ACP_I2SSP_COMP_VERSION__I2SSP_APB_DATA_WIDTH_MASK 0xffffffff2012#define ACP_I2SSP_COMP_VERSION__I2SSP_APB_DATA_WIDTH__SHIFT 0x02013#define ACP_I2SSP_COMP_TYPE__I2SSP_COMP_TYPE_MASK 0xffffffff2014#define ACP_I2SSP_COMP_TYPE__I2SSP_COMP_TYPE__SHIFT 0x02015#define ACP_I2SMICSP_IER__I2SMICSP_IEN_MASK 0x12016#define ACP_I2SMICSP_IER__I2SMICSP_IEN__SHIFT 0x02017#define ACP_I2SMICSP_IRER__I2SMICSP_RXEN_MASK 0x12018#define ACP_I2SMICSP_IRER__I2SMICSP_RXEN__SHIFT 0x02019#define ACP_I2SMICSP_ITER__I2SMICSP_TXEN_MASK 0x12020#define ACP_I2SMICSP_ITER__I2SMICSP_TXEN__SHIFT 0x02021#define ACP_I2SMICSP_CER__I2SMICSP_CLKEN_MASK 0x12022#define ACP_I2SMICSP_CER__I2SMICSP_CLKEN__SHIFT 0x02023#define ACP_I2SMICSP_CCR__I2SMICSP_SCLKG_MASK 0x72024#define ACP_I2SMICSP_CCR__I2SMICSP_SCLKG__SHIFT 0x02025#define ACP_I2SMICSP_CCR__I2SMICSP_WSS_MASK 0x182026#define ACP_I2SMICSP_CCR__I2SMICSP_WSS__SHIFT 0x32027#define ACP_I2SMICSP_RXFFR__I2SMICSP_RXFFR_MASK 0x12028#define ACP_I2SMICSP_RXFFR__I2SMICSP_RXFFR__SHIFT 0x02029#define ACP_I2SMICSP_TXFFR__I2SMICSP_TXFFR_MASK 0x12030#define ACP_I2SMICSP_TXFFR__I2SMICSP_TXFFR__SHIFT 0x02031#define ACP_I2SMICSP_LRBR0__I2SMICSP_LRBR0_MASK 0xffffffff2032#define ACP_I2SMICSP_LRBR0__I2SMICSP_LRBR0__SHIFT 0x02033#define ACP_I2SMICSP_RRBR0__I2SMICSP_RRBR0_MASK 0xffffffff2034#define ACP_I2SMICSP_RRBR0__I2SMICSP_RRBR0__SHIFT 0x02035#define ACP_I2SMICSP_RER0__I2SMICSP_RXCHEN0_MASK 0x12036#define ACP_I2SMICSP_RER0__I2SMICSP_RXCHEN0__SHIFT 0x02037#define ACP_I2SMICSP_TER0__I2SMICSP_TXCHEN0_MASK 0x12038#define ACP_I2SMICSP_TER0__I2SMICSP_TXCHEN0__SHIFT 0x02039#define ACP_I2SMICSP_RCR0__I2SMICSP_WLEN_MASK 0x72040#define ACP_I2SMICSP_RCR0__I2SMICSP_WLEN__SHIFT 0x02041#define ACP_I2SMICSP_TCR0__I2SMICSP_WLEN_MASK 0x72042#define ACP_I2SMICSP_TCR0__I2SMICSP_WLEN__SHIFT 0x02043#define ACP_I2SMICSP_ISR0__I2SMICSP_RXDA_MASK 0x12044#define ACP_I2SMICSP_ISR0__I2SMICSP_RXDA__SHIFT 0x02045#define ACP_I2SMICSP_ISR0__I2SMICSP_RXFO_MASK 0x22046#define ACP_I2SMICSP_ISR0__I2SMICSP_RXFO__SHIFT 0x12047#define ACP_I2SMICSP_ISR0__I2SMICSP_TXFE_MASK 0x102048#define ACP_I2SMICSP_ISR0__I2SMICSP_TXFE__SHIFT 0x42049#define ACP_I2SMICSP_ISR0__I2SMICSP_TXFO_MASK 0x202050#define ACP_I2SMICSP_ISR0__I2SMICSP_TXFO__SHIFT 0x52051#define ACP_I2SMICSP_IMR0__I2SMICSP_RXDAM_MASK 0x12052#define ACP_I2SMICSP_IMR0__I2SMICSP_RXDAM__SHIFT 0x02053#define ACP_I2SMICSP_IMR0__I2SMICSP_RXFOM_MASK 0x22054#define ACP_I2SMICSP_IMR0__I2SMICSP_RXFOM__SHIFT 0x12055#define ACP_I2SMICSP_IMR0__I2SMICSP_TXFEM_MASK 0x102056#define ACP_I2SMICSP_IMR0__I2SMICSP_TXFEM__SHIFT 0x42057#define ACP_I2SMICSP_IMR0__I2SMICSP_TXFOM_MASK 0x202058#define ACP_I2SMICSP_IMR0__I2SMICSP_TXFOM__SHIFT 0x52059#define ACP_I2SMICSP_ROR0__I2SMICSP_RXCHO_MASK 0x12060#define ACP_I2SMICSP_ROR0__I2SMICSP_RXCHO__SHIFT 0x02061#define ACP_I2SMICSP_TOR0__I2SMICSP_TXCHO_MASK 0x12062#define ACP_I2SMICSP_TOR0__I2SMICSP_TXCHO__SHIFT 0x02063#define ACP_I2SMICSP_RFCR0__I2SMICSP_RXCHDT_MASK 0xf2064#define ACP_I2SMICSP_RFCR0__I2SMICSP_RXCHDT__SHIFT 0x02065#define ACP_I2SMICSP_TFCR0__I2SMICSP_TXCHET_MASK 0xf2066#define ACP_I2SMICSP_TFCR0__I2SMICSP_TXCHET__SHIFT 0x02067#define ACP_I2SMICSP_RFF0__I2SMICSP_RXCHFR_MASK 0x12068#define ACP_I2SMICSP_RFF0__I2SMICSP_RXCHFR__SHIFT 0x02069#define ACP_I2SMICSP_TFF0__I2SMICSP_TXCHFR_MASK 0x12070#define ACP_I2SMICSP_TFF0__I2SMICSP_TXCHFR__SHIFT 0x02071#define ACP_I2SMICSP_LRBR1__I2SMICSP_LRBR1_MASK 0xffffffff2072#define ACP_I2SMICSP_LRBR1__I2SMICSP_LRBR1__SHIFT 0x02073#define ACP_I2SMICSP_RRBR1__I2SMICSP_RRBR1_MASK 0xffffffff2074#define ACP_I2SMICSP_RRBR1__I2SMICSP_RRBR1__SHIFT 0x02075#define ACP_I2SMICSP_RER1__I2SMICSP_RXCHEN1_MASK 0x12076#define ACP_I2SMICSP_RER1__I2SMICSP_RXCHEN1__SHIFT 0x02077#define ACP_I2SMICSP_TER1__I2SMICSP_TXCHEN1_MASK 0x12078#define ACP_I2SMICSP_TER1__I2SMICSP_TXCHEN1__SHIFT 0x02079#define ACP_I2SMICSP_RCR1__I2SMICSP_WLEN_MASK 0x72080#define ACP_I2SMICSP_RCR1__I2SMICSP_WLEN__SHIFT 0x02081#define ACP_I2SMICSP_TCR1__I2SMICSP_WLEN_MASK 0x72082#define ACP_I2SMICSP_TCR1__I2SMICSP_WLEN__SHIFT 0x02083#define ACP_I2SMICSP_ISR1__I2SMICSP_RXDA_MASK 0x12084#define ACP_I2SMICSP_ISR1__I2SMICSP_RXDA__SHIFT 0x02085#define ACP_I2SMICSP_ISR1__I2SMICSP_RXFO_MASK 0x22086#define ACP_I2SMICSP_ISR1__I2SMICSP_RXFO__SHIFT 0x12087#define ACP_I2SMICSP_ISR1__I2SMICSP_TXFE_MASK 0x102088#define ACP_I2SMICSP_ISR1__I2SMICSP_TXFE__SHIFT 0x42089#define ACP_I2SMICSP_ISR1__I2SMICSP_TXFO_MASK 0x202090#define ACP_I2SMICSP_ISR1__I2SMICSP_TXFO__SHIFT 0x52091#define ACP_I2SMICSP_IMR1__I2SMICSP_RXDAM_MASK 0x12092#define ACP_I2SMICSP_IMR1__I2SMICSP_RXDAM__SHIFT 0x02093#define ACP_I2SMICSP_IMR1__I2SMICSP_RXFOM_MASK 0x22094#define ACP_I2SMICSP_IMR1__I2SMICSP_RXFOM__SHIFT 0x12095#define ACP_I2SMICSP_IMR1__I2SMICSP_TXFEM_MASK 0x102096#define ACP_I2SMICSP_IMR1__I2SMICSP_TXFEM__SHIFT 0x42097#define ACP_I2SMICSP_IMR1__I2SMICSP_TXFOM_MASK 0x202098#define ACP_I2SMICSP_IMR1__I2SMICSP_TXFOM__SHIFT 0x52099#define ACP_I2SMICSP_ROR1__I2SMICSP_RXCHO_MASK 0x12100#define ACP_I2SMICSP_ROR1__I2SMICSP_RXCHO__SHIFT 0x02101#define ACP_I2SMICSP_TOR1__I2SMICSP_TXCHO_MASK 0x12102#define ACP_I2SMICSP_TOR1__I2SMICSP_TXCHO__SHIFT 0x02103#define ACP_I2SMICSP_RFCR1__I2SMICSP_RXCHDT_MASK 0xf2104#define ACP_I2SMICSP_RFCR1__I2SMICSP_RXCHDT__SHIFT 0x02105#define ACP_I2SMICSP_TFCR1__I2SMICSP_TXCHET_MASK 0xf2106#define ACP_I2SMICSP_TFCR1__I2SMICSP_TXCHET__SHIFT 0x02107#define ACP_I2SMICSP_RFF1__I2SMICSP_RXCHFR_MASK 0x12108#define ACP_I2SMICSP_RFF1__I2SMICSP_RXCHFR__SHIFT 0x02109#define ACP_I2SMICSP_TFF1__I2SMICSP_TXCHFR_MASK 0x12110#define ACP_I2SMICSP_TFF1__I2SMICSP_TXCHFR__SHIFT 0x02111#define ACP_I2SMICSP_RXDMA__I2SMICSP_RXDMA_MASK 0xffffffff2112#define ACP_I2SMICSP_RXDMA__I2SMICSP_RXDMA__SHIFT 0x02113#define ACP_I2SMICSP_RRXDMA__I2SMICSP_RRXDMA_MASK 0x12114#define ACP_I2SMICSP_RRXDMA__I2SMICSP_RRXDMA__SHIFT 0x02115#define ACP_I2SMICSP_TXDMA__I2SMICSP_TXDMA_MASK 0xffffffff2116#define ACP_I2SMICSP_TXDMA__I2SMICSP_TXDMA__SHIFT 0x02117#define ACP_I2SMICSP_RTXDMA__I2SMICSP_RTXDMA_MASK 0x12118#define ACP_I2SMICSP_RTXDMA__I2SMICSP_RTXDMA__SHIFT 0x02119#define ACP_I2SMICSP_COMP_PARAM_2__I2SMICSP_RX_WPRDSIZE_0_MASK 0x72120#define ACP_I2SMICSP_COMP_PARAM_2__I2SMICSP_RX_WPRDSIZE_0__SHIFT 0x02121#define ACP_I2SMICSP_COMP_PARAM_2__I2SMICSP_RX_WPRDSIZE_1_MASK 0x382122#define ACP_I2SMICSP_COMP_PARAM_2__I2SMICSP_RX_WPRDSIZE_1__SHIFT 0x32123#define ACP_I2SMICSP_COMP_PARAM_2__I2SMICSP_RX_WPRDSIZE_2_MASK 0x3802124#define ACP_I2SMICSP_COMP_PARAM_2__I2SMICSP_RX_WPRDSIZE_2__SHIFT 0x72125#define ACP_I2SMICSP_COMP_PARAM_2__I2SMICSP_RX_WPRDSIZE_3_MASK 0x1c002126#define ACP_I2SMICSP_COMP_PARAM_2__I2SMICSP_RX_WPRDSIZE_3__SHIFT 0xa2127#define ACP_I2SMICSP_COMP_PARAM_1__I2SMICSP_APB_DATA_WIDTH_MASK 0x32128#define ACP_I2SMICSP_COMP_PARAM_1__I2SMICSP_APB_DATA_WIDTH__SHIFT 0x02129#define ACP_I2SMICSP_COMP_PARAM_1__I2SMICSP_FIFO_DEPTH_GLOBAL_MASK 0xc2130#define ACP_I2SMICSP_COMP_PARAM_1__I2SMICSP_FIFO_DEPTH_GLOBAL__SHIFT 0x22131#define ACP_I2SMICSP_COMP_PARAM_1__I2SMICSP_MODE_EN_MASK 0x102132#define ACP_I2SMICSP_COMP_PARAM_1__I2SMICSP_MODE_EN__SHIFT 0x42133#define ACP_I2SMICSP_COMP_PARAM_1__I2SMICSP_TRANSMITTER_BLOCK_MASK 0x202134#define ACP_I2SMICSP_COMP_PARAM_1__I2SMICSP_TRANSMITTER_BLOCK__SHIFT 0x52135#define ACP_I2SMICSP_COMP_PARAM_1__I2SMICSP_RECEIVER_BLOCK_MASK 0x402136#define ACP_I2SMICSP_COMP_PARAM_1__I2SMICSP_RECEIVER_BLOCK__SHIFT 0x62137#define ACP_I2SMICSP_COMP_PARAM_1__I2SMICSP_RX_CHANNLES_MASK 0x1802138#define ACP_I2SMICSP_COMP_PARAM_1__I2SMICSP_RX_CHANNLES__SHIFT 0x72139#define ACP_I2SMICSP_COMP_PARAM_1__I2SMICSP_TX_CHANNLES_MASK 0x6002140#define ACP_I2SMICSP_COMP_PARAM_1__I2SMICSP_TX_CHANNLES__SHIFT 0x92141#define ACP_I2SMICSP_COMP_PARAM_1__I2SMICSP_TX_WORDSIZE_0_MASK 0x700002142#define ACP_I2SMICSP_COMP_PARAM_1__I2SMICSP_TX_WORDSIZE_0__SHIFT 0x102143#define ACP_I2SMICSP_COMP_PARAM_1__I2SMICSP_TX_WORDSIZE_1_MASK 0x3800002144#define ACP_I2SMICSP_COMP_PARAM_1__I2SMICSP_TX_WORDSIZE_1__SHIFT 0x132145#define ACP_I2SMICSP_COMP_PARAM_1__I2SMICSP_TX_WORDSIZE_2_MASK 0x1c000002146#define ACP_I2SMICSP_COMP_PARAM_1__I2SMICSP_TX_WORDSIZE_2__SHIFT 0x162147#define ACP_I2SMICSP_COMP_PARAM_1__I2SMICSP_TX_WORDSIZE_3_MASK 0xe0000002148#define ACP_I2SMICSP_COMP_PARAM_1__I2SMICSP_TX_WORDSIZE_3__SHIFT 0x192149#define ACP_I2SMICSP_COMP_VERSION__I2SMICSP_APB_DATA_WIDTH_MASK 0xffffffff2150#define ACP_I2SMICSP_COMP_VERSION__I2SMICSP_APB_DATA_WIDTH__SHIFT 0x02151#define ACP_I2SMICSP_COMP_TYPE__I2SMICSP_COMP_TYPE_MASK 0xffffffff2152#define ACP_I2SMICSP_COMP_TYPE__I2SMICSP_COMP_TYPE__SHIFT 0x02153#define ACP_I2SBT_IER__I2SBT_IEN_MASK 0x12154#define ACP_I2SBT_IER__I2SBT_IEN__SHIFT 0x02155#define ACP_I2SBT_IRER__I2SBT_RXEN_MASK 0x12156#define ACP_I2SBT_IRER__I2SBT_RXEN__SHIFT 0x02157#define ACP_I2SBT_ITER__I2SBT_TXEN_MASK 0x12158#define ACP_I2SBT_ITER__I2SBT_TXEN__SHIFT 0x02159#define ACP_I2SBT_CER__I2SBT_CLKEN_MASK 0x12160#define ACP_I2SBT_CER__I2SBT_CLKEN__SHIFT 0x02161#define ACP_I2SBT_CCR__I2SBT_SCLKG_MASK 0x72162#define ACP_I2SBT_CCR__I2SBT_SCLKG__SHIFT 0x02163#define ACP_I2SBT_CCR__I2SBT_WSS_MASK 0x182164#define ACP_I2SBT_CCR__I2SBT_WSS__SHIFT 0x32165#define ACP_I2SBT_RXFFR__I2SBT_RXFFR_MASK 0x12166#define ACP_I2SBT_RXFFR__I2SBT_RXFFR__SHIFT 0x02167#define ACP_I2SBT_TXFFR__I2SBT_TXFFR_MASK 0x12168#define ACP_I2SBT_TXFFR__I2SBT_TXFFR__SHIFT 0x02169#define ACP_I2SBT_LRBR0__I2SBT_LRBR0_MASK 0xffffffff2170#define ACP_I2SBT_LRBR0__I2SBT_LRBR0__SHIFT 0x02171#define ACP_I2SBT_RRBR0__I2SBT_RRBR0_MASK 0xffffffff2172#define ACP_I2SBT_RRBR0__I2SBT_RRBR0__SHIFT 0x02173#define ACP_I2SBT_RER0__I2SBT_RXCHEN0_MASK 0x12174#define ACP_I2SBT_RER0__I2SBT_RXCHEN0__SHIFT 0x02175#define ACP_I2SBT_TER0__I2SBT_TXCHEN0_MASK 0x12176#define ACP_I2SBT_TER0__I2SBT_TXCHEN0__SHIFT 0x02177#define ACP_I2SBT_RCR0__I2SBT_WLEN_MASK 0x72178#define ACP_I2SBT_RCR0__I2SBT_WLEN__SHIFT 0x02179#define ACP_I2SBT_TCR0__I2SBT_WLEN_MASK 0x72180#define ACP_I2SBT_TCR0__I2SBT_WLEN__SHIFT 0x02181#define ACP_I2SBT_ISR0__I2SBT_RXDA_MASK 0x12182#define ACP_I2SBT_ISR0__I2SBT_RXDA__SHIFT 0x02183#define ACP_I2SBT_ISR0__I2SBT_RXFO_MASK 0x22184#define ACP_I2SBT_ISR0__I2SBT_RXFO__SHIFT 0x12185#define ACP_I2SBT_ISR0__I2SBT_TXFE_MASK 0x102186#define ACP_I2SBT_ISR0__I2SBT_TXFE__SHIFT 0x42187#define ACP_I2SBT_ISR0__I2SBT_TXFO_MASK 0x202188#define ACP_I2SBT_ISR0__I2SBT_TXFO__SHIFT 0x52189#define ACP_I2SBT_IMR0__I2SBT_RXDAM_MASK 0x12190#define ACP_I2SBT_IMR0__I2SBT_RXDAM__SHIFT 0x02191#define ACP_I2SBT_IMR0__I2SBT_RXFOM_MASK 0x22192#define ACP_I2SBT_IMR0__I2SBT_RXFOM__SHIFT 0x12193#define ACP_I2SBT_IMR0__I2SBT_TXFEM_MASK 0x102194#define ACP_I2SBT_IMR0__I2SBT_TXFEM__SHIFT 0x42195#define ACP_I2SBT_IMR0__I2SBT_TXFOM_MASK 0x202196#define ACP_I2SBT_IMR0__I2SBT_TXFOM__SHIFT 0x52197#define ACP_I2SBT_ROR0__I2SBT_RXCHO_MASK 0x12198#define ACP_I2SBT_ROR0__I2SBT_RXCHO__SHIFT 0x02199#define ACP_I2SBT_TOR0__I2SBT_TXCHO_MASK 0x12200#define ACP_I2SBT_TOR0__I2SBT_TXCHO__SHIFT 0x02201#define ACP_I2SBT_RFCR0__I2SBT_RXCHDT_MASK 0xf2202#define ACP_I2SBT_RFCR0__I2SBT_RXCHDT__SHIFT 0x02203#define ACP_I2SBT_TFCR0__I2SBT_TXCHET_MASK 0xf2204#define ACP_I2SBT_TFCR0__I2SBT_TXCHET__SHIFT 0x02205#define ACP_I2SBT_RFF0__I2SBT_RXCHFR_MASK 0x12206#define ACP_I2SBT_RFF0__I2SBT_RXCHFR__SHIFT 0x02207#define ACP_I2SBT_TFF0__I2SBT_TXCHFR_MASK 0x12208#define ACP_I2SBT_TFF0__I2SBT_TXCHFR__SHIFT 0x02209#define ACP_I2SBT_LRBR1__I2SBT_LRBR1_MASK 0xffffffff2210#define ACP_I2SBT_LRBR1__I2SBT_LRBR1__SHIFT 0x02211#define ACP_I2SBT_RRBR1__I2SBT_RRBR1_MASK 0xffffffff2212#define ACP_I2SBT_RRBR1__I2SBT_RRBR1__SHIFT 0x02213#define ACP_I2SBT_RER1__I2SBT_RXCHEN1_MASK 0x12214#define ACP_I2SBT_RER1__I2SBT_RXCHEN1__SHIFT 0x02215#define ACP_I2SBT_TER1__I2SBT_TXCHEN1_MASK 0x12216#define ACP_I2SBT_TER1__I2SBT_TXCHEN1__SHIFT 0x02217#define ACP_I2SBT_RCR1__I2SBT_WLEN_MASK 0x72218#define ACP_I2SBT_RCR1__I2SBT_WLEN__SHIFT 0x02219#define ACP_I2SBT_TCR1__I2SBT_WLEN_MASK 0x72220#define ACP_I2SBT_TCR1__I2SBT_WLEN__SHIFT 0x02221#define ACP_I2SBT_ISR1__I2SBT_RXDA_MASK 0x12222#define ACP_I2SBT_ISR1__I2SBT_RXDA__SHIFT 0x02223#define ACP_I2SBT_ISR1__I2SBT_RXFO_MASK 0x22224#define ACP_I2SBT_ISR1__I2SBT_RXFO__SHIFT 0x12225#define ACP_I2SBT_ISR1__I2SBT_TXFE_MASK 0x102226#define ACP_I2SBT_ISR1__I2SBT_TXFE__SHIFT 0x42227#define ACP_I2SBT_ISR1__I2SBT_TXFO_MASK 0x202228#define ACP_I2SBT_ISR1__I2SBT_TXFO__SHIFT 0x52229#define ACP_I2SBT_IMR1__I2SBT_RXDAM_MASK 0x12230#define ACP_I2SBT_IMR1__I2SBT_RXDAM__SHIFT 0x02231#define ACP_I2SBT_IMR1__I2SBT_RXFOM_MASK 0x22232#define ACP_I2SBT_IMR1__I2SBT_RXFOM__SHIFT 0x12233#define ACP_I2SBT_IMR1__I2SBT_TXFEM_MASK 0x102234#define ACP_I2SBT_IMR1__I2SBT_TXFEM__SHIFT 0x42235#define ACP_I2SBT_IMR1__I2SBT_TXFOM_MASK 0x202236#define ACP_I2SBT_IMR1__I2SBT_TXFOM__SHIFT 0x52237#define ACP_I2SBT_ROR1__I2SBT_RXCHO_MASK 0x12238#define ACP_I2SBT_ROR1__I2SBT_RXCHO__SHIFT 0x02239#define ACP_I2SBT_TOR1__I2SBT_TXCHO_MASK 0x12240#define ACP_I2SBT_TOR1__I2SBT_TXCHO__SHIFT 0x02241#define ACP_I2SBT_RFCR1__I2SBT_RXCHDT_MASK 0xf2242#define ACP_I2SBT_RFCR1__I2SBT_RXCHDT__SHIFT 0x02243#define ACP_I2SBT_TFCR1__I2SBT_TXCHET_MASK 0xf2244#define ACP_I2SBT_TFCR1__I2SBT_TXCHET__SHIFT 0x02245#define ACP_I2SBT_RFF1__I2SBT_RXCHFR_MASK 0x12246#define ACP_I2SBT_RFF1__I2SBT_RXCHFR__SHIFT 0x02247#define ACP_I2SBT_TFF1__I2SBT_TXCHFR_MASK 0x12248#define ACP_I2SBT_TFF1__I2SBT_TXCHFR__SHIFT 0x02249#define ACP_I2SBT_RXDMA__I2SBT_RXDMA_MASK 0xffffffff2250#define ACP_I2SBT_RXDMA__I2SBT_RXDMA__SHIFT 0x02251#define ACP_I2SBT_RRXDMA__I2SBT_RRXDMA_MASK 0x12252#define ACP_I2SBT_RRXDMA__I2SBT_RRXDMA__SHIFT 0x02253#define ACP_I2SBT_TXDMA__I2SBT_TXDMA_MASK 0xffffffff2254#define ACP_I2SBT_TXDMA__I2SBT_TXDMA__SHIFT 0x02255#define ACP_I2SBT_RTXDMA__I2SBT_RTXDMA_MASK 0x12256#define ACP_I2SBT_RTXDMA__I2SBT_RTXDMA__SHIFT 0x02257#define ACP_I2SBT_COMP_PARAM_2__I2SBT_RX_WPRDSIZE_0_MASK 0x72258#define ACP_I2SBT_COMP_PARAM_2__I2SBT_RX_WPRDSIZE_0__SHIFT 0x02259#define ACP_I2SBT_COMP_PARAM_2__I2SBT_RX_WPRDSIZE_1_MASK 0x382260#define ACP_I2SBT_COMP_PARAM_2__I2SBT_RX_WPRDSIZE_1__SHIFT 0x32261#define ACP_I2SBT_COMP_PARAM_2__I2SBT_RX_WPRDSIZE_2_MASK 0x3802262#define ACP_I2SBT_COMP_PARAM_2__I2SBT_RX_WPRDSIZE_2__SHIFT 0x72263#define ACP_I2SBT_COMP_PARAM_2__I2SBT_RX_WPRDSIZE_3_MASK 0x1c002264#define ACP_I2SBT_COMP_PARAM_2__I2SBT_RX_WPRDSIZE_3__SHIFT 0xa2265#define ACP_I2SBT_COMP_PARAM_1__I2SBT_APB_DATA_WIDTH_MASK 0x32266#define ACP_I2SBT_COMP_PARAM_1__I2SBT_APB_DATA_WIDTH__SHIFT 0x02267#define ACP_I2SBT_COMP_PARAM_1__I2SBT_FIFO_DEPTH_GLOBAL_MASK 0xc2268#define ACP_I2SBT_COMP_PARAM_1__I2SBT_FIFO_DEPTH_GLOBAL__SHIFT 0x22269#define ACP_I2SBT_COMP_PARAM_1__I2SBT_MODE_EN_MASK 0x102270#define ACP_I2SBT_COMP_PARAM_1__I2SBT_MODE_EN__SHIFT 0x42271#define ACP_I2SBT_COMP_PARAM_1__I2SBT_TRANSMITTER_BLOCK_MASK 0x202272#define ACP_I2SBT_COMP_PARAM_1__I2SBT_TRANSMITTER_BLOCK__SHIFT 0x52273#define ACP_I2SBT_COMP_PARAM_1__I2SBT_RECEIVER_BLOCK_MASK 0x402274#define ACP_I2SBT_COMP_PARAM_1__I2SBT_RECEIVER_BLOCK__SHIFT 0x62275#define ACP_I2SBT_COMP_PARAM_1__I2SBT_RX_CHANNLES_MASK 0x1802276#define ACP_I2SBT_COMP_PARAM_1__I2SBT_RX_CHANNLES__SHIFT 0x72277#define ACP_I2SBT_COMP_PARAM_1__I2SBT_TX_CHANNLES_MASK 0x6002278#define ACP_I2SBT_COMP_PARAM_1__I2SBT_TX_CHANNLES__SHIFT 0x92279#define ACP_I2SBT_COMP_PARAM_1__I2SBT_TX_WORDSIZE_0_MASK 0x700002280#define ACP_I2SBT_COMP_PARAM_1__I2SBT_TX_WORDSIZE_0__SHIFT 0x102281#define ACP_I2SBT_COMP_PARAM_1__I2SBT_TX_WORDSIZE_1_MASK 0x3800002282#define ACP_I2SBT_COMP_PARAM_1__I2SBT_TX_WORDSIZE_1__SHIFT 0x132283#define ACP_I2SBT_COMP_PARAM_1__I2SBT_TX_WORDSIZE_2_MASK 0x1c000002284#define ACP_I2SBT_COMP_PARAM_1__I2SBT_TX_WORDSIZE_2__SHIFT 0x162285#define ACP_I2SBT_COMP_PARAM_1__I2SBT_TX_WORDSIZE_3_MASK 0xe0000002286#define ACP_I2SBT_COMP_PARAM_1__I2SBT_TX_WORDSIZE_3__SHIFT 0x192287#define ACP_I2SBT_COMP_VERSION__I2SBT_APB_DATA_WIDTH_MASK 0xffffffff2288#define ACP_I2SBT_COMP_VERSION__I2SBT_APB_DATA_WIDTH__SHIFT 0x02289#define ACP_I2SBT_COMP_TYPE__I2SBT_COMP_TYPE_MASK 0xffffffff2290#define ACP_I2SBT_COMP_TYPE__I2SBT_COMP_TYPE__SHIFT 0x02291 2292#endif /* ACP_2_2_SH_MASK_H */2293