163 lines · c
1/* SPDX-License-Identifier: GPL-2.0+ */2/*3 * AMD ALSA SoC PCM Driver4 *5 * Copyright 2016 Advanced Micro Devices, Inc.6 */7 8#include "chip_offset_byte.h"9#include <sound/pcm.h>10#define I2S_SP_INSTANCE 0x0111#define I2S_BT_INSTANCE 0x0212 13#define TDM_ENABLE 114#define TDM_DISABLE 015 16#define ACP3x_DEVS 417#define ACP3x_PHY_BASE_ADDRESS 0x124000018#define ACP3x_I2S_MODE 019#define ACP3x_REG_START 0x124000020#define ACP3x_REG_END 0x125020021#define ACP3x_I2STDM_REG_START 0x124240022#define ACP3x_I2STDM_REG_END 0x124241023#define ACP3x_BT_TDM_REG_START 0x124280024#define ACP3x_BT_TDM_REG_END 0x124281025#define I2S_MODE 0x0426#define I2S_RX_THRESHOLD 2727#define I2S_TX_THRESHOLD 2828#define BT_TX_THRESHOLD 2629#define BT_RX_THRESHOLD 2530#define ACP_ERR_INTR_MASK 2931#define ACP3x_POWER_ON 0x0032#define ACP3x_POWER_ON_IN_PROGRESS 0x0133#define ACP3x_POWER_OFF 0x0234#define ACP3x_POWER_OFF_IN_PROGRESS 0x0335#define ACP3x_SOFT_RESET__SoftResetAudDone_MASK 0x0001000136 37#define ACP_SRAM_PTE_OFFSET 0x0205000038#define ACP_SRAM_SP_PB_PTE_OFFSET 0x039#define ACP_SRAM_SP_CP_PTE_OFFSET 0x10040#define ACP_SRAM_BT_PB_PTE_OFFSET 0x20041#define ACP_SRAM_BT_CP_PTE_OFFSET 0x30042#define PAGE_SIZE_4K_ENABLE 0x243#define I2S_SP_TX_MEM_WINDOW_START 0x400000044#define I2S_SP_RX_MEM_WINDOW_START 0x402000045#define I2S_BT_TX_MEM_WINDOW_START 0x404000046#define I2S_BT_RX_MEM_WINDOW_START 0x406000047 48#define SP_PB_FIFO_ADDR_OFFSET 0x50049#define SP_CAPT_FIFO_ADDR_OFFSET 0x70050#define BT_PB_FIFO_ADDR_OFFSET 0x90051#define BT_CAPT_FIFO_ADDR_OFFSET 0xB0052#define PLAYBACK_MIN_NUM_PERIODS 253#define PLAYBACK_MAX_NUM_PERIODS 854#define PLAYBACK_MAX_PERIOD_SIZE 819255#define PLAYBACK_MIN_PERIOD_SIZE 102456#define CAPTURE_MIN_NUM_PERIODS 257#define CAPTURE_MAX_NUM_PERIODS 858#define CAPTURE_MAX_PERIOD_SIZE 819259#define CAPTURE_MIN_PERIOD_SIZE 102460 61#define MAX_BUFFER (PLAYBACK_MAX_PERIOD_SIZE * PLAYBACK_MAX_NUM_PERIODS)62#define MIN_BUFFER MAX_BUFFER63#define FIFO_SIZE 0x10064#define DMA_SIZE 0x4065#define FRM_LEN 0x10066 67#define SLOT_WIDTH_8 0x0868#define SLOT_WIDTH_16 0x1069#define SLOT_WIDTH_24 0x1870#define SLOT_WIDTH_32 0x2071#define ACP_PGFSM_CNTL_POWER_ON_MASK 0x0172#define ACP_PGFSM_CNTL_POWER_OFF_MASK 0x0073#define ACP_PGFSM_STATUS_MASK 0x0374#define ACP_POWERED_ON 0x0075#define ACP_POWER_ON_IN_PROGRESS 0x0176#define ACP_POWERED_OFF 0x0277#define ACP_POWER_OFF_IN_PROGRESS 0x0378 79#define ACP3x_ITER_IRER_SAMP_LEN_MASK 0x3880#define ACP_EXT_INTR_STAT_CLEAR_MASK 0xFFFFFFFF81 82struct acp3x_platform_info {83 u16 play_i2s_instance;84 u16 cap_i2s_instance;85 u16 capture_channel;86};87 88struct i2s_dev_data {89 bool tdm_mode;90 int i2s_irq;91 u16 i2s_instance;92 u32 tdm_fmt;93 u32 substream_type;94 void __iomem *acp3x_base;95 struct snd_pcm_substream *play_stream;96 struct snd_pcm_substream *capture_stream;97 struct snd_pcm_substream *i2ssp_play_stream;98 struct snd_pcm_substream *i2ssp_capture_stream;99};100 101struct i2s_stream_instance {102 u16 num_pages;103 u16 i2s_instance;104 u16 capture_channel;105 u16 direction;106 u16 channels;107 u32 xfer_resolution;108 u32 val;109 dma_addr_t dma_addr;110 u64 bytescount;111 void __iomem *acp3x_base;112};113 114static inline u32 rv_readl(void __iomem *base_addr)115{116 return readl(base_addr - ACP3x_PHY_BASE_ADDRESS);117}118 119static inline void rv_writel(u32 val, void __iomem *base_addr)120{121 writel(val, base_addr - ACP3x_PHY_BASE_ADDRESS);122}123 124static inline u64 acp_get_byte_count(struct i2s_stream_instance *rtd,125 int direction)126{127 u64 byte_count;128 129 if (direction == SNDRV_PCM_STREAM_PLAYBACK) {130 switch (rtd->i2s_instance) {131 case I2S_BT_INSTANCE:132 byte_count = rv_readl(rtd->acp3x_base +133 mmACP_BT_TX_LINEARPOSITIONCNTR_HIGH);134 byte_count |= rv_readl(rtd->acp3x_base +135 mmACP_BT_TX_LINEARPOSITIONCNTR_LOW);136 break;137 case I2S_SP_INSTANCE:138 default:139 byte_count = rv_readl(rtd->acp3x_base +140 mmACP_I2S_TX_LINEARPOSITIONCNTR_HIGH);141 byte_count |= rv_readl(rtd->acp3x_base +142 mmACP_I2S_TX_LINEARPOSITIONCNTR_LOW);143 }144 145 } else {146 switch (rtd->i2s_instance) {147 case I2S_BT_INSTANCE:148 byte_count = rv_readl(rtd->acp3x_base +149 mmACP_BT_RX_LINEARPOSITIONCNTR_HIGH);150 byte_count |= rv_readl(rtd->acp3x_base +151 mmACP_BT_RX_LINEARPOSITIONCNTR_LOW);152 break;153 case I2S_SP_INSTANCE:154 default:155 byte_count = rv_readl(rtd->acp3x_base +156 mmACP_I2S_RX_LINEARPOSITIONCNTR_HIGH);157 byte_count |= rv_readl(rtd->acp3x_base +158 mmACP_I2S_RX_LINEARPOSITIONCNTR_LOW);159 }160 }161 return byte_count;162}163