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1/* SPDX-License-Identifier: GPL-2.0+ */2/*3 * AMD ACP 3.0 Register Documentation4 *5 * Copyright 2016 Advanced Micro Devices, Inc.6 */7 8#ifndef _acp_ip_OFFSET_HEADER9#define _acp_ip_OFFSET_HEADER10// Registers from ACP_DMA block11 12#define mmACP_DMA_CNTL_0 0x124000013#define mmACP_DMA_CNTL_1 0x124000414#define mmACP_DMA_CNTL_2 0x124000815#define mmACP_DMA_CNTL_3 0x124000C16#define mmACP_DMA_CNTL_4 0x124001017#define mmACP_DMA_CNTL_5 0x124001418#define mmACP_DMA_CNTL_6 0x124001819#define mmACP_DMA_CNTL_7 0x124001C20#define mmACP_DMA_DSCR_STRT_IDX_0 0x124002021#define mmACP_DMA_DSCR_STRT_IDX_1 0x124002422#define mmACP_DMA_DSCR_STRT_IDX_2 0x124002823#define mmACP_DMA_DSCR_STRT_IDX_3 0x124002C24#define mmACP_DMA_DSCR_STRT_IDX_4 0x124003025#define mmACP_DMA_DSCR_STRT_IDX_5 0x124003426#define mmACP_DMA_DSCR_STRT_IDX_6 0x124003827#define mmACP_DMA_DSCR_STRT_IDX_7 0x124003C28#define mmACP_DMA_DSCR_CNT_0 0x124004029#define mmACP_DMA_DSCR_CNT_1 0x124004430#define mmACP_DMA_DSCR_CNT_2 0x124004831#define mmACP_DMA_DSCR_CNT_3 0x124004C32#define mmACP_DMA_DSCR_CNT_4 0x124005033#define mmACP_DMA_DSCR_CNT_5 0x124005434#define mmACP_DMA_DSCR_CNT_6 0x124005835#define mmACP_DMA_DSCR_CNT_7 0x124005C36#define mmACP_DMA_PRIO_0 0x124006037#define mmACP_DMA_PRIO_1 0x124006438#define mmACP_DMA_PRIO_2 0x124006839#define mmACP_DMA_PRIO_3 0x124006C40#define mmACP_DMA_PRIO_4 0x124007041#define mmACP_DMA_PRIO_5 0x124007442#define mmACP_DMA_PRIO_6 0x124007843#define mmACP_DMA_PRIO_7 0x124007C44#define mmACP_DMA_CUR_DSCR_0 0x124008045#define mmACP_DMA_CUR_DSCR_1 0x124008446#define mmACP_DMA_CUR_DSCR_2 0x124008847#define mmACP_DMA_CUR_DSCR_3 0x124008C48#define mmACP_DMA_CUR_DSCR_4 0x124009049#define mmACP_DMA_CUR_DSCR_5 0x124009450#define mmACP_DMA_CUR_DSCR_6 0x124009851#define mmACP_DMA_CUR_DSCR_7 0x124009C52#define mmACP_DMA_CUR_TRANS_CNT_0 0x12400A053#define mmACP_DMA_CUR_TRANS_CNT_1 0x12400A454#define mmACP_DMA_CUR_TRANS_CNT_2 0x12400A855#define mmACP_DMA_CUR_TRANS_CNT_3 0x12400AC56#define mmACP_DMA_CUR_TRANS_CNT_4 0x12400B057#define mmACP_DMA_CUR_TRANS_CNT_5 0x12400B458#define mmACP_DMA_CUR_TRANS_CNT_6 0x12400B859#define mmACP_DMA_CUR_TRANS_CNT_7 0x12400BC60#define mmACP_DMA_ERR_STS_0 0x12400C061#define mmACP_DMA_ERR_STS_1 0x12400C462#define mmACP_DMA_ERR_STS_2 0x12400C863#define mmACP_DMA_ERR_STS_3 0x12400CC64#define mmACP_DMA_ERR_STS_4 0x12400D065#define mmACP_DMA_ERR_STS_5 0x12400D466#define mmACP_DMA_ERR_STS_6 0x12400D867#define mmACP_DMA_ERR_STS_7 0x12400DC68#define mmACP_DMA_DESC_BASE_ADDR 0x12400E069#define mmACP_DMA_DESC_MAX_NUM_DSCR 0x12400E470#define mmACP_DMA_CH_STS 0x12400E871#define mmACP_DMA_CH_GROUP 0x12400EC72#define mmACP_DMA_CH_RST_STS 0x12400F073 74 75// Registers from ACP_AXI2AXIATU block76 77#define mmACPAXI2AXI_ATU_PAGE_SIZE_GRP_1 0x1240C0078#define mmACPAXI2AXI_ATU_BASE_ADDR_GRP_1 0x1240C0479#define mmACPAXI2AXI_ATU_PAGE_SIZE_GRP_2 0x1240C0880#define mmACPAXI2AXI_ATU_BASE_ADDR_GRP_2 0x1240C0C81#define mmACPAXI2AXI_ATU_PAGE_SIZE_GRP_3 0x1240C1082#define mmACPAXI2AXI_ATU_BASE_ADDR_GRP_3 0x1240C1483#define mmACPAXI2AXI_ATU_PAGE_SIZE_GRP_4 0x1240C1884#define mmACPAXI2AXI_ATU_BASE_ADDR_GRP_4 0x1240C1C85#define mmACPAXI2AXI_ATU_PAGE_SIZE_GRP_5 0x1240C2086#define mmACPAXI2AXI_ATU_BASE_ADDR_GRP_5 0x1240C2487#define mmACPAXI2AXI_ATU_PAGE_SIZE_GRP_6 0x1240C2888#define mmACPAXI2AXI_ATU_BASE_ADDR_GRP_6 0x1240C2C89#define mmACPAXI2AXI_ATU_PAGE_SIZE_GRP_7 0x1240C3090#define mmACPAXI2AXI_ATU_BASE_ADDR_GRP_7 0x1240C3491#define mmACPAXI2AXI_ATU_PAGE_SIZE_GRP_8 0x1240C3892#define mmACPAXI2AXI_ATU_BASE_ADDR_GRP_8 0x1240C3C93#define mmACPAXI2AXI_ATU_CTRL 0x1240C4094 95 96// Registers from ACP_CLKRST block97 98#define mmACP_SOFT_RESET 0x124100099#define mmACP_CONTROL 0x1241004100#define mmACP_STATUS 0x1241008101#define mmACP_DSP0_OCD_HALT_ON_RST 0x124100C102#define mmACP_DYNAMIC_CG_MASTER_CONTROL 0x1241010103 104 105// Registers from ACP_MISC block106 107#define mmACP_EXTERNAL_INTR_ENB 0x1241800108#define mmACP_EXTERNAL_INTR_CNTL 0x1241804109#define mmACP_EXTERNAL_INTR_STAT 0x1241808110#define mmACP_DSP0_INTR_CNTL 0x124180C111#define mmACP_DSP0_INTR_STAT 0x1241810112#define mmACP_DSP_SW_INTR_CNTL 0x1241814113#define mmACP_DSP_SW_INTR_STAT 0x1241818114#define mmACP_SW_INTR_TRIG 0x124181C115#define mmACP_SMU_MAILBOX 0x1241820116#define mmDSP_INTERRUPT_ROUTING_CTRL 0x1241824117#define mmACP_DSP0_WATCHDOG_TIMER_CNTL 0x1241828118#define mmACP_DSP0_EXT_TIMER1_CNTL 0x124182C119#define mmACP_DSP0_EXT_TIMER2_CNTL 0x1241830120#define mmACP_DSP0_EXT_TIMER3_CNTL 0x1241834121#define mmACP_DSP0_EXT_TIMER4_CNTL 0x1241838122#define mmACP_DSP0_EXT_TIMER5_CNTL 0x124183C123#define mmACP_DSP0_EXT_TIMER6_CNTL 0x1241840124#define mmACP_DSP0_EXT_TIMER1_CURR_VALUE 0x1241844125#define mmACP_DSP0_EXT_TIMER2_CURR_VALUE 0x1241848126#define mmACP_DSP0_EXT_TIMER3_CURR_VALUE 0x124184C127#define mmACP_DSP0_EXT_TIMER4_CURR_VALUE 0x1241850128#define mmACP_DSP0_EXT_TIMER5_CURR_VALUE 0x1241854129#define mmACP_DSP0_EXT_TIMER6_CURR_VALUE 0x1241858130#define mmACP_FW_STATUS 0x124185C131#define mmACP_TIMER 0x1241874132#define mmACP_TIMER_CNTL 0x1241878133#define mmACP_PGMEM_CTRL 0x12418C0134#define mmACP_ERROR_STATUS 0x12418C4135#define mmACP_SW_I2S_ERROR_REASON 0x12418C8136#define mmACP_MEM_PG_STS 0x12418CC137 138 139// Registers from ACP_PGFSM block140 141#define mmACP_I2S_PIN_CONFIG 0x1241400142#define mmACP_PAD_PULLUP_PULLDOWN_CTRL 0x1241404143#define mmACP_PAD_DRIVE_STRENGTH_CTRL 0x1241408144#define mmACP_SW_PAD_KEEPER_EN 0x124140C145#define mmACP_SW_WAKE_EN 0x1241410146#define mmACP_I2S_WAKE_EN 0x1241414147#define mmACP_PME_EN 0x1241418148#define mmACP_PGFSM_CONTROL 0x124141C149#define mmACP_PGFSM_STATUS 0x1241420150 151 152// Registers from ACP_SCRATCH block153 154#define mmACP_SCRATCH_REG_0 0x1250000155#define mmACP_SCRATCH_REG_1 0x1250004156#define mmACP_SCRATCH_REG_2 0x1250008157#define mmACP_SCRATCH_REG_3 0x125000C158#define mmACP_SCRATCH_REG_4 0x1250010159#define mmACP_SCRATCH_REG_5 0x1250014160#define mmACP_SCRATCH_REG_6 0x1250018161#define mmACP_SCRATCH_REG_7 0x125001C162#define mmACP_SCRATCH_REG_8 0x1250020163#define mmACP_SCRATCH_REG_9 0x1250024164#define mmACP_SCRATCH_REG_10 0x1250028165#define mmACP_SCRATCH_REG_11 0x125002C166#define mmACP_SCRATCH_REG_12 0x1250030167#define mmACP_SCRATCH_REG_13 0x1250034168#define mmACP_SCRATCH_REG_14 0x1250038169#define mmACP_SCRATCH_REG_15 0x125003C170#define mmACP_SCRATCH_REG_16 0x1250040171#define mmACP_SCRATCH_REG_17 0x1250044172#define mmACP_SCRATCH_REG_18 0x1250048173#define mmACP_SCRATCH_REG_19 0x125004C174#define mmACP_SCRATCH_REG_20 0x1250050175#define mmACP_SCRATCH_REG_21 0x1250054176#define mmACP_SCRATCH_REG_22 0x1250058177#define mmACP_SCRATCH_REG_23 0x125005C178#define mmACP_SCRATCH_REG_24 0x1250060179#define mmACP_SCRATCH_REG_25 0x1250064180#define mmACP_SCRATCH_REG_26 0x1250068181#define mmACP_SCRATCH_REG_27 0x125006C182#define mmACP_SCRATCH_REG_28 0x1250070183#define mmACP_SCRATCH_REG_29 0x1250074184#define mmACP_SCRATCH_REG_30 0x1250078185#define mmACP_SCRATCH_REG_31 0x125007C186#define mmACP_SCRATCH_REG_32 0x1250080187#define mmACP_SCRATCH_REG_33 0x1250084188#define mmACP_SCRATCH_REG_34 0x1250088189#define mmACP_SCRATCH_REG_35 0x125008C190#define mmACP_SCRATCH_REG_36 0x1250090191#define mmACP_SCRATCH_REG_37 0x1250094192#define mmACP_SCRATCH_REG_38 0x1250098193#define mmACP_SCRATCH_REG_39 0x125009C194#define mmACP_SCRATCH_REG_40 0x12500A0195#define mmACP_SCRATCH_REG_41 0x12500A4196#define mmACP_SCRATCH_REG_42 0x12500A8197#define mmACP_SCRATCH_REG_43 0x12500AC198#define mmACP_SCRATCH_REG_44 0x12500B0199#define mmACP_SCRATCH_REG_45 0x12500B4200#define mmACP_SCRATCH_REG_46 0x12500B8201#define mmACP_SCRATCH_REG_47 0x12500BC202#define mmACP_SCRATCH_REG_48 0x12500C0203#define mmACP_SCRATCH_REG_49 0x12500C4204#define mmACP_SCRATCH_REG_50 0x12500C8205#define mmACP_SCRATCH_REG_51 0x12500CC206#define mmACP_SCRATCH_REG_52 0x12500D0207#define mmACP_SCRATCH_REG_53 0x12500D4208#define mmACP_SCRATCH_REG_54 0x12500D8209#define mmACP_SCRATCH_REG_55 0x12500DC210#define mmACP_SCRATCH_REG_56 0x12500E0211#define mmACP_SCRATCH_REG_57 0x12500E4212#define mmACP_SCRATCH_REG_58 0x12500E8213#define mmACP_SCRATCH_REG_59 0x12500EC214#define mmACP_SCRATCH_REG_60 0x12500F0215#define mmACP_SCRATCH_REG_61 0x12500F4216#define mmACP_SCRATCH_REG_62 0x12500F8217#define mmACP_SCRATCH_REG_63 0x12500FC218#define mmACP_SCRATCH_REG_64 0x1250100219#define mmACP_SCRATCH_REG_65 0x1250104220#define mmACP_SCRATCH_REG_66 0x1250108221#define mmACP_SCRATCH_REG_67 0x125010C222#define mmACP_SCRATCH_REG_68 0x1250110223#define mmACP_SCRATCH_REG_69 0x1250114224#define mmACP_SCRATCH_REG_70 0x1250118225#define mmACP_SCRATCH_REG_71 0x125011C226#define mmACP_SCRATCH_REG_72 0x1250120227#define mmACP_SCRATCH_REG_73 0x1250124228#define mmACP_SCRATCH_REG_74 0x1250128229#define mmACP_SCRATCH_REG_75 0x125012C230#define mmACP_SCRATCH_REG_76 0x1250130231#define mmACP_SCRATCH_REG_77 0x1250134232#define mmACP_SCRATCH_REG_78 0x1250138233#define mmACP_SCRATCH_REG_79 0x125013C234#define mmACP_SCRATCH_REG_80 0x1250140235#define mmACP_SCRATCH_REG_81 0x1250144236#define mmACP_SCRATCH_REG_82 0x1250148237#define mmACP_SCRATCH_REG_83 0x125014C238#define mmACP_SCRATCH_REG_84 0x1250150239#define mmACP_SCRATCH_REG_85 0x1250154240#define mmACP_SCRATCH_REG_86 0x1250158241#define mmACP_SCRATCH_REG_87 0x125015C242#define mmACP_SCRATCH_REG_88 0x1250160243#define mmACP_SCRATCH_REG_89 0x1250164244#define mmACP_SCRATCH_REG_90 0x1250168245#define mmACP_SCRATCH_REG_91 0x125016C246#define mmACP_SCRATCH_REG_92 0x1250170247#define mmACP_SCRATCH_REG_93 0x1250174248#define mmACP_SCRATCH_REG_94 0x1250178249#define mmACP_SCRATCH_REG_95 0x125017C250#define mmACP_SCRATCH_REG_96 0x1250180251#define mmACP_SCRATCH_REG_97 0x1250184252#define mmACP_SCRATCH_REG_98 0x1250188253#define mmACP_SCRATCH_REG_99 0x125018C254#define mmACP_SCRATCH_REG_100 0x1250190255#define mmACP_SCRATCH_REG_101 0x1250194256#define mmACP_SCRATCH_REG_102 0x1250198257#define mmACP_SCRATCH_REG_103 0x125019C258#define mmACP_SCRATCH_REG_104 0x12501A0259#define mmACP_SCRATCH_REG_105 0x12501A4260#define mmACP_SCRATCH_REG_106 0x12501A8261#define mmACP_SCRATCH_REG_107 0x12501AC262#define mmACP_SCRATCH_REG_108 0x12501B0263#define mmACP_SCRATCH_REG_109 0x12501B4264#define mmACP_SCRATCH_REG_110 0x12501B8265#define mmACP_SCRATCH_REG_111 0x12501BC266#define mmACP_SCRATCH_REG_112 0x12501C0267#define mmACP_SCRATCH_REG_113 0x12501C4268#define mmACP_SCRATCH_REG_114 0x12501C8269#define mmACP_SCRATCH_REG_115 0x12501CC270#define mmACP_SCRATCH_REG_116 0x12501D0271#define mmACP_SCRATCH_REG_117 0x12501D4272#define mmACP_SCRATCH_REG_118 0x12501D8273#define mmACP_SCRATCH_REG_119 0x12501DC274#define mmACP_SCRATCH_REG_120 0x12501E0275#define mmACP_SCRATCH_REG_121 0x12501E4276#define mmACP_SCRATCH_REG_122 0x12501E8277#define mmACP_SCRATCH_REG_123 0x12501EC278#define mmACP_SCRATCH_REG_124 0x12501F0279#define mmACP_SCRATCH_REG_125 0x12501F4280#define mmACP_SCRATCH_REG_126 0x12501F8281#define mmACP_SCRATCH_REG_127 0x12501FC282#define mmACP_SCRATCH_REG_128 0x1250200283 284 285// Registers from ACP_SW_ACLK block286 287#define mmSW_CORB_Base_Address 0x1243200288#define mmSW_CORB_Write_Pointer 0x1243204289#define mmSW_CORB_Read_Pointer 0x1243208290#define mmSW_CORB_Control 0x124320C291#define mmSW_CORB_Size 0x1243214292#define mmSW_RIRB_Base_Address 0x1243218293#define mmSW_RIRB_Write_Pointer 0x124321C294#define mmSW_RIRB_Response_Interrupt_Count 0x1243220295#define mmSW_RIRB_Control 0x1243224296#define mmSW_RIRB_Size 0x1243228297#define mmSW_RIRB_FIFO_MIN_THDL 0x124322C298#define mmSW_imm_cmd_UPPER_WORD 0x1243230299#define mmSW_imm_cmd_LOWER_QWORD 0x1243234300#define mmSW_imm_resp_UPPER_WORD 0x1243238301#define mmSW_imm_resp_LOWER_QWORD 0x124323C302#define mmSW_imm_cmd_sts 0x1243240303#define mmSW_BRA_BASE_ADDRESS 0x1243244304#define mmSW_BRA_TRANSFER_SIZE 0x1243248305#define mmSW_BRA_DMA_BUSY 0x124324C306#define mmSW_BRA_RESP 0x1243250307#define mmSW_BRA_RESP_FRAME_ADDR 0x1243254308#define mmSW_BRA_CURRENT_TRANSFER_SIZE 0x1243258309#define mmSW_STATE_CHANGE_STATUS_0TO7 0x124325C310#define mmSW_STATE_CHANGE_STATUS_8TO11 0x1243260311#define mmSW_STATE_CHANGE_STATUS_MASK_0to7 0x1243264312#define mmSW_STATE_CHANGE_STATUS_MASK_8to11 0x1243268313#define mmSW_CLK_FREQUENCY_CTRL 0x124326C314#define mmSW_ERROR_INTR_MASK 0x1243270315#define mmSW_PHY_TEST_MODE_DATA_OFF 0x1243274316 317 318// Registers from ACP_SW_SWCLK block319 320#define mmACP_SW_EN 0x1243000321#define mmACP_SW_EN_STATUS 0x1243004322#define mmACP_SW_FRAMESIZE 0x1243008323#define mmACP_SW_SSP_Counter 0x124300C324#define mmACP_SW_Audio_TX_EN 0x1243010325#define mmACP_SW_Audio_TX_EN_STATUS 0x1243014326#define mmACP_SW_Audio_TX_Frame_Format 0x1243018327#define mmACP_SW_Audio_TX_SampleInterval 0x124301C328#define mmACP_SW_Audio_TX_Hctrl_DP0 0x1243020329#define mmACP_SW_Audio_TX_Hctrl_DP1 0x1243024330#define mmACP_SW_Audio_TX_Hctrl_DP2 0x1243028331#define mmACP_SW_Audio_TX_Hctrl_DP3 0x124302C332#define mmACP_SW_Audio_TX_offset_DP0 0x1243030333#define mmACP_SW_Audio_TX_offset_DP1 0x1243034334#define mmACP_SW_Audio_TX_offset_DP2 0x1243038335#define mmACP_SW_Audio_TX_offset_DP3 0x124303C336#define mmACP_SW_Audio_TX_Channel_Enable_DP0 0x1243040337#define mmACP_SW_Audio_TX_Channel_Enable_DP1 0x1243044338#define mmACP_SW_Audio_TX_Channel_Enable_DP2 0x1243048339#define mmACP_SW_Audio_TX_Channel_Enable_DP3 0x124304C340#define mmACP_SW_BT_TX_EN 0x1243050341#define mmACP_SW_BT_TX_EN_STATUS 0x1243054342#define mmACP_SW_BT_TX_Frame_Format 0x1243058343#define mmACP_SW_BT_TX_SampleInterval 0x124305C344#define mmACP_SW_BT_TX_Hctrl 0x1243060345#define mmACP_SW_BT_TX_offset 0x1243064346#define mmACP_SW_BT_TX_Channel_Enable_DP0 0x1243068347#define mmACP_SW_Headset_TX_EN 0x124306C348#define mmACP_SW_Headset_TX_EN_STATUS 0x1243070349#define mmACP_SW_Headset_TX_Frame_Format 0x1243074350#define mmACP_SW_Headset_TX_SampleInterval 0x1243078351#define mmACP_SW_Headset_TX_Hctrl 0x124307C352#define mmACP_SW_Headset_TX_offset 0x1243080353#define mmACP_SW_Headset_TX_Channel_Enable_DP0 0x1243084354#define mmACP_SW_Audio_RX_EN 0x1243088355#define mmACP_SW_Audio_RX_EN_STATUS 0x124308C356#define mmACP_SW_Audio_RX_Frame_Format 0x1243090357#define mmACP_SW_Audio_RX_SampleInterval 0x1243094358#define mmACP_SW_Audio_RX_Hctrl_DP0 0x1243098359#define mmACP_SW_Audio_RX_Hctrl_DP1 0x124309C360#define mmACP_SW_Audio_RX_Hctrl_DP2 0x1243100361#define mmACP_SW_Audio_RX_Hctrl_DP3 0x1243104362#define mmACP_SW_Audio_RX_offset_DP0 0x1243108363#define mmACP_SW_Audio_RX_offset_DP1 0x124310C364#define mmACP_SW_Audio_RX_offset_DP2 0x1243110365#define mmACP_SW_Audio_RX_offset_DP3 0x1243114366#define mmACP_SW_Audio_RX_Channel_Enable_DP0 0x1243118367#define mmACP_SW_Audio_RX_Channel_Enable_DP1 0x124311C368#define mmACP_SW_Audio_RX_Channel_Enable_DP2 0x1243120369#define mmACP_SW_Audio_RX_Channel_Enable_DP3 0x1243124370#define mmACP_SW_BT_RX_EN 0x1243128371#define mmACP_SW_BT_RX_EN_STATUS 0x124312C372#define mmACP_SW_BT_RX_Frame_Format 0x1243130373#define mmACP_SW_BT_RX_SampleInterval 0x1243134374#define mmACP_SW_BT_RX_Hctrl 0x1243138375#define mmACP_SW_BT_RX_offset 0x124313C376#define mmACP_SW_BT_RX_Channel_Enable_DP0 0x1243140377#define mmACP_SW_Headset_RX_EN 0x1243144378#define mmACP_SW_Headset_RX_EN_STATUS 0x1243148379#define mmACP_SW_Headset_RX_Frame_Format 0x124314C380#define mmACP_SW_Headset_RX_SampleInterval 0x1243150381#define mmACP_SW_Headset_RX_Hctrl 0x1243154382#define mmACP_SW_Headset_RX_offset 0x1243158383#define mmACP_SW_Headset_RX_Channel_Enable_DP0 0x124315C384#define mmACP_SW_BPT_PORT_EN 0x1243160385#define mmACP_SW_BPT_PORT_EN_STATUS 0x1243164386#define mmACP_SW_BPT_PORT_Frame_Format 0x1243168387#define mmACP_SW_BPT_PORT_SampleInterval 0x124316C388#define mmACP_SW_BPT_PORT_Hctrl 0x1243170389#define mmACP_SW_BPT_PORT_offset 0x1243174390#define mmACP_SW_BPT_PORT_Channel_Enable 0x1243178391#define mmACP_SW_BPT_PORT_First_byte_addr 0x124317C392#define mmACP_SW_CLK_RESUME_CTRL 0x1243180393#define mmACP_SW_CLK_RESUME_Delay_Cntr 0x1243184394#define mmACP_SW_BUS_RESET_CTRL 0x1243188395#define mmACP_SW_PRBS_ERR_STATUS 0x124318C396 397 398// Registers from ACP_AUDIO_BUFFERS block399 400#define mmACP_I2S_RX_RINGBUFADDR 0x1242000401#define mmACP_I2S_RX_RINGBUFSIZE 0x1242004402#define mmACP_I2S_RX_LINKPOSITIONCNTR 0x1242008403#define mmACP_I2S_RX_FIFOADDR 0x124200C404#define mmACP_I2S_RX_FIFOSIZE 0x1242010405#define mmACP_I2S_RX_DMA_SIZE 0x1242014406#define mmACP_I2S_RX_LINEARPOSITIONCNTR_HIGH 0x1242018407#define mmACP_I2S_RX_LINEARPOSITIONCNTR_LOW 0x124201C408#define mmACP_I2S_RX_INTR_WATERMARK_SIZE 0x1242020409#define mmACP_I2S_TX_RINGBUFADDR 0x1242024410#define mmACP_I2S_TX_RINGBUFSIZE 0x1242028411#define mmACP_I2S_TX_LINKPOSITIONCNTR 0x124202C412#define mmACP_I2S_TX_FIFOADDR 0x1242030413#define mmACP_I2S_TX_FIFOSIZE 0x1242034414#define mmACP_I2S_TX_DMA_SIZE 0x1242038415#define mmACP_I2S_TX_LINEARPOSITIONCNTR_HIGH 0x124203C416#define mmACP_I2S_TX_LINEARPOSITIONCNTR_LOW 0x1242040417#define mmACP_I2S_TX_INTR_WATERMARK_SIZE 0x1242044418#define mmACP_BT_RX_RINGBUFADDR 0x1242048419#define mmACP_BT_RX_RINGBUFSIZE 0x124204C420#define mmACP_BT_RX_LINKPOSITIONCNTR 0x1242050421#define mmACP_BT_RX_FIFOADDR 0x1242054422#define mmACP_BT_RX_FIFOSIZE 0x1242058423#define mmACP_BT_RX_DMA_SIZE 0x124205C424#define mmACP_BT_RX_LINEARPOSITIONCNTR_HIGH 0x1242060425#define mmACP_BT_RX_LINEARPOSITIONCNTR_LOW 0x1242064426#define mmACP_BT_RX_INTR_WATERMARK_SIZE 0x1242068427#define mmACP_BT_TX_RINGBUFADDR 0x124206C428#define mmACP_BT_TX_RINGBUFSIZE 0x1242070429#define mmACP_BT_TX_LINKPOSITIONCNTR 0x1242074430#define mmACP_BT_TX_FIFOADDR 0x1242078431#define mmACP_BT_TX_FIFOSIZE 0x124207C432#define mmACP_BT_TX_DMA_SIZE 0x1242080433#define mmACP_BT_TX_LINEARPOSITIONCNTR_HIGH 0x1242084434#define mmACP_BT_TX_LINEARPOSITIONCNTR_LOW 0x1242088435#define mmACP_BT_TX_INTR_WATERMARK_SIZE 0x124208C436#define mmACP_HS_RX_RINGBUFADDR 0x1242090437#define mmACP_HS_RX_RINGBUFSIZE 0x1242094438#define mmACP_HS_RX_LINKPOSITIONCNTR 0x1242098439#define mmACP_HS_RX_FIFOADDR 0x124209C440#define mmACP_HS_RX_FIFOSIZE 0x12420A0441#define mmACP_HS_RX_DMA_SIZE 0x12420A4442#define mmACP_HS_RX_LINEARPOSITIONCNTR_HIGH 0x12420A8443#define mmACP_HS_RX_LINEARPOSITIONCNTR_LOW 0x12420AC444#define mmACP_HS_RX_INTR_WATERMARK_SIZE 0x12420B0445#define mmACP_HS_TX_RINGBUFADDR 0x12420B4446#define mmACP_HS_TX_RINGBUFSIZE 0x12420B8447#define mmACP_HS_TX_LINKPOSITIONCNTR 0x12420BC448#define mmACP_HS_TX_FIFOADDR 0x12420C0449#define mmACP_HS_TX_FIFOSIZE 0x12420C4450#define mmACP_HS_TX_DMA_SIZE 0x12420C8451#define mmACP_HS_TX_LINEARPOSITIONCNTR_HIGH 0x12420CC452#define mmACP_HS_TX_LINEARPOSITIONCNTR_LOW 0x12420D0453#define mmACP_HS_TX_INTR_WATERMARK_SIZE 0x12420D4454 455 456// Registers from ACP_I2S_TDM block457 458#define mmACP_I2STDM_IER 0x1242400459#define mmACP_I2STDM_IRER 0x1242404460#define mmACP_I2STDM_RXFRMT 0x1242408461#define mmACP_I2STDM_ITER 0x124240C462#define mmACP_I2STDM_TXFRMT 0x1242410463 464 465// Registers from ACP_BT_TDM block466 467#define mmACP_BTTDM_IER 0x1242800468#define mmACP_BTTDM_IRER 0x1242804469#define mmACP_BTTDM_RXFRMT 0x1242808470#define mmACP_BTTDM_ITER 0x124280C471#define mmACP_BTTDM_TXFRMT 0x1242810472 473 474// Registers from AZALIA_IP block475 476#define mmAudio_Az_Global_Capabilities 0x1200000477#define mmAudio_Az_Minor_Version 0x1200002478#define mmAudio_Az_Major_Version 0x1200003479#define mmAudio_Az_Output_Payload_Capability 0x1200004480#define mmAudio_Az_Input_Payload_Capability 0x1200006481#define mmAudio_Az_Global_Control 0x1200008482#define mmAudio_Az_Wake_Enable 0x120000C483#define mmAudio_Az_State_Change_Status 0x120000E484#define mmAudio_Az_Global_Status 0x1200010485#define mmAudio_Az_Linked_List_Capability_Header 0x1200014486#define mmAudio_Az_Output_Stream_Payload_Capability 0x1200018487#define mmAudio_Az_Input_Stream_Payload_Capability 0x120001A488#define mmAudio_Az_Interrupt_Control 0x1200020489#define mmAudio_Az_Interrupt_Status 0x1200024490#define mmAudio_Az_Wall_Clock_Counter 0x1200030491#define mmAudio_Az_Stream_Synchronization 0x1200038492#define mmAudio_Az_CORB_Lower_Base_Address 0x1200040493#define mmAudio_Az_CORB_Upper_Base_Address 0x1200044494#define mmAudio_Az_CORB_Write_Pointer 0x1200048495#define mmAudio_Az_CORB_Read_Pointer 0x120004A496#define mmAudio_Az_CORB_Control 0x120004C497#define mmAudio_Az_CORB_Status 0x120004D498#define mmAudio_Az_CORB_Size 0x120004E499#define mmAudio_Az_RIRB_Lower_Base_Address 0x1200050500#define mmAudio_Az_RIRB_Upper_Base_Address 0x1200054501#define mmAudio_Az_RIRB_Write_Pointer 0x1200058502#define mmAudio_Az_RIRB_Response_Interrupt_Count 0x120005A503#define mmAudio_Az_RIRB_Control 0x120005C504#define mmAudio_Az_RIRB_Status 0x120005D505#define mmAudio_Az_RIRB_Size 0x120005E506#define mmAudio_Az_Immediate_Command_Output_Interface 0x1200060507#define mmAudio_Az_Immediate_Response_Input_Interface 0x1200064508#define mmAudio_Az_Immediate_Command_Status 0x1200068509#define mmAudio_Az_DPLBASE 0x1200070510#define mmAudio_Az_DPUBASE 0x1200074511#define mmAudio_Az_Input_SD0CTL_and_STS 0x1200080512#define mmAudio_Az_Input_SD0LPIB 0x1200084513#define mmAudio_Az_Input_SD0CBL 0x1200088514#define mmAudio_Az_Input_SD0LVI 0x120008C515#define mmAudio_Az_Input_SD0FIFOS 0x1200090516#define mmAudio_Az_Input_SD0FMT 0x1200092517#define mmAudio_Az_Input_SD0BDPL 0x1200098518#define mmAudio_Az_Input_SD0BDPU 0x120009C519#define mmAudio_Az_Input_SD1CTL_and_STS 0x12000A0520#define mmAudio_Az_Input_SD1LPIB 0x12000A4521#define mmAudio_Az_Input_SD1CBL 0x12000A8522#define mmAudio_Az_Input_SD1LVI 0x12000AC523#define mmAudio_Az_Input_SD1FIFOS 0x12000B0524#define mmAudio_Az_Input_SD1FMT 0x12000B2525#define mmAudio_Az_Input_SD1BDPL 0x12000B8526#define mmAudio_Az_Input_SD1BDPU 0x12000BC527#define mmAudio_Az_Input_SD2CTL_and_STS 0x12000C0528#define mmAudio_Az_Input_SD2LPIB 0x12000C4529#define mmAudio_Az_Input_SD2CBL 0x12000C8530#define mmAudio_Az_Input_SD2LVI 0x12000CC531#define mmAudio_Az_Input_SD2FIFOS 0x12000D0532#define mmAudio_Az_Input_SD2FMT 0x12000D2533#define mmAudio_Az_Input_SD2BDPL 0x12000D8534#define mmAudio_Az_Input_SD2BDPU 0x12000DC535#define mmAudio_Az_Input_SD3CTL_and_STS 0x12000E0536#define mmAudio_Az_Input_SD3LPIB 0x12000E4537#define mmAudio_Az_Input_SD3CBL 0x12000E8538#define mmAudio_Az_Input_SD3LVI 0x12000EC539#define mmAudio_Az_Input_SD3FIFOS 0x12000F0540#define mmAudio_Az_Input_SD3FMT 0x12000F2541#define mmAudio_Az_Input_SD3BDPL 0x12000F8542#define mmAudio_Az_Input_SD3BDPU 0x12000FC543#define mmAudio_Az_Output_SD0CTL_and_STS 0x1200100544#define mmAudio_Az_Output_SD0LPIB 0x1200104545#define mmAudio_Az_Output_SD0CBL 0x1200108546#define mmAudio_Az_Output_SD0LVI 0x120010C547#define mmAudio_Az_Output_SD0FIFOS 0x1200110548#define mmAudio_Az_Output_SD0FMT 0x1200112549#define mmAudio_Az_Output_SD0BDPL 0x1200118550#define mmAudio_Az_Output_SD0BDPU 0x120011C551#define mmAudio_Az_Output_SD1CTL_and_STS 0x1200120552#define mmAudio_Az_Output_SD1LPIB 0x1200124553#define mmAudio_Az_Output_SD1CBL 0x1200128554#define mmAudio_Az_Output_SD1LVI 0x120012C555#define mmAudio_Az_Output_SD1FIFOS 0x1200130556#define mmAudio_Az_Output_SD1FMT 0x1200132557#define mmAudio_Az_Output_SD1BDPL 0x1200138558#define mmAudio_Az_Output_SD1BDPU 0x120013C559#define mmAudio_Az_Output_SD2CTL_and_STS 0x1200140560#define mmAudio_Az_Output_SD2LPIB 0x1200144561#define mmAudio_Az_Output_SD2CBL 0x1200148562#define mmAudio_Az_Output_SD2LVI 0x120014C563#define mmAudio_Az_Output_SD2FIFOS 0x1200150564#define mmAudio_Az_Output_SD2FMT 0x1200152565#define mmAudio_Az_Output_SD2BDPL 0x1200158566#define mmAudio_Az_Output_SD2BDPU 0x120015C567#define mmAudio_Az_Output_SD3CTL_and_STS 0x1200160568#define mmAudio_Az_Output_SD3LPIB 0x1200164569#define mmAudio_Az_Output_SD3CBL 0x1200168570#define mmAudio_Az_Output_SD3LVI 0x120016C571#define mmAudio_Az_Output_SD3FIFOS 0x1200170572#define mmAudio_Az_Output_SD3FMT 0x1200172573#define mmAudio_Az_Output_SD3BDPL 0x1200178574#define mmAudio_Az_Output_SD3BDPU 0x120017C575#define mmAudioAZ_Misc_Control_Register_1 0x1200180576#define mmAudioAZ_Misc_Control_Register_2 0x1200182577#define mmAudioAZ_Misc_Control_Register_3 0x1200183578#define mmAudio_AZ_Multiple_Links_Capability_Header 0x1200200579#define mmAudio_AZ_Multiple_Links_Capability_Declaration 0x1200204580#define mmAudio_AZ_Link0_Capabilities 0x1200240581#define mmAudio_AZ_Link0_Control 0x1200244582#define mmAudio_AZ_Link0_Output_Stream_ID 0x1200248583#define mmAudio_AZ_Link0_SDI_Identifier 0x120024C584#define mmAudio_AZ_Link0_Per_Stream_Overhead 0x1200250585#define mmAudio_AZ_Link0_Wall_Frame_Counter 0x1200258586#define mmAudio_AZ_Link0_Output_Payload_Capability_L 0x1200260587#define mmAudio_AZ_Link0_Output_Payload_Capability_U 0x1200264588#define mmAudio_AZ_Link0_Input_Payload_Capability_L 0x1200270589#define mmAudio_AZ_Link0_Input_Payload_Capability_U 0x1200274590#define mmAudio_Az_Input_SD0LICBA 0x1202084591#define mmAudio_Az_Input_SD1LICBA 0x12020A4592#define mmAudio_Az_Input_SD2LICBA 0x12020C4593#define mmAudio_Az_Input_SD3LICBA 0x12020E4594#define mmAudio_Az_Output_SD0LICBA 0x1202104595#define mmAudio_Az_Output_SD1LICBA 0x1202124596#define mmAudio_Az_Output_SD2LICBA 0x1202144597#define mmAudio_Az_Output_SD3LICBA 0x1202164598#define mmAUDIO_AZ_POWER_MANAGEMENT_CONTROL 0x1204000599#define mmAUDIO_AZ_IOC_SOFTRST_CONTROL 0x1204004600#define mmAUDIO_AZ_IOC_CLKGATE_CONTROL 0x1204008601 602 603// Registers from ACP_AZALIA block604 605#define mmACP_AZ_PAGE0_LBASE_ADDR 0x1243800606#define mmACP_AZ_PAGE0_UBASE_ADDR 0x1243804607#define mmACP_AZ_PAGE0_PGEN_SIZE 0x1243808608#define mmACP_AZ_PAGE0_OFFSET 0x124380C609#define mmACP_AZ_PAGE1_LBASE_ADDR 0x1243810610#define mmACP_AZ_PAGE1_UBASE_ADDR 0x1243814611#define mmACP_AZ_PAGE1_PGEN_SIZE 0x1243818612#define mmACP_AZ_PAGE1_OFFSET 0x124381C613#define mmACP_AZ_PAGE2_LBASE_ADDR 0x1243820614#define mmACP_AZ_PAGE2_UBASE_ADDR 0x1243824615#define mmACP_AZ_PAGE2_PGEN_SIZE 0x1243828616#define mmACP_AZ_PAGE2_OFFSET 0x124382C617#define mmACP_AZ_PAGE3_LBASE_ADDR 0x1243830618#define mmACP_AZ_PAGE3_UBASE_ADDR 0x1243834619#define mmACP_AZ_PAGE3_PGEN_SIZE 0x1243838620#define mmACP_AZ_PAGE3_OFFSET 0x124383C621#define mmACP_AZ_PAGE4_LBASE_ADDR 0x1243840622#define mmACP_AZ_PAGE4_UBASE_ADDR 0x1243844623#define mmACP_AZ_PAGE4_PGEN_SIZE 0x1243848624#define mmACP_AZ_PAGE4_OFFSET 0x124384C625#define mmACP_AZ_PAGE5_LBASE_ADDR 0x1243850626#define mmACP_AZ_PAGE5_UBASE_ADDR 0x1243854627#define mmACP_AZ_PAGE5_PGEN_SIZE 0x1243858628#define mmACP_AZ_PAGE5_OFFSET 0x124385C629#define mmACP_AZ_PAGE6_LBASE_ADDR 0x1243860630#define mmACP_AZ_PAGE6_UBASE_ADDR 0x1243864631#define mmACP_AZ_PAGE6_PGEN_SIZE 0x1243868632#define mmACP_AZ_PAGE6_OFFSET 0x124386C633#define mmACP_AZ_PAGE7_LBASE_ADDR 0x1243870634#define mmACP_AZ_PAGE7_UBASE_ADDR 0x1243874635#define mmACP_AZ_PAGE7_PGEN_SIZE 0x1243878636#define mmACP_AZ_PAGE7_OFFSET 0x124387C637 638 639#endif640