94 lines · c
1/* SPDX-License-Identifier: GPL-2.0+ */2/*3 * AMD ALSA SoC PDM Driver4 *5 * Copyright 2020 Advanced Micro Devices, Inc.6 */7 8#include "rn_chip_offset_byte.h"9 10#define ACP_DEVS 311#define ACP_PHY_BASE_ADDRESS 0x124000012#define ACP_REG_START 0x124000013#define ACP_REG_END 0x125020014 15#define ACP_DEVICE_ID 0x15E216#define ACP_POWER_ON 0x0017#define ACP_POWER_ON_IN_PROGRESS 0x0118#define ACP_POWER_OFF 0x0219#define ACP_POWER_OFF_IN_PROGRESS 0x0320#define ACP_SOFT_RESET_SOFTRESET_AUDDONE_MASK 0x0001000121 22#define ACP_PGFSM_CNTL_POWER_ON_MASK 0x0123#define ACP_PGFSM_CNTL_POWER_OFF_MASK 0x0024#define ACP_PGFSM_STATUS_MASK 0x0325#define ACP_POWERED_ON 0x0026#define ACP_POWER_ON_IN_PROGRESS 0x0127#define ACP_POWERED_OFF 0x0228#define ACP_POWER_OFF_IN_PROGRESS 0x0329 30#define ACP_ERROR_MASK 0x2000000031#define ACP_EXT_INTR_STAT_CLEAR_MASK 0xFFFFFFFF32#define PDM_DMA_STAT 0x1033#define PDM_DMA_INTR_MASK 0x1000034#define ACP_ERROR_STAT 2935#define PDM_DECIMATION_FACTOR 0x236#define ACP_PDM_CLK_FREQ_MASK 0x0737#define ACP_WOV_GAIN_CONTROL GENMASK(4, 3)38#define ACP_PDM_ENABLE 0x0139#define ACP_PDM_DISABLE 0x0040#define ACP_PDM_DMA_EN_STATUS 0x0241#define TWO_CH 0x0242#define DELAY_US 543#define ACP_COUNTER 2000044/* time in ms for runtime suspend delay */45#define ACP_SUSPEND_DELAY_MS 200046 47#define ACP_SRAM_PTE_OFFSET 0x0205000048#define PAGE_SIZE_4K_ENABLE 0x249#define MEM_WINDOW_START 0x400000050 51#define CAPTURE_MIN_NUM_PERIODS 452#define CAPTURE_MAX_NUM_PERIODS 453#define CAPTURE_MAX_PERIOD_SIZE 819254#define CAPTURE_MIN_PERIOD_SIZE 409655 56#define MAX_BUFFER (CAPTURE_MAX_PERIOD_SIZE * CAPTURE_MAX_NUM_PERIODS)57#define MIN_BUFFER MAX_BUFFER58#define ACP_DMIC_AUTO -159 60struct pdm_dev_data {61 u32 pdm_irq;62 void __iomem *acp_base;63 struct snd_pcm_substream *capture_stream;64};65 66struct pdm_stream_instance {67 u16 num_pages;68 u16 channels;69 dma_addr_t dma_addr;70 u64 bytescount;71 void __iomem *acp_base;72};73 74union acp_pdm_dma_count {75 struct {76 u32 low;77 u32 high;78 } bcount;79 u64 bytescount;80};81 82static inline u32 rn_readl(void __iomem *base_addr)83{84 return readl(base_addr - ACP_PHY_BASE_ADDRESS);85}86 87static inline void rn_writel(u32 val, void __iomem *base_addr)88{89 writel(val, base_addr - ACP_PHY_BASE_ADDRESS);90}91 92/* Machine configuration */93int snd_amd_acp_find_config(struct pci_dev *pci);94