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1/* SPDX-License-Identifier: GPL-2.0+ */2/*3 * AMD ACP 3.1 Register Documentation4 *5 * Copyright 2020 Advanced Micro Devices, Inc.6 */7 8#ifndef _rn_OFFSET_HEADER9#define _rn_OFFSET_HEADER10// Registers from ACP_DMA block11 12#define ACP_DMA_CNTL_0 0x124000013#define ACP_DMA_CNTL_1 0x124000414#define ACP_DMA_CNTL_2 0x124000815#define ACP_DMA_CNTL_3 0x124000C16#define ACP_DMA_CNTL_4 0x124001017#define ACP_DMA_CNTL_5 0x124001418#define ACP_DMA_CNTL_6 0x124001819#define ACP_DMA_CNTL_7 0x124001C20#define ACP_DMA_DSCR_STRT_IDX_0 0x124002021#define ACP_DMA_DSCR_STRT_IDX_1 0x124002422#define ACP_DMA_DSCR_STRT_IDX_2 0x124002823#define ACP_DMA_DSCR_STRT_IDX_3 0x124002C24#define ACP_DMA_DSCR_STRT_IDX_4 0x124003025#define ACP_DMA_DSCR_STRT_IDX_5 0x124003426#define ACP_DMA_DSCR_STRT_IDX_6 0x124003827#define ACP_DMA_DSCR_STRT_IDX_7 0x124003C28#define ACP_DMA_DSCR_CNT_0 0x124004029#define ACP_DMA_DSCR_CNT_1 0x124004430#define ACP_DMA_DSCR_CNT_2 0x124004831#define ACP_DMA_DSCR_CNT_3 0x124004C32#define ACP_DMA_DSCR_CNT_4 0x124005033#define ACP_DMA_DSCR_CNT_5 0x124005434#define ACP_DMA_DSCR_CNT_6 0x124005835#define ACP_DMA_DSCR_CNT_7 0x124005C36#define ACP_DMA_PRIO_0 0x124006037#define ACP_DMA_PRIO_1 0x124006438#define ACP_DMA_PRIO_2 0x124006839#define ACP_DMA_PRIO_3 0x124006C40#define ACP_DMA_PRIO_4 0x124007041#define ACP_DMA_PRIO_5 0x124007442#define ACP_DMA_PRIO_6 0x124007843#define ACP_DMA_PRIO_7 0x124007C44#define ACP_DMA_CUR_DSCR_0 0x124008045#define ACP_DMA_CUR_DSCR_1 0x124008446#define ACP_DMA_CUR_DSCR_2 0x124008847#define ACP_DMA_CUR_DSCR_3 0x124008C48#define ACP_DMA_CUR_DSCR_4 0x124009049#define ACP_DMA_CUR_DSCR_5 0x124009450#define ACP_DMA_CUR_DSCR_6 0x124009851#define ACP_DMA_CUR_DSCR_7 0x124009C52#define ACP_DMA_CUR_TRANS_CNT_0 0x12400A053#define ACP_DMA_CUR_TRANS_CNT_1 0x12400A454#define ACP_DMA_CUR_TRANS_CNT_2 0x12400A855#define ACP_DMA_CUR_TRANS_CNT_3 0x12400AC56#define ACP_DMA_CUR_TRANS_CNT_4 0x12400B057#define ACP_DMA_CUR_TRANS_CNT_5 0x12400B458#define ACP_DMA_CUR_TRANS_CNT_6 0x12400B859#define ACP_DMA_CUR_TRANS_CNT_7 0x12400BC60#define ACP_DMA_ERR_STS_0 0x12400C061#define ACP_DMA_ERR_STS_1 0x12400C462#define ACP_DMA_ERR_STS_2 0x12400C863#define ACP_DMA_ERR_STS_3 0x12400CC64#define ACP_DMA_ERR_STS_4 0x12400D065#define ACP_DMA_ERR_STS_5 0x12400D466#define ACP_DMA_ERR_STS_6 0x12400D867#define ACP_DMA_ERR_STS_7 0x12400DC68#define ACP_DMA_DESC_BASE_ADDR 0x12400E069#define ACP_DMA_DESC_MAX_NUM_DSCR 0x12400E470#define ACP_DMA_CH_STS 0x12400E871#define ACP_DMA_CH_GROUP 0x12400EC72#define ACP_DMA_CH_RST_STS 0x12400F073 74// Registers from ACP_AXI2AXIATU block75 76#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_1 0x1240C0077#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_1 0x1240C0478#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_2 0x1240C0879#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_2 0x1240C0C80#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_3 0x1240C1081#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_3 0x1240C1482#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_4 0x1240C1883#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_4 0x1240C1C84#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_5 0x1240C2085#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_5 0x1240C2486#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_6 0x1240C2887#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_6 0x1240C2C88#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_7 0x1240C3089#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_7 0x1240C3490#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_8 0x1240C3891#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_8 0x1240C3C92#define ACPAXI2AXI_ATU_CTRL 0x1240C4093 94// Registers from ACP_CLKRST block95 96#define ACP_SOFT_RESET 0x124100097#define ACP_CONTROL 0x124100498#define ACP_STATUS 0x124100899#define ACP_DYNAMIC_CG_MASTER_CONTROL 0x1241010100 101// Registers from ACP_MISC block102 103#define ACP_EXTERNAL_INTR_ENB 0x1241800104#define ACP_EXTERNAL_INTR_CNTL 0x1241804105#define ACP_EXTERNAL_INTR_STAT 0x1241808106#define ACP_PGMEM_CTRL 0x12418C0107#define ACP_ERROR_STATUS 0x12418C4108#define ACP_SW_I2S_ERROR_REASON 0x12418C8109#define ACP_MEM_PG_STS 0x12418CC110 111// Registers from ACP_PGFSM block112 113#define ACP_I2S_PIN_CONFIG 0x1241400114#define ACP_PAD_PULLUP_PULLDOWN_CTRL 0x1241404115#define ACP_PAD_DRIVE_STRENGTH_CTRL 0x1241408116#define ACP_SW_PAD_KEEPER_EN 0x124140C117#define ACP_PGFSM_CONTROL 0x124141C118#define ACP_PGFSM_STATUS 0x1241420119#define ACP_CLKMUX_SEL 0x1241424120#define ACP_DEVICE_STATE 0x1241428121#define AZ_DEVICE_STATE 0x124142C122#define ACP_INTR_URGENCY_TIMER 0x1241430123#define AZ_INTR_URGENCY_TIMER 0x1241434124 125// Registers from ACP_SCRATCH block126 127#define ACP_SCRATCH_REG_0 0x1250000128#define ACP_SCRATCH_REG_1 0x1250004129#define ACP_SCRATCH_REG_2 0x1250008130#define ACP_SCRATCH_REG_3 0x125000C131#define ACP_SCRATCH_REG_4 0x1250010132#define ACP_SCRATCH_REG_5 0x1250014133#define ACP_SCRATCH_REG_6 0x1250018134#define ACP_SCRATCH_REG_7 0x125001C135#define ACP_SCRATCH_REG_8 0x1250020136#define ACP_SCRATCH_REG_9 0x1250024137#define ACP_SCRATCH_REG_10 0x1250028138#define ACP_SCRATCH_REG_11 0x125002C139#define ACP_SCRATCH_REG_12 0x1250030140#define ACP_SCRATCH_REG_13 0x1250034141#define ACP_SCRATCH_REG_14 0x1250038142#define ACP_SCRATCH_REG_15 0x125003C143#define ACP_SCRATCH_REG_16 0x1250040144#define ACP_SCRATCH_REG_17 0x1250044145#define ACP_SCRATCH_REG_18 0x1250048146#define ACP_SCRATCH_REG_19 0x125004C147#define ACP_SCRATCH_REG_20 0x1250050148#define ACP_SCRATCH_REG_21 0x1250054149#define ACP_SCRATCH_REG_22 0x1250058150#define ACP_SCRATCH_REG_23 0x125005C151#define ACP_SCRATCH_REG_24 0x1250060152#define ACP_SCRATCH_REG_25 0x1250064153#define ACP_SCRATCH_REG_26 0x1250068154#define ACP_SCRATCH_REG_27 0x125006C155#define ACP_SCRATCH_REG_28 0x1250070156#define ACP_SCRATCH_REG_29 0x1250074157#define ACP_SCRATCH_REG_30 0x1250078158#define ACP_SCRATCH_REG_31 0x125007C159#define ACP_SCRATCH_REG_32 0x1250080160#define ACP_SCRATCH_REG_33 0x1250084161#define ACP_SCRATCH_REG_34 0x1250088162#define ACP_SCRATCH_REG_35 0x125008C163#define ACP_SCRATCH_REG_36 0x1250090164#define ACP_SCRATCH_REG_37 0x1250094165#define ACP_SCRATCH_REG_38 0x1250098166#define ACP_SCRATCH_REG_39 0x125009C167#define ACP_SCRATCH_REG_40 0x12500A0168#define ACP_SCRATCH_REG_41 0x12500A4169#define ACP_SCRATCH_REG_42 0x12500A8170#define ACP_SCRATCH_REG_43 0x12500AC171#define ACP_SCRATCH_REG_44 0x12500B0172#define ACP_SCRATCH_REG_45 0x12500B4173#define ACP_SCRATCH_REG_46 0x12500B8174#define ACP_SCRATCH_REG_47 0x12500BC175#define ACP_SCRATCH_REG_48 0x12500C0176#define ACP_SCRATCH_REG_49 0x12500C4177#define ACP_SCRATCH_REG_50 0x12500C8178#define ACP_SCRATCH_REG_51 0x12500CC179#define ACP_SCRATCH_REG_52 0x12500D0180#define ACP_SCRATCH_REG_53 0x12500D4181#define ACP_SCRATCH_REG_54 0x12500D8182#define ACP_SCRATCH_REG_55 0x12500DC183#define ACP_SCRATCH_REG_56 0x12500E0184#define ACP_SCRATCH_REG_57 0x12500E4185#define ACP_SCRATCH_REG_58 0x12500E8186#define ACP_SCRATCH_REG_59 0x12500EC187#define ACP_SCRATCH_REG_60 0x12500F0188#define ACP_SCRATCH_REG_61 0x12500F4189#define ACP_SCRATCH_REG_62 0x12500F8190#define ACP_SCRATCH_REG_63 0x12500FC191#define ACP_SCRATCH_REG_64 0x1250100192#define ACP_SCRATCH_REG_65 0x1250104193#define ACP_SCRATCH_REG_66 0x1250108194#define ACP_SCRATCH_REG_67 0x125010C195#define ACP_SCRATCH_REG_68 0x1250110196#define ACP_SCRATCH_REG_69 0x1250114197#define ACP_SCRATCH_REG_70 0x1250118198#define ACP_SCRATCH_REG_71 0x125011C199#define ACP_SCRATCH_REG_72 0x1250120200#define ACP_SCRATCH_REG_73 0x1250124201#define ACP_SCRATCH_REG_74 0x1250128202#define ACP_SCRATCH_REG_75 0x125012C203#define ACP_SCRATCH_REG_76 0x1250130204#define ACP_SCRATCH_REG_77 0x1250134205#define ACP_SCRATCH_REG_78 0x1250138206#define ACP_SCRATCH_REG_79 0x125013C207#define ACP_SCRATCH_REG_80 0x1250140208#define ACP_SCRATCH_REG_81 0x1250144209#define ACP_SCRATCH_REG_82 0x1250148210#define ACP_SCRATCH_REG_83 0x125014C211#define ACP_SCRATCH_REG_84 0x1250150212#define ACP_SCRATCH_REG_85 0x1250154213#define ACP_SCRATCH_REG_86 0x1250158214#define ACP_SCRATCH_REG_87 0x125015C215#define ACP_SCRATCH_REG_88 0x1250160216#define ACP_SCRATCH_REG_89 0x1250164217#define ACP_SCRATCH_REG_90 0x1250168218#define ACP_SCRATCH_REG_91 0x125016C219#define ACP_SCRATCH_REG_92 0x1250170220#define ACP_SCRATCH_REG_93 0x1250174221#define ACP_SCRATCH_REG_94 0x1250178222#define ACP_SCRATCH_REG_95 0x125017C223#define ACP_SCRATCH_REG_96 0x1250180224#define ACP_SCRATCH_REG_97 0x1250184225#define ACP_SCRATCH_REG_98 0x1250188226#define ACP_SCRATCH_REG_99 0x125018C227#define ACP_SCRATCH_REG_100 0x1250190228#define ACP_SCRATCH_REG_101 0x1250194229#define ACP_SCRATCH_REG_102 0x1250198230#define ACP_SCRATCH_REG_103 0x125019C231#define ACP_SCRATCH_REG_104 0x12501A0232#define ACP_SCRATCH_REG_105 0x12501A4233#define ACP_SCRATCH_REG_106 0x12501A8234#define ACP_SCRATCH_REG_107 0x12501AC235#define ACP_SCRATCH_REG_108 0x12501B0236#define ACP_SCRATCH_REG_109 0x12501B4237#define ACP_SCRATCH_REG_110 0x12501B8238#define ACP_SCRATCH_REG_111 0x12501BC239#define ACP_SCRATCH_REG_112 0x12501C0240#define ACP_SCRATCH_REG_113 0x12501C4241#define ACP_SCRATCH_REG_114 0x12501C8242#define ACP_SCRATCH_REG_115 0x12501CC243#define ACP_SCRATCH_REG_116 0x12501D0244#define ACP_SCRATCH_REG_117 0x12501D4245#define ACP_SCRATCH_REG_118 0x12501D8246#define ACP_SCRATCH_REG_119 0x12501DC247#define ACP_SCRATCH_REG_120 0x12501E0248#define ACP_SCRATCH_REG_121 0x12501E4249#define ACP_SCRATCH_REG_122 0x12501E8250#define ACP_SCRATCH_REG_123 0x12501EC251#define ACP_SCRATCH_REG_124 0x12501F0252#define ACP_SCRATCH_REG_125 0x12501F4253#define ACP_SCRATCH_REG_126 0x12501F8254#define ACP_SCRATCH_REG_127 0x12501FC255#define ACP_SCRATCH_REG_128 0x1250200256 257// Registers from ACP_AUDIO_BUFFERS block258 259#define ACP_I2S_RX_RINGBUFADDR 0x1242000260#define ACP_I2S_RX_RINGBUFSIZE 0x1242004261#define ACP_I2S_RX_LINKPOSITIONCNTR 0x1242008262#define ACP_I2S_RX_FIFOADDR 0x124200C263#define ACP_I2S_RX_FIFOSIZE 0x1242010264#define ACP_I2S_RX_DMA_SIZE 0x1242014265#define ACP_I2S_RX_LINEARPOSITIONCNTR_HIGH 0x1242018266#define ACP_I2S_RX_LINEARPOSITIONCNTR_LOW 0x124201C267#define ACP_I2S_RX_INTR_WATERMARK_SIZE 0x1242020268#define ACP_I2S_TX_RINGBUFADDR 0x1242024269#define ACP_I2S_TX_RINGBUFSIZE 0x1242028270#define ACP_I2S_TX_LINKPOSITIONCNTR 0x124202C271#define ACP_I2S_TX_FIFOADDR 0x1242030272#define ACP_I2S_TX_FIFOSIZE 0x1242034273#define ACP_I2S_TX_DMA_SIZE 0x1242038274#define ACP_I2S_TX_LINEARPOSITIONCNTR_HIGH 0x124203C275#define ACP_I2S_TX_LINEARPOSITIONCNTR_LOW 0x1242040276#define ACP_I2S_TX_INTR_WATERMARK_SIZE 0x1242044277#define ACP_BT_RX_RINGBUFADDR 0x1242048278#define ACP_BT_RX_RINGBUFSIZE 0x124204C279#define ACP_BT_RX_LINKPOSITIONCNTR 0x1242050280#define ACP_BT_RX_FIFOADDR 0x1242054281#define ACP_BT_RX_FIFOSIZE 0x1242058282#define ACP_BT_RX_DMA_SIZE 0x124205C283#define ACP_BT_RX_LINEARPOSITIONCNTR_HIGH 0x1242060284#define ACP_BT_RX_LINEARPOSITIONCNTR_LOW 0x1242064285#define ACP_BT_RX_INTR_WATERMARK_SIZE 0x1242068286#define ACP_BT_TX_RINGBUFADDR 0x124206C287#define ACP_BT_TX_RINGBUFSIZE 0x1242070288#define ACP_BT_TX_LINKPOSITIONCNTR 0x1242074289#define ACP_BT_TX_FIFOADDR 0x1242078290#define ACP_BT_TX_FIFOSIZE 0x124207C291#define ACP_BT_TX_DMA_SIZE 0x1242080292#define ACP_BT_TX_LINEARPOSITIONCNTR_HIGH 0x1242084293#define ACP_BT_TX_LINEARPOSITIONCNTR_LOW 0x1242088294#define ACP_BT_TX_INTR_WATERMARK_SIZE 0x124208C295#define ACP_HS_RX_RINGBUFADDR 0x1242090296#define ACP_HS_RX_RINGBUFSIZE 0x1242094297#define ACP_HS_RX_LINKPOSITIONCNTR 0x1242098298#define ACP_HS_RX_FIFOADDR 0x124209C299#define ACP_HS_RX_FIFOSIZE 0x12420A0300#define ACP_HS_RX_DMA_SIZE 0x12420A4301#define ACP_HS_RX_LINEARPOSITIONCNTR_HIGH 0x12420A8302#define ACP_HS_RX_LINEARPOSITIONCNTR_LOW 0x12420AC303#define ACP_HS_RX_INTR_WATERMARK_SIZE 0x12420B0304#define ACP_HS_TX_RINGBUFADDR 0x12420B4305#define ACP_HS_TX_RINGBUFSIZE 0x12420B8306#define ACP_HS_TX_LINKPOSITIONCNTR 0x12420BC307#define ACP_HS_TX_FIFOADDR 0x12420C0308#define ACP_HS_TX_FIFOSIZE 0x12420C4309#define ACP_HS_TX_DMA_SIZE 0x12420C8310#define ACP_HS_TX_LINEARPOSITIONCNTR_HIGH 0x12420CC311#define ACP_HS_TX_LINEARPOSITIONCNTR_LOW 0x12420D0312#define ACP_HS_TX_INTR_WATERMARK_SIZE 0x12420D4313 314// Registers from ACP_I2S_TDM block315 316#define ACP_I2STDM_IER 0x1242400317#define ACP_I2STDM_IRER 0x1242404318#define ACP_I2STDM_RXFRMT 0x1242408319#define ACP_I2STDM_ITER 0x124240C320#define ACP_I2STDM_TXFRMT 0x1242410321 322// Registers from ACP_BT_TDM block323 324#define ACP_BTTDM_IER 0x1242800325#define ACP_BTTDM_IRER 0x1242804326#define ACP_BTTDM_RXFRMT 0x1242808327#define ACP_BTTDM_ITER 0x124280C328#define ACP_BTTDM_TXFRMT 0x1242810329 330// Registers from ACP_WOV block331 332#define ACP_WOV_PDM_ENABLE 0x1242C04333#define ACP_WOV_PDM_DMA_ENABLE 0x1242C08334#define ACP_WOV_RX_RINGBUFADDR 0x1242C0C335#define ACP_WOV_RX_RINGBUFSIZE 0x1242C10336#define ACP_WOV_RX_LINKPOSITIONCNTR 0x1242C14337#define ACP_WOV_RX_LINEARPOSITIONCNTR_HIGH 0x1242C18338#define ACP_WOV_RX_LINEARPOSITIONCNTR_LOW 0x1242C1C339#define ACP_WOV_RX_INTR_WATERMARK_SIZE 0x1242C20340#define ACP_WOV_PDM_FIFO_FLUSH 0x1242C24341#define ACP_WOV_PDM_NO_OF_CHANNELS 0x1242C28342#define ACP_WOV_PDM_DECIMATION_FACTOR 0x1242C2C343#define ACP_WOV_PDM_VAD_CTRL 0x1242C30344#define ACP_WOV_BUFFER_STATUS 0x1242C58345#define ACP_WOV_MISC_CTRL 0x1242C5C346#define ACP_WOV_CLK_CTRL 0x1242C60347#define ACP_PDM_VAD_DYNAMIC_CLK_GATING_EN 0x1242C64348#define ACP_WOV_ERROR_STATUS_REGISTER 0x1242C68349#endif350