338 lines · c
1/* SPDX-License-Identifier: GPL-2.0+ */2/*3 * AMD ACP 5.x Register Documentation4 *5 * Copyright 2021 Advanced Micro Devices, Inc.6 */7 8#ifndef _acp_ip_OFFSET_HEADER9#define _acp_ip_OFFSET_HEADER10 11/* Registers from ACP_DMA block */12#define ACP_DMA_CNTL_0 0x124000013#define ACP_DMA_CNTL_1 0x124000414#define ACP_DMA_CNTL_2 0x124000815#define ACP_DMA_CNTL_3 0x124000C16#define ACP_DMA_CNTL_4 0x124001017#define ACP_DMA_CNTL_5 0x124001418#define ACP_DMA_CNTL_6 0x124001819#define ACP_DMA_CNTL_7 0x124001C20#define ACP_DMA_DSCR_STRT_IDX_0 0x124002021#define ACP_DMA_DSCR_STRT_IDX_1 0x124002422#define ACP_DMA_DSCR_STRT_IDX_2 0x124002823#define ACP_DMA_DSCR_STRT_IDX_3 0x124002C24#define ACP_DMA_DSCR_STRT_IDX_4 0x124003025#define ACP_DMA_DSCR_STRT_IDX_5 0x124003426#define ACP_DMA_DSCR_STRT_IDX_6 0x124003827#define ACP_DMA_DSCR_STRT_IDX_7 0x124003C28#define ACP_DMA_DSCR_CNT_0 0x124004029#define ACP_DMA_DSCR_CNT_1 0x124004430#define ACP_DMA_DSCR_CNT_2 0x124004831#define ACP_DMA_DSCR_CNT_3 0x124004C32#define ACP_DMA_DSCR_CNT_4 0x124005033#define ACP_DMA_DSCR_CNT_5 0x124005434#define ACP_DMA_DSCR_CNT_6 0x124005835#define ACP_DMA_DSCR_CNT_7 0x124005C36#define ACP_DMA_PRIO_0 0x124006037#define ACP_DMA_PRIO_1 0x124006438#define ACP_DMA_PRIO_2 0x124006839#define ACP_DMA_PRIO_3 0x124006C40#define ACP_DMA_PRIO_4 0x124007041#define ACP_DMA_PRIO_5 0x124007442#define ACP_DMA_PRIO_6 0x124007843#define ACP_DMA_PRIO_7 0x124007C44#define ACP_DMA_CUR_DSCR_0 0x124008045#define ACP_DMA_CUR_DSCR_1 0x124008446#define ACP_DMA_CUR_DSCR_2 0x124008847#define ACP_DMA_CUR_DSCR_3 0x124008C48#define ACP_DMA_CUR_DSCR_4 0x124009049#define ACP_DMA_CUR_DSCR_5 0x124009450#define ACP_DMA_CUR_DSCR_6 0x124009851#define ACP_DMA_CUR_DSCR_7 0x124009C52#define ACP_DMA_CUR_TRANS_CNT_0 0x12400A053#define ACP_DMA_CUR_TRANS_CNT_1 0x12400A454#define ACP_DMA_CUR_TRANS_CNT_2 0x12400A855#define ACP_DMA_CUR_TRANS_CNT_3 0x12400AC56#define ACP_DMA_CUR_TRANS_CNT_4 0x12400B057#define ACP_DMA_CUR_TRANS_CNT_5 0x12400B458#define ACP_DMA_CUR_TRANS_CNT_6 0x12400B859#define ACP_DMA_CUR_TRANS_CNT_7 0x12400BC60#define ACP_DMA_ERR_STS_0 0x12400C061#define ACP_DMA_ERR_STS_1 0x12400C462#define ACP_DMA_ERR_STS_2 0x12400C863#define ACP_DMA_ERR_STS_3 0x12400CC64#define ACP_DMA_ERR_STS_4 0x12400D065#define ACP_DMA_ERR_STS_5 0x12400D466#define ACP_DMA_ERR_STS_6 0x12400D867#define ACP_DMA_ERR_STS_7 0x12400DC68#define ACP_DMA_DESC_BASE_ADDR 0x12400E069#define ACP_DMA_DESC_MAX_NUM_DSCR 0x12400E470#define ACP_DMA_CH_STS 0x12400E871#define ACP_DMA_CH_GROUP 0x12400EC72#define ACP_DMA_CH_RST_STS 0x12400F073 74/* Registers from ACP_AXI2AXIATU block */75#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_1 0x1240C0076#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_1 0x1240C0477#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_2 0x1240C0878#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_2 0x1240C0C79#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_3 0x1240C1080#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_3 0x1240C1481#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_4 0x1240C1882#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_4 0x1240C1C83#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_5 0x1240C2084#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_5 0x1240C2485#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_6 0x1240C2886#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_6 0x1240C2C87#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_7 0x1240C3088#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_7 0x1240C3489#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_8 0x1240C3890#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_8 0x1240C3C91#define ACPAXI2AXI_ATU_CTRL 0x1240C4092 93/* Registers from ACP_CLKRST block */94#define ACP_SOFT_RESET 0x124100095#define ACP_CONTROL 0x124100496#define ACP_STATUS 0x124100897#define ACP_DYNAMIC_CG_MASTER_CONTROL 0x124101098 99/* Registers from ACP_MISC block */100#define ACP_EXTERNAL_INTR_ENB 0x1241800101#define ACP_EXTERNAL_INTR_CNTL 0x1241804102#define ACP_EXTERNAL_INTR_STAT 0x1241808103#define ACP_ERROR_STATUS 0x12418C4104#define ACP_SW_I2S_ERROR_REASON 0x12418C8105#define ACP_MEM_PG_STS 0x12418CC106#define ACP_PGMEM_DEEP_SLEEP_CTRL 0x12418D0107#define ACP_PGMEM_SHUT_DOWN_CTRL 0x12418D4108 109/* Registers from ACP_PGFSM block */110#define ACP_PIN_CONFIG 0x1241400111#define ACP_PAD_PULLUP_CTRL 0x1241404112#define ACP_PAD_PULLDOWN_CTRL 0x1241408113#define ACP_PAD_DRIVE_STRENGTH_CTRL 0x124140C114#define ACP_PAD_SCHMEN_CTRL 0x1241410115#define ACP_SW_PAD_KEEPER_EN 0x1241414116#define ACP_SW_WAKE_EN 0x1241418117#define ACP_I2S_WAKE_EN 0x124141C118#define ACP_PME_EN 0x1241420119#define ACP_PGFSM_CONTROL 0x1241424120#define ACP_PGFSM_STATUS 0x1241428121#define ACP_CLKMUX_SEL 0x124142C122#define ACP_DEVICE_STATE 0x1241430123#define AZ_DEVICE_STATE 0x1241434124#define ACP_INTR_URGENCY_TIMER 0x1241438125#define AZ_INTR_URGENCY_TIMER 0x124143C126#define ACP_AON_SW_INTR_TRIG 0x1241440127 128/* Registers from ACP_SCRATCH block */129#define ACP_SCRATCH_REG_0 0x1250000130#define ACP_SCRATCH_REG_1 0x1250004131#define ACP_SCRATCH_REG_2 0x1250008132#define ACP_SCRATCH_REG_3 0x125000C133#define ACP_SCRATCH_REG_4 0x1250010134#define ACP_SCRATCH_REG_5 0x1250014135#define ACP_SCRATCH_REG_6 0x1250018136#define ACP_SCRATCH_REG_7 0x125001C137#define ACP_SCRATCH_REG_8 0x1250020138#define ACP_SCRATCH_REG_9 0x1250024139#define ACP_SCRATCH_REG_10 0x1250028140#define ACP_SCRATCH_REG_11 0x125002C141#define ACP_SCRATCH_REG_12 0x1250030142#define ACP_SCRATCH_REG_13 0x1250034143#define ACP_SCRATCH_REG_14 0x1250038144#define ACP_SCRATCH_REG_15 0x125003C145#define ACP_SCRATCH_REG_16 0x1250040146#define ACP_SCRATCH_REG_17 0x1250044147#define ACP_SCRATCH_REG_18 0x1250048148#define ACP_SCRATCH_REG_19 0x125004C149#define ACP_SCRATCH_REG_20 0x1250050150#define ACP_SCRATCH_REG_21 0x1250054151#define ACP_SCRATCH_REG_22 0x1250058152#define ACP_SCRATCH_REG_23 0x125005C153#define ACP_SCRATCH_REG_24 0x1250060154#define ACP_SCRATCH_REG_25 0x1250064155#define ACP_SCRATCH_REG_26 0x1250068156#define ACP_SCRATCH_REG_27 0x125006C157#define ACP_SCRATCH_REG_28 0x1250070158#define ACP_SCRATCH_REG_29 0x1250074159#define ACP_SCRATCH_REG_30 0x1250078160#define ACP_SCRATCH_REG_31 0x125007C161#define ACP_SCRATCH_REG_32 0x1250080162#define ACP_SCRATCH_REG_33 0x1250084163#define ACP_SCRATCH_REG_34 0x1250088164#define ACP_SCRATCH_REG_35 0x125008C165#define ACP_SCRATCH_REG_36 0x1250090166#define ACP_SCRATCH_REG_37 0x1250094167#define ACP_SCRATCH_REG_38 0x1250098168#define ACP_SCRATCH_REG_39 0x125009C169#define ACP_SCRATCH_REG_40 0x12500A0170#define ACP_SCRATCH_REG_41 0x12500A4171#define ACP_SCRATCH_REG_42 0x12500A8172#define ACP_SCRATCH_REG_43 0x12500AC173#define ACP_SCRATCH_REG_44 0x12500B0174#define ACP_SCRATCH_REG_45 0x12500B4175#define ACP_SCRATCH_REG_46 0x12500B8176#define ACP_SCRATCH_REG_47 0x12500BC177#define ACP_SCRATCH_REG_48 0x12500C0178#define ACP_SCRATCH_REG_49 0x12500C4179#define ACP_SCRATCH_REG_50 0x12500C8180#define ACP_SCRATCH_REG_51 0x12500CC181#define ACP_SCRATCH_REG_52 0x12500D0182#define ACP_SCRATCH_REG_53 0x12500D4183#define ACP_SCRATCH_REG_54 0x12500D8184#define ACP_SCRATCH_REG_55 0x12500DC185#define ACP_SCRATCH_REG_56 0x12500E0186#define ACP_SCRATCH_REG_57 0x12500E4187#define ACP_SCRATCH_REG_58 0x12500E8188#define ACP_SCRATCH_REG_59 0x12500EC189#define ACP_SCRATCH_REG_60 0x12500F0190#define ACP_SCRATCH_REG_61 0x12500F4191#define ACP_SCRATCH_REG_62 0x12500F8192#define ACP_SCRATCH_REG_63 0x12500FC193#define ACP_SCRATCH_REG_64 0x1250100194#define ACP_SCRATCH_REG_65 0x1250104195#define ACP_SCRATCH_REG_66 0x1250108196#define ACP_SCRATCH_REG_67 0x125010C197#define ACP_SCRATCH_REG_68 0x1250110198#define ACP_SCRATCH_REG_69 0x1250114199#define ACP_SCRATCH_REG_70 0x1250118200#define ACP_SCRATCH_REG_71 0x125011C201#define ACP_SCRATCH_REG_72 0x1250120202#define ACP_SCRATCH_REG_73 0x1250124203#define ACP_SCRATCH_REG_74 0x1250128204#define ACP_SCRATCH_REG_75 0x125012C205#define ACP_SCRATCH_REG_76 0x1250130206#define ACP_SCRATCH_REG_77 0x1250134207#define ACP_SCRATCH_REG_78 0x1250138208#define ACP_SCRATCH_REG_79 0x125013C209#define ACP_SCRATCH_REG_80 0x1250140210#define ACP_SCRATCH_REG_81 0x1250144211#define ACP_SCRATCH_REG_82 0x1250148212#define ACP_SCRATCH_REG_83 0x125014C213#define ACP_SCRATCH_REG_84 0x1250150214#define ACP_SCRATCH_REG_85 0x1250154215#define ACP_SCRATCH_REG_86 0x1250158216#define ACP_SCRATCH_REG_87 0x125015C217#define ACP_SCRATCH_REG_88 0x1250160218#define ACP_SCRATCH_REG_89 0x1250164219#define ACP_SCRATCH_REG_90 0x1250168220#define ACP_SCRATCH_REG_91 0x125016C221#define ACP_SCRATCH_REG_92 0x1250170222#define ACP_SCRATCH_REG_93 0x1250174223#define ACP_SCRATCH_REG_94 0x1250178224#define ACP_SCRATCH_REG_95 0x125017C225#define ACP_SCRATCH_REG_96 0x1250180226#define ACP_SCRATCH_REG_97 0x1250184227#define ACP_SCRATCH_REG_98 0x1250188228#define ACP_SCRATCH_REG_99 0x125018C229#define ACP_SCRATCH_REG_100 0x1250190230#define ACP_SCRATCH_REG_101 0x1250194231#define ACP_SCRATCH_REG_102 0x1250198232#define ACP_SCRATCH_REG_103 0x125019C233#define ACP_SCRATCH_REG_104 0x12501A0234#define ACP_SCRATCH_REG_105 0x12501A4235#define ACP_SCRATCH_REG_106 0x12501A8236#define ACP_SCRATCH_REG_107 0x12501AC237#define ACP_SCRATCH_REG_108 0x12501B0238#define ACP_SCRATCH_REG_109 0x12501B4239#define ACP_SCRATCH_REG_110 0x12501B8240#define ACP_SCRATCH_REG_111 0x12501BC241#define ACP_SCRATCH_REG_112 0x12501C0242#define ACP_SCRATCH_REG_113 0x12501C4243#define ACP_SCRATCH_REG_114 0x12501C8244#define ACP_SCRATCH_REG_115 0x12501CC245#define ACP_SCRATCH_REG_116 0x12501D0246#define ACP_SCRATCH_REG_117 0x12501D4247#define ACP_SCRATCH_REG_118 0x12501D8248#define ACP_SCRATCH_REG_119 0x12501DC249#define ACP_SCRATCH_REG_120 0x12501E0250#define ACP_SCRATCH_REG_121 0x12501E4251#define ACP_SCRATCH_REG_122 0x12501E8252#define ACP_SCRATCH_REG_123 0x12501EC253#define ACP_SCRATCH_REG_124 0x12501F0254#define ACP_SCRATCH_REG_125 0x12501F4255#define ACP_SCRATCH_REG_126 0x12501F8256#define ACP_SCRATCH_REG_127 0x12501FC257#define ACP_SCRATCH_REG_128 0x1250200258 259/* Registers from ACP_AUDIO_BUFFERS block */260#define ACP_I2S_RX_RINGBUFADDR 0x1242000261#define ACP_I2S_RX_RINGBUFSIZE 0x1242004262#define ACP_I2S_RX_LINKPOSITIONCNTR 0x1242008263#define ACP_I2S_RX_FIFOADDR 0x124200C264#define ACP_I2S_RX_FIFOSIZE 0x1242010265#define ACP_I2S_RX_DMA_SIZE 0x1242014266#define ACP_I2S_RX_LINEARPOSCNTR_HIGH 0x1242018267#define ACP_I2S_RX_LINEARPOSCNTR_LOW 0x124201C268#define ACP_I2S_RX_INTR_WATERMARK_SIZE 0x1242020269#define ACP_I2S_TX_RINGBUFADDR 0x1242024270#define ACP_I2S_TX_RINGBUFSIZE 0x1242028271#define ACP_I2S_TX_LINKPOSITIONCNTR 0x124202C272#define ACP_I2S_TX_FIFOADDR 0x1242030273#define ACP_I2S_TX_FIFOSIZE 0x1242034274#define ACP_I2S_TX_DMA_SIZE 0x1242038275#define ACP_I2S_TX_LINEARPOSCNTR_HIGH 0x124203C276#define ACP_I2S_TX_LINEARPOSCNTR_LOW 0x1242040277#define ACP_I2S_TX_INTR_WATERMARK_SIZE 0x1242044278#define ACP_BT_RX_RINGBUFADDR 0x1242048279#define ACP_BT_RX_RINGBUFSIZE 0x124204C280#define ACP_BT_RX_LINKPOSITIONCNTR 0x1242050281#define ACP_BT_RX_FIFOADDR 0x1242054282#define ACP_BT_RX_FIFOSIZE 0x1242058283#define ACP_BT_RX_DMA_SIZE 0x124205C284#define ACP_BT_RX_LINEARPOSCNTR_HIGH 0x1242060285#define ACP_BT_RX_LINEARPOSCNTR_LOW 0x1242064286#define ACP_BT_RX_INTR_WATERMARK_SIZE 0x1242068287#define ACP_BT_TX_RINGBUFADDR 0x124206C288#define ACP_BT_TX_RINGBUFSIZE 0x1242070289#define ACP_BT_TX_LINKPOSITIONCNTR 0x1242074290#define ACP_BT_TX_FIFOADDR 0x1242078291#define ACP_BT_TX_FIFOSIZE 0x124207C292#define ACP_BT_TX_DMA_SIZE 0x1242080293#define ACP_BT_TX_LINEARPOSCNTR_HIGH 0x1242084294#define ACP_BT_TX_LINEARPOSCNTR_LOW 0x1242088295#define ACP_BT_TX_INTR_WATERMARK_SIZE 0x124208C296#define ACP_HS_RX_RINGBUFADDR 0x1242090297#define ACP_HS_RX_RINGBUFSIZE 0x1242094298#define ACP_HS_RX_LINKPOSITIONCNTR 0x1242098299#define ACP_HS_RX_FIFOADDR 0x124209C300#define ACP_HS_RX_FIFOSIZE 0x12420A0301#define ACP_HS_RX_DMA_SIZE 0x12420A4302#define ACP_HS_RX_LINEARPOSCNTR_HIGH 0x12420A8303#define ACP_HS_RX_LINEARPOSCNTR_LOW 0x12420AC304#define ACP_HS_RX_INTR_WATERMARK_SIZE 0x12420B0305#define ACP_HS_TX_RINGBUFADDR 0x12420B4306#define ACP_HS_TX_RINGBUFSIZE 0x12420B8307#define ACP_HS_TX_LINKPOSITIONCNTR 0x12420BC308#define ACP_HS_TX_FIFOADDR 0x12420C0309#define ACP_HS_TX_FIFOSIZE 0x12420C4310#define ACP_HS_TX_DMA_SIZE 0x12420C8311#define ACP_HS_TX_LINEARPOSCNTR_HIGH 0x12420CC312#define ACP_HS_TX_LINEARPOSCNTR_LOW 0x12420D0313#define ACP_HS_TX_INTR_WATERMARK_SIZE 0x12420D4314 315/* Registers from ACP_I2S_TDM block */316#define ACP_I2STDM_IER 0x1242400317#define ACP_I2STDM_IRER 0x1242404318#define ACP_I2STDM_RXFRMT 0x1242408319#define ACP_I2STDM_ITER 0x124240C320#define ACP_I2STDM_TXFRMT 0x1242410321#define ACP_I2STDM0_MSTRCLKGEN 0x1242414322#define ACP_I2STDM1_MSTRCLKGEN 0x1242418323#define ACP_I2STDM2_MSTRCLKGEN 0x124241C324#define ACP_I2STDM_REFCLKGEN 0x1242420325 326/* Registers from ACP_BT_TDM block */327#define ACP_BTTDM_IER 0x1242800328#define ACP_BTTDM_IRER 0x1242804329#define ACP_BTTDM_RXFRMT 0x1242808330#define ACP_BTTDM_ITER 0x124280C331#define ACP_BTTDM_TXFRMT 0x1242810332#define ACP_HSTDM_IER 0x1242814333#define ACP_HSTDM_IRER 0x1242818334#define ACP_HSTDM_RXFRMT 0x124281C335#define ACP_HSTDM_ITER 0x1242820336#define ACP_HSTDM_TXFRMT 0x1242824337#endif338