111 lines · c
1/* SPDX-License-Identifier: GPL-2.0+ */2/*3 * AMD ALSA SoC PDM Driver4 *5 * Copyright (C) 2021 Advanced Micro Devices, Inc. All rights reserved.6 */7 8#include "acp6x_chip_offset_byte.h"9 10#define ACP_DEVICE_ID 0x15E211#define ACP6x_PHY_BASE_ADDRESS 0x124000012#define ACP6x_REG_START 0x124000013#define ACP6x_REG_END 0x125020014#define ACP6x_DEVS 315#define ACP6x_PDM_MODE 116 17#define ACP_SOFT_RESET_SOFTRESET_AUDDONE_MASK 0x0001000118#define ACP_PGFSM_CNTL_POWER_ON_MASK 119#define ACP_PGFSM_CNTL_POWER_OFF_MASK 020#define ACP_PGFSM_STATUS_MASK 321#define ACP_POWERED_ON 022#define ACP_POWER_ON_IN_PROGRESS 123#define ACP_POWERED_OFF 224#define ACP_POWER_OFF_IN_PROGRESS 325 26#define ACP_ERROR_MASK 0x2000000027#define ACP_EXT_INTR_STAT_CLEAR_MASK 0xFFFFFFFF28#define PDM_DMA_STAT 0x1029 30#define PDM_DMA_INTR_MASK 0x1000031#define ACP_ERROR_STAT 2932#define PDM_DECIMATION_FACTOR 233#define ACP_PDM_CLK_FREQ_MASK 734#define ACP_WOV_GAIN_CONTROL GENMASK(4, 3)35#define ACP_PDM_ENABLE 136#define ACP_PDM_DISABLE 037#define ACP_PDM_DMA_EN_STATUS 238#define TWO_CH 239#define DELAY_US 540#define ACP_COUNTER 2000041 42#define ACP_SRAM_PTE_OFFSET 0x0380000043#define PAGE_SIZE_4K_ENABLE 244#define PDM_PTE_OFFSET 045#define PDM_MEM_WINDOW_START 0x400000046 47#define CAPTURE_MIN_NUM_PERIODS 448#define CAPTURE_MAX_NUM_PERIODS 449#define CAPTURE_MAX_PERIOD_SIZE 819250#define CAPTURE_MIN_PERIOD_SIZE 409651 52#define MAX_BUFFER (CAPTURE_MAX_PERIOD_SIZE * CAPTURE_MAX_NUM_PERIODS)53#define MIN_BUFFER MAX_BUFFER54 55/* time in ms for runtime suspend delay */56#define ACP_SUSPEND_DELAY_MS 200057 58enum acp_config {59 ACP_CONFIG_0 = 0,60 ACP_CONFIG_1,61 ACP_CONFIG_2,62 ACP_CONFIG_3,63 ACP_CONFIG_4,64 ACP_CONFIG_5,65 ACP_CONFIG_6,66 ACP_CONFIG_7,67 ACP_CONFIG_8,68 ACP_CONFIG_9,69 ACP_CONFIG_10,70 ACP_CONFIG_11,71 ACP_CONFIG_12,72 ACP_CONFIG_13,73 ACP_CONFIG_14,74 ACP_CONFIG_15,75};76 77struct pdm_dev_data {78 u32 pdm_irq;79 void __iomem *acp6x_base;80 struct snd_pcm_substream *capture_stream;81};82 83struct pdm_stream_instance {84 u16 num_pages;85 u16 channels;86 dma_addr_t dma_addr;87 u64 bytescount;88 void __iomem *acp6x_base;89};90 91union acp_pdm_dma_count {92 struct {93 u32 low;94 u32 high;95 } bcount;96 u64 bytescount;97};98 99static inline u32 acp6x_readl(void __iomem *base_addr)100{101 return readl(base_addr - ACP6x_PHY_BASE_ADDRESS);102}103 104static inline void acp6x_writel(u32 val, void __iomem *base_addr)105{106 writel(val, base_addr - ACP6x_PHY_BASE_ADDRESS);107}108 109int snd_amd_acp_find_config(struct pci_dev *pci);110 111