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1/* SPDX-License-Identifier: GPL-2.0+ */2/*3 * AMD ACP 6.x Register Documentation4 *5 * Copyright 2021 Advanced Micro Devices, Inc.6 */7 8#ifndef _acp6x_OFFSET_HEADER9#define _acp6x_OFFSET_HEADER10 11/* Registers from ACP_DMA block */12#define ACP_DMA_CNTL_0 0x124000013#define ACP_DMA_CNTL_1 0x124000414#define ACP_DMA_CNTL_2 0x124000815#define ACP_DMA_CNTL_3 0x124000C16#define ACP_DMA_CNTL_4 0x124001017#define ACP_DMA_CNTL_5 0x124001418#define ACP_DMA_CNTL_6 0x124001819#define ACP_DMA_CNTL_7 0x124001C20#define ACP_DMA_DSCR_STRT_IDX_0 0x124002021#define ACP_DMA_DSCR_STRT_IDX_1 0x124002422#define ACP_DMA_DSCR_STRT_IDX_2 0x124002823#define ACP_DMA_DSCR_STRT_IDX_3 0x124002C24#define ACP_DMA_DSCR_STRT_IDX_4 0x124003025#define ACP_DMA_DSCR_STRT_IDX_5 0x124003426#define ACP_DMA_DSCR_STRT_IDX_6 0x124003827#define ACP_DMA_DSCR_STRT_IDX_7 0x124003C28#define ACP_DMA_DSCR_CNT_0 0x124004029#define ACP_DMA_DSCR_CNT_1 0x124004430#define ACP_DMA_DSCR_CNT_2 0x124004831#define ACP_DMA_DSCR_CNT_3 0x124004C32#define ACP_DMA_DSCR_CNT_4 0x124005033#define ACP_DMA_DSCR_CNT_5 0x124005434#define ACP_DMA_DSCR_CNT_6 0x124005835#define ACP_DMA_DSCR_CNT_7 0x124005C36#define ACP_DMA_PRIO_0 0x124006037#define ACP_DMA_PRIO_1 0x124006438#define ACP_DMA_PRIO_2 0x124006839#define ACP_DMA_PRIO_3 0x124006C40#define ACP_DMA_PRIO_4 0x124007041#define ACP_DMA_PRIO_5 0x124007442#define ACP_DMA_PRIO_6 0x124007843#define ACP_DMA_PRIO_7 0x124007C44#define ACP_DMA_CUR_DSCR_0 0x124008045#define ACP_DMA_CUR_DSCR_1 0x124008446#define ACP_DMA_CUR_DSCR_2 0x124008847#define ACP_DMA_CUR_DSCR_3 0x124008C48#define ACP_DMA_CUR_DSCR_4 0x124009049#define ACP_DMA_CUR_DSCR_5 0x124009450#define ACP_DMA_CUR_DSCR_6 0x124009851#define ACP_DMA_CUR_DSCR_7 0x124009C52#define ACP_DMA_CUR_TRANS_CNT_0 0x12400A053#define ACP_DMA_CUR_TRANS_CNT_1 0x12400A454#define ACP_DMA_CUR_TRANS_CNT_2 0x12400A855#define ACP_DMA_CUR_TRANS_CNT_3 0x12400AC56#define ACP_DMA_CUR_TRANS_CNT_4 0x12400B057#define ACP_DMA_CUR_TRANS_CNT_5 0x12400B458#define ACP_DMA_CUR_TRANS_CNT_6 0x12400B859#define ACP_DMA_CUR_TRANS_CNT_7 0x12400BC60#define ACP_DMA_ERR_STS_0 0x12400C061#define ACP_DMA_ERR_STS_1 0x12400C462#define ACP_DMA_ERR_STS_2 0x12400C863#define ACP_DMA_ERR_STS_3 0x12400CC64#define ACP_DMA_ERR_STS_4 0x12400D065#define ACP_DMA_ERR_STS_5 0x12400D466#define ACP_DMA_ERR_STS_6 0x12400D867#define ACP_DMA_ERR_STS_7 0x12400DC68#define ACP_DMA_DESC_BASE_ADDR 0x12400E069#define ACP_DMA_DESC_MAX_NUM_DSCR 0x12400E470#define ACP_DMA_CH_STS 0x12400E871#define ACP_DMA_CH_GROUP 0x12400EC72#define ACP_DMA_CH_RST_STS 0x12400F073 74/* Registers from ACP_AXI2AXIATU block */75#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_1 0x1240C0076#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_1 0x1240C0477#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_2 0x1240C0878#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_2 0x1240C0C79#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_3 0x1240C1080#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_3 0x1240C1481#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_4 0x1240C1882#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_4 0x1240C1C83#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_5 0x1240C2084#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_5 0x1240C2485#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_6 0x1240C2886#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_6 0x1240C2C87#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_7 0x1240C3088#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_7 0x1240C3489#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_8 0x1240C3890#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_8 0x1240C3C91#define ACPAXI2AXI_ATU_CTRL 0x1240C4092#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_9 0x1240C4493#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_9 0x1240C4894#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_10 0x1240C4C95#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_10 0x1240C5096#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_11 0x1240C5497#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_11 0x1240C5898#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_12 0x1240C5C99#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_12 0x1240C60100#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_13 0x1240C64101#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_13 0x1240C68102#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_14 0x1240C6C103#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_14 0x1240C70104#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_15 0x1240C74105#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_15 0x1240C78106#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_16 0x1240C7C107#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_16 0x1240C80108 109/* Registers from ACP_CLKRST block */110#define ACP_SOFT_RESET 0x1241000111#define ACP_CONTROL 0x1241004112#define ACP_STATUS 0x1241008113#define ACP_DYNAMIC_CG_MASTER_CONTROL 0x1241010114#define ACP_ZSC_DSP_CTRL 0x1241014115#define ACP_ZSC_STS 0x1241018116#define ACP_PGFSM_CONTROL 0x1241024117#define ACP_PGFSM_STATUS 0x1241028118#define ACP_CLKMUX_SEL 0x124102C119 120/* Registers from ACP_AON block */121#define ACP_PME_EN 0x1241400122#define ACP_DEVICE_STATE 0x1241404123#define AZ_DEVICE_STATE 0x1241408124#define ACP_PIN_CONFIG 0x1241440125#define ACP_PAD_PULLUP_CTRL 0x1241444126#define ACP_PAD_PULLDOWN_CTRL 0x1241448127#define ACP_PAD_DRIVE_STRENGTH_CTRL 0x124144C128#define ACP_PAD_SCHMEN_CTRL 0x1241450129#define ACP_SW_PAD_KEEPER_EN 0x1241454130#define ACP_SW_WAKE_EN 0x1241458131#define ACP_I2S_WAKE_EN 0x124145C132#define ACP_SW1_WAKE_EN 0x1241460133 134/* Registers from ACP_P1_MISC block */135#define ACP_EXTERNAL_INTR_ENB 0x1241A00136#define ACP_EXTERNAL_INTR_CNTL 0x1241A04137#define ACP_EXTERNAL_INTR_CNTL1 0x1241A08138#define ACP_EXTERNAL_INTR_STAT 0x1241A0C139#define ACP_EXTERNAL_INTR_STAT1 0x1241A10140#define ACP_ERROR_STATUS 0x1241A4C141#define ACP_P1_SW_I2S_ERROR_REASON 0x1241A50142#define ACP_P1_SW_POS_TRACK_I2S_TX_CTRL 0x1241A6C143#define ACP_P1_SW_I2S_TX_DMA_POS 0x1241A70144#define ACP_P1_SW_POS_TRACK_I2S_RX_CTRL 0x1241A74145#define ACP_P1_SW_I2S_RX_DMA_POS 0x1241A78146#define ACP_P1_DMIC_I2S_GPIO_INTR_CTRL 0x1241A7C147#define ACP_P1_DMIC_I2S_GPIO_INTR_STATUS 0x1241A80148#define ACP_SCRATCH_REG_BASE_ADDR 0x1241A84149#define ACP_P1_SW_POS_TRACK_BT_TX_CTRL 0x1241A88150#define ACP_P1_SW_BT_TX_DMA_POS 0x1241A8C151#define ACP_P1_SW_POS_TRACK_HS_TX_CTRL 0x1241A90152#define ACP_P1_SW_HS_TX_DMA_POS 0x1241A94153#define ACP_P1_SW_POS_TRACK_BT_RX_CTRL 0x1241A98154#define ACP_P1_SW_BT_RX_DMA_POS 0x1241A9C155#define ACP_P1_SW_POS_TRACK_HS_RX_CTRL 0x1241AA0156#define ACP_P1_SW_HS_RX_DMA_POS 0x1241AA4157 158/* Registers from ACP_AUDIO_BUFFERS block */159#define ACP_I2S_RX_RINGBUFADDR 0x1242000160#define ACP_I2S_RX_RINGBUFSIZE 0x1242004161#define ACP_I2S_RX_LINKPOSITIONCNTR 0x1242008162#define ACP_I2S_RX_FIFOADDR 0x124200C163#define ACP_I2S_RX_FIFOSIZE 0x1242010164#define ACP_I2S_RX_DMA_SIZE 0x1242014165#define ACP_I2S_RX_LINEARPOSITIONCNTR_HIGH 0x1242018166#define ACP_I2S_RX_LINEARPOSITIONCNTR_LOW 0x124201C167#define ACP_I2S_RX_INTR_WATERMARK_SIZE 0x1242020168#define ACP_I2S_TX_RINGBUFADDR 0x1242024169#define ACP_I2S_TX_RINGBUFSIZE 0x1242028170#define ACP_I2S_TX_LINKPOSITIONCNTR 0x124202C171#define ACP_I2S_TX_FIFOADDR 0x1242030172#define ACP_I2S_TX_FIFOSIZE 0x1242034173#define ACP_I2S_TX_DMA_SIZE 0x1242038174#define ACP_I2S_TX_LINEARPOSITIONCNTR_HIGH 0x124203C175#define ACP_I2S_TX_LINEARPOSITIONCNTR_LOW 0x1242040176#define ACP_I2S_TX_INTR_WATERMARK_SIZE 0x1242044177#define ACP_BT_RX_RINGBUFADDR 0x1242048178#define ACP_BT_RX_RINGBUFSIZE 0x124204C179#define ACP_BT_RX_LINKPOSITIONCNTR 0x1242050180#define ACP_BT_RX_FIFOADDR 0x1242054181#define ACP_BT_RX_FIFOSIZE 0x1242058182#define ACP_BT_RX_DMA_SIZE 0x124205C183#define ACP_BT_RX_LINEARPOSITIONCNTR_HIGH 0x1242060184#define ACP_BT_RX_LINEARPOSITIONCNTR_LOW 0x1242064185#define ACP_BT_RX_INTR_WATERMARK_SIZE 0x1242068186#define ACP_BT_TX_RINGBUFADDR 0x124206C187#define ACP_BT_TX_RINGBUFSIZE 0x1242070188#define ACP_BT_TX_LINKPOSITIONCNTR 0x1242074189#define ACP_BT_TX_FIFOADDR 0x1242078190#define ACP_BT_TX_FIFOSIZE 0x124207C191#define ACP_BT_TX_DMA_SIZE 0x1242080192#define ACP_BT_TX_LINEARPOSITIONCNTR_HIGH 0x1242084193#define ACP_BT_TX_LINEARPOSITIONCNTR_LOW 0x1242088194#define ACP_BT_TX_INTR_WATERMARK_SIZE 0x124208C195#define ACP_HS_RX_RINGBUFADDR 0x1242090196#define ACP_HS_RX_RINGBUFSIZE 0x1242094197#define ACP_HS_RX_LINKPOSITIONCNTR 0x1242098198#define ACP_HS_RX_FIFOADDR 0x124209C199#define ACP_HS_RX_FIFOSIZE 0x12420A0200#define ACP_HS_RX_DMA_SIZE 0x12420A4201#define ACP_HS_RX_LINEARPOSITIONCNTR_HIGH 0x12420A8202#define ACP_HS_RX_LINEARPOSITIONCNTR_LOW 0x12420AC203#define ACP_HS_RX_INTR_WATERMARK_SIZE 0x12420B0204#define ACP_HS_TX_RINGBUFADDR 0x12420B4205#define ACP_HS_TX_RINGBUFSIZE 0x12420B8206#define ACP_HS_TX_LINKPOSITIONCNTR 0x12420BC207#define ACP_HS_TX_FIFOADDR 0x12420C0208#define ACP_HS_TX_FIFOSIZE 0x12420C4209#define ACP_HS_TX_DMA_SIZE 0x12420C8210#define ACP_HS_TX_LINEARPOSITIONCNTR_HIGH 0x12420CC211#define ACP_HS_TX_LINEARPOSITIONCNTR_LOW 0x12420D0212#define ACP_HS_TX_INTR_WATERMARK_SIZE 0x12420D4213 214/* Registers from ACP_I2S_TDM block */215#define ACP_I2STDM_IER 0x1242400216#define ACP_I2STDM_IRER 0x1242404217#define ACP_I2STDM_RXFRMT 0x1242408218#define ACP_I2STDM_ITER 0x124240C219#define ACP_I2STDM_TXFRMT 0x1242410220#define ACP_I2STDM0_MSTRCLKGEN 0x1242414221#define ACP_I2STDM1_MSTRCLKGEN 0x1242418222#define ACP_I2STDM2_MSTRCLKGEN 0x124241C223#define ACP_I2STDM_REFCLKGEN 0x1242420224 225/* Registers from ACP_BT_TDM block */226#define ACP_BTTDM_IER 0x1242800227#define ACP_BTTDM_IRER 0x1242804228#define ACP_BTTDM_RXFRMT 0x1242808229#define ACP_BTTDM_ITER 0x124280C230#define ACP_BTTDM_TXFRMT 0x1242810231#define ACP_HSTDM_IER 0x1242814232#define ACP_HSTDM_IRER 0x1242818233#define ACP_HSTDM_RXFRMT 0x124281C234#define ACP_HSTDM_ITER 0x1242820235#define ACP_HSTDM_TXFRMT 0x1242824236 237/* Registers from ACP_WOV block */238#define ACP_WOV_PDM_ENABLE 0x1242C04239#define ACP_WOV_PDM_DMA_ENABLE 0x1242C08240#define ACP_WOV_RX_RINGBUFADDR 0x1242C0C241#define ACP_WOV_RX_RINGBUFSIZE 0x1242C10242#define ACP_WOV_RX_LINKPOSITIONCNTR 0x1242C14243#define ACP_WOV_RX_LINEARPOSITIONCNTR_HIGH 0x1242C18244#define ACP_WOV_RX_LINEARPOSITIONCNTR_LOW 0x1242C1C245#define ACP_WOV_RX_INTR_WATERMARK_SIZE 0x1242C20246#define ACP_WOV_PDM_FIFO_FLUSH 0x1242C24247#define ACP_WOV_PDM_NO_OF_CHANNELS 0x1242C28248#define ACP_WOV_PDM_DECIMATION_FACTOR 0x1242C2C249#define ACP_WOV_PDM_VAD_CTRL 0x1242C30250#define ACP_WOV_WAKE 0x1242C54251#define ACP_WOV_BUFFER_STATUS 0x1242C58252#define ACP_WOV_MISC_CTRL 0x1242C5C253#define ACP_WOV_CLK_CTRL 0x1242C60254#define ACP_PDM_VAD_DYNAMIC_CLK_GATING_EN 0x1242C64255#define ACP_WOV_ERROR_STATUS_REGISTER 0x1242C68256#define ACP_PDM_CLKDIV 0x1242C6C257 258/* Registers from ACP_P1_AUDIO_BUFFERS block */259#define ACP_P1_I2S_RX_RINGBUFADDR 0x1243A00260#define ACP_P1_I2S_RX_RINGBUFSIZE 0x1243A04261#define ACP_P1_I2S_RX_LINKPOSITIONCNTR 0x1243A08262#define ACP_P1_I2S_RX_FIFOADDR 0x1243A0C263#define ACP_P1_I2S_RX_FIFOSIZE 0x1243A10264#define ACP_P1_I2S_RX_DMA_SIZE 0x1243A14265#define ACP_P1_I2S_RX_LINEARPOSITIONCNTR_HIGH 0x1243A18266#define ACP_P1_I2S_RX_LINEARPOSITIONCNTR_LOW 0x1243A1C267#define ACP_P1_I2S_RX_INTR_WATERMARK_SIZE 0x1243A20268#define ACP_P1_I2S_TX_RINGBUFADDR 0x1243A24269#define ACP_P1_I2S_TX_RINGBUFSIZE 0x1243A28270#define ACP_P1_I2S_TX_LINKPOSITIONCNTR 0x1243A2C271#define ACP_P1_I2S_TX_FIFOADDR 0x1243A30272#define ACP_P1_I2S_TX_FIFOSIZE 0x1243A34273#define ACP_P1_I2S_TX_DMA_SIZE 0x1243A38274#define ACP_P1_I2S_TX_LINEARPOSITIONCNTR_HIGH 0x1243A3C275#define ACP_P1_I2S_TX_LINEARPOSITIONCNTR_LOW 0x1243A40276#define ACP_P1_I2S_TX_INTR_WATERMARK_SIZE 0x1243A44277#define ACP_P1_BT_RX_RINGBUFADDR 0x1243A48278#define ACP_P1_BT_RX_RINGBUFSIZE 0x1243A4C279#define ACP_P1_BT_RX_LINKPOSITIONCNTR 0x1243A50280#define ACP_P1_BT_RX_FIFOADDR 0x1243A54281#define ACP_P1_BT_RX_FIFOSIZE 0x1243A58282#define ACP_P1_BT_RX_DMA_SIZE 0x1243A5C283#define ACP_P1_BT_RX_LINEARPOSITIONCNTR_HIGH 0x1243A60284#define ACP_P1_BT_RX_LINEARPOSITIONCNTR_LOW 0x1243A64285#define ACP_P1_BT_RX_INTR_WATERMARK_SIZE 0x1243A68286#define ACP_P1_BT_TX_RINGBUFADDR 0x1243A6C287#define ACP_P1_BT_TX_RINGBUFSIZE 0x1243A70288#define ACP_P1_BT_TX_LINKPOSITIONCNTR 0x1243A74289#define ACP_P1_BT_TX_FIFOADDR 0x1243A78290#define ACP_P1_BT_TX_FIFOSIZE 0x1243A7C291#define ACP_P1_BT_TX_DMA_SIZE 0x1243A80292#define ACP_P1_BT_TX_LINEARPOSITIONCNTR_HIGH 0x1243A84293#define ACP_P1_BT_TX_LINEARPOSITIONCNTR_LOW 0x1243A88294#define ACP_P1_BT_TX_INTR_WATERMARK_SIZE 0x1243A8C295#define ACP_P1_HS_RX_RINGBUFADDR 0x1243A90296#define ACP_P1_HS_RX_RINGBUFSIZE 0x1243A94297#define ACP_P1_HS_RX_LINKPOSITIONCNTR 0x1243A98298#define ACP_P1_HS_RX_FIFOADDR 0x1243A9C299#define ACP_P1_HS_RX_FIFOSIZE 0x1243AA0300#define ACP_P1_HS_RX_DMA_SIZE 0x1243AA4301#define ACP_P1_HS_RX_LINEARPOSITIONCNTR_HIGH 0x1243AA8302#define ACP_P1_HS_RX_LINEARPOSITIONCNTR_LOW 0x1243AAC303#define ACP_P1_HS_RX_INTR_WATERMARK_SIZE 0x1243AB0304#define ACP_P1_HS_TX_RINGBUFADDR 0x1243AB4305#define ACP_P1_HS_TX_RINGBUFSIZE 0x1243AB8306#define ACP_P1_HS_TX_LINKPOSITIONCNTR 0x1243ABC307#define ACP_P1_HS_TX_FIFOADDR 0x1243AC0308#define ACP_P1_HS_TX_FIFOSIZE 0x1243AC4309#define ACP_P1_HS_TX_DMA_SIZE 0x1243AC8310#define ACP_P1_HS_TX_LINEARPOSITIONCNTR_HIGH 0x1243ACC311#define ACP_P1_HS_TX_LINEARPOSITIONCNTR_LOW 0x1243AD0312#define ACP_P1_HS_TX_INTR_WATERMARK_SIZE 0x1243AD4313 314/* Registers from ACP_SCRATCH block */315#define ACP_SCRATCH_REG_0 0x1250000316#define ACP_SCRATCH_REG_1 0x1250004317#define ACP_SCRATCH_REG_2 0x1250008318#define ACP_SCRATCH_REG_3 0x125000C319#define ACP_SCRATCH_REG_4 0x1250010320#define ACP_SCRATCH_REG_5 0x1250014321#define ACP_SCRATCH_REG_6 0x1250018322#define ACP_SCRATCH_REG_7 0x125001C323#define ACP_SCRATCH_REG_8 0x1250020324#define ACP_SCRATCH_REG_9 0x1250024325#define ACP_SCRATCH_REG_10 0x1250028326#define ACP_SCRATCH_REG_11 0x125002C327#define ACP_SCRATCH_REG_12 0x1250030328#define ACP_SCRATCH_REG_13 0x1250034329#define ACP_SCRATCH_REG_14 0x1250038330#define ACP_SCRATCH_REG_15 0x125003C331#define ACP_SCRATCH_REG_16 0x1250040332#define ACP_SCRATCH_REG_17 0x1250044333#define ACP_SCRATCH_REG_18 0x1250048334#define ACP_SCRATCH_REG_19 0x125004C335#define ACP_SCRATCH_REG_20 0x1250050336#define ACP_SCRATCH_REG_21 0x1250054337#define ACP_SCRATCH_REG_22 0x1250058338#define ACP_SCRATCH_REG_23 0x125005C339#define ACP_SCRATCH_REG_24 0x1250060340#define ACP_SCRATCH_REG_25 0x1250064341#define ACP_SCRATCH_REG_26 0x1250068342#define ACP_SCRATCH_REG_27 0x125006C343#define ACP_SCRATCH_REG_28 0x1250070344#define ACP_SCRATCH_REG_29 0x1250074345#define ACP_SCRATCH_REG_30 0x1250078346#define ACP_SCRATCH_REG_31 0x125007C347#define ACP_SCRATCH_REG_32 0x1250080348#define ACP_SCRATCH_REG_33 0x1250084349#define ACP_SCRATCH_REG_34 0x1250088350#define ACP_SCRATCH_REG_35 0x125008C351#define ACP_SCRATCH_REG_36 0x1250090352#define ACP_SCRATCH_REG_37 0x1250094353#define ACP_SCRATCH_REG_38 0x1250098354#define ACP_SCRATCH_REG_39 0x125009C355#define ACP_SCRATCH_REG_40 0x12500A0356#define ACP_SCRATCH_REG_41 0x12500A4357#define ACP_SCRATCH_REG_42 0x12500A8358#define ACP_SCRATCH_REG_43 0x12500AC359#define ACP_SCRATCH_REG_44 0x12500B0360#define ACP_SCRATCH_REG_45 0x12500B4361#define ACP_SCRATCH_REG_46 0x12500B8362#define ACP_SCRATCH_REG_47 0x12500BC363#define ACP_SCRATCH_REG_48 0x12500C0364#define ACP_SCRATCH_REG_49 0x12500C4365#define ACP_SCRATCH_REG_50 0x12500C8366#define ACP_SCRATCH_REG_51 0x12500CC367#define ACP_SCRATCH_REG_52 0x12500D0368#define ACP_SCRATCH_REG_53 0x12500D4369#define ACP_SCRATCH_REG_54 0x12500D8370#define ACP_SCRATCH_REG_55 0x12500DC371#define ACP_SCRATCH_REG_56 0x12500E0372#define ACP_SCRATCH_REG_57 0x12500E4373#define ACP_SCRATCH_REG_58 0x12500E8374#define ACP_SCRATCH_REG_59 0x12500EC375#define ACP_SCRATCH_REG_60 0x12500F0376#define ACP_SCRATCH_REG_61 0x12500F4377#define ACP_SCRATCH_REG_62 0x12500F8378#define ACP_SCRATCH_REG_63 0x12500FC379#define ACP_SCRATCH_REG_64 0x1250100380#define ACP_SCRATCH_REG_65 0x1250104381#define ACP_SCRATCH_REG_66 0x1250108382#define ACP_SCRATCH_REG_67 0x125010C383#define ACP_SCRATCH_REG_68 0x1250110384#define ACP_SCRATCH_REG_69 0x1250114385#define ACP_SCRATCH_REG_70 0x1250118386#define ACP_SCRATCH_REG_71 0x125011C387#define ACP_SCRATCH_REG_72 0x1250120388#define ACP_SCRATCH_REG_73 0x1250124389#define ACP_SCRATCH_REG_74 0x1250128390#define ACP_SCRATCH_REG_75 0x125012C391#define ACP_SCRATCH_REG_76 0x1250130392#define ACP_SCRATCH_REG_77 0x1250134393#define ACP_SCRATCH_REG_78 0x1250138394#define ACP_SCRATCH_REG_79 0x125013C395#define ACP_SCRATCH_REG_80 0x1250140396#define ACP_SCRATCH_REG_81 0x1250144397#define ACP_SCRATCH_REG_82 0x1250148398#define ACP_SCRATCH_REG_83 0x125014C399#define ACP_SCRATCH_REG_84 0x1250150400#define ACP_SCRATCH_REG_85 0x1250154401#define ACP_SCRATCH_REG_86 0x1250158402#define ACP_SCRATCH_REG_87 0x125015C403#define ACP_SCRATCH_REG_88 0x1250160404#define ACP_SCRATCH_REG_89 0x1250164405#define ACP_SCRATCH_REG_90 0x1250168406#define ACP_SCRATCH_REG_91 0x125016C407#define ACP_SCRATCH_REG_92 0x1250170408#define ACP_SCRATCH_REG_93 0x1250174409#define ACP_SCRATCH_REG_94 0x1250178410#define ACP_SCRATCH_REG_95 0x125017C411#define ACP_SCRATCH_REG_96 0x1250180412#define ACP_SCRATCH_REG_97 0x1250184413#define ACP_SCRATCH_REG_98 0x1250188414#define ACP_SCRATCH_REG_99 0x125018C415#define ACP_SCRATCH_REG_100 0x1250190416#define ACP_SCRATCH_REG_101 0x1250194417#define ACP_SCRATCH_REG_102 0x1250198418#define ACP_SCRATCH_REG_103 0x125019C419#define ACP_SCRATCH_REG_104 0x12501A0420#define ACP_SCRATCH_REG_105 0x12501A4421#define ACP_SCRATCH_REG_106 0x12501A8422#define ACP_SCRATCH_REG_107 0x12501AC423#define ACP_SCRATCH_REG_108 0x12501B0424#define ACP_SCRATCH_REG_109 0x12501B4425#define ACP_SCRATCH_REG_110 0x12501B8426#define ACP_SCRATCH_REG_111 0x12501BC427#define ACP_SCRATCH_REG_112 0x12501C0428#define ACP_SCRATCH_REG_113 0x12501C4429#define ACP_SCRATCH_REG_114 0x12501C8430#define ACP_SCRATCH_REG_115 0x12501CC431#define ACP_SCRATCH_REG_116 0x12501D0432#define ACP_SCRATCH_REG_117 0x12501D4433#define ACP_SCRATCH_REG_118 0x12501D8434#define ACP_SCRATCH_REG_119 0x12501DC435#define ACP_SCRATCH_REG_120 0x12501E0436#define ACP_SCRATCH_REG_121 0x12501E4437#define ACP_SCRATCH_REG_122 0x12501E8438#define ACP_SCRATCH_REG_123 0x12501EC439#define ACP_SCRATCH_REG_124 0x12501F0440#define ACP_SCRATCH_REG_125 0x12501F4441#define ACP_SCRATCH_REG_126 0x12501F8442#define ACP_SCRATCH_REG_127 0x12501FC443#define ACP_SCRATCH_REG_128 0x1250200444#endif445