1139 lines · c
1// SPDX-License-Identifier: GPL-2.02//3// Driver for Microchip I2S Multi-channel controller4//5// Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries6//7// Author: Codrin Ciubotariu <codrin.ciubotariu@microchip.com>8 9#include <linux/init.h>10#include <linux/module.h>11#include <linux/device.h>12#include <linux/slab.h>13 14#include <linux/delay.h>15#include <linux/io.h>16#include <linux/clk.h>17#include <linux/mfd/syscon.h>18#include <linux/lcm.h>19#include <linux/of.h>20 21#include <sound/core.h>22#include <sound/pcm.h>23#include <sound/pcm_params.h>24#include <sound/initval.h>25#include <sound/soc.h>26#include <sound/dmaengine_pcm.h>27 28/*29 * ---- I2S Controller Register map ----30 */31#define MCHP_I2SMCC_CR 0x0000 /* Control Register */32#define MCHP_I2SMCC_MRA 0x0004 /* Mode Register A */33#define MCHP_I2SMCC_MRB 0x0008 /* Mode Register B */34#define MCHP_I2SMCC_SR 0x000C /* Status Register */35#define MCHP_I2SMCC_IERA 0x0010 /* Interrupt Enable Register A */36#define MCHP_I2SMCC_IDRA 0x0014 /* Interrupt Disable Register A */37#define MCHP_I2SMCC_IMRA 0x0018 /* Interrupt Mask Register A */38#define MCHP_I2SMCC_ISRA 0X001C /* Interrupt Status Register A */39 40#define MCHP_I2SMCC_IERB 0x0020 /* Interrupt Enable Register B */41#define MCHP_I2SMCC_IDRB 0x0024 /* Interrupt Disable Register B */42#define MCHP_I2SMCC_IMRB 0x0028 /* Interrupt Mask Register B */43#define MCHP_I2SMCC_ISRB 0X002C /* Interrupt Status Register B */44 45#define MCHP_I2SMCC_RHR 0x0030 /* Receiver Holding Register */46#define MCHP_I2SMCC_THR 0x0034 /* Transmitter Holding Register */47 48#define MCHP_I2SMCC_RHL0R 0x0040 /* Receiver Holding Left 0 Register */49#define MCHP_I2SMCC_RHR0R 0x0044 /* Receiver Holding Right 0 Register */50 51#define MCHP_I2SMCC_RHL1R 0x0048 /* Receiver Holding Left 1 Register */52#define MCHP_I2SMCC_RHR1R 0x004C /* Receiver Holding Right 1 Register */53 54#define MCHP_I2SMCC_RHL2R 0x0050 /* Receiver Holding Left 2 Register */55#define MCHP_I2SMCC_RHR2R 0x0054 /* Receiver Holding Right 2 Register */56 57#define MCHP_I2SMCC_RHL3R 0x0058 /* Receiver Holding Left 3 Register */58#define MCHP_I2SMCC_RHR3R 0x005C /* Receiver Holding Right 3 Register */59 60#define MCHP_I2SMCC_THL0R 0x0060 /* Transmitter Holding Left 0 Register */61#define MCHP_I2SMCC_THR0R 0x0064 /* Transmitter Holding Right 0 Register */62 63#define MCHP_I2SMCC_THL1R 0x0068 /* Transmitter Holding Left 1 Register */64#define MCHP_I2SMCC_THR1R 0x006C /* Transmitter Holding Right 1 Register */65 66#define MCHP_I2SMCC_THL2R 0x0070 /* Transmitter Holding Left 2 Register */67#define MCHP_I2SMCC_THR2R 0x0074 /* Transmitter Holding Right 2 Register */68 69#define MCHP_I2SMCC_THL3R 0x0078 /* Transmitter Holding Left 3 Register */70#define MCHP_I2SMCC_THR3R 0x007C /* Transmitter Holding Right 3 Register */71 72#define MCHP_I2SMCC_VERSION 0x00FC /* Version Register */73 74/*75 * ---- Control Register (Write-only) ----76 */77#define MCHP_I2SMCC_CR_RXEN BIT(0) /* Receiver Enable */78#define MCHP_I2SMCC_CR_RXDIS BIT(1) /* Receiver Disable */79#define MCHP_I2SMCC_CR_CKEN BIT(2) /* Clock Enable */80#define MCHP_I2SMCC_CR_CKDIS BIT(3) /* Clock Disable */81#define MCHP_I2SMCC_CR_TXEN BIT(4) /* Transmitter Enable */82#define MCHP_I2SMCC_CR_TXDIS BIT(5) /* Transmitter Disable */83#define MCHP_I2SMCC_CR_SWRST BIT(7) /* Software Reset */84 85/*86 * ---- Mode Register A (Read/Write) ----87 */88#define MCHP_I2SMCC_MRA_MODE_MASK GENMASK(0, 0)89#define MCHP_I2SMCC_MRA_MODE_SLAVE (0 << 0)90#define MCHP_I2SMCC_MRA_MODE_MASTER (1 << 0)91 92#define MCHP_I2SMCC_MRA_DATALENGTH_MASK GENMASK(3, 1)93#define MCHP_I2SMCC_MRA_DATALENGTH_32_BITS (0 << 1)94#define MCHP_I2SMCC_MRA_DATALENGTH_24_BITS (1 << 1)95#define MCHP_I2SMCC_MRA_DATALENGTH_20_BITS (2 << 1)96#define MCHP_I2SMCC_MRA_DATALENGTH_18_BITS (3 << 1)97#define MCHP_I2SMCC_MRA_DATALENGTH_16_BITS (4 << 1)98#define MCHP_I2SMCC_MRA_DATALENGTH_16_BITS_COMPACT (5 << 1)99#define MCHP_I2SMCC_MRA_DATALENGTH_8_BITS (6 << 1)100#define MCHP_I2SMCC_MRA_DATALENGTH_8_BITS_COMPACT (7 << 1)101 102#define MCHP_I2SMCC_MRA_WIRECFG_MASK GENMASK(5, 4)103#define MCHP_I2SMCC_MRA_WIRECFG_TDM(pin) (((pin) << 4) & \104 MCHP_I2SMCC_MRA_WIRECFG_MASK)105#define MCHP_I2SMCC_MRA_WIRECFG_I2S_1_TDM_0 (0 << 4)106#define MCHP_I2SMCC_MRA_WIRECFG_I2S_2_TDM_1 (1 << 4)107#define MCHP_I2SMCC_MRA_WIRECFG_I2S_4_TDM_2 (2 << 4)108#define MCHP_I2SMCC_MRA_WIRECFG_TDM_3 (3 << 4)109 110#define MCHP_I2SMCC_MRA_FORMAT_MASK GENMASK(7, 6)111#define MCHP_I2SMCC_MRA_FORMAT_I2S (0 << 6)112#define MCHP_I2SMCC_MRA_FORMAT_LJ (1 << 6) /* Left Justified */113#define MCHP_I2SMCC_MRA_FORMAT_TDM (2 << 6)114#define MCHP_I2SMCC_MRA_FORMAT_TDMLJ (3 << 6)115 116/* Transmitter uses one DMA channel ... */117/* Left audio samples duplicated to right audio channel */118#define MCHP_I2SMCC_MRA_RXMONO BIT(8)119 120/* I2SDO output of I2SC is internally connected to I2SDI input */121#define MCHP_I2SMCC_MRA_RXLOOP BIT(9)122 123/* Receiver uses one DMA channel ... */124/* Left audio samples duplicated to right audio channel */125#define MCHP_I2SMCC_MRA_TXMONO BIT(10)126 127/* x sample transmitted when underrun */128#define MCHP_I2SMCC_MRA_TXSAME_ZERO (0 << 11) /* Zero sample */129#define MCHP_I2SMCC_MRA_TXSAME_PREVIOUS (1 << 11) /* Previous sample */130 131/* select between peripheral clock and generated clock */132#define MCHP_I2SMCC_MRA_SRCCLK_PCLK (0 << 12)133#define MCHP_I2SMCC_MRA_SRCCLK_GCLK (1 << 12)134 135/* Number of TDM Channels - 1 */136#define MCHP_I2SMCC_MRA_NBCHAN_MASK GENMASK(15, 13)137#define MCHP_I2SMCC_MRA_NBCHAN(ch) \138 ((((ch) - 1) << 13) & MCHP_I2SMCC_MRA_NBCHAN_MASK)139 140/* Selected Clock to I2SMCC Master Clock ratio */141#define MCHP_I2SMCC_MRA_IMCKDIV_MASK GENMASK(21, 16)142#define MCHP_I2SMCC_MRA_IMCKDIV(div) \143 (((div) << 16) & MCHP_I2SMCC_MRA_IMCKDIV_MASK)144 145/* TDM Frame Synchronization */146#define MCHP_I2SMCC_MRA_TDMFS_MASK GENMASK(23, 22)147#define MCHP_I2SMCC_MRA_TDMFS_SLOT (0 << 22)148#define MCHP_I2SMCC_MRA_TDMFS_HALF (1 << 22)149#define MCHP_I2SMCC_MRA_TDMFS_BIT (2 << 22)150 151/* Selected Clock to I2SMC Serial Clock ratio */152#define MCHP_I2SMCC_MRA_ISCKDIV_MASK GENMASK(29, 24)153#define MCHP_I2SMCC_MRA_ISCKDIV(div) \154 (((div) << 24) & MCHP_I2SMCC_MRA_ISCKDIV_MASK)155 156/* Master Clock mode */157#define MCHP_I2SMCC_MRA_IMCKMODE_MASK GENMASK(30, 30)158/* 0: No master clock generated*/159#define MCHP_I2SMCC_MRA_IMCKMODE_NONE (0 << 30)160/* 1: master clock generated (internally generated clock drives I2SMCK pin) */161#define MCHP_I2SMCC_MRA_IMCKMODE_GEN (1 << 30)162 163/* Slot Width */164/* 0: slot is 32 bits wide for DATALENGTH = 18/20/24 bits. */165/* 1: slot is 24 bits wide for DATALENGTH = 18/20/24 bits. */166#define MCHP_I2SMCC_MRA_IWS BIT(31)167 168/*169 * ---- Mode Register B (Read/Write) ----170 */171/* all enabled I2S left channels are filled first, then I2S right channels */172#define MCHP_I2SMCC_MRB_CRAMODE_LEFT_FIRST (0 << 0)173/*174 * an enabled I2S left channel is filled, then the corresponding right175 * channel, until all channels are filled176 */177#define MCHP_I2SMCC_MRB_CRAMODE_REGULAR (1 << 0)178 179#define MCHP_I2SMCC_MRB_FIFOEN BIT(4)180 181#define MCHP_I2SMCC_MRB_DMACHUNK_MASK GENMASK(9, 8)182#define MCHP_I2SMCC_MRB_DMACHUNK(no_words) \183 (((fls(no_words) - 1) << 8) & MCHP_I2SMCC_MRB_DMACHUNK_MASK)184 185#define MCHP_I2SMCC_MRB_CLKSEL_MASK GENMASK(16, 16)186#define MCHP_I2SMCC_MRB_CLKSEL_EXT (0 << 16)187#define MCHP_I2SMCC_MRB_CLKSEL_INT (1 << 16)188 189/*190 * ---- Status Registers (Read-only) ----191 */192#define MCHP_I2SMCC_SR_RXEN BIT(0) /* Receiver Enabled */193#define MCHP_I2SMCC_SR_TXEN BIT(4) /* Transmitter Enabled */194 195/*196 * ---- Interrupt Enable/Disable/Mask/Status Registers A ----197 */198#define MCHP_I2SMCC_INT_TXRDY_MASK(ch) GENMASK((ch) - 1, 0)199#define MCHP_I2SMCC_INT_TXRDYCH(ch) BIT(ch)200#define MCHP_I2SMCC_INT_TXUNF_MASK(ch) GENMASK((ch) + 7, 8)201#define MCHP_I2SMCC_INT_TXUNFCH(ch) BIT((ch) + 8)202#define MCHP_I2SMCC_INT_RXRDY_MASK(ch) GENMASK((ch) + 15, 16)203#define MCHP_I2SMCC_INT_RXRDYCH(ch) BIT((ch) + 16)204#define MCHP_I2SMCC_INT_RXOVF_MASK(ch) GENMASK((ch) + 23, 24)205#define MCHP_I2SMCC_INT_RXOVFCH(ch) BIT((ch) + 24)206 207/*208 * ---- Interrupt Enable/Disable/Mask/Status Registers B ----209 */210#define MCHP_I2SMCC_INT_WERR BIT(0)211#define MCHP_I2SMCC_INT_TXFFRDY BIT(8)212#define MCHP_I2SMCC_INT_TXFFEMP BIT(9)213#define MCHP_I2SMCC_INT_RXFFRDY BIT(12)214#define MCHP_I2SMCC_INT_RXFFFUL BIT(13)215 216/*217 * ---- Version Register (Read-only) ----218 */219#define MCHP_I2SMCC_VERSION_MASK GENMASK(11, 0)220 221#define MCHP_I2SMCC_MAX_CHANNELS 8222#define MCHP_I2MCC_TDM_SLOT_WIDTH 32223 224/*225 * ---- DMA chunk size allowed ----226 */227#define MCHP_I2SMCC_DMA_8_WORD_CHUNK 8228#define MCHP_I2SMCC_DMA_4_WORD_CHUNK 4229#define MCHP_I2SMCC_DMA_2_WORD_CHUNK 2230#define MCHP_I2SMCC_DMA_1_WORD_CHUNK 1231#define DMA_BURST_ALIGNED(_p, _s, _w) !(_p % (_s * _w))232 233static const struct regmap_config mchp_i2s_mcc_regmap_config = {234 .reg_bits = 32,235 .reg_stride = 4,236 .val_bits = 32,237 .max_register = MCHP_I2SMCC_VERSION,238};239 240struct mchp_i2s_mcc_soc_data {241 unsigned int data_pin_pair_num;242 bool has_fifo;243};244 245struct mchp_i2s_mcc_dev {246 struct wait_queue_head wq_txrdy;247 struct wait_queue_head wq_rxrdy;248 struct device *dev;249 struct regmap *regmap;250 struct clk *pclk;251 struct clk *gclk;252 const struct mchp_i2s_mcc_soc_data *soc;253 struct snd_dmaengine_dai_dma_data playback;254 struct snd_dmaengine_dai_dma_data capture;255 unsigned int fmt;256 unsigned int sysclk;257 unsigned int frame_length;258 int tdm_slots;259 int channels;260 u8 tdm_data_pair;261 unsigned int gclk_use:1;262 unsigned int gclk_running:1;263 unsigned int tx_rdy:1;264 unsigned int rx_rdy:1;265};266 267static irqreturn_t mchp_i2s_mcc_interrupt(int irq, void *dev_id)268{269 struct mchp_i2s_mcc_dev *dev = dev_id;270 u32 sra, imra, srb, imrb, pendinga, pendingb, idra = 0, idrb = 0;271 irqreturn_t ret = IRQ_NONE;272 273 regmap_read(dev->regmap, MCHP_I2SMCC_IMRA, &imra);274 regmap_read(dev->regmap, MCHP_I2SMCC_ISRA, &sra);275 pendinga = imra & sra;276 277 regmap_read(dev->regmap, MCHP_I2SMCC_IMRB, &imrb);278 regmap_read(dev->regmap, MCHP_I2SMCC_ISRB, &srb);279 pendingb = imrb & srb;280 281 if (!pendinga && !pendingb)282 return IRQ_NONE;283 284 /*285 * Tx/Rx ready interrupts are enabled when stopping only, to assure286 * availability and to disable clocks if necessary287 */288 if (dev->soc->has_fifo) {289 idrb |= pendingb & (MCHP_I2SMCC_INT_TXFFRDY |290 MCHP_I2SMCC_INT_RXFFRDY);291 } else {292 idra |= pendinga & (MCHP_I2SMCC_INT_TXRDY_MASK(dev->channels) |293 MCHP_I2SMCC_INT_RXRDY_MASK(dev->channels));294 }295 if (idra || idrb)296 ret = IRQ_HANDLED;297 298 if ((!dev->soc->has_fifo &&299 (imra & MCHP_I2SMCC_INT_TXRDY_MASK(dev->channels)) &&300 (imra & MCHP_I2SMCC_INT_TXRDY_MASK(dev->channels)) ==301 (idra & MCHP_I2SMCC_INT_TXRDY_MASK(dev->channels))) ||302 (dev->soc->has_fifo && imrb & MCHP_I2SMCC_INT_TXFFRDY)) {303 dev->tx_rdy = 1;304 wake_up_interruptible(&dev->wq_txrdy);305 }306 if ((!dev->soc->has_fifo &&307 (imra & MCHP_I2SMCC_INT_RXRDY_MASK(dev->channels)) &&308 (imra & MCHP_I2SMCC_INT_RXRDY_MASK(dev->channels)) ==309 (idra & MCHP_I2SMCC_INT_RXRDY_MASK(dev->channels))) ||310 (dev->soc->has_fifo && imrb & MCHP_I2SMCC_INT_RXFFRDY)) {311 dev->rx_rdy = 1;312 wake_up_interruptible(&dev->wq_rxrdy);313 }314 if (dev->soc->has_fifo)315 regmap_write(dev->regmap, MCHP_I2SMCC_IDRB, idrb);316 else317 regmap_write(dev->regmap, MCHP_I2SMCC_IDRA, idra);318 319 return ret;320}321 322static int mchp_i2s_mcc_set_sysclk(struct snd_soc_dai *dai,323 int clk_id, unsigned int freq, int dir)324{325 struct mchp_i2s_mcc_dev *dev = snd_soc_dai_get_drvdata(dai);326 327 dev_dbg(dev->dev, "%s() clk_id=%d freq=%u dir=%d\n",328 __func__, clk_id, freq, dir);329 330 /* We do not need SYSCLK */331 if (dir == SND_SOC_CLOCK_IN)332 return 0;333 334 dev->sysclk = freq;335 336 return 0;337}338 339static int mchp_i2s_mcc_set_bclk_ratio(struct snd_soc_dai *dai,340 unsigned int ratio)341{342 struct mchp_i2s_mcc_dev *dev = snd_soc_dai_get_drvdata(dai);343 344 dev_dbg(dev->dev, "%s() ratio=%u\n", __func__, ratio);345 346 dev->frame_length = ratio;347 348 return 0;349}350 351static int mchp_i2s_mcc_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)352{353 struct mchp_i2s_mcc_dev *dev = snd_soc_dai_get_drvdata(dai);354 355 dev_dbg(dev->dev, "%s() fmt=%#x\n", __func__, fmt);356 357 /* We don't support any kind of clock inversion */358 if ((fmt & SND_SOC_DAIFMT_INV_MASK) != SND_SOC_DAIFMT_NB_NF)359 return -EINVAL;360 361 /* We can't generate only FSYNC */362 if ((fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) == SND_SOC_DAIFMT_BC_FP)363 return -EINVAL;364 365 /* We can only reconfigure the IP when it's stopped */366 if (fmt & SND_SOC_DAIFMT_CONT)367 return -EINVAL;368 369 dev->fmt = fmt;370 371 return 0;372}373 374static int mchp_i2s_mcc_set_dai_tdm_slot(struct snd_soc_dai *dai,375 unsigned int tx_mask,376 unsigned int rx_mask,377 int slots, int slot_width)378{379 struct mchp_i2s_mcc_dev *dev = snd_soc_dai_get_drvdata(dai);380 381 dev_dbg(dev->dev,382 "%s() tx_mask=0x%08x rx_mask=0x%08x slots=%d width=%d\n",383 __func__, tx_mask, rx_mask, slots, slot_width);384 385 if (slots < 0 || slots > MCHP_I2SMCC_MAX_CHANNELS ||386 slot_width != MCHP_I2MCC_TDM_SLOT_WIDTH)387 return -EINVAL;388 389 if (slots) {390 /* We do not support daisy chain */391 if (rx_mask != GENMASK(slots - 1, 0) ||392 rx_mask != tx_mask)393 return -EINVAL;394 }395 396 dev->tdm_slots = slots;397 dev->frame_length = slots * MCHP_I2MCC_TDM_SLOT_WIDTH;398 399 return 0;400}401 402static int mchp_i2s_mcc_clk_get_rate_diff(struct clk *clk,403 unsigned long rate,404 struct clk **best_clk,405 unsigned long *best_rate,406 unsigned long *best_diff_rate)407{408 long round_rate;409 unsigned int diff_rate;410 411 round_rate = clk_round_rate(clk, rate);412 if (round_rate < 0)413 return (int)round_rate;414 415 diff_rate = abs(rate - round_rate);416 if (diff_rate < *best_diff_rate) {417 *best_clk = clk;418 *best_diff_rate = diff_rate;419 *best_rate = rate;420 }421 422 return 0;423}424 425static int mchp_i2s_mcc_config_divs(struct mchp_i2s_mcc_dev *dev,426 unsigned int bclk, unsigned int *mra,427 unsigned long *best_rate)428{429 unsigned long clk_rate;430 unsigned long lcm_rate;431 unsigned long best_diff_rate = ~0;432 unsigned int sysclk;433 struct clk *best_clk = NULL;434 int ret;435 436 /* For code simplification */437 if (!dev->sysclk)438 sysclk = bclk;439 else440 sysclk = dev->sysclk;441 442 /*443 * MCLK is Selected CLK / (2 * IMCKDIV),444 * BCLK is Selected CLK / (2 * ISCKDIV);445 * if IMCKDIV or ISCKDIV are 0, MCLK or BCLK = Selected CLK446 */447 lcm_rate = lcm(sysclk, bclk);448 if ((lcm_rate / sysclk % 2 == 1 && lcm_rate / sysclk > 2) ||449 (lcm_rate / bclk % 2 == 1 && lcm_rate / bclk > 2))450 lcm_rate *= 2;451 452 for (clk_rate = lcm_rate;453 (clk_rate == sysclk || clk_rate / (sysclk * 2) <= GENMASK(5, 0)) &&454 (clk_rate == bclk || clk_rate / (bclk * 2) <= GENMASK(5, 0));455 clk_rate += lcm_rate) {456 ret = mchp_i2s_mcc_clk_get_rate_diff(dev->gclk, clk_rate,457 &best_clk, best_rate,458 &best_diff_rate);459 if (ret) {460 dev_err(dev->dev, "gclk error for rate %lu: %d",461 clk_rate, ret);462 } else {463 if (!best_diff_rate) {464 dev_dbg(dev->dev, "found perfect rate on gclk: %lu\n",465 clk_rate);466 break;467 }468 }469 470 ret = mchp_i2s_mcc_clk_get_rate_diff(dev->pclk, clk_rate,471 &best_clk, best_rate,472 &best_diff_rate);473 if (ret) {474 dev_err(dev->dev, "pclk error for rate %lu: %d",475 clk_rate, ret);476 } else {477 if (!best_diff_rate) {478 dev_dbg(dev->dev, "found perfect rate on pclk: %lu\n",479 clk_rate);480 break;481 }482 }483 }484 485 /* check if clocks returned only errors */486 if (!best_clk) {487 dev_err(dev->dev, "unable to change rate to clocks\n");488 return -EINVAL;489 }490 491 dev_dbg(dev->dev, "source CLK is %s with rate %lu, diff %lu\n",492 best_clk == dev->pclk ? "pclk" : "gclk",493 *best_rate, best_diff_rate);494 495 /* Configure divisors */496 if (dev->sysclk)497 *mra |= MCHP_I2SMCC_MRA_IMCKDIV(*best_rate / (2 * sysclk));498 *mra |= MCHP_I2SMCC_MRA_ISCKDIV(*best_rate / (2 * bclk));499 500 if (best_clk == dev->gclk)501 *mra |= MCHP_I2SMCC_MRA_SRCCLK_GCLK;502 else503 *mra |= MCHP_I2SMCC_MRA_SRCCLK_PCLK;504 505 return 0;506}507 508static int mchp_i2s_mcc_is_running(struct mchp_i2s_mcc_dev *dev)509{510 u32 sr;511 512 regmap_read(dev->regmap, MCHP_I2SMCC_SR, &sr);513 return !!(sr & (MCHP_I2SMCC_SR_TXEN | MCHP_I2SMCC_SR_RXEN));514}515 516static inline int mchp_i2s_mcc_period_to_maxburst(int period_size, int sample_size)517{518 int p_size = period_size;519 int s_size = sample_size;520 521 if (DMA_BURST_ALIGNED(p_size, s_size, MCHP_I2SMCC_DMA_8_WORD_CHUNK))522 return MCHP_I2SMCC_DMA_8_WORD_CHUNK;523 if (DMA_BURST_ALIGNED(p_size, s_size, MCHP_I2SMCC_DMA_4_WORD_CHUNK))524 return MCHP_I2SMCC_DMA_4_WORD_CHUNK;525 if (DMA_BURST_ALIGNED(p_size, s_size, MCHP_I2SMCC_DMA_2_WORD_CHUNK))526 return MCHP_I2SMCC_DMA_2_WORD_CHUNK;527 return MCHP_I2SMCC_DMA_1_WORD_CHUNK;528}529 530static int mchp_i2s_mcc_hw_params(struct snd_pcm_substream *substream,531 struct snd_pcm_hw_params *params,532 struct snd_soc_dai *dai)533{534 unsigned long rate = 0;535 struct mchp_i2s_mcc_dev *dev = snd_soc_dai_get_drvdata(dai);536 int sample_bytes = params_physical_width(params) / 8;537 int period_bytes = params_period_size(params) *538 params_channels(params) * sample_bytes;539 int maxburst;540 u32 mra = 0;541 u32 mrb = 0;542 unsigned int channels = params_channels(params);543 unsigned int frame_length = dev->frame_length;544 unsigned int bclk_rate;545 int set_divs = 0;546 int ret;547 bool is_playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);548 549 dev_dbg(dev->dev, "%s() rate=%u format=%#x width=%u channels=%u period_bytes=%d\n",550 __func__, params_rate(params), params_format(params),551 params_width(params), params_channels(params), period_bytes);552 553 switch (dev->fmt & SND_SOC_DAIFMT_FORMAT_MASK) {554 case SND_SOC_DAIFMT_I2S:555 if (dev->tdm_slots) {556 dev_err(dev->dev, "I2S with TDM is not supported\n");557 return -EINVAL;558 }559 mra |= MCHP_I2SMCC_MRA_FORMAT_I2S;560 break;561 case SND_SOC_DAIFMT_LEFT_J:562 if (dev->tdm_slots) {563 dev_err(dev->dev, "Left-Justified with TDM is not supported\n");564 return -EINVAL;565 }566 mra |= MCHP_I2SMCC_MRA_FORMAT_LJ;567 break;568 case SND_SOC_DAIFMT_DSP_A:569 mra |= MCHP_I2SMCC_MRA_FORMAT_TDM;570 break;571 default:572 dev_err(dev->dev, "unsupported bus format\n");573 return -EINVAL;574 }575 576 switch (dev->fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {577 case SND_SOC_DAIFMT_BP_FP:578 /* cpu is BCLK and LRC master */579 mra |= MCHP_I2SMCC_MRA_MODE_MASTER;580 if (dev->sysclk)581 mra |= MCHP_I2SMCC_MRA_IMCKMODE_GEN;582 set_divs = 1;583 break;584 case SND_SOC_DAIFMT_BP_FC:585 /* cpu is BCLK master */586 mrb |= MCHP_I2SMCC_MRB_CLKSEL_INT;587 set_divs = 1;588 fallthrough;589 case SND_SOC_DAIFMT_BC_FC:590 /* cpu is slave */591 mra |= MCHP_I2SMCC_MRA_MODE_SLAVE;592 if (dev->sysclk)593 dev_warn(dev->dev, "Unable to generate MCLK in Slave mode\n");594 break;595 default:596 dev_err(dev->dev, "unsupported master/slave mode\n");597 return -EINVAL;598 }599 600 if (dev->fmt & (SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_LEFT_J)) {601 /* for I2S and LEFT_J one pin is needed for every 2 channels */602 if (channels > dev->soc->data_pin_pair_num * 2) {603 dev_err(dev->dev,604 "unsupported number of audio channels: %d\n",605 channels);606 return -EINVAL;607 }608 609 /* enable for interleaved format */610 mrb |= MCHP_I2SMCC_MRB_CRAMODE_REGULAR;611 612 switch (channels) {613 case 1:614 if (is_playback)615 mra |= MCHP_I2SMCC_MRA_TXMONO;616 else617 mra |= MCHP_I2SMCC_MRA_RXMONO;618 break;619 case 2:620 break;621 case 4:622 mra |= MCHP_I2SMCC_MRA_WIRECFG_I2S_2_TDM_1;623 break;624 case 8:625 mra |= MCHP_I2SMCC_MRA_WIRECFG_I2S_4_TDM_2;626 break;627 default:628 dev_err(dev->dev, "unsupported number of audio channels\n");629 return -EINVAL;630 }631 632 if (!frame_length)633 frame_length = 2 * params_physical_width(params);634 } else if (dev->fmt & SND_SOC_DAIFMT_DSP_A) {635 mra |= MCHP_I2SMCC_MRA_WIRECFG_TDM(dev->tdm_data_pair);636 637 if (dev->tdm_slots) {638 if (channels % 2 && channels * 2 <= dev->tdm_slots) {639 /*640 * Duplicate data for even-numbered channels641 * to odd-numbered channels642 */643 if (is_playback)644 mra |= MCHP_I2SMCC_MRA_TXMONO;645 else646 mra |= MCHP_I2SMCC_MRA_RXMONO;647 }648 channels = dev->tdm_slots;649 }650 651 mra |= MCHP_I2SMCC_MRA_NBCHAN(channels);652 if (!frame_length)653 frame_length = channels * MCHP_I2MCC_TDM_SLOT_WIDTH;654 }655 656 /*657 * We must have the same burst size configured658 * in the DMA transfer and in out IP659 */660 maxburst = mchp_i2s_mcc_period_to_maxburst(period_bytes, sample_bytes);661 mrb |= MCHP_I2SMCC_MRB_DMACHUNK(maxburst);662 if (is_playback)663 dev->playback.maxburst = maxburst;664 else665 dev->capture.maxburst = maxburst;666 667 switch (params_format(params)) {668 case SNDRV_PCM_FORMAT_S8:669 mra |= MCHP_I2SMCC_MRA_DATALENGTH_8_BITS;670 break;671 case SNDRV_PCM_FORMAT_S16_LE:672 mra |= MCHP_I2SMCC_MRA_DATALENGTH_16_BITS;673 break;674 case SNDRV_PCM_FORMAT_S18_3LE:675 mra |= MCHP_I2SMCC_MRA_DATALENGTH_18_BITS |676 MCHP_I2SMCC_MRA_IWS;677 break;678 case SNDRV_PCM_FORMAT_S20_3LE:679 mra |= MCHP_I2SMCC_MRA_DATALENGTH_20_BITS |680 MCHP_I2SMCC_MRA_IWS;681 break;682 case SNDRV_PCM_FORMAT_S24_3LE:683 mra |= MCHP_I2SMCC_MRA_DATALENGTH_24_BITS |684 MCHP_I2SMCC_MRA_IWS;685 break;686 case SNDRV_PCM_FORMAT_S24_LE:687 mra |= MCHP_I2SMCC_MRA_DATALENGTH_24_BITS;688 break;689 case SNDRV_PCM_FORMAT_S32_LE:690 mra |= MCHP_I2SMCC_MRA_DATALENGTH_32_BITS;691 break;692 default:693 dev_err(dev->dev, "unsupported size/endianness for audio samples\n");694 return -EINVAL;695 }696 697 if (set_divs) {698 bclk_rate = frame_length * params_rate(params);699 ret = mchp_i2s_mcc_config_divs(dev, bclk_rate, &mra,700 &rate);701 if (ret) {702 dev_err(dev->dev,703 "unable to configure the divisors: %d\n", ret);704 return ret;705 }706 }707 708 /* enable FIFO if available */709 if (dev->soc->has_fifo)710 mrb |= MCHP_I2SMCC_MRB_FIFOEN;711 712 /*713 * If we are already running, the wanted setup must be714 * the same with the one that's currently ongoing715 */716 if (mchp_i2s_mcc_is_running(dev)) {717 u32 mra_cur;718 u32 mrb_cur;719 720 regmap_read(dev->regmap, MCHP_I2SMCC_MRA, &mra_cur);721 regmap_read(dev->regmap, MCHP_I2SMCC_MRB, &mrb_cur);722 if (mra != mra_cur || mrb != mrb_cur)723 return -EINVAL;724 725 return 0;726 }727 728 if (mra & MCHP_I2SMCC_MRA_SRCCLK_GCLK && !dev->gclk_use) {729 /* set the rate */730 ret = clk_set_rate(dev->gclk, rate);731 if (ret) {732 dev_err(dev->dev,733 "unable to set rate %lu to GCLK: %d\n",734 rate, ret);735 return ret;736 }737 738 ret = clk_prepare(dev->gclk);739 if (ret < 0) {740 dev_err(dev->dev, "unable to prepare GCLK: %d\n", ret);741 return ret;742 }743 dev->gclk_use = 1;744 }745 746 /* Save the number of channels to know what interrupts to enable */747 dev->channels = channels;748 749 ret = regmap_write(dev->regmap, MCHP_I2SMCC_MRA, mra);750 if (ret < 0) {751 if (dev->gclk_use) {752 clk_unprepare(dev->gclk);753 dev->gclk_use = 0;754 }755 return ret;756 }757 return regmap_write(dev->regmap, MCHP_I2SMCC_MRB, mrb);758}759 760static int mchp_i2s_mcc_hw_free(struct snd_pcm_substream *substream,761 struct snd_soc_dai *dai)762{763 struct mchp_i2s_mcc_dev *dev = snd_soc_dai_get_drvdata(dai);764 bool is_playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);765 long err;766 767 if (is_playback) {768 err = wait_event_interruptible_timeout(dev->wq_txrdy,769 dev->tx_rdy,770 msecs_to_jiffies(500));771 if (err == 0) {772 dev_warn_once(dev->dev,773 "Timeout waiting for Tx ready\n");774 if (dev->soc->has_fifo)775 regmap_write(dev->regmap, MCHP_I2SMCC_IDRB,776 MCHP_I2SMCC_INT_TXFFRDY);777 else778 regmap_write(dev->regmap, MCHP_I2SMCC_IDRA,779 MCHP_I2SMCC_INT_TXRDY_MASK(dev->channels));780 781 dev->tx_rdy = 1;782 }783 } else {784 err = wait_event_interruptible_timeout(dev->wq_rxrdy,785 dev->rx_rdy,786 msecs_to_jiffies(500));787 if (err == 0) {788 dev_warn_once(dev->dev,789 "Timeout waiting for Rx ready\n");790 if (dev->soc->has_fifo)791 regmap_write(dev->regmap, MCHP_I2SMCC_IDRB,792 MCHP_I2SMCC_INT_RXFFRDY);793 else794 regmap_write(dev->regmap, MCHP_I2SMCC_IDRA,795 MCHP_I2SMCC_INT_RXRDY_MASK(dev->channels));796 dev->rx_rdy = 1;797 }798 }799 800 if (!mchp_i2s_mcc_is_running(dev)) {801 regmap_write(dev->regmap, MCHP_I2SMCC_CR, MCHP_I2SMCC_CR_CKDIS);802 803 if (dev->gclk_running) {804 clk_disable(dev->gclk);805 dev->gclk_running = 0;806 }807 if (dev->gclk_use) {808 clk_unprepare(dev->gclk);809 dev->gclk_use = 0;810 }811 }812 813 return 0;814}815 816static int mchp_i2s_mcc_trigger(struct snd_pcm_substream *substream, int cmd,817 struct snd_soc_dai *dai)818{819 struct mchp_i2s_mcc_dev *dev = snd_soc_dai_get_drvdata(dai);820 bool is_playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);821 u32 cr = 0;822 u32 iera = 0, ierb = 0;823 u32 sr;824 int err;825 826 switch (cmd) {827 case SNDRV_PCM_TRIGGER_START:828 case SNDRV_PCM_TRIGGER_RESUME:829 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:830 if (is_playback)831 cr = MCHP_I2SMCC_CR_TXEN | MCHP_I2SMCC_CR_CKEN;832 else833 cr = MCHP_I2SMCC_CR_RXEN | MCHP_I2SMCC_CR_CKEN;834 break;835 case SNDRV_PCM_TRIGGER_STOP:836 case SNDRV_PCM_TRIGGER_SUSPEND:837 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:838 regmap_read(dev->regmap, MCHP_I2SMCC_SR, &sr);839 if (is_playback && (sr & MCHP_I2SMCC_SR_TXEN)) {840 cr = MCHP_I2SMCC_CR_TXDIS;841 dev->tx_rdy = 0;842 /*843 * Enable Tx Ready interrupts on all channels844 * to assure all data is sent845 */846 if (dev->soc->has_fifo)847 ierb = MCHP_I2SMCC_INT_TXFFRDY;848 else849 iera = MCHP_I2SMCC_INT_TXRDY_MASK(dev->channels);850 } else if (!is_playback && (sr & MCHP_I2SMCC_SR_RXEN)) {851 cr = MCHP_I2SMCC_CR_RXDIS;852 dev->rx_rdy = 0;853 /*854 * Enable Rx Ready interrupts on all channels855 * to assure all data is received856 */857 if (dev->soc->has_fifo)858 ierb = MCHP_I2SMCC_INT_RXFFRDY;859 else860 iera = MCHP_I2SMCC_INT_RXRDY_MASK(dev->channels);861 }862 break;863 default:864 return -EINVAL;865 }866 867 if ((cr & MCHP_I2SMCC_CR_CKEN) && dev->gclk_use &&868 !dev->gclk_running) {869 err = clk_enable(dev->gclk);870 if (err) {871 dev_err_once(dev->dev, "failed to enable GCLK: %d\n",872 err);873 } else {874 dev->gclk_running = 1;875 }876 }877 878 if (dev->soc->has_fifo)879 regmap_write(dev->regmap, MCHP_I2SMCC_IERB, ierb);880 else881 regmap_write(dev->regmap, MCHP_I2SMCC_IERA, iera);882 regmap_write(dev->regmap, MCHP_I2SMCC_CR, cr);883 884 return 0;885}886 887static int mchp_i2s_mcc_startup(struct snd_pcm_substream *substream,888 struct snd_soc_dai *dai)889{890 struct mchp_i2s_mcc_dev *dev = snd_soc_dai_get_drvdata(dai);891 892 /* Software reset the IP if it's not running */893 if (!mchp_i2s_mcc_is_running(dev)) {894 return regmap_write(dev->regmap, MCHP_I2SMCC_CR,895 MCHP_I2SMCC_CR_SWRST);896 }897 898 return 0;899}900 901static int mchp_i2s_mcc_dai_probe(struct snd_soc_dai *dai)902{903 struct mchp_i2s_mcc_dev *dev = snd_soc_dai_get_drvdata(dai);904 905 init_waitqueue_head(&dev->wq_txrdy);906 init_waitqueue_head(&dev->wq_rxrdy);907 dev->tx_rdy = 1;908 dev->rx_rdy = 1;909 910 snd_soc_dai_init_dma_data(dai, &dev->playback, &dev->capture);911 912 return 0;913}914 915static const struct snd_soc_dai_ops mchp_i2s_mcc_dai_ops = {916 .probe = mchp_i2s_mcc_dai_probe,917 .set_sysclk = mchp_i2s_mcc_set_sysclk,918 .set_bclk_ratio = mchp_i2s_mcc_set_bclk_ratio,919 .startup = mchp_i2s_mcc_startup,920 .trigger = mchp_i2s_mcc_trigger,921 .hw_params = mchp_i2s_mcc_hw_params,922 .hw_free = mchp_i2s_mcc_hw_free,923 .set_fmt = mchp_i2s_mcc_set_dai_fmt,924 .set_tdm_slot = mchp_i2s_mcc_set_dai_tdm_slot,925};926 927#define MCHP_I2SMCC_RATES SNDRV_PCM_RATE_8000_192000928 929#define MCHP_I2SMCC_FORMATS (SNDRV_PCM_FMTBIT_S8 | \930 SNDRV_PCM_FMTBIT_S16_LE | \931 SNDRV_PCM_FMTBIT_S18_3LE | \932 SNDRV_PCM_FMTBIT_S20_3LE | \933 SNDRV_PCM_FMTBIT_S24_3LE | \934 SNDRV_PCM_FMTBIT_S24_LE | \935 SNDRV_PCM_FMTBIT_S32_LE)936 937static struct snd_soc_dai_driver mchp_i2s_mcc_dai = {938 .playback = {939 .stream_name = "Playback",940 .channels_min = 1,941 .channels_max = 8,942 .rates = MCHP_I2SMCC_RATES,943 .formats = MCHP_I2SMCC_FORMATS,944 },945 .capture = {946 .stream_name = "Capture",947 .channels_min = 1,948 .channels_max = 8,949 .rates = MCHP_I2SMCC_RATES,950 .formats = MCHP_I2SMCC_FORMATS,951 },952 .ops = &mchp_i2s_mcc_dai_ops,953 .symmetric_rate = 1,954 .symmetric_sample_bits = 1,955 .symmetric_channels = 1,956};957 958static const struct snd_soc_component_driver mchp_i2s_mcc_component = {959 .name = "mchp-i2s-mcc",960 .legacy_dai_naming = 1,961};962 963#ifdef CONFIG_OF964static struct mchp_i2s_mcc_soc_data mchp_i2s_mcc_sam9x60 = {965 .data_pin_pair_num = 1,966};967 968static struct mchp_i2s_mcc_soc_data mchp_i2s_mcc_sama7g5 = {969 .data_pin_pair_num = 4,970 .has_fifo = true,971};972 973static const struct of_device_id mchp_i2s_mcc_dt_ids[] = {974 {975 .compatible = "microchip,sam9x60-i2smcc",976 .data = &mchp_i2s_mcc_sam9x60,977 },978 {979 .compatible = "microchip,sama7g5-i2smcc",980 .data = &mchp_i2s_mcc_sama7g5,981 },982 { /* sentinel */ }983};984MODULE_DEVICE_TABLE(of, mchp_i2s_mcc_dt_ids);985#endif986 987static int mchp_i2s_mcc_soc_data_parse(struct platform_device *pdev,988 struct mchp_i2s_mcc_dev *dev)989{990 int err;991 992 if (!dev->soc) {993 dev_err(&pdev->dev, "failed to get soc data\n");994 return -ENODEV;995 }996 997 if (dev->soc->data_pin_pair_num == 1)998 return 0;999 1000 err = of_property_read_u8(pdev->dev.of_node, "microchip,tdm-data-pair",1001 &dev->tdm_data_pair);1002 if (err < 0 && err != -EINVAL) {1003 dev_err(&pdev->dev,1004 "bad property data for 'microchip,tdm-data-pair': %d",1005 err);1006 return err;1007 }1008 if (err == -EINVAL) {1009 dev_info(&pdev->dev,1010 "'microchip,tdm-data-pair' not found; assuming DIN/DOUT 0 for TDM\n");1011 dev->tdm_data_pair = 0;1012 } else {1013 if (dev->tdm_data_pair > dev->soc->data_pin_pair_num - 1) {1014 dev_err(&pdev->dev,1015 "invalid value for 'microchip,tdm-data-pair': %d\n",1016 dev->tdm_data_pair);1017 return -EINVAL;1018 }1019 dev_dbg(&pdev->dev, "TMD format on DIN/DOUT %d pins\n",1020 dev->tdm_data_pair);1021 }1022 1023 return 0;1024}1025 1026static int mchp_i2s_mcc_probe(struct platform_device *pdev)1027{1028 struct mchp_i2s_mcc_dev *dev;1029 struct resource *mem;1030 struct regmap *regmap;1031 void __iomem *base;1032 u32 version;1033 int irq;1034 int err;1035 1036 dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);1037 if (!dev)1038 return -ENOMEM;1039 1040 base = devm_platform_get_and_ioremap_resource(pdev, 0, &mem);1041 if (IS_ERR(base))1042 return PTR_ERR(base);1043 1044 regmap = devm_regmap_init_mmio(&pdev->dev, base,1045 &mchp_i2s_mcc_regmap_config);1046 if (IS_ERR(regmap))1047 return PTR_ERR(regmap);1048 1049 irq = platform_get_irq(pdev, 0);1050 if (irq < 0)1051 return irq;1052 1053 err = devm_request_irq(&pdev->dev, irq, mchp_i2s_mcc_interrupt, 0,1054 dev_name(&pdev->dev), dev);1055 if (err)1056 return err;1057 1058 dev->pclk = devm_clk_get(&pdev->dev, "pclk");1059 if (IS_ERR(dev->pclk)) {1060 err = PTR_ERR(dev->pclk);1061 dev_err(&pdev->dev,1062 "failed to get the peripheral clock: %d\n", err);1063 return err;1064 }1065 1066 /* Get the optional generated clock */1067 dev->gclk = devm_clk_get(&pdev->dev, "gclk");1068 if (IS_ERR(dev->gclk)) {1069 if (PTR_ERR(dev->gclk) == -EPROBE_DEFER)1070 return -EPROBE_DEFER;1071 dev_warn(&pdev->dev,1072 "generated clock not found: %d\n", err);1073 dev->gclk = NULL;1074 }1075 1076 dev->soc = of_device_get_match_data(&pdev->dev);1077 err = mchp_i2s_mcc_soc_data_parse(pdev, dev);1078 if (err < 0)1079 return err;1080 1081 dev->dev = &pdev->dev;1082 dev->regmap = regmap;1083 platform_set_drvdata(pdev, dev);1084 1085 err = clk_prepare_enable(dev->pclk);1086 if (err) {1087 dev_err(&pdev->dev,1088 "failed to enable the peripheral clock: %d\n", err);1089 return err;1090 }1091 1092 err = devm_snd_soc_register_component(&pdev->dev,1093 &mchp_i2s_mcc_component,1094 &mchp_i2s_mcc_dai, 1);1095 if (err) {1096 dev_err(&pdev->dev, "failed to register DAI: %d\n", err);1097 clk_disable_unprepare(dev->pclk);1098 return err;1099 }1100 1101 dev->playback.addr = (dma_addr_t)mem->start + MCHP_I2SMCC_THR;1102 dev->capture.addr = (dma_addr_t)mem->start + MCHP_I2SMCC_RHR;1103 1104 err = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);1105 if (err) {1106 dev_err(&pdev->dev, "failed to register PCM: %d\n", err);1107 clk_disable_unprepare(dev->pclk);1108 return err;1109 }1110 1111 /* Get IP version. */1112 regmap_read(dev->regmap, MCHP_I2SMCC_VERSION, &version);1113 dev_info(&pdev->dev, "hw version: %#lx\n",1114 version & MCHP_I2SMCC_VERSION_MASK);1115 1116 return 0;1117}1118 1119static void mchp_i2s_mcc_remove(struct platform_device *pdev)1120{1121 struct mchp_i2s_mcc_dev *dev = platform_get_drvdata(pdev);1122 1123 clk_disable_unprepare(dev->pclk);1124}1125 1126static struct platform_driver mchp_i2s_mcc_driver = {1127 .driver = {1128 .name = "mchp_i2s_mcc",1129 .of_match_table = mchp_i2s_mcc_dt_ids,1130 },1131 .probe = mchp_i2s_mcc_probe,1132 .remove = mchp_i2s_mcc_remove,1133};1134module_platform_driver(mchp_i2s_mcc_driver);1135 1136MODULE_DESCRIPTION("Microchip I2S Multi-Channel Controller driver");1137MODULE_AUTHOR("Codrin Ciubotariu <codrin.ciubotariu@microchip.com>");1138MODULE_LICENSE("GPL v2");1139