608 lines · c
1// SPDX-License-Identifier: GPL-2.0-or-later2 3/*4 * Based on code by Hu Jin5 * Copyright (C) 2014 Asahi Kasei Microdevices Corporation6 */7 8#include <linux/delay.h>9#include <linux/gpio/consumer.h>10#include <linux/i2c.h>11#include <linux/module.h>12#include <linux/of.h>13#include <linux/pm_runtime.h>14#include <linux/regulator/consumer.h>15#include <sound/soc.h>16#include <sound/tlv.h>17 18/* Registers and fields */19#define AK4375_00_POWER_MANAGEMENT1 0x0020#define PMPLL BIT(0) /* 0: PLL off, 1: PLL on */21#define AK4375_01_POWER_MANAGEMENT2 0x0122#define PMCP1 BIT(0) /* Charge Pump 1: LDO1 and DAC */23#define PMCP2 BIT(1) /* Charge Pump 2: Class-G HP Amp */24#define PMLDO1P BIT(4)25#define PMLDO1N BIT(5)26#define PMLDO (PMLDO1P | PMLDO1N)27#define AK4375_02_POWER_MANAGEMENT3 0x0228#define AK4375_03_POWER_MANAGEMENT4 0x0329#define AK4375_04_OUTPUT_MODE_SETTING 0x0430#define AK4375_05_CLOCK_MODE_SELECT 0x0531#define FS_MASK GENMASK(4, 0)32#define FS_8KHZ 0x0033#define FS_11_025KHZ 0x0134#define FS_16KHZ 0x0435#define FS_22_05KHZ 0x0536#define FS_32KHZ 0x0837#define FS_44_1KHZ 0x0938#define FS_48KHZ 0x0a39#define FS_88_2KHZ 0x0d40#define FS_96KHZ 0x0e41#define FS_176_4KHZ 0x1142#define FS_192KHZ 0x1243#define CM_MASK GENMASK(6, 5) /* For SRC Bypass mode */44#define CM_0 (0x0 << 5)45#define CM_1 (0x1 << 5)46#define CM_2 (0x2 << 5)47#define CM_3 (0x3 << 5)48#define AK4375_06_DIGITAL_FILTER_SELECT 0x0649#define DADFSEL BIT(5) /* 0: in SRC Bypass mode, 1: in SRC mode */50#define DASL BIT(6)51#define DASD BIT(7)52#define AK4375_07_DAC_MONO_MIXING 0x0753#define DACMUTE_MASK (GENMASK(5, 4) | GENMASK(1, 0)) /* Clear to mute */54#define AK4375_08_JITTER_CLEANER_SETTING1 0x0855#define AK4375_09_JITTER_CLEANER_SETTING2 0x0956#define AK4375_0A_JITTER_CLEANER_SETTING3 0x0a57#define SELDAIN BIT(1) /* 0: SRC Bypass mode, 1: SRC mode */58#define XCKSEL BIT(6) /* 0: PLL0, 1: MCKI */59#define XCKCPSEL BIT(7) /* Should be equal to SELDAIN and XCKSEL */60#define AK4375_0B_LCH_OUTPUT_VOLUME 0x0b61#define AK4375_0C_RCH_OUTPUT_VOLUME 0x0c62#define AK4375_0D_HP_VOLUME_CONTROL 0x0d63#define AK4375_0E_PLL_CLK_SOURCE_SELECT 0x0e64#define PLS BIT(0) /* 0: MCKI, 1: BCLK */65#define AK4375_0F_PLL_REF_CLK_DIVIDER1 0x0f /* Reference clock divider [15:8] bits */66#define AK4375_10_PLL_REF_CLK_DIVIDER2 0x10 /* Reference clock divider [7:0] bis */67#define AK4375_11_PLL_FB_CLK_DIVIDER1 0x11 /* Feedback clock divider [15:8] bits */68#define AK4375_12_PLL_FB_CLK_DIVIDER2 0x12 /* Feedback clock divider [7:0] bits */69#define AK4375_13_SRC_CLK_SOURCE 0x13 /* SRC Bypass: SRCCKS=XCKSEL=SELDAIN=0 */70#define SRCCKS BIT(0) /* SRC Clock source 0: MCKI, 1: PLL0 */71#define DIV BIT(4)72#define AK4375_14_DAC_CLK_DIVIDER 0x1473#define AK4375_15_AUDIO_IF_FORMAT 0x1574#define DEVICEID_MASK GENMASK(7, 5)75#define AK4375_24_MODE_CONTROL 0x2476 77#define AK4375_PLL_FREQ_OUT_112896000 112896000 /* 44.1 kHz base rate */78#define AK4375_PLL_FREQ_OUT_122880000 122880000 /* 32 and 48 kHz base rates */79 80#define DEVICEID_AK4375 0x0081#define DEVICEID_AK4375A 0x0182#define DEVICEID_AK4376A 0x0283#define DEVICEID_AK4377 0x0384#define DEVICEID_AK4331 0x0785 86static const char * const supply_names[] = {87 "avdd", "tvdd"88};89 90struct ak4375_drvdata {91 struct snd_soc_dai_driver *dai_drv;92 const struct snd_soc_component_driver *comp_drv;93};94 95struct ak4375_priv {96 struct device *dev;97 struct regmap *regmap;98 struct gpio_desc *pdn_gpiod;99 struct regulator_bulk_data supplies[ARRAY_SIZE(supply_names)];100 unsigned int rate;101 unsigned int pld;102 u8 mute_save;103};104 105static const struct reg_default ak4375_reg_defaults[] = {106 { 0x00, 0x00 }, { 0x01, 0x00 }, { 0x02, 0x00 },107 { 0x03, 0x00 }, { 0x04, 0x00 }, { 0x05, 0x00 },108 { 0x06, 0x00 }, { 0x07, 0x00 }, { 0x08, 0x00 },109 { 0x09, 0x00 }, { 0x0a, 0x00 }, { 0x0b, 0x19 },110 { 0x0c, 0x19 }, { 0x0d, 0x75 }, { 0x0e, 0x01 },111 { 0x0f, 0x00 }, { 0x10, 0x00 }, { 0x11, 0x00 },112 { 0x12, 0x00 }, { 0x13, 0x00 }, { 0x14, 0x00 },113 { 0x15, 0x00 }, { 0x24, 0x00 },114};115 116/*117 * Output Digital volume control:118 * from -12.5 to 3 dB in 0.5 dB steps (mute instead of -12.5 dB)119 */120static DECLARE_TLV_DB_SCALE(dac_tlv, -1250, 50, 0);121 122/*123 * HP-Amp Analog volume control:124 * from -4.2 to 6 dB in 2 dB steps (mute instead of -4.2 dB)125 */126static DECLARE_TLV_DB_SCALE(hpg_tlv, -4200, 20, 0);127 128static const char * const ak4375_ovolcn_select_texts[] = { "Dependent", "Independent" };129static const char * const ak4375_mdac_select_texts[] = { "x1", "x1/2" };130static const char * const ak4375_cpmode_select_texts[] = {131 "Automatic Switching",132 "+-VDD Operation",133 "+-1/2VDD Operation"134};135 136/*137 * DASD, DASL bits Digital Filter Setting138 * 0, 0 : Sharp Roll-Off Filter139 * 0, 1 : Slow Roll-Off Filter140 * 1, 0 : Short delay Sharp Roll-Off Filter141 * 1, 1 : Short delay Slow Roll-Off Filter142 */143static const char * const ak4375_digfil_select_texts[] = {144 "Sharp Roll-Off Filter",145 "Slow Roll-Off Filter",146 "Short delay Sharp Roll-Off Filter",147 "Short delay Slow Roll-Off Filter",148};149 150static const struct soc_enum ak4375_ovolcn_enum =151 SOC_ENUM_SINGLE(AK4375_0B_LCH_OUTPUT_VOLUME, 7,152 ARRAY_SIZE(ak4375_ovolcn_select_texts), ak4375_ovolcn_select_texts);153static const struct soc_enum ak4375_mdacl_enum =154 SOC_ENUM_SINGLE(AK4375_07_DAC_MONO_MIXING, 2,155 ARRAY_SIZE(ak4375_mdac_select_texts), ak4375_mdac_select_texts);156static const struct soc_enum ak4375_mdacr_enum =157 SOC_ENUM_SINGLE(AK4375_07_DAC_MONO_MIXING, 6,158 ARRAY_SIZE(ak4375_mdac_select_texts), ak4375_mdac_select_texts);159static const struct soc_enum ak4375_cpmode_enum =160 SOC_ENUM_SINGLE(AK4375_03_POWER_MANAGEMENT4, 2,161 ARRAY_SIZE(ak4375_cpmode_select_texts), ak4375_cpmode_select_texts);162static const struct soc_enum ak4375_digfil_enum =163 SOC_ENUM_SINGLE(AK4375_06_DIGITAL_FILTER_SELECT, 6,164 ARRAY_SIZE(ak4375_digfil_select_texts), ak4375_digfil_select_texts);165 166static const struct snd_kcontrol_new ak4375_snd_controls[] = {167 SOC_DOUBLE_R_TLV("Digital Output Volume", AK4375_0B_LCH_OUTPUT_VOLUME,168 AK4375_0C_RCH_OUTPUT_VOLUME, 0, 0x1f, 0, dac_tlv),169 SOC_SINGLE_TLV("HP-Amp Analog Volume",170 AK4375_0D_HP_VOLUME_CONTROL, 0, 0x1f, 0, hpg_tlv),171 172 SOC_DOUBLE("DAC Signal Invert Switch", AK4375_07_DAC_MONO_MIXING, 3, 7, 1, 0),173 174 SOC_ENUM("Digital Volume Control", ak4375_ovolcn_enum),175 SOC_ENUM("DACL Signal Level", ak4375_mdacl_enum),176 SOC_ENUM("DACR Signal Level", ak4375_mdacr_enum),177 SOC_ENUM("Charge Pump Mode", ak4375_cpmode_enum),178 SOC_ENUM("DAC Digital Filter Mode", ak4375_digfil_enum),179};180 181static const struct snd_kcontrol_new ak4375_hpl_mixer_controls[] = {182 SOC_DAPM_SINGLE("LDACL Switch", AK4375_07_DAC_MONO_MIXING, 0, 1, 0),183 SOC_DAPM_SINGLE("RDACL Switch", AK4375_07_DAC_MONO_MIXING, 1, 1, 0),184};185 186static const struct snd_kcontrol_new ak4375_hpr_mixer_controls[] = {187 SOC_DAPM_SINGLE("LDACR Switch", AK4375_07_DAC_MONO_MIXING, 4, 1, 0),188 SOC_DAPM_SINGLE("RDACR Switch", AK4375_07_DAC_MONO_MIXING, 5, 1, 0),189};190 191static int ak4375_dac_event(struct snd_soc_dapm_widget *w,192 struct snd_kcontrol *kcontrol, int event)193{194 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);195 196 switch (event) {197 case SND_SOC_DAPM_PRE_PMU:198 snd_soc_component_update_bits(component, AK4375_00_POWER_MANAGEMENT1, PMPLL, PMPLL);199 snd_soc_component_update_bits(component, AK4375_01_POWER_MANAGEMENT2, PMCP1, PMCP1);200 usleep_range(6500, 7000);201 snd_soc_component_update_bits(component, AK4375_01_POWER_MANAGEMENT2, PMLDO, PMLDO);202 usleep_range(1000, 2000);203 break;204 case SND_SOC_DAPM_POST_PMU:205 snd_soc_component_update_bits(component, AK4375_01_POWER_MANAGEMENT2, PMCP2, PMCP2);206 usleep_range(4500, 5000);207 break;208 case SND_SOC_DAPM_PRE_PMD:209 snd_soc_component_update_bits(component, AK4375_01_POWER_MANAGEMENT2, PMCP2, 0x0);210 break;211 case SND_SOC_DAPM_POST_PMD:212 snd_soc_component_update_bits(component, AK4375_01_POWER_MANAGEMENT2, PMLDO, 0x0);213 snd_soc_component_update_bits(component, AK4375_01_POWER_MANAGEMENT2, PMCP1, 0x0);214 snd_soc_component_update_bits(component, AK4375_00_POWER_MANAGEMENT1, PMPLL, 0x0);215 break;216 }217 218 return 0;219}220 221static const struct snd_soc_dapm_widget ak4375_dapm_widgets[] = {222 SND_SOC_DAPM_DAC_E("DAC", NULL, AK4375_02_POWER_MANAGEMENT3, 0, 0, ak4375_dac_event,223 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |224 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),225 226 SND_SOC_DAPM_AIF_IN("SDTI", "HiFi Playback", 0, SND_SOC_NOPM, 0, 0),227 228 SND_SOC_DAPM_OUTPUT("HPL"),229 SND_SOC_DAPM_OUTPUT("HPR"),230 231 SND_SOC_DAPM_MIXER("HPR Mixer", AK4375_03_POWER_MANAGEMENT4, 1, 0,232 &ak4375_hpr_mixer_controls[0], ARRAY_SIZE(ak4375_hpr_mixer_controls)),233 SND_SOC_DAPM_MIXER("HPL Mixer", AK4375_03_POWER_MANAGEMENT4, 0, 0,234 &ak4375_hpl_mixer_controls[0], ARRAY_SIZE(ak4375_hpl_mixer_controls)),235};236 237static const struct snd_soc_dapm_route ak4375_intercon[] = {238 { "DAC", NULL, "SDTI" },239 240 { "HPL Mixer", "LDACL Switch", "DAC" },241 { "HPL Mixer", "RDACL Switch", "DAC" },242 { "HPR Mixer", "LDACR Switch", "DAC" },243 { "HPR Mixer", "RDACR Switch", "DAC" },244 245 { "HPL", NULL, "HPL Mixer" },246 { "HPR", NULL, "HPR Mixer" },247};248 249static int ak4375_hw_params(struct snd_pcm_substream *substream,250 struct snd_pcm_hw_params *params,251 struct snd_soc_dai *dai)252{253 struct snd_soc_component *component = dai->component;254 struct ak4375_priv *ak4375 = snd_soc_component_get_drvdata(component);255 unsigned int freq_in, freq_out;256 257 ak4375->rate = params_rate(params);258 259 if (ak4375->rate <= 96000)260 ak4375->pld = 0;261 else262 ak4375->pld = 1;263 264 freq_in = 32 * ak4375->rate / (ak4375->pld + 1);265 266 if ((ak4375->rate % 8000) == 0)267 freq_out = AK4375_PLL_FREQ_OUT_122880000;268 else269 freq_out = AK4375_PLL_FREQ_OUT_112896000;270 271 return snd_soc_dai_set_pll(dai, 0, 0, freq_in, freq_out);272}273 274static int ak4375_dai_set_pll(struct snd_soc_dai *dai, int pll_id, int source,275 unsigned int freq_in, unsigned int freq_out)276{277 struct snd_soc_component *component = dai->component;278 struct ak4375_priv *ak4375 = snd_soc_component_get_drvdata(component);279 unsigned int mclk, plm, mdiv, div;280 u8 cms, fs, cm;281 282 cms = snd_soc_component_read(component, AK4375_05_CLOCK_MODE_SELECT);283 fs = cms & ~FS_MASK;284 cm = cms & ~CM_MASK;285 286 switch (ak4375->rate) {287 case 8000:288 fs |= FS_8KHZ;289 break;290 case 11025:291 fs |= FS_11_025KHZ;292 break;293 case 16000:294 fs |= FS_16KHZ;295 break;296 case 22050:297 fs |= FS_22_05KHZ;298 break;299 case 32000:300 fs |= FS_32KHZ;301 break;302 case 44100:303 fs |= FS_44_1KHZ;304 break;305 case 48000:306 fs |= FS_48KHZ;307 break;308 case 88200:309 fs |= FS_88_2KHZ;310 break;311 case 96000:312 fs |= FS_96KHZ;313 break;314 case 176400:315 fs |= FS_176_4KHZ;316 break;317 case 192000:318 fs |= FS_192KHZ;319 break;320 default:321 return -EINVAL;322 }323 324 if (ak4375->rate <= 24000) {325 cm |= CM_1;326 mclk = 512 * ak4375->rate;327 mdiv = freq_out / mclk - 1;328 div = 0;329 } else if (ak4375->rate <= 96000) {330 cm |= CM_0;331 mclk = 256 * ak4375->rate;332 mdiv = freq_out / mclk - 1;333 div = 0;334 } else {335 cm |= CM_3;336 mclk = 128 * ak4375->rate;337 mdiv = 4;338 div = 1;339 }340 341 /* Writing both fields in one go seems to make playback choppy on start */342 snd_soc_component_update_bits(component, AK4375_05_CLOCK_MODE_SELECT, FS_MASK, fs);343 snd_soc_component_update_bits(component, AK4375_05_CLOCK_MODE_SELECT, CM_MASK, cm);344 345 snd_soc_component_write(component, AK4375_0F_PLL_REF_CLK_DIVIDER1,346 (ak4375->pld & 0xff00) >> 8);347 snd_soc_component_write(component, AK4375_10_PLL_REF_CLK_DIVIDER2,348 ak4375->pld & 0x00ff);349 350 plm = freq_out / freq_in - 1;351 snd_soc_component_write(component, AK4375_11_PLL_FB_CLK_DIVIDER1, (plm & 0xff00) >> 8);352 snd_soc_component_write(component, AK4375_12_PLL_FB_CLK_DIVIDER2, plm & 0x00ff);353 354 snd_soc_component_update_bits(component, AK4375_13_SRC_CLK_SOURCE, DIV, div);355 356 /* SRCCKS bit: force to 1 for SRC PLL source clock */357 snd_soc_component_update_bits(component, AK4375_13_SRC_CLK_SOURCE, SRCCKS, SRCCKS);358 359 snd_soc_component_write(component, AK4375_14_DAC_CLK_DIVIDER, mdiv);360 361 dev_dbg(ak4375->dev, "rate=%d mclk=%d f_in=%d f_out=%d PLD=%d PLM=%d MDIV=%d DIV=%d\n",362 ak4375->rate, mclk, freq_in, freq_out, ak4375->pld, plm, mdiv, div);363 364 return 0;365}366 367static int ak4375_mute(struct snd_soc_dai *dai, int mute, int direction)368{369 struct snd_soc_component *component = dai->component;370 struct ak4375_priv *ak4375 = snd_soc_component_get_drvdata(component);371 u8 val = snd_soc_component_read(component, AK4375_07_DAC_MONO_MIXING);372 373 dev_dbg(ak4375->dev, "mute=%d val=%d\n", mute, val);374 375 if (mute) {376 ak4375->mute_save = val & DACMUTE_MASK;377 val &= ~DACMUTE_MASK;378 } else {379 val |= ak4375->mute_save;380 }381 382 snd_soc_component_write(component, AK4375_07_DAC_MONO_MIXING, val);383 384 return 0;385}386 387#define AK4375_RATES (SNDRV_PCM_RATE_8000_48000 |\388 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 |\389 SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_192000)390 391#define AK4375_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\392 SNDRV_PCM_FMTBIT_S24_LE |\393 SNDRV_PCM_FMTBIT_S32_LE)394 395static const struct snd_soc_dai_ops ak4375_dai_ops = {396 .hw_params = ak4375_hw_params,397 .mute_stream = ak4375_mute,398 .set_pll = ak4375_dai_set_pll,399};400 401static struct snd_soc_dai_driver ak4375_dai = {402 .name = "ak4375-hifi",403 .playback = {404 .stream_name = "HiFi Playback",405 .channels_min = 1,406 .channels_max = 2,407 .rates = AK4375_RATES,408 .rate_min = 8000,409 .rate_max = 192000,410 .formats = AK4375_FORMATS,411 },412 .ops = &ak4375_dai_ops,413};414 415static void ak4375_power_off(struct ak4375_priv *ak4375)416{417 gpiod_set_value_cansleep(ak4375->pdn_gpiod, 0);418 usleep_range(1000, 2000);419 420 regulator_bulk_disable(ARRAY_SIZE(ak4375->supplies), ak4375->supplies);421}422 423static int ak4375_power_on(struct ak4375_priv *ak4375)424{425 int ret;426 427 ret = regulator_bulk_enable(ARRAY_SIZE(ak4375->supplies), ak4375->supplies);428 if (ret < 0) {429 dev_err(ak4375->dev, "Failed to enable regulators: %d\n", ret);430 return ret;431 }432 433 usleep_range(3000, 4000);434 435 gpiod_set_value_cansleep(ak4375->pdn_gpiod, 1);436 usleep_range(1000, 2000);437 438 return 0;439}440 441static int __maybe_unused ak4375_runtime_suspend(struct device *dev)442{443 struct ak4375_priv *ak4375 = dev_get_drvdata(dev);444 445 regcache_cache_only(ak4375->regmap, true);446 ak4375_power_off(ak4375);447 448 return 0;449}450 451static int __maybe_unused ak4375_runtime_resume(struct device *dev)452{453 struct ak4375_priv *ak4375 = dev_get_drvdata(dev);454 int ret;455 456 ret = ak4375_power_on(ak4375);457 if (ret < 0)458 return ret;459 460 regcache_cache_only(ak4375->regmap, false);461 regcache_mark_dirty(ak4375->regmap);462 463 return regcache_sync(ak4375->regmap);464}465 466static const struct snd_soc_component_driver soc_codec_dev_ak4375 = {467 .controls = ak4375_snd_controls,468 .num_controls = ARRAY_SIZE(ak4375_snd_controls),469 .dapm_widgets = ak4375_dapm_widgets,470 .num_dapm_widgets = ARRAY_SIZE(ak4375_dapm_widgets),471 .dapm_routes = ak4375_intercon,472 .num_dapm_routes = ARRAY_SIZE(ak4375_intercon),473 .idle_bias_on = 1,474 .use_pmdown_time = 1,475 .endianness = 1,476};477 478static const struct regmap_config ak4375_regmap = {479 .reg_bits = 8,480 .val_bits = 8,481 .max_register = AK4375_24_MODE_CONTROL,482 .reg_defaults = ak4375_reg_defaults,483 .num_reg_defaults = ARRAY_SIZE(ak4375_reg_defaults),484 .cache_type = REGCACHE_RBTREE,485};486 487static const struct ak4375_drvdata ak4375_drvdata = {488 .dai_drv = &ak4375_dai,489 .comp_drv = &soc_codec_dev_ak4375,490};491 492static const struct dev_pm_ops ak4375_pm = {493 SET_RUNTIME_PM_OPS(ak4375_runtime_suspend, ak4375_runtime_resume, NULL)494 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,495 pm_runtime_force_resume)496};497 498static int ak4375_i2c_probe(struct i2c_client *i2c)499{500 struct ak4375_priv *ak4375;501 const struct ak4375_drvdata *drvdata;502 unsigned int deviceid;503 int ret, i;504 505 ak4375 = devm_kzalloc(&i2c->dev, sizeof(*ak4375), GFP_KERNEL);506 if (!ak4375)507 return -ENOMEM;508 509 ak4375->regmap = devm_regmap_init_i2c(i2c, &ak4375_regmap);510 if (IS_ERR(ak4375->regmap))511 return PTR_ERR(ak4375->regmap);512 513 i2c_set_clientdata(i2c, ak4375);514 ak4375->dev = &i2c->dev;515 516 drvdata = of_device_get_match_data(&i2c->dev);517 518 for (i = 0; i < ARRAY_SIZE(supply_names); i++)519 ak4375->supplies[i].supply = supply_names[i];520 521 ret = devm_regulator_bulk_get(ak4375->dev, ARRAY_SIZE(ak4375->supplies), ak4375->supplies);522 if (ret < 0) {523 dev_err(ak4375->dev, "Failed to get regulators: %d\n", ret);524 return ret;525 }526 527 ak4375->pdn_gpiod = devm_gpiod_get_optional(ak4375->dev, "pdn", GPIOD_OUT_LOW);528 if (IS_ERR(ak4375->pdn_gpiod))529 return dev_err_probe(ak4375->dev, PTR_ERR(ak4375->pdn_gpiod),530 "failed to get pdn\n");531 532 ret = ak4375_power_on(ak4375);533 if (ret < 0)534 return ret;535 536 /* Don't read deviceid from cache */537 regcache_cache_bypass(ak4375->regmap, true);538 539 ret = regmap_read(ak4375->regmap, AK4375_15_AUDIO_IF_FORMAT, &deviceid);540 if (ret < 0) {541 dev_err(ak4375->dev, "unable to read DEVICEID!\n");542 return ret;543 }544 545 regcache_cache_bypass(ak4375->regmap, false);546 547 deviceid = (deviceid & DEVICEID_MASK) >> 5;548 549 switch (deviceid) {550 case DEVICEID_AK4331:551 dev_err(ak4375->dev, "found untested AK4331\n");552 return -EINVAL;553 case DEVICEID_AK4375:554 dev_dbg(ak4375->dev, "found AK4375\n");555 break;556 case DEVICEID_AK4375A:557 dev_dbg(ak4375->dev, "found AK4375A\n");558 break;559 case DEVICEID_AK4376A:560 dev_err(ak4375->dev, "found unsupported AK4376/A!\n");561 return -EINVAL;562 case DEVICEID_AK4377:563 dev_err(ak4375->dev, "found unsupported AK4377!\n");564 return -EINVAL;565 default:566 dev_err(ak4375->dev, "unrecognized DEVICEID!\n");567 return -EINVAL;568 }569 570 pm_runtime_set_active(ak4375->dev);571 pm_runtime_enable(ak4375->dev);572 573 ret = devm_snd_soc_register_component(ak4375->dev, drvdata->comp_drv,574 drvdata->dai_drv, 1);575 if (ret < 0) {576 dev_err(ak4375->dev, "Failed to register CODEC: %d\n", ret);577 return ret;578 }579 580 return 0;581}582 583static void ak4375_i2c_remove(struct i2c_client *i2c)584{585 pm_runtime_disable(&i2c->dev);586}587 588static const struct of_device_id ak4375_of_match[] = {589 { .compatible = "asahi-kasei,ak4375", .data = &ak4375_drvdata },590 { },591};592MODULE_DEVICE_TABLE(of, ak4375_of_match);593 594static struct i2c_driver ak4375_i2c_driver = {595 .driver = {596 .name = "ak4375",597 .pm = &ak4375_pm,598 .of_match_table = ak4375_of_match,599 },600 .probe = ak4375_i2c_probe,601 .remove = ak4375_i2c_remove,602};603module_i2c_driver(ak4375_i2c_driver);604 605MODULE_AUTHOR("Vincent Knecht <vincent.knecht@mailoo.org>");606MODULE_DESCRIPTION("ASoC AK4375 DAC driver");607MODULE_LICENSE("GPL");608