384 lines · c
1// SPDX-License-Identifier: GPL-2.0-only2//3// aw88395_reg.h -- AW88395 chip register file4//5// Copyright (c) 2022-2023 AWINIC Technology CO., LTD6//7// Author: Bruce zhao <zhaolei@awinic.com>8//9 10#ifndef __AW88395_REG_H__11#define __AW88395_REG_H__12 13#define AW88395_ID_REG (0x00)14#define AW88395_SYSST_REG (0x01)15#define AW88395_SYSINT_REG (0x02)16#define AW88395_SYSINTM_REG (0x03)17#define AW88395_SYSCTRL_REG (0x04)18#define AW88395_SYSCTRL2_REG (0x05)19#define AW88395_I2SCTRL_REG (0x06)20#define AW88395_I2SCFG1_REG (0x07)21#define AW88395_I2SCFG2_REG (0x08)22#define AW88395_HAGCCFG1_REG (0x09)23#define AW88395_HAGCCFG2_REG (0x0A)24#define AW88395_HAGCCFG3_REG (0x0B)25#define AW88395_HAGCCFG4_REG (0x0C)26#define AW88395_HAGCCFG5_REG (0x0D)27#define AW88395_HAGCCFG6_REG (0x0E)28#define AW88395_HAGCCFG7_REG (0x0F)29#define AW88395_MPDCFG_REG (0x10)30#define AW88395_PWMCTRL_REG (0x11)31#define AW88395_I2SCFG3_REG (0x12)32#define AW88395_DBGCTRL_REG (0x13)33#define AW88395_HAGCST_REG (0x20)34#define AW88395_VBAT_REG (0x21)35#define AW88395_TEMP_REG (0x22)36#define AW88395_PVDD_REG (0x23)37#define AW88395_ISNDAT_REG (0x24)38#define AW88395_VSNDAT_REG (0x25)39#define AW88395_I2SINT_REG (0x26)40#define AW88395_I2SCAPCNT_REG (0x27)41#define AW88395_ANASTA1_REG (0x28)42#define AW88395_ANASTA2_REG (0x29)43#define AW88395_ANASTA3_REG (0x2A)44#define AW88395_ANASTA4_REG (0x2B)45#define AW88395_TESTDET_REG (0x2C)46#define AW88395_TESTIN_REG (0x38)47#define AW88395_TESTOUT_REG (0x39)48#define AW88395_DSPMADD_REG (0x40)49#define AW88395_DSPMDAT_REG (0x41)50#define AW88395_WDT_REG (0x42)51#define AW88395_ACR1_REG (0x43)52#define AW88395_ACR2_REG (0x44)53#define AW88395_ASR1_REG (0x45)54#define AW88395_ASR2_REG (0x46)55#define AW88395_DSPCFG_REG (0x47)56#define AW88395_ASR3_REG (0x48)57#define AW88395_ASR4_REG (0x49)58#define AW88395_VSNCTRL1_REG (0x50)59#define AW88395_ISNCTRL1_REG (0x51)60#define AW88395_PLLCTRL1_REG (0x52)61#define AW88395_PLLCTRL2_REG (0x53)62#define AW88395_PLLCTRL3_REG (0x54)63#define AW88395_CDACTRL1_REG (0x55)64#define AW88395_CDACTRL2_REG (0x56)65#define AW88395_SADCCTRL1_REG (0x57)66#define AW88395_SADCCTRL2_REG (0x58)67#define AW88395_CPCTRL1_REG (0x59)68#define AW88395_BSTCTRL1_REG (0x60)69#define AW88395_BSTCTRL2_REG (0x61)70#define AW88395_BSTCTRL3_REG (0x62)71#define AW88395_BSTCTRL4_REG (0x63)72#define AW88395_BSTCTRL5_REG (0x64)73#define AW88395_BSTCTRL6_REG (0x65)74#define AW88395_BSTCTRL7_REG (0x66)75#define AW88395_DSMCFG1_REG (0x67)76#define AW88395_DSMCFG2_REG (0x68)77#define AW88395_DSMCFG3_REG (0x69)78#define AW88395_DSMCFG4_REG (0x6A)79#define AW88395_DSMCFG5_REG (0x6B)80#define AW88395_DSMCFG6_REG (0x6C)81#define AW88395_DSMCFG7_REG (0x6D)82#define AW88395_DSMCFG8_REG (0x6E)83#define AW88395_TESTCTRL1_REG (0x70)84#define AW88395_TESTCTRL2_REG (0x71)85#define AW88395_EFCTRL1_REG (0x72)86#define AW88395_EFCTRL2_REG (0x73)87#define AW88395_EFWH_REG (0x74)88#define AW88395_EFWM2_REG (0x75)89#define AW88395_EFWM1_REG (0x76)90#define AW88395_EFWL_REG (0x77)91#define AW88395_EFRH_REG (0x78)92#define AW88395_EFRM2_REG (0x79)93#define AW88395_EFRM1_REG (0x7A)94#define AW88395_EFRL_REG (0x7B)95#define AW88395_TM_REG (0x7C)96 97enum aw88395_id {98 AW88395_CHIP_ID = 0x2049,99};100 101#define AW88395_REG_MAX (0x7D)102 103#define AW88395_VOLUME_STEP_DB (6 * 8)104 105#define AW88395_UVLS_START_BIT (14)106#define AW88395_UVLS_NORMAL (0)107#define AW88395_UVLS_NORMAL_VALUE \108 (AW88395_UVLS_NORMAL << AW88395_UVLS_START_BIT)109 110#define AW88395_DSPS_START_BIT (12)111#define AW88395_DSPS_BITS_LEN (1)112#define AW88395_DSPS_MASK \113 (~(((1<<AW88395_DSPS_BITS_LEN)-1) << AW88395_DSPS_START_BIT))114 115#define AW88395_DSPS_NORMAL (0)116#define AW88395_DSPS_NORMAL_VALUE \117 (AW88395_DSPS_NORMAL << AW88395_DSPS_START_BIT)118 119#define AW88395_BSTOCS_START_BIT (11)120#define AW88395_BSTOCS_OVER_CURRENT (1)121#define AW88395_BSTOCS_OVER_CURRENT_VALUE \122 (AW88395_BSTOCS_OVER_CURRENT << AW88395_BSTOCS_START_BIT)123 124#define AW88395_BSTS_START_BIT (9)125#define AW88395_BSTS_FINISHED (1)126#define AW88395_BSTS_FINISHED_VALUE \127 (AW88395_BSTS_FINISHED << AW88395_BSTS_START_BIT)128 129#define AW88395_SWS_START_BIT (8)130#define AW88395_SWS_SWITCHING (1)131#define AW88395_SWS_SWITCHING_VALUE \132 (AW88395_SWS_SWITCHING << AW88395_SWS_START_BIT)133 134#define AW88395_NOCLKS_START_BIT (5)135#define AW88395_NOCLKS_NO_CLOCK (1)136#define AW88395_NOCLKS_NO_CLOCK_VALUE \137 (AW88395_NOCLKS_NO_CLOCK << AW88395_NOCLKS_START_BIT)138 139#define AW88395_CLKS_START_BIT (4)140#define AW88395_CLKS_STABLE (1)141#define AW88395_CLKS_STABLE_VALUE \142 (AW88395_CLKS_STABLE << AW88395_CLKS_START_BIT)143 144#define AW88395_OCDS_START_BIT (3)145#define AW88395_OCDS_OC (1)146#define AW88395_OCDS_OC_VALUE \147 (AW88395_OCDS_OC << AW88395_OCDS_START_BIT)148 149#define AW88395_OTHS_START_BIT (1)150#define AW88395_OTHS_OT (1)151#define AW88395_OTHS_OT_VALUE \152 (AW88395_OTHS_OT << AW88395_OTHS_START_BIT)153 154#define AW88395_PLLS_START_BIT (0)155#define AW88395_PLLS_LOCKED (1)156#define AW88395_PLLS_LOCKED_VALUE \157 (AW88395_PLLS_LOCKED << AW88395_PLLS_START_BIT)158 159#define AW88395_BIT_PLL_CHECK \160 (AW88395_CLKS_STABLE_VALUE | \161 AW88395_PLLS_LOCKED_VALUE)162 163#define AW88395_BIT_SYSST_CHECK_MASK \164 (~(AW88395_UVLS_NORMAL_VALUE | \165 AW88395_BSTOCS_OVER_CURRENT_VALUE | \166 AW88395_BSTS_FINISHED_VALUE | \167 AW88395_SWS_SWITCHING_VALUE | \168 AW88395_NOCLKS_NO_CLOCK_VALUE | \169 AW88395_CLKS_STABLE_VALUE | \170 AW88395_OCDS_OC_VALUE | \171 AW88395_OTHS_OT_VALUE | \172 AW88395_PLLS_LOCKED_VALUE))173 174#define AW88395_BIT_SYSST_CHECK \175 (AW88395_BSTS_FINISHED_VALUE | \176 AW88395_SWS_SWITCHING_VALUE | \177 AW88395_CLKS_STABLE_VALUE | \178 AW88395_PLLS_LOCKED_VALUE)179 180#define AW88395_WDI_START_BIT (6)181#define AW88395_WDI_INT_VALUE (1)182#define AW88395_WDI_INTERRUPT \183 (AW88395_WDI_INT_VALUE << AW88395_WDI_START_BIT)184 185#define AW88395_NOCLKI_START_BIT (5)186#define AW88395_NOCLKI_INT_VALUE (1)187#define AW88395_NOCLKI_INTERRUPT \188 (AW88395_NOCLKI_INT_VALUE << AW88395_NOCLKI_START_BIT)189 190#define AW88395_CLKI_START_BIT (4)191#define AW88395_CLKI_INT_VALUE (1)192#define AW88395_CLKI_INTERRUPT \193 (AW88395_CLKI_INT_VALUE << AW88395_CLKI_START_BIT)194 195#define AW88395_PLLI_START_BIT (0)196#define AW88395_PLLI_INT_VALUE (1)197#define AW88395_PLLI_INTERRUPT \198 (AW88395_PLLI_INT_VALUE << AW88395_PLLI_START_BIT)199 200#define AW88395_BIT_SYSINT_CHECK \201 (AW88395_WDI_INTERRUPT | \202 AW88395_CLKI_INTERRUPT | \203 AW88395_NOCLKI_INTERRUPT | \204 AW88395_PLLI_INTERRUPT)205 206#define AW88395_HMUTE_START_BIT (8)207#define AW88395_HMUTE_BITS_LEN (1)208#define AW88395_HMUTE_MASK \209 (~(((1<<AW88395_HMUTE_BITS_LEN)-1) << AW88395_HMUTE_START_BIT))210 211#define AW88395_HMUTE_DISABLE (0)212#define AW88395_HMUTE_DISABLE_VALUE \213 (AW88395_HMUTE_DISABLE << AW88395_HMUTE_START_BIT)214 215#define AW88395_HMUTE_ENABLE (1)216#define AW88395_HMUTE_ENABLE_VALUE \217 (AW88395_HMUTE_ENABLE << AW88395_HMUTE_START_BIT)218 219#define AW88395_RCV_MODE_START_BIT (7)220#define AW88395_RCV_MODE_BITS_LEN (1)221#define AW88395_RCV_MODE_MASK \222 (~(((1<<AW88395_RCV_MODE_BITS_LEN)-1) << AW88395_RCV_MODE_START_BIT))223 224#define AW88395_RCV_MODE_RECEIVER (1)225#define AW88395_RCV_MODE_RECEIVER_VALUE \226 (AW88395_RCV_MODE_RECEIVER << AW88395_RCV_MODE_START_BIT)227 228#define AW88395_DSPBY_START_BIT (2)229#define AW88395_DSPBY_BITS_LEN (1)230#define AW88395_DSPBY_MASK \231 (~(((1<<AW88395_DSPBY_BITS_LEN)-1) << AW88395_DSPBY_START_BIT))232 233#define AW88395_DSPBY_WORKING (0)234#define AW88395_DSPBY_WORKING_VALUE \235 (AW88395_DSPBY_WORKING << AW88395_DSPBY_START_BIT)236 237#define AW88395_DSPBY_BYPASS (1)238#define AW88395_DSPBY_BYPASS_VALUE \239 (AW88395_DSPBY_BYPASS << AW88395_DSPBY_START_BIT)240 241#define AW88395_AMPPD_START_BIT (1)242#define AW88395_AMPPD_BITS_LEN (1)243#define AW88395_AMPPD_MASK \244 (~(((1<<AW88395_AMPPD_BITS_LEN)-1) << AW88395_AMPPD_START_BIT))245 246#define AW88395_AMPPD_WORKING (0)247#define AW88395_AMPPD_WORKING_VALUE \248 (AW88395_AMPPD_WORKING << AW88395_AMPPD_START_BIT)249 250#define AW88395_AMPPD_POWER_DOWN (1)251#define AW88395_AMPPD_POWER_DOWN_VALUE \252 (AW88395_AMPPD_POWER_DOWN << AW88395_AMPPD_START_BIT)253 254#define AW88395_PWDN_START_BIT (0)255#define AW88395_PWDN_BITS_LEN (1)256#define AW88395_PWDN_MASK \257 (~(((1<<AW88395_PWDN_BITS_LEN)-1) << AW88395_PWDN_START_BIT))258 259#define AW88395_PWDN_WORKING (0)260#define AW88395_PWDN_WORKING_VALUE \261 (AW88395_PWDN_WORKING << AW88395_PWDN_START_BIT)262 263#define AW88395_PWDN_POWER_DOWN (1)264#define AW88395_PWDN_POWER_DOWN_VALUE \265 (AW88395_PWDN_POWER_DOWN << AW88395_PWDN_START_BIT)266 267#define AW88395_MUTE_VOL (90 * 8)268#define AW88395_VOLUME_STEP_DB (6 * 8)269 270#define AW88395_VOL_6DB_START (6)271#define AW88395_VOL_START_BIT (6)272#define AW88395_VOL_BITS_LEN (10)273#define AW88395_VOL_MASK \274 (~(((1<<AW88395_VOL_BITS_LEN)-1) << AW88395_VOL_START_BIT))275 276#define AW88395_VOL_DEFAULT_VALUE (0)277 278#define AW88395_I2STXEN_START_BIT (0)279#define AW88395_I2STXEN_BITS_LEN (1)280#define AW88395_I2STXEN_MASK \281 (~(((1<<AW88395_I2STXEN_BITS_LEN)-1) << AW88395_I2STXEN_START_BIT))282 283#define AW88395_I2STXEN_DISABLE (0)284#define AW88395_I2STXEN_DISABLE_VALUE \285 (AW88395_I2STXEN_DISABLE << AW88395_I2STXEN_START_BIT)286 287#define AW88395_I2STXEN_ENABLE (1)288#define AW88395_I2STXEN_ENABLE_VALUE \289 (AW88395_I2STXEN_ENABLE << AW88395_I2STXEN_START_BIT)290 291#define AW88395_AGC_DSP_CTL_START_BIT (15)292#define AW88395_AGC_DSP_CTL_BITS_LEN (1)293#define AW88395_AGC_DSP_CTL_MASK \294 (~(((1<<AW88395_AGC_DSP_CTL_BITS_LEN)-1) << AW88395_AGC_DSP_CTL_START_BIT))295 296#define AW88395_AGC_DSP_CTL_DISABLE (0)297#define AW88395_AGC_DSP_CTL_DISABLE_VALUE \298 (AW88395_AGC_DSP_CTL_DISABLE << AW88395_AGC_DSP_CTL_START_BIT)299 300#define AW88395_AGC_DSP_CTL_ENABLE (1)301#define AW88395_AGC_DSP_CTL_ENABLE_VALUE \302 (AW88395_AGC_DSP_CTL_ENABLE << AW88395_AGC_DSP_CTL_START_BIT)303 304#define AW88395_VDSEL_START_BIT (0)305#define AW88395_VDSEL_BITS_LEN (1)306#define AW88395_VDSEL_MASK \307 (~(((1<<AW88395_VDSEL_BITS_LEN)-1) << AW88395_VDSEL_START_BIT))308 309#define AW88395_MEM_CLKSEL_START_BIT (3)310#define AW88395_MEM_CLKSEL_BITS_LEN (1)311#define AW88395_MEM_CLKSEL_MASK \312 (~(((1<<AW88395_MEM_CLKSEL_BITS_LEN)-1) << AW88395_MEM_CLKSEL_START_BIT))313 314#define AW88395_MEM_CLKSEL_OSC_CLK (0)315#define AW88395_MEM_CLKSEL_OSC_CLK_VALUE \316 (AW88395_MEM_CLKSEL_OSC_CLK << AW88395_MEM_CLKSEL_START_BIT)317 318#define AW88395_MEM_CLKSEL_DAP_HCLK (1)319#define AW88395_MEM_CLKSEL_DAP_HCLK_VALUE \320 (AW88395_MEM_CLKSEL_DAP_HCLK << AW88395_MEM_CLKSEL_START_BIT)321 322#define AW88395_CCO_MUX_START_BIT (14)323#define AW88395_CCO_MUX_BITS_LEN (1)324#define AW88395_CCO_MUX_MASK \325 (~(((1<<AW88395_CCO_MUX_BITS_LEN)-1) << AW88395_CCO_MUX_START_BIT))326 327#define AW88395_CCO_MUX_DIVIDED (0)328#define AW88395_CCO_MUX_DIVIDED_VALUE \329 (AW88395_CCO_MUX_DIVIDED << AW88395_CCO_MUX_START_BIT)330 331#define AW88395_CCO_MUX_BYPASS (1)332#define AW88395_CCO_MUX_BYPASS_VALUE \333 (AW88395_CCO_MUX_BYPASS << AW88395_CCO_MUX_START_BIT)334 335#define AW88395_EF_VSN_GESLP_START_BIT (0)336#define AW88395_EF_VSN_GESLP_BITS_LEN (10)337#define AW88395_EF_VSN_GESLP_MASK \338 (~(((1<<AW88395_EF_VSN_GESLP_BITS_LEN)-1) << AW88395_EF_VSN_GESLP_START_BIT))339 340#define AW88395_EF_VSN_GESLP_SIGN_MASK (~(1 << 9))341#define AW88395_EF_VSN_GESLP_SIGN_NEG (0xfe00)342 343#define AW88395_EF_ISN_GESLP_START_BIT (0)344#define AW88395_EF_ISN_GESLP_BITS_LEN (10)345#define AW88395_EF_ISN_GESLP_MASK \346 (~(((1<<AW88395_EF_ISN_GESLP_BITS_LEN)-1) << AW88395_EF_ISN_GESLP_START_BIT))347 348#define AW88395_EF_ISN_GESLP_SIGN_MASK (~(1 << 9))349#define AW88395_EF_ISN_GESLP_SIGN_NEG (0xfe00)350 351#define AW88395_CABL_BASE_VALUE (1000)352#define AW88395_ICABLK_FACTOR (1)353#define AW88395_VCABLK_FACTOR (1)354#define AW88395_VCAL_FACTOR (1 << 12)355#define AW88395_VSCAL_FACTOR (16500)356#define AW88395_ISCAL_FACTOR (3667)357#define AW88395_EF_VSENSE_GAIN_SHIFT (0)358 359#define AW88395_VCABLK_FACTOR_DAC (2)360#define AW88395_VSCAL_FACTOR_DAC (11790)361#define AW88395_EF_DAC_GESLP_SHIFT (10)362#define AW88395_EF_DAC_GESLP_SIGN_MASK (1 << 5)363#define AW88395_EF_DAC_GESLP_SIGN_NEG (0xffc0)364 365#define AW88395_VCALB_ADJ_FACTOR (12)366 367#define AW88395_WDT_CNT_START_BIT (0)368#define AW88395_WDT_CNT_BITS_LEN (8)369#define AW88395_WDT_CNT_MASK \370 (~(((1<<AW88395_WDT_CNT_BITS_LEN)-1) << AW88395_WDT_CNT_START_BIT))371 372#define AW88395_DSP_CFG_ADDR (0x9C80)373#define AW88395_DSP_FW_ADDR (0x8C00)374#define AW88395_DSP_REG_VMAX (0x9C94)375#define AW88395_DSP_REG_CFG_ADPZ_RE (0x9D00)376#define AW88395_DSP_REG_VCALB (0x9CF7)377#define AW88395_DSP_RE_SHIFT (12)378 379#define AW88395_DSP_REG_CFG_ADPZ_RA (0x9D02)380#define AW88395_DSP_REG_CRC_ADDR (0x9F42)381#define AW88395_DSP_CALI_F0_DELAY (0x9CFD)382 383#endif384