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1/* SPDX-License-Identifier: GPL-2.0-only */2/*3 * cs42l52.h -- CS42L52 ALSA SoC audio driver4 *5 * Copyright 2012 CirrusLogic, Inc.6 *7 * Author: Georgi Vlaev <joe@nucleusys.com>8 * Author: Brian Austin <brian.austin@cirrus.com>9 */10 11#ifndef __CS42L52_H__12#define __CS42L52_H__13 14#define CS42L52_NAME "CS42L52"15#define CS42L52_DEFAULT_CLK 1200000016#define CS42L52_MIN_CLK 1100000017#define CS42L52_MAX_CLK 2700000018#define CS42L52_DEFAULT_FORMAT SNDRV_PCM_FMTBIT_S16_LE19#define CS42L52_DEFAULT_MAX_CHANS 220#define CS42L52_SYSCLK 121 22#define CS42L52_CHIP_SWICTH (1 << 17)23#define CS42L52_ALL_IN_ONE (1 << 16)24#define CS42L52_CHIP_ONE 0x0025#define CS42L52_CHIP_TWO 0x0126#define CS42L52_CHIP_THR 0x0227#define CS42L52_CHIP_MASK 0x0f28 29#define CS42L52_FIX_BITS_CTL 0x0030#define CS42L52_CHIP 0x0131#define CS42L52_CHIP_ID 0xE032#define CS42L52_CHIP_ID_MASK 0xF833#define CS42L52_CHIP_REV_A0 0x0034#define CS42L52_CHIP_REV_A1 0x0135#define CS42L52_CHIP_REV_B0 0x0236#define CS42L52_CHIP_REV_MASK 0x0737 38#define CS42L52_PWRCTL1 0x0239#define CS42L52_PWRCTL1_PDN_ALL 0x9F40#define CS42L52_PWRCTL1_PDN_CHRG 0x8041#define CS42L52_PWRCTL1_PDN_PGAB 0x1042#define CS42L52_PWRCTL1_PDN_PGAA 0x0843#define CS42L52_PWRCTL1_PDN_ADCB 0x0444#define CS42L52_PWRCTL1_PDN_ADCA 0x0245#define CS42L52_PWRCTL1_PDN_CODEC 0x0146 47#define CS42L52_PWRCTL2 0x0348#define CS42L52_PWRCTL2_OVRDB (1 << 4)49#define CS42L52_PWRCTL2_OVRDA (1 << 3)50#define CS42L52_PWRCTL2_PDN_MICB (1 << 2)51#define CS42L52_PWRCTL2_PDN_MICB_SHIFT 252#define CS42L52_PWRCTL2_PDN_MICA (1 << 1)53#define CS42L52_PWRCTL2_PDN_MICA_SHIFT 154#define CS42L52_PWRCTL2_PDN_MICBIAS (1 << 0)55#define CS42L52_PWRCTL2_PDN_MICBIAS_SHIFT 056 57#define CS42L52_PWRCTL3 0x0458#define CS42L52_PWRCTL3_HPB_PDN_SHIFT 659#define CS42L52_PWRCTL3_HPB_ON_LOW 0x0060#define CS42L52_PWRCTL3_HPB_ON_HIGH 0x0161#define CS42L52_PWRCTL3_HPB_ALWAYS_ON 0x0262#define CS42L52_PWRCTL3_HPB_ALWAYS_OFF 0x0363#define CS42L52_PWRCTL3_HPA_PDN_SHIFT 464#define CS42L52_PWRCTL3_HPA_ON_LOW 0x0065#define CS42L52_PWRCTL3_HPA_ON_HIGH 0x0166#define CS42L52_PWRCTL3_HPA_ALWAYS_ON 0x0267#define CS42L52_PWRCTL3_HPA_ALWAYS_OFF 0x0368#define CS42L52_PWRCTL3_SPKB_PDN_SHIFT 269#define CS42L52_PWRCTL3_SPKB_ON_LOW 0x0070#define CS42L52_PWRCTL3_SPKB_ON_HIGH 0x0171#define CS42L52_PWRCTL3_SPKB_ALWAYS_ON 0x0272#define CS42L52_PWRCTL3_PDN_SPKB (1 << 2)73#define CS42L52_PWRCTL3_PDN_SPKA (1 << 0)74#define CS42L52_PWRCTL3_SPKA_PDN_SHIFT 075#define CS42L52_PWRCTL3_SPKA_ON_LOW 0x0076#define CS42L52_PWRCTL3_SPKA_ON_HIGH 0x0177#define CS42L52_PWRCTL3_SPKA_ALWAYS_ON 0x0278 79#define CS42L52_DEFAULT_OUTPUT_STATE 0x0580#define CS42L52_PWRCTL3_CONF_MASK 0x0381 82#define CS42L52_CLK_CTL 0x0583#define CLK_AUTODECT_ENABLE (1 << 7)84#define CLK_SPEED_SHIFT 585#define CLK_DS_MODE 0x0086#define CLK_SS_MODE 0x0187#define CLK_HS_MODE 0x0288#define CLK_QS_MODE 0x0389#define CLK_32K_SR_SHIFT 490#define CLK_32K 0x0191#define CLK_NO_32K 0x0092#define CLK_27M_MCLK_SHIFT 393#define CLK_27M_MCLK 0x0194#define CLK_NO_27M 0x0095#define CLK_RATIO_SHIFT 196#define CLK_R_128 0x0097#define CLK_R_125 0x0198#define CLK_R_132 0x0299#define CLK_R_136 0x03100 101#define CS42L52_IFACE_CTL1 0x06102#define CS42L52_IFACE_CTL1_MASTER (1 << 7)103#define CS42L52_IFACE_CTL1_SLAVE (0 << 7)104#define CS42L52_IFACE_CTL1_INV_SCLK (1 << 6)105#define CS42L52_IFACE_CTL1_ADC_FMT_I2S (1 << 5)106#define CS42L52_IFACE_CTL1_ADC_FMT_LEFT_J (0 << 5)107#define CS42L52_IFACE_CTL1_DSP_MODE_EN (1 << 4)108#define CS42L52_IFACE_CTL1_DAC_FMT_LEFT_J (0 << 2)109#define CS42L52_IFACE_CTL1_DAC_FMT_I2S (1 << 2)110#define CS42L52_IFACE_CTL1_DAC_FMT_RIGHT_J (2 << 2)111#define CS42L52_IFACE_CTL1_WL_32BIT (0x00)112#define CS42L52_IFACE_CTL1_WL_24BIT (0x01)113#define CS42L52_IFACE_CTL1_WL_20BIT (0x02)114#define CS42L52_IFACE_CTL1_WL_16BIT (0x03)115#define CS42L52_IFACE_CTL1_WL_MASK 0xFFFF116 117#define CS42L52_IFACE_CTL2 0x07118#define CS42L52_IFACE_CTL2_SC_MC_EQ (1 << 6)119#define CS42L52_IFACE_CTL2_LOOPBACK (1 << 5)120#define CS42L52_IFACE_CTL2_S_MODE_OUTPUT_EN (0 << 4)121#define CS42L52_IFACE_CTL2_S_MODE_OUTPUT_HIZ (1 << 4)122#define CS42L52_IFACE_CTL2_HP_SW_INV (1 << 3)123#define CS42L52_IFACE_CTL2_BIAS_LVL 0x07124 125#define CS42L52_ADC_PGA_A 0x08126#define CS42L52_ADC_PGA_B 0x09127#define CS42L52_ADC_SEL_SHIFT 5128#define CS42L52_ADC_SEL_AIN1 0x00129#define CS42L52_ADC_SEL_AIN2 0x01130#define CS42L52_ADC_SEL_AIN3 0x02131#define CS42L52_ADC_SEL_AIN4 0x03132#define CS42L52_ADC_SEL_PGA 0x04133 134#define CS42L52_ANALOG_HPF_CTL 0x0A135#define CS42L52_HPF_CTL_ANLGSFTB (1 << 3)136#define CS42L52_HPF_CTL_ANLGSFTA (1 << 0)137 138#define CS42L52_ADC_HPF_FREQ 0x0B139#define CS42L52_ADC_MISC_CTL 0x0C140#define CS42L52_ADC_MISC_CTL_SOURCE_DSP (1 << 6)141 142#define CS42L52_PB_CTL1 0x0D143#define CS42L52_PB_CTL1_HP_GAIN_SHIFT 5144#define CS42L52_PB_CTL1_HP_GAIN_03959 0x00145#define CS42L52_PB_CTL1_HP_GAIN_04571 0x01146#define CS42L52_PB_CTL1_HP_GAIN_05111 0x02147#define CS42L52_PB_CTL1_HP_GAIN_06047 0x03148#define CS42L52_PB_CTL1_HP_GAIN_07099 0x04149#define CS42L52_PB_CTL1_HP_GAIN_08399 0x05150#define CS42L52_PB_CTL1_HP_GAIN_10000 0x06151#define CS42L52_PB_CTL1_HP_GAIN_11430 0x07152#define CS42L52_PB_CTL1_INV_PCMB (1 << 3)153#define CS42L52_PB_CTL1_INV_PCMA (1 << 2)154#define CS42L52_PB_CTL1_MSTB_MUTE (1 << 1)155#define CS42L52_PB_CTL1_MSTA_MUTE (1 << 0)156#define CS42L52_PB_CTL1_MUTE_MASK 0x03157#define CS42L52_PB_CTL1_MUTE 3158#define CS42L52_PB_CTL1_UNMUTE 0159 160#define CS42L52_MISC_CTL 0x0E161#define CS42L52_MISC_CTL_DEEMPH (1 << 2)162#define CS42L52_MISC_CTL_DIGSFT (1 << 1)163#define CS42L52_MISC_CTL_DIGZC (1 << 0)164 165#define CS42L52_PB_CTL2 0x0F166#define CS42L52_PB_CTL2_HPB_MUTE (1 << 7)167#define CS42L52_PB_CTL2_HPA_MUTE (1 << 6)168#define CS42L52_PB_CTL2_SPKB_MUTE (1 << 5)169#define CS42L52_PB_CTL2_SPKA_MUTE (1 << 4)170#define CS42L52_PB_CTL2_SPK_SWAP (1 << 2)171#define CS42L52_PB_CTL2_SPK_MONO (1 << 1)172#define CS42L52_PB_CTL2_SPK_MUTE50 (1 << 0)173 174#define CS42L52_MICA_CTL 0x10175#define CS42L52_MICB_CTL 0x11176#define CS42L52_MIC_CTL_MIC_SEL_MASK 0xBF177#define CS42L52_MIC_CTL_MIC_SEL_SHIFT 6178#define CS42L52_MIC_CTL_TYPE_MASK 0x20179#define CS42L52_MIC_CTL_TYPE_SHIFT 5180 181 182#define CS42L52_PGAA_CTL 0x12183#define CS42L52_PGAB_CTL 0x13184#define CS42L52_PGAX_CTL_VOL_12DB 24185#define CS42L52_PGAX_CTL_VOL_6DB 12 /*step size 0.5db*/186 187#define CS42L52_PASSTHRUA_VOL 0x14188#define CS42L52_PASSTHRUB_VOL 0x15189 190#define CS42L52_ADCA_VOL 0x16191#define CS42L52_ADCB_VOL 0x17192#define CS42L52_ADCX_VOL_24DB 24 /*step size 1db*/193#define CS42L52_ADCX_VOL_12DB 12194#define CS42L52_ADCX_VOL_6DB 6195 196#define CS42L52_ADCA_MIXER_VOL 0x18197#define CS42L52_ADCB_MIXER_VOL 0x19198#define CS42L52_ADC_MIXER_VOL_12DB 0x18199 200#define CS42L52_PCMA_MIXER_VOL 0x1A201#define CS42L52_PCMB_MIXER_VOL 0x1B202 203#define CS42L52_BEEP_FREQ 0x1C204#define CS42L52_BEEP_VOL 0x1D205#define CS42L52_BEEP_TONE_CTL 0x1E206#define CS42L52_BEEP_RATE_SHIFT 4207#define CS42L52_BEEP_RATE_MASK 0x0F208 209#define CS42L52_TONE_CTL 0x1F210#define CS42L52_BEEP_EN_MASK 0x3F211 212#define CS42L52_MASTERA_VOL 0x20213#define CS42L52_MASTERB_VOL 0x21214 215#define CS42L52_HPA_VOL 0x22216#define CS42L52_HPB_VOL 0x23217#define CS42L52_DEFAULT_HP_VOL 0xF0218 219#define CS42L52_SPKA_VOL 0x24220#define CS42L52_SPKB_VOL 0x25221#define CS42L52_DEFAULT_SPK_VOL 0xF0222 223#define CS42L52_ADC_PCM_MIXER 0x26224 225#define CS42L52_LIMITER_CTL1 0x27226#define CS42L52_LIMITER_CTL2 0x28227#define CS42L52_LIMITER_AT_RATE 0x29228 229#define CS42L52_ALC_CTL 0x2A230#define CS42L52_ALC_CTL_ALCB_ENABLE_SHIFT 7231#define CS42L52_ALC_CTL_ALCA_ENABLE_SHIFT 6232#define CS42L52_ALC_CTL_FASTEST_ATTACK 0233 234#define CS42L52_ALC_RATE 0x2B235#define CS42L52_ALC_SLOWEST_RELEASE 0x3F236 237#define CS42L52_ALC_THRESHOLD 0x2C238#define CS42L52_ALC_MAX_RATE_SHIFT 5239#define CS42L52_ALC_MIN_RATE_SHIFT 2240#define CS42L52_ALC_RATE_0DB 0241#define CS42L52_ALC_RATE_3DB 1242#define CS42L52_ALC_RATE_6DB 2243 244#define CS42L52_NOISE_GATE_CTL 0x2D245#define CS42L52_NG_ENABLE_SHIFT 6246#define CS42L52_NG_THRESHOLD_SHIFT 2247#define CS42L52_NG_MIN_70DB 2248#define CS42L52_NG_DELAY_SHIFT 0249#define CS42L52_NG_DELAY_100MS 1250 251#define CS42L52_CLK_STATUS 0x2E252#define CS42L52_BATT_COMPEN 0x2F253 254#define CS42L52_BATT_LEVEL 0x30255#define CS42L52_SPK_STATUS 0x31256#define CS42L52_SPK_STATUS_PIN_SHIFT 3257#define CS42L52_SPK_STATUS_PIN_HIGH 1258 259#define CS42L52_TEM_CTL 0x32260#define CS42L52_TEM_CTL_SET 0x80261#define CS42L52_THE_FOLDBACK 0x33262#define CS42L52_CHARGE_PUMP 0x34263#define CS42L52_CHARGE_PUMP_MASK 0xF0264#define CS42L52_CHARGE_PUMP_SHIFT 4265#define CS42L52_FIX_BITS1 0x3E266#define CS42L52_FIX_BITS2 0x47267 268#define CS42L52_MAX_REGISTER 0x47269 270#endif271