542 lines · c
1/* SPDX-License-Identifier: GPL-2.0-only */2/*3 * ALSA SoC CS43130 codec driver4 *5 * Copyright 2017 Cirrus Logic, Inc.6 *7 * Author: Li Xu <li.xu@cirrus.com>8 */9 10#ifndef __CS43130_H__11#define __CS43130_H__12 13#include <linux/math.h>14 15/* CS43130 registers addresses */16/* all reg address is shifted by a byte for control byte to be LSB */17#define CS43130_FIRSTREG 0x01000018#define CS43130_LASTREG 0x19000019#define CS43130_CHIP_ID 0x0004313020#define CS4399_CHIP_ID 0x0004399021#define CS43131_CHIP_ID 0x0004313122#define CS43198_CHIP_ID 0x0004319823#define CS43130_DEVID_AB 0x010000 /* Device ID A & B [RO] */24#define CS43130_DEVID_CD 0x010001 /* Device ID C & D [RO] */25#define CS43130_DEVID_E 0x010002 /* Device ID E [RO] */26#define CS43130_FAB_ID 0x010003 /* Fab ID [RO] */27#define CS43130_REV_ID 0x010004 /* Revision ID [RO] */28#define CS43130_SUBREV_ID 0x010005 /* Subrevision ID */29#define CS43130_SYS_CLK_CTL_1 0x010006 /* System Clocking Ctl 1 */30#define CS43130_SP_SRATE 0x01000B /* Serial Port Sample Rate */31#define CS43130_SP_BITSIZE 0x01000C /* Serial Port Bit Size */32#define CS43130_PAD_INT_CFG 0x01000D /* Pad Interface Config */33#define CS43130_DXD1 0x010010 /* DXD1 */34#define CS43130_DXD7 0x010025 /* DXD7 */35#define CS43130_DXD19 0x010026 /* DXD19 */36#define CS43130_DXD17 0x010027 /* DXD17 */37#define CS43130_DXD18 0x010028 /* DXD18 */38#define CS43130_DXD12 0x01002C /* DXD12 */39#define CS43130_DXD8 0x01002E /* DXD8 */40#define CS43130_PWDN_CTL 0x020000 /* Power Down Ctl */41#define CS43130_DXD2 0x020019 /* DXD2 */42#define CS43130_CRYSTAL_SET 0x020052 /* Crystal Setting */43#define CS43130_PLL_SET_1 0x030001 /* PLL Setting 1 */44#define CS43130_PLL_SET_2 0x030002 /* PLL Setting 2 */45#define CS43130_PLL_SET_3 0x030003 /* PLL Setting 3 */46#define CS43130_PLL_SET_4 0x030004 /* PLL Setting 4 */47#define CS43130_PLL_SET_5 0x030005 /* PLL Setting 5 */48#define CS43130_PLL_SET_6 0x030008 /* PLL Setting 6 */49#define CS43130_PLL_SET_7 0x03000A /* PLL Setting 7 */50#define CS43130_PLL_SET_8 0x03001B /* PLL Setting 8 */51#define CS43130_PLL_SET_9 0x040002 /* PLL Setting 9 */52#define CS43130_PLL_SET_10 0x040003 /* PLL Setting 10 */53#define CS43130_CLKOUT_CTL 0x040004 /* CLKOUT Ctl */54#define CS43130_ASP_NUM_1 0x040010 /* ASP Numerator 1 */55#define CS43130_ASP_NUM_2 0x040011 /* ASP Numerator 2 */56#define CS43130_ASP_DEN_1 0x040012 /* ASP Denominator 1 */57#define CS43130_ASP_DEN_2 0x040013 /* ASP Denominator 2 */58#define CS43130_ASP_LRCK_HI_TIME_1 0x040014 /* ASP LRCK High Time 1 */59#define CS43130_ASP_LRCK_HI_TIME_2 0x040015 /* ASP LRCK High Time 2 */60#define CS43130_ASP_LRCK_PERIOD_1 0x040016 /* ASP LRCK Period 1 */61#define CS43130_ASP_LRCK_PERIOD_2 0x040017 /* ASP LRCK Period 2 */62#define CS43130_ASP_CLOCK_CONF 0x040018 /* ASP Clock Config */63#define CS43130_ASP_FRAME_CONF 0x040019 /* ASP Frame Config */64#define CS43130_XSP_NUM_1 0x040020 /* XSP Numerator 1 */65#define CS43130_XSP_NUM_2 0x040021 /* XSP Numerator 2 */66#define CS43130_XSP_DEN_1 0x040022 /* XSP Denominator 1 */67#define CS43130_XSP_DEN_2 0x040023 /* XSP Denominator 2 */68#define CS43130_XSP_LRCK_HI_TIME_1 0x040024 /* XSP LRCK High Time 1 */69#define CS43130_XSP_LRCK_HI_TIME_2 0x040025 /* XSP LRCK High Time 2 */70#define CS43130_XSP_LRCK_PERIOD_1 0x040026 /* XSP LRCK Period 1 */71#define CS43130_XSP_LRCK_PERIOD_2 0x040027 /* XSP LRCK Period 2 */72#define CS43130_XSP_CLOCK_CONF 0x040028 /* XSP Clock Config */73#define CS43130_XSP_FRAME_CONF 0x040029 /* XSP Frame Config */74#define CS43130_ASP_CH_1_LOC 0x050000 /* ASP Chan 1 Location */75#define CS43130_ASP_CH_2_LOC 0x050001 /* ASP Chan 2 Location */76#define CS43130_ASP_CH_1_SZ_EN 0x05000A /* ASP Chan 1 Size, Enable */77#define CS43130_ASP_CH_2_SZ_EN 0x05000B /* ASP Chan 2 Size, Enable */78#define CS43130_XSP_CH_1_LOC 0x060000 /* XSP Chan 1 Location */79#define CS43130_XSP_CH_2_LOC 0x060001 /* XSP Chan 2 Location */80#define CS43130_XSP_CH_1_SZ_EN 0x06000A /* XSP Chan 1 Size, Enable */81#define CS43130_XSP_CH_2_SZ_EN 0x06000B /* XSP Chan 2 Size, Enable */82#define CS43130_DSD_VOL_B 0x070000 /* DSD Volume B */83#define CS43130_DSD_VOL_A 0x070001 /* DSD Volume A */84#define CS43130_DSD_PATH_CTL_1 0x070002 /* DSD Proc Path Sig Ctl 1 */85#define CS43130_DSD_INT_CFG 0x070003 /* DSD Interface Config */86#define CS43130_DSD_PATH_CTL_2 0x070004 /* DSD Proc Path Sig Ctl 2 */87#define CS43130_DSD_PCM_MIX_CTL 0x070005 /* DSD and PCM Mixing Ctl */88#define CS43130_DSD_PATH_CTL_3 0x070006 /* DSD Proc Path Sig Ctl 3 */89#define CS43130_HP_OUT_CTL_1 0x080000 /* HP Output Ctl 1 */90#define CS43130_DXD16 0x080024 /* DXD16 */91#define CS43130_DXD13 0x080032 /* DXD13 */92#define CS43130_PCM_FILT_OPT 0x090000 /* PCM Filter Option */93#define CS43130_PCM_VOL_B 0x090001 /* PCM Volume B */94#define CS43130_PCM_VOL_A 0x090002 /* PCM Volume A */95#define CS43130_PCM_PATH_CTL_1 0x090003 /* PCM Path Signal Ctl 1 */96#define CS43130_PCM_PATH_CTL_2 0x090004 /* PCM Path Signal Ctl 2 */97#define CS43130_DXD6 0x090097 /* DXD6 */98#define CS43130_CLASS_H_CTL 0x0B0000 /* Class H Ctl */99#define CS43130_DXD15 0x0B0005 /* DXD15 */100#define CS43130_DXD14 0x0B0006 /* DXD14 */101#define CS43130_DXD3 0x0C0002 /* DXD3 */102#define CS43130_DXD10 0x0C0003 /* DXD10 */103#define CS43130_DXD11 0x0C0005 /* DXD11 */104#define CS43130_DXD9 0x0C0006 /* DXD9 */105#define CS43130_DXD4 0x0C0009 /* DXD4 */106#define CS43130_DXD5 0x0C000E /* DXD5 */107#define CS43130_HP_DETECT 0x0D0000 /* HP Detect */108#define CS43130_HP_STATUS 0x0D0001 /* HP Status [RO] */109#define CS43130_HP_LOAD_1 0x0E0000 /* HP Load 1 */110#define CS43130_HP_MEAS_LOAD_1 0x0E0003 /* HP Load Measurement 1 */111#define CS43130_HP_MEAS_LOAD_2 0x0E0004 /* HP Load Measurement 2 */112#define CS43130_HP_DC_STAT_1 0x0E000D /* HP DC Load Status 0 [RO] */113#define CS43130_HP_DC_STAT_2 0x0E000E /* HP DC Load Status 1 [RO] */114#define CS43130_HP_AC_STAT_1 0x0E0010 /* HP AC Load Status 0 [RO] */115#define CS43130_HP_AC_STAT_2 0x0E0011 /* HP AC Load Status 1 [RO] */116#define CS43130_HP_LOAD_STAT 0x0E001A /* HP Load Status [RO] */117#define CS43130_INT_STATUS_1 0x0F0000 /* Interrupt Status 1 */118#define CS43130_INT_STATUS_2 0x0F0001 /* Interrupt Status 2 */119#define CS43130_INT_STATUS_3 0x0F0002 /* Interrupt Status 3 */120#define CS43130_INT_STATUS_4 0x0F0003 /* Interrupt Status 4 */121#define CS43130_INT_STATUS_5 0x0F0004 /* Interrupt Status 5 */122#define CS43130_INT_MASK_1 0x0F0010 /* Interrupt Mask 1 */123#define CS43130_INT_MASK_2 0x0F0011 /* Interrupt Mask 2 */124#define CS43130_INT_MASK_3 0x0F0012 /* Interrupt Mask 3 */125#define CS43130_INT_MASK_4 0x0F0013 /* Interrupt Mask 4 */126#define CS43130_INT_MASK_5 0x0F0014 /* Interrupt Mask 5 */127 128#define CS43130_MCLK_SRC_SEL_MASK 0x03129#define CS43130_MCLK_SRC_SEL_SHIFT 0130#define CS43130_MCLK_INT_MASK 0x04131#define CS43130_MCLK_INT_SHIFT 2132#define CS43130_CH_BITSIZE_MASK 0x03133#define CS43130_CH_EN_MASK 0x04134#define CS43130_CH_EN_SHIFT 2135#define CS43130_ASP_BITSIZE_MASK 0x03136#define CS43130_XSP_BITSIZE_MASK 0x0C137#define CS43130_XSP_BITSIZE_SHIFT 2138#define CS43130_SP_BITSIZE_ASP_SHIFT 0139#define CS43130_HP_DETECT_CTRL_SHIFT 6140#define CS43130_HP_DETECT_CTRL_MASK (0x03 << CS43130_HP_DETECT_CTRL_SHIFT)141#define CS43130_HP_DETECT_INV_SHIFT 5142#define CS43130_HP_DETECT_INV_MASK (1 << CS43130_HP_DETECT_INV_SHIFT)143 144/* CS43130_INT_MASK_1 */145#define CS43130_HP_PLUG_INT_SHIFT 6146#define CS43130_HP_PLUG_INT (1 << CS43130_HP_PLUG_INT_SHIFT)147#define CS43130_HP_UNPLUG_INT_SHIFT 5148#define CS43130_HP_UNPLUG_INT (1 << CS43130_HP_UNPLUG_INT_SHIFT)149#define CS43130_XTAL_RDY_INT_SHIFT 4150#define CS43130_XTAL_RDY_INT_MASK 0x10151#define CS43130_XTAL_RDY_INT (1 << CS43130_XTAL_RDY_INT_SHIFT)152#define CS43130_XTAL_ERR_INT_SHIFT 3153#define CS43130_XTAL_ERR_INT (1 << CS43130_XTAL_ERR_INT_SHIFT)154#define CS43130_PLL_RDY_INT_MASK 0x04155#define CS43130_PLL_RDY_INT_SHIFT 2156#define CS43130_PLL_RDY_INT (1 << CS43130_PLL_RDY_INT_SHIFT)157 158/* CS43130_INT_MASK_4 */159#define CS43130_INT_MASK_ALL 0xFF160#define CS43130_HPLOAD_NO_DC_INT_SHIFT 7161#define CS43130_HPLOAD_NO_DC_INT (1 << CS43130_HPLOAD_NO_DC_INT_SHIFT)162#define CS43130_HPLOAD_UNPLUG_INT_SHIFT 6163#define CS43130_HPLOAD_UNPLUG_INT (1 << CS43130_HPLOAD_UNPLUG_INT_SHIFT)164#define CS43130_HPLOAD_OOR_INT_SHIFT 4165#define CS43130_HPLOAD_OOR_INT (1 << CS43130_HPLOAD_OOR_INT_SHIFT)166#define CS43130_HPLOAD_AC_INT_SHIFT 3167#define CS43130_HPLOAD_AC_INT (1 << CS43130_HPLOAD_AC_INT_SHIFT)168#define CS43130_HPLOAD_DC_INT_SHIFT 2169#define CS43130_HPLOAD_DC_INT (1 << CS43130_HPLOAD_DC_INT_SHIFT)170#define CS43130_HPLOAD_OFF_INT_SHIFT 1171#define CS43130_HPLOAD_OFF_INT (1 << CS43130_HPLOAD_OFF_INT_SHIFT)172#define CS43130_HPLOAD_ON_INT 1173 174/* CS43130_HP_LOAD_1 */175#define CS43130_HPLOAD_EN_SHIFT 7176#define CS43130_HPLOAD_EN (1 << CS43130_HPLOAD_EN_SHIFT)177#define CS43130_HPLOAD_CHN_SEL_SHIFT 4178#define CS43130_HPLOAD_CHN_SEL (1 << CS43130_HPLOAD_CHN_SEL_SHIFT)179#define CS43130_HPLOAD_AC_START_SHIFT 1180#define CS43130_HPLOAD_AC_START (1 << CS43130_HPLOAD_AC_START_SHIFT)181#define CS43130_HPLOAD_DC_START 1182 183/* Reg CS43130_SP_BITSIZE */184#define CS43130_SP_BIT_SIZE_8 0x03185#define CS43130_SP_BIT_SIZE_16 0x02186#define CS43130_SP_BIT_SIZE_24 0x01187#define CS43130_SP_BIT_SIZE_32 0x00188 189/* Reg CS43130_SP_CH_SZ_EN */190#define CS43130_CH_BIT_SIZE_8 0x00191#define CS43130_CH_BIT_SIZE_16 0x01192#define CS43130_CH_BIT_SIZE_24 0x02193#define CS43130_CH_BIT_SIZE_32 0x03194 195/* PLL */196#define CS43130_PLL_START_MASK 0x01197#define CS43130_PLL_MODE_MASK 0x02198#define CS43130_PLL_MODE_SHIFT 1199 200#define CS43130_PLL_REF_PREDIV_MASK 0x3201 202#define CS43130_SP_STP_MASK 0x10203#define CS43130_SP_STP_SHIFT 4204#define CS43130_SP_5050_MASK 0x08205#define CS43130_SP_5050_SHIFT 3206#define CS43130_SP_FSD_MASK 0x07207 208#define CS43130_SP_MODE_MASK 0x10209#define CS43130_SP_MODE_SHIFT 4210#define CS43130_SP_SCPOL_OUT_MASK 0x08211#define CS43130_SP_SCPOL_OUT_SHIFT 3212#define CS43130_SP_SCPOL_IN_MASK 0x04213#define CS43130_SP_SCPOL_IN_SHIFT 2214#define CS43130_SP_LCPOL_OUT_MASK 0x02215#define CS43130_SP_LCPOL_OUT_SHIFT 1216#define CS43130_SP_LCPOL_IN_MASK 0x01217#define CS43130_SP_LCPOL_IN_SHIFT 0218 219/* Reg CS43130_PWDN_CTL */220#define CS43130_PDN_XSP_MASK 0x80221#define CS43130_PDN_XSP_SHIFT 7222#define CS43130_PDN_ASP_MASK 0x40223#define CS43130_PDN_ASP_SHIFT 6224#define CS43130_PDN_DSPIF_MASK 0x20225#define CS43130_PDN_DSDIF_SHIFT 5226#define CS43130_PDN_HP_MASK 0x10227#define CS43130_PDN_HP_SHIFT 4228#define CS43130_PDN_XTAL_MASK 0x08229#define CS43130_PDN_XTAL_SHIFT 3230#define CS43130_PDN_PLL_MASK 0x04231#define CS43130_PDN_PLL_SHIFT 2232#define CS43130_PDN_CLKOUT_MASK 0x02233#define CS43130_PDN_CLKOUT_SHIFT 1234 235/* Reg CS43130_HP_OUT_CTL_1 */236#define CS43130_HP_IN_EN_SHIFT 3237#define CS43130_HP_IN_EN_MASK 0x08238 239/* Reg CS43130_PAD_INT_CFG */240#define CS43130_ASP_3ST_MASK 0x01241#define CS43130_XSP_3ST_MASK 0x02242 243/* Reg CS43130_PLL_SET_2 */244#define CS43130_PLL_DIV_DATA_MASK 0x000000FF245#define CS43130_PLL_DIV_FRAC_0_DATA_SHIFT 0246 247/* Reg CS43130_PLL_SET_3 */248#define CS43130_PLL_DIV_FRAC_1_DATA_SHIFT 8249 250/* Reg CS43130_PLL_SET_4 */251#define CS43130_PLL_DIV_FRAC_2_DATA_SHIFT 16252 253/* Reg CS43130_SP_DEN_1 */254#define CS43130_SP_M_LSB_DATA_MASK 0x00FF255#define CS43130_SP_M_LSB_DATA_SHIFT 0256 257/* Reg CS43130_SP_DEN_2 */258#define CS43130_SP_M_MSB_DATA_MASK 0xFF00259#define CS43130_SP_M_MSB_DATA_SHIFT 8260 261/* Reg CS43130_SP_NUM_1 */262#define CS43130_SP_N_LSB_DATA_MASK 0x00FF263#define CS43130_SP_N_LSB_DATA_SHIFT 0264 265/* Reg CS43130_SP_NUM_2 */266#define CS43130_SP_N_MSB_DATA_MASK 0xFF00267#define CS43130_SP_N_MSB_DATA_SHIFT 8268 269/* Reg CS43130_SP_LRCK_HI_TIME_1 */270#define CS43130_SP_LCHI_DATA_MASK 0x00FF271#define CS43130_SP_LCHI_LSB_DATA_SHIFT 0272 273/* Reg CS43130_SP_LRCK_HI_TIME_2 */274#define CS43130_SP_LCHI_MSB_DATA_SHIFT 8275 276/* Reg CS43130_SP_LRCK_PERIOD_1 */277#define CS43130_SP_LCPR_DATA_MASK 0x00FF278#define CS43130_SP_LCPR_LSB_DATA_SHIFT 0279 280/* Reg CS43130_SP_LRCK_PERIOD_2 */281#define CS43130_SP_LCPR_MSB_DATA_SHIFT 8282 283#define CS43130_PCM_FORMATS (SNDRV_PCM_FMTBIT_S8 | \284 SNDRV_PCM_FMTBIT_S16_LE | \285 SNDRV_PCM_FMTBIT_S24_LE | \286 SNDRV_PCM_FMTBIT_S32_LE)287 288#define CS43130_DOP_FORMATS (SNDRV_PCM_FMTBIT_DSD_U16_LE | \289 SNDRV_PCM_FMTBIT_DSD_U16_BE | \290 SNDRV_PCM_FMTBIT_S24_LE)291 292/* Reg CS43130_CRYSTAL_SET */293#define CS43130_XTAL_IBIAS_MASK 0x07294 295/* Reg CS43130_PATH_CTL_1 */296#define CS43130_MUTE_MASK 0x03297#define CS43130_MUTE_EN 0x03298 299/* Reg CS43130_DSD_INT_CFG */300#define CS43130_DSD_MASTER 0x04301 302/* Reg CS43130_DSD_PATH_CTL_2 */303#define CS43130_DSD_SRC_MASK 0x60304#define CS43130_DSD_SRC_SHIFT 5305#define CS43130_DSD_EN_SHIFT 4306#define CS43130_DSD_SPEED_MASK 0x04307#define CS43130_DSD_SPEED_SHIFT 2308 309/* Reg CS43130_DSD_PCM_MIX_CTL */310#define CS43130_MIX_PCM_PREP_SHIFT 1311#define CS43130_MIX_PCM_PREP_MASK 0x02312 313#define CS43130_MIX_PCM_DSD_SHIFT 0314#define CS43130_MIX_PCM_DSD_MASK 0x01315 316/* Reg CS43130_HP_MEAS_LOAD */317#define CS43130_HP_MEAS_LOAD_MASK 0x000000FF318#define CS43130_HP_MEAS_LOAD_1_SHIFT 0319#define CS43130_HP_MEAS_LOAD_2_SHIFT 8320 321#define CS43130_MCLK_22M 22579200322#define CS43130_MCLK_24M 24576000323 324#define CS43130_LINEOUT_LOAD 5000325#define CS43130_JACK_LINEOUT (SND_JACK_MECHANICAL | SND_JACK_LINEOUT)326#define CS43130_JACK_HEADPHONE (SND_JACK_MECHANICAL | \327 SND_JACK_HEADPHONE)328#define CS43130_JACK_MASK (SND_JACK_MECHANICAL | \329 SND_JACK_LINEOUT | \330 SND_JACK_HEADPHONE)331 332enum cs43130_dsd_src {333 CS43130_DSD_SRC_DSD = 0,334 CS43130_DSD_SRC_ASP = 2,335 CS43130_DSD_SRC_XSP = 3,336};337 338enum cs43130_asp_rate {339 CS43130_ASP_SPRATE_32K = 0,340 CS43130_ASP_SPRATE_44_1K,341 CS43130_ASP_SPRATE_48K,342 CS43130_ASP_SPRATE_88_2K,343 CS43130_ASP_SPRATE_96K,344 CS43130_ASP_SPRATE_176_4K,345 CS43130_ASP_SPRATE_192K,346 CS43130_ASP_SPRATE_352_8K,347 CS43130_ASP_SPRATE_384K,348};349 350enum cs43130_mclk_src_sel {351 CS43130_MCLK_SRC_EXT = 0,352 CS43130_MCLK_SRC_PLL,353 CS43130_MCLK_SRC_RCO354};355 356enum cs43130_mclk_int_freq {357 CS43130_MCLK_24P5 = 0,358 CS43130_MCLK_22P5,359};360 361enum cs43130_xtal_ibias {362 CS43130_XTAL_UNUSED = -1,363 CS43130_XTAL_IBIAS_15UA = 2,364 CS43130_XTAL_IBIAS_12_5UA = 4,365 CS43130_XTAL_IBIAS_7_5UA = 6,366};367 368enum cs43130_dai_id {369 CS43130_ASP_PCM_DAI = 0,370 CS43130_ASP_DOP_DAI,371 CS43130_XSP_DOP_DAI,372 CS43130_XSP_DSD_DAI,373 CS43130_DAI_ID_MAX,374};375 376struct cs43130_clk_gen {377 unsigned int mclk_int;378 int fs;379 struct u16_fract v;380};381 382/* frm_size = 16 */383static const struct cs43130_clk_gen cs43130_16_clk_gen[] = {384 { 22579200, 32000, .v = { 10, 441, }, },385 { 22579200, 44100, .v = { 1, 32, }, },386 { 22579200, 48000, .v = { 5, 147, }, },387 { 22579200, 88200, .v = { 1, 16, }, },388 { 22579200, 96000, .v = { 10, 147, }, },389 { 22579200, 176400, .v = { 1, 8, }, },390 { 22579200, 192000, .v = { 20, 147, }, },391 { 22579200, 352800, .v = { 1, 4, }, },392 { 22579200, 384000, .v = { 40, 147, }, },393 { 24576000, 32000, .v = { 1, 48, }, },394 { 24576000, 44100, .v = { 147, 5120, }, },395 { 24576000, 48000, .v = { 1, 32, }, },396 { 24576000, 88200, .v = { 147, 2560, }, },397 { 24576000, 96000, .v = { 1, 16, }, },398 { 24576000, 176400, .v = { 147, 1280, }, },399 { 24576000, 192000, .v = { 1, 8, }, },400 { 24576000, 352800, .v = { 147, 640, }, },401 { 24576000, 384000, .v = { 1, 4, }, },402};403 404/* frm_size = 32 */405static const struct cs43130_clk_gen cs43130_32_clk_gen[] = {406 { 22579200, 32000, .v = { 20, 441, }, },407 { 22579200, 44100, .v = { 1, 16, }, },408 { 22579200, 48000, .v = { 10, 147, }, },409 { 22579200, 88200, .v = { 1, 8, }, },410 { 22579200, 96000, .v = { 20, 147, }, },411 { 22579200, 176400, .v = { 1, 4, }, },412 { 22579200, 192000, .v = { 40, 147, }, },413 { 22579200, 352800, .v = { 1, 2, }, },414 { 22579200, 384000, .v = { 80, 147, }, },415 { 24576000, 32000, .v = { 1, 24, }, },416 { 24576000, 44100, .v = { 147, 2560, }, },417 { 24576000, 48000, .v = { 1, 16, }, },418 { 24576000, 88200, .v = { 147, 1280, }, },419 { 24576000, 96000, .v = { 1, 8, }, },420 { 24576000, 176400, .v = { 147, 640, }, },421 { 24576000, 192000, .v = { 1, 4, }, },422 { 24576000, 352800, .v = { 147, 320, }, },423 { 24576000, 384000, .v = { 1, 2, }, },424};425 426/* frm_size = 48 */427static const struct cs43130_clk_gen cs43130_48_clk_gen[] = {428 { 22579200, 32000, .v = { 100, 147, }, },429 { 22579200, 44100, .v = { 3, 32, }, },430 { 22579200, 48000, .v = { 5, 49, }, },431 { 22579200, 88200, .v = { 3, 16, }, },432 { 22579200, 96000, .v = { 10, 49, }, },433 { 22579200, 176400, .v = { 3, 8, }, },434 { 22579200, 192000, .v = { 20, 49, }, },435 { 22579200, 352800, .v = { 3, 4, }, },436 { 22579200, 384000, .v = { 40, 49, }, },437 { 24576000, 32000, .v = { 1, 16, }, },438 { 24576000, 44100, .v = { 441, 5120, }, },439 { 24576000, 48000, .v = { 3, 32, }, },440 { 24576000, 88200, .v = { 441, 2560, }, },441 { 24576000, 96000, .v = { 3, 16, }, },442 { 24576000, 176400, .v = { 441, 1280, }, },443 { 24576000, 192000, .v = { 3, 8, }, },444 { 24576000, 352800, .v = { 441, 640, }, },445 { 24576000, 384000, .v = { 3, 4, }, },446};447 448/* frm_size = 64 */449static const struct cs43130_clk_gen cs43130_64_clk_gen[] = {450 { 22579200, 32000, .v = { 40, 441, }, },451 { 22579200, 44100, .v = { 1, 8, }, },452 { 22579200, 48000, .v = { 20, 147, }, },453 { 22579200, 88200, .v = { 1, 4, }, },454 { 22579200, 96000, .v = { 40, 147, }, },455 { 22579200, 176400, .v = { 1, 2, }, },456 { 22579200, 192000, .v = { 80, 147, }, },457 { 22579200, 352800, .v = { 1, 1, }, },458 { 24576000, 32000, .v = { 1, 12, }, },459 { 24576000, 44100, .v = { 147, 1280, }, },460 { 24576000, 48000, .v = { 1, 8, }, },461 { 24576000, 88200, .v = { 147, 640, }, },462 { 24576000, 96000, .v = { 1, 4, }, },463 { 24576000, 176400, .v = { 147, 320, }, },464 { 24576000, 192000, .v = { 1, 2, }, },465 { 24576000, 352800, .v = { 147, 160, }, },466 { 24576000, 384000, .v = { 1, 1, }, },467};468 469struct cs43130_bitwidth_map {470 unsigned int bitwidth;471 u8 sp_bit;472 u8 ch_bit;473};474 475struct cs43130_rate_map {476 int fs;477 int val;478};479 480#define HP_LEFT 0481#define HP_RIGHT 1482#define CS43130_AC_FREQ 10483#define CS43130_DC_THRESHOLD 2484 485#define CS43130_NUM_SUPPLIES 5486static const char *const cs43130_supply_names[CS43130_NUM_SUPPLIES] = {487 "VA",488 "VP",489 "VCP",490 "VD",491 "VL",492};493 494#define CS43130_NUM_INT 5 /* number of interrupt status reg */495 496struct cs43130_dai {497 unsigned int sclk;498 unsigned int dai_format;499 unsigned int dai_mode;500 unsigned int dai_invert;501};502 503struct cs43130_private {504 struct device *dev;505 struct snd_soc_component *component;506 struct regmap *regmap;507 struct regulator_bulk_data supplies[CS43130_NUM_SUPPLIES];508 struct gpio_desc *reset_gpio;509 unsigned int dev_id; /* codec device ID */510 int xtal_ibias;511 bool has_irq_line;512 513 /* shared by both DAIs */514 struct mutex clk_mutex;515 int clk_req;516 bool pll_bypass;517 struct completion xtal_rdy;518 struct completion pll_rdy;519 unsigned int mclk;520 unsigned int mclk_int;521 int mclk_int_src;522 523 /* DAI specific */524 struct cs43130_dai dais[CS43130_DAI_ID_MAX];525 526 /* HP load specific */527 bool dc_meas;528 bool ac_meas;529 bool hpload_done;530 struct completion hpload_evt;531 unsigned int hpload_stat;532 u16 hpload_dc[2];533 u16 dc_threshold[CS43130_DC_THRESHOLD];534 u16 ac_freq[CS43130_AC_FREQ];535 u16 hpload_ac[CS43130_AC_FREQ][2];536 struct workqueue_struct *wq;537 struct work_struct work;538 struct snd_soc_jack jack;539};540 541#endif /* __CS43130_H__ */542