224 lines · c
1/* SPDX-License-Identifier: GPL-2.0 */2/*3 * CS530x CODEC driver internal data4 *5 * Copyright (C) 2023-2024 Cirrus Logic, Inc. and6 * Cirrus Logic International Semiconductor Ltd.7 */8 9#ifndef _CS530X_H10#define _CS530X_H11 12#include <linux/device.h>13#include <linux/gpio/consumer.h>14#include <linux/regmap.h>15#include <linux/regulator/consumer.h>16 17/* Devices */18#define CS530X_2CH_ADC_DEV_ID 0x530219#define CS530X_4CH_ADC_DEV_ID 0x530420#define CS530X_8CH_ADC_DEV_ID 0x530821 22/* Registers */23 24#define CS530X_DEVID 0x000000025#define CS530X_REVID 0x000000426#define CS530X_SW_RESET 0x000002227 28#define CS530X_CLK_CFG_0 0x000004029#define CS530X_CLK_CFG_1 0x000004230#define CS530X_CHIP_ENABLE 0x000004431#define CS530X_ASP_CFG 0x000004832#define CS530X_SIGNAL_PATH_CFG 0x000005033#define CS530X_IN_ENABLES 0x000008034#define CS530X_IN_RAMP_SUM 0x000008235#define CS530X_IN_FILTER 0x000008636#define CS530X_IN_HIZ 0x000008837#define CS530X_IN_INV 0x000008A38#define CS530X_IN_VOL_CTRL1_0 0x000009039#define CS530X_IN_VOL_CTRL1_1 0x000009240#define CS530X_IN_VOL_CTRL2_0 0x000009441#define CS530X_IN_VOL_CTRL2_1 0x000009642#define CS530X_IN_VOL_CTRL3_0 0x000009843#define CS530X_IN_VOL_CTRL3_1 0x000009A44#define CS530X_IN_VOL_CTRL4_0 0x000009C45#define CS530X_IN_VOL_CTRL4_1 0x000009E46#define CS530X_IN_VOL_CTRL5 0x00000A047 48#define CS530X_PAD_FN 0x0003D2449#define CS530X_PAD_LVL 0x0003D2850 51#define CS530X_MAX_REGISTER CS530X_PAD_LVL52 53/* Register Fields */54 55/* REVID */56#define CS530X_MTLREVID GENMASK(3, 0)57#define CS530X_AREVID GENMASK(7, 4)58 59/* SW_RESET */60#define CS530X_SW_RST_SHIFT 861#define CS530X_SW_RST_VAL (0x5A << CS530X_SW_RST_SHIFT)62 63/* CLK_CFG_0 */64#define CS530X_PLL_REFCLK_SRC_MASK BIT(0)65#define CS530X_PLL_REFCLK_FREQ_MASK GENMASK(5, 4)66#define CS530X_SYSCLK_SRC_MASK BIT(12)67#define CS530X_SYSCLK_SRC_SHIFT 1268#define CS530X_REFCLK_2P822_3P072 069#define CS530X_REFCLK_5P6448_6P144 0x1070#define CS530X_REFCLK_11P2896_12P288 0x2071#define CS530X_REFCLK_24P5792_24P576 0x3072 73/* CLK_CFG_1 */74#define CS530X_SAMPLE_RATE_MASK GENMASK(2, 0)75#define CS530X_FS_32K 076#define CS530X_FS_48K_44P1K 177#define CS530X_FS_96K_88P2K 278#define CS530X_FS_192K_176P4K 379#define CS530X_FS_384K_356P8K 480#define CS530X_FS_768K_705P6K 581 82/* CHIP_ENABLE */83#define CS530X_GLOBAL_EN BIT(0)84 85/* ASP_CFG */86#define CS530X_ASP_BCLK_FREQ_MASK GENMASK(1, 0)87#define CS530X_ASP_PRIMARY BIT(5)88#define CS530X_ASP_BCLK_INV BIT(6)89#define CS530X_BCLK_2P822_3P072 090#define CS530X_BCLK_5P6448_6P144 191#define CS530X_BCLK_11P2896_12P288 292#define CS530X_BCLK_24P5792_24P576 393 94/* SIGNAL_PATH_CFG */95#define CS530X_ASP_FMT_MASK GENMASK(2, 0)96#define CS530X_ASP_TDM_SLOT_MASK GENMASK(5, 3)97#define CS530X_ASP_TDM_SLOT_SHIFT 398#define CS530X_ASP_CH_REVERSE BIT(9)99#define CS530X_TDM_EN_MASK BIT(2)100#define CS530X_ASP_FMT_I2S 0101#define CS530X_ASP_FMT_LJ 1102#define CS530X_ASP_FMT_DSP_A 0x6103 104/* TDM Slots */105#define CS530X_0_1_TDM_SLOT_MASK GENMASK(1, 0)106#define CS530X_0_3_TDM_SLOT_MASK GENMASK(3, 0)107#define CS530X_0_7_TDM_SLOT_MASK GENMASK(7, 0)108#define CS530X_0_7_TDM_SLOT_VAL 0109 110#define CS530X_2_3_TDM_SLOT_MASK GENMASK(3, 2)111#define CS530X_2_3_TDM_SLOT_VAL 1112 113#define CS530X_4_5_TDM_SLOT_MASK GENMASK(5, 4)114#define CS530X_4_7_TDM_SLOT_MASK GENMASK(7, 4)115#define CS530X_4_7_TDM_SLOT_VAL 2116 117#define CS530X_6_7_TDM_SLOT_MASK GENMASK(7, 6)118#define CS530X_6_7_TDM_SLOT_VAL 3119 120#define CS530X_8_9_TDM_SLOT_MASK GENMASK(9, 8)121#define CS530X_8_11_TDM_SLOT_MASK GENMASK(11, 8)122#define CS530X_8_15_TDM_SLOT_MASK GENMASK(15, 8)123#define CS530X_8_15_TDM_SLOT_VAL 4124 125#define CS530X_10_11_TDM_SLOT_MASK GENMASK(11, 10)126#define CS530X_10_11_TDM_SLOT_VAL 5127 128#define CS530X_12_13_TDM_SLOT_MASK GENMASK(13, 12)129#define CS530X_12_15_TDM_SLOT_MASK GENMASK(15, 12)130#define CS530X_12_15_TDM_SLOT_VAL 6131 132#define CS530X_14_15_TDM_SLOT_MASK GENMASK(15, 14)133#define CS530X_14_15_TDM_SLOT_VAL 7134 135/* IN_RAMP_SUM */136#define CS530X_RAMP_RATE_INC_SHIFT 0137#define CS530X_RAMP_RATE_DEC_SHIFT 4138#define CS530X_IN_SUM_MODE_SHIFT 13139 140/* IN_FILTER */141#define CS530X_IN_FILTER_SHIFT 8142#define CS530X_IN_HPF_EN_SHIFT 12143 144/* IN_HIZ */145#define CS530X_IN12_HIZ BIT(0)146#define CS530X_IN34_HIZ BIT(1)147#define CS530X_IN56_HIZ BIT(2)148#define CS530X_IN78_HIZ BIT(3)149 150/* IN_INV */151#define CS530X_IN1_INV_SHIFT 0152#define CS530X_IN2_INV_SHIFT 1153#define CS530X_IN3_INV_SHIFT 2154#define CS530X_IN4_INV_SHIFT 3155#define CS530X_IN5_INV_SHIFT 4156#define CS530X_IN6_INV_SHIFT 5157#define CS530X_IN7_INV_SHIFT 6158#define CS530X_IN8_INV_SHIFT 7159 160/* IN_VOL_CTLy_z */161#define CS530X_IN_MUTE BIT(15)162 163/* IN_VOL_CTL5 */164#define CS530X_IN_VU BIT(0)165 166/* PAD_FN */167#define CS530X_DOUT2_FN BIT(0)168#define CS530X_DOUT3_FN BIT(1)169#define CS530X_DOUT4_FN BIT(2)170#define CS530X_SPI_CS_FN BIT(3)171#define CS530X_CONFIG2_FN BIT(6)172#define CS530X_CONFIG3_FN BIT(7)173#define CS530X_CONFIG4_FN BIT(8)174#define CS530X_CONFIG5_FN BIT(9)175 176/* PAD_LVL */177#define CS530X_CONFIG2_LVL BIT(6)178#define CS530X_CONFIG3_LVL BIT(7)179#define CS530X_CONFIG4_LVL BIT(8)180#define CS530X_CONFIG5_LVL BIT(9)181 182/* System Clock Source */183#define CS530X_SYSCLK_SRC_MCLK 0184#define CS530X_SYSCLK_SRC_PLL 1185 186/* PLL Reference Clock Source */187#define CS530X_PLL_SRC_BCLK 0188#define CS530X_PLL_SRC_MCLK 1189 190#define CS530X_NUM_SUPPLIES 2191 192enum cs530x_type {193 CS5302,194 CS5304,195 CS5308,196};197 198/* codec private data */199struct cs530x_priv {200 struct regmap *regmap;201 struct device *dev;202 struct snd_soc_dai_driver *dev_dai;203 204 enum cs530x_type devtype;205 int num_adcs;206 int num_dacs;207 208 struct regulator_bulk_data supplies[CS530X_NUM_SUPPLIES];209 210 unsigned int mclk_rate;211 212 int tdm_width;213 int tdm_slots;214 int fs;215 int adc_pairs_count;216 217 struct gpio_desc *reset_gpio;218};219 220extern const struct regmap_config cs530x_regmap;221int cs530x_probe(struct cs530x_priv *cs530x);222 223#endif224