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1/* SPDX-License-Identifier: GPL-2.0 */2/*3 * ALSA SoC CX20721/CX20723 codec driver4 *5 * Copyright: (C) 2017 Conexant Systems, Inc.6 * Author: Simon Ho, <Simon.ho@conexant.com>7 */8 9#ifndef __CX2072X_H__10#define __CX2072X_H__11 12#define CX2072X_MCLK_PLL 113#define CX2072X_MCLK_EXTERNAL_PLL 114#define CX2072X_MCLK_INTERNAL_OSC 215 16/*#define CX2072X_RATES SNDRV_PCM_RATE_8000_192000*/17#define CX2072X_RATES_DSP SNDRV_PCM_RATE_4800018 19#define CX2072X_REG_MAX 0x8a3c20 21#define CX2072X_VENDOR_ID 0x020022#define CX2072X_REVISION_ID 0x020823#define CX2072X_CURRENT_BCLK_FREQUENCY 0x00dc24#define CX2072X_AFG_POWER_STATE 0x041425#define CX2072X_UM_RESPONSE 0x042026#define CX2072X_GPIO_DATA 0x045427#define CX2072X_GPIO_ENABLE 0x045828#define CX2072X_GPIO_DIRECTION 0x045c29#define CX2072X_GPIO_WAKE 0x046030#define CX2072X_GPIO_UM_ENABLE 0x046431#define CX2072X_GPIO_STICKY_MASK 0x046832#define CX2072X_AFG_FUNCTION_RESET 0x07fc33#define CX2072X_DAC1_CONVERTER_FORMAT 0x43c834#define CX2072X_DAC1_AMP_GAIN_RIGHT 0x41c035#define CX2072X_DAC1_AMP_GAIN_LEFT 0x41e036#define CX2072X_DAC1_POWER_STATE 0x401437#define CX2072X_DAC1_CONVERTER_STREAM_CHANNEL 0x401838#define CX2072X_DAC1_EAPD_ENABLE 0x403039#define CX2072X_DAC2_CONVERTER_FORMAT 0x47c840#define CX2072X_DAC2_AMP_GAIN_RIGHT 0x45c041#define CX2072X_DAC2_AMP_GAIN_LEFT 0x45e042#define CX2072X_DAC2_POWER_STATE 0x441443#define CX2072X_DAC2_CONVERTER_STREAM_CHANNEL 0x441844#define CX2072X_ADC1_CONVERTER_FORMAT 0x4fc845#define CX2072X_ADC1_AMP_GAIN_RIGHT_0 0x4d8046#define CX2072X_ADC1_AMP_GAIN_LEFT_0 0x4da047#define CX2072X_ADC1_AMP_GAIN_RIGHT_1 0x4d8448#define CX2072X_ADC1_AMP_GAIN_LEFT_1 0x4da449#define CX2072X_ADC1_AMP_GAIN_RIGHT_2 0x4d8850#define CX2072X_ADC1_AMP_GAIN_LEFT_2 0x4da851#define CX2072X_ADC1_AMP_GAIN_RIGHT_3 0x4d8c52#define CX2072X_ADC1_AMP_GAIN_LEFT_3 0x4dac53#define CX2072X_ADC1_AMP_GAIN_RIGHT_4 0x4d9054#define CX2072X_ADC1_AMP_GAIN_LEFT_4 0x4db055#define CX2072X_ADC1_AMP_GAIN_RIGHT_5 0x4d9456#define CX2072X_ADC1_AMP_GAIN_LEFT_5 0x4db457#define CX2072X_ADC1_AMP_GAIN_RIGHT_6 0x4d9858#define CX2072X_ADC1_AMP_GAIN_LEFT_6 0x4db859#define CX2072X_ADC1_CONNECTION_SELECT_CONTROL 0x4c0460#define CX2072X_ADC1_POWER_STATE 0x4c1461#define CX2072X_ADC1_CONVERTER_STREAM_CHANNEL 0x4c1862#define CX2072X_ADC2_CONVERTER_FORMAT 0x53c863#define CX2072X_ADC2_AMP_GAIN_RIGHT_0 0x518064#define CX2072X_ADC2_AMP_GAIN_LEFT_0 0x51a065#define CX2072X_ADC2_AMP_GAIN_RIGHT_1 0x518466#define CX2072X_ADC2_AMP_GAIN_LEFT_1 0x51a467#define CX2072X_ADC2_AMP_GAIN_RIGHT_2 0x518868#define CX2072X_ADC2_AMP_GAIN_LEFT_2 0x51a869#define CX2072X_ADC2_CONNECTION_SELECT_CONTROL 0x500470#define CX2072X_ADC2_POWER_STATE 0x501471#define CX2072X_ADC2_CONVERTER_STREAM_CHANNEL 0x501872#define CX2072X_PORTA_CONNECTION_SELECT_CTRL 0x580473#define CX2072X_PORTA_POWER_STATE 0x581474#define CX2072X_PORTA_PIN_CTRL 0x581c75#define CX2072X_PORTA_UNSOLICITED_RESPONSE 0x582076#define CX2072X_PORTA_PIN_SENSE 0x582477#define CX2072X_PORTA_EAPD_BTL 0x583078#define CX2072X_PORTB_POWER_STATE 0x601479#define CX2072X_PORTB_PIN_CTRL 0x601c80#define CX2072X_PORTB_UNSOLICITED_RESPONSE 0x602081#define CX2072X_PORTB_PIN_SENSE 0x602482#define CX2072X_PORTB_EAPD_BTL 0x603083#define CX2072X_PORTB_GAIN_RIGHT 0x618084#define CX2072X_PORTB_GAIN_LEFT 0x61a085#define CX2072X_PORTC_POWER_STATE 0x681486#define CX2072X_PORTC_PIN_CTRL 0x681c87#define CX2072X_PORTC_GAIN_RIGHT 0x698088#define CX2072X_PORTC_GAIN_LEFT 0x69a089#define CX2072X_PORTD_POWER_STATE 0x641490#define CX2072X_PORTD_PIN_CTRL 0x641c91#define CX2072X_PORTD_UNSOLICITED_RESPONSE 0x642092#define CX2072X_PORTD_PIN_SENSE 0x642493#define CX2072X_PORTD_GAIN_RIGHT 0x658094#define CX2072X_PORTD_GAIN_LEFT 0x65a095#define CX2072X_PORTE_CONNECTION_SELECT_CTRL 0x740496#define CX2072X_PORTE_POWER_STATE 0x741497#define CX2072X_PORTE_PIN_CTRL 0x741c98#define CX2072X_PORTE_UNSOLICITED_RESPONSE 0x742099#define CX2072X_PORTE_PIN_SENSE 0x7424100#define CX2072X_PORTE_EAPD_BTL 0x7430101#define CX2072X_PORTE_GAIN_RIGHT 0x7580102#define CX2072X_PORTE_GAIN_LEFT 0x75a0103#define CX2072X_PORTF_POWER_STATE 0x7814104#define CX2072X_PORTF_PIN_CTRL 0x781c105#define CX2072X_PORTF_UNSOLICITED_RESPONSE 0x7820106#define CX2072X_PORTF_PIN_SENSE 0x7824107#define CX2072X_PORTF_GAIN_RIGHT 0x7980108#define CX2072X_PORTF_GAIN_LEFT 0x79a0109#define CX2072X_PORTG_POWER_STATE 0x5c14110#define CX2072X_PORTG_PIN_CTRL 0x5c1c111#define CX2072X_PORTG_CONNECTION_SELECT_CTRL 0x5c04112#define CX2072X_PORTG_EAPD_BTL 0x5c30113#define CX2072X_PORTM_POWER_STATE 0x8814114#define CX2072X_PORTM_PIN_CTRL 0x881c115#define CX2072X_PORTM_CONNECTION_SELECT_CTRL 0x8804116#define CX2072X_PORTM_EAPD_BTL 0x8830117#define CX2072X_MIXER_POWER_STATE 0x5414118#define CX2072X_MIXER_GAIN_RIGHT_0 0x5580119#define CX2072X_MIXER_GAIN_LEFT_0 0x55a0120#define CX2072X_MIXER_GAIN_RIGHT_1 0x5584121#define CX2072X_MIXER_GAIN_LEFT_1 0x55a4122#define CX2072X_EQ_ENABLE_BYPASS 0x6d00123#define CX2072X_EQ_B0_COEFF 0x6d02124#define CX2072X_EQ_B1_COEFF 0x6d04125#define CX2072X_EQ_B2_COEFF 0x6d06126#define CX2072X_EQ_A1_COEFF 0x6d08127#define CX2072X_EQ_A2_COEFF 0x6d0a128#define CX2072X_EQ_G_COEFF 0x6d0c129#define CX2072X_EQ_BAND 0x6d0d130#define CX2072X_SPKR_DRC_ENABLE_STEP 0x6d10131#define CX2072X_SPKR_DRC_CONTROL 0x6d14132#define CX2072X_SPKR_DRC_TEST 0x6d18133#define CX2072X_DIGITAL_BIOS_TEST0 0x6d80134#define CX2072X_DIGITAL_BIOS_TEST2 0x6d84135#define CX2072X_I2SPCM_CONTROL1 0x6e00136#define CX2072X_I2SPCM_CONTROL2 0x6e04137#define CX2072X_I2SPCM_CONTROL3 0x6e08138#define CX2072X_I2SPCM_CONTROL4 0x6e0c139#define CX2072X_I2SPCM_CONTROL5 0x6e10140#define CX2072X_I2SPCM_CONTROL6 0x6e18141#define CX2072X_UM_INTERRUPT_CRTL_E 0x6e14142#define CX2072X_CODEC_TEST2 0x7108143#define CX2072X_CODEC_TEST9 0x7124144#define CX2072X_CODEC_TESTXX 0x7290145#define CX2072X_CODEC_TEST20 0x7310146#define CX2072X_CODEC_TEST24 0x731c147#define CX2072X_CODEC_TEST26 0x7328148#define CX2072X_ANALOG_TEST3 0x718c149#define CX2072X_ANALOG_TEST4 0x7190150#define CX2072X_ANALOG_TEST5 0x7194151#define CX2072X_ANALOG_TEST6 0x7198152#define CX2072X_ANALOG_TEST7 0x719c153#define CX2072X_ANALOG_TEST8 0x71a0154#define CX2072X_ANALOG_TEST9 0x71a4155#define CX2072X_ANALOG_TEST10 0x71a8156#define CX2072X_ANALOG_TEST11 0x71ac157#define CX2072X_ANALOG_TEST12 0x71b0158#define CX2072X_ANALOG_TEST13 0x71b4159#define CX2072X_DIGITAL_TEST0 0x7200160#define CX2072X_DIGITAL_TEST1 0x7204161#define CX2072X_DIGITAL_TEST11 0x722c162#define CX2072X_DIGITAL_TEST12 0x7230163#define CX2072X_DIGITAL_TEST15 0x723c164#define CX2072X_DIGITAL_TEST16 0x7080165#define CX2072X_DIGITAL_TEST17 0x7084166#define CX2072X_DIGITAL_TEST18 0x7088167#define CX2072X_DIGITAL_TEST19 0x708c168#define CX2072X_DIGITAL_TEST20 0x7090169 170/* not used in the current code, for future extensions (if any) */171#define CX2072X_MAX_EQ_BAND 7172#define CX2072X_MAX_EQ_COEFF 11173#define CX2072X_MAX_DRC_REGS 9174#define CX2072X_MIC_EQ_COEFF 10175#define CX2072X_PLBK_EQ_BAND_NUM 7176#define CX2072X_PLBK_EQ_COEF_LEN 11177#define CX2072X_PLBK_DRC_PARM_LEN 9178#define CX2072X_CLASSD_AMP_LEN 6179 180/* DAI interface type */181#define CX2072X_DAI_HIFI 1182#define CX2072X_DAI_DSP 2183#define CX2072X_DAI_DSP_PWM 3 /* 4 ch, including mic and AEC */184 185enum cx2072x_reg_sample_size {186 CX2072X_SAMPLE_SIZE_8_BITS = 0,187 CX2072X_SAMPLE_SIZE_16_BITS = 1,188 CX2072X_SAMPLE_SIZE_24_BITS = 2,189 CX2072X_SAMPLE_SIZE_RESERVED = 3,190};191 192union cx2072x_reg_i2spcm_ctrl_reg1 {193 struct {194 u32 rx_data_one_line:1;195 u32 rx_ws_pol:1;196 u32 rx_ws_wid:7;197 u32 rx_frm_len:5;198 u32 rx_sa_size:2;199 u32 tx_data_one_line:1;200 u32 tx_ws_pol:1;201 u32 tx_ws_wid:7;202 u32 tx_frm_len:5;203 u32 tx_sa_size:2;204 } r;205 u32 ulval;206};207 208union cx2072x_reg_i2spcm_ctrl_reg2 {209 struct {210 u32 tx_en_ch1:1;211 u32 tx_en_ch2:1;212 u32 tx_en_ch3:1;213 u32 tx_en_ch4:1;214 u32 tx_en_ch5:1;215 u32 tx_en_ch6:1;216 u32 tx_slot_1:5;217 u32 tx_slot_2:5;218 u32 tx_slot_3:5;219 u32 tx_slot_4:5;220 u32 res:1;221 u32 tx_data_neg_bclk:1;222 u32 tx_master:1;223 u32 tx_tri_n:1;224 u32 tx_endian_sel:1;225 u32 tx_dstart_dly:1;226 } r;227 u32 ulval;228};229 230union cx2072x_reg_i2spcm_ctrl_reg3 {231 struct {232 u32 rx_en_ch1:1;233 u32 rx_en_ch2:1;234 u32 rx_en_ch3:1;235 u32 rx_en_ch4:1;236 u32 rx_en_ch5:1;237 u32 rx_en_ch6:1;238 u32 rx_slot_1:5;239 u32 rx_slot_2:5;240 u32 rx_slot_3:5;241 u32 rx_slot_4:5;242 u32 res:1;243 u32 rx_data_neg_bclk:1;244 u32 rx_master:1;245 u32 rx_tri_n:1;246 u32 rx_endian_sel:1;247 u32 rx_dstart_dly:1;248 } r;249 u32 ulval;250};251 252union cx2072x_reg_i2spcm_ctrl_reg4 {253 struct {254 u32 rx_mute:1;255 u32 tx_mute:1;256 u32 reserved:1;257 u32 dac_34_independent:1;258 u32 dac_bclk_lrck_share:1;259 u32 bclk_lrck_share_en:1;260 u32 reserved2:2;261 u32 rx_last_dac_ch_en:1;262 u32 rx_last_dac_ch:3;263 u32 tx_last_adc_ch_en:1;264 u32 tx_last_adc_ch:3;265 u32 rx_slot_5:5;266 u32 rx_slot_6:5;267 u32 reserved3:6;268 } r;269 u32 ulval;270};271 272union cx2072x_reg_i2spcm_ctrl_reg5 {273 struct {274 u32 tx_slot_5:5;275 u32 reserved:3;276 u32 tx_slot_6:5;277 u32 reserved2:3;278 u32 reserved3:8;279 u32 i2s_pcm_clk_div:7;280 u32 i2s_pcm_clk_div_chan_en:1;281 } r;282 u32 ulval;283};284 285union cx2072x_reg_i2spcm_ctrl_reg6 {286 struct {287 u32 reserved:5;288 u32 rx_pause_cycles:3;289 u32 rx_pause_start_pos:8;290 u32 reserved2:5;291 u32 tx_pause_cycles:3;292 u32 tx_pause_start_pos:8;293 } r;294 u32 ulval;295};296 297union cx2072x_reg_digital_bios_test2 {298 struct {299 u32 pull_down_eapd:2;300 u32 input_en_eapd_pad:1;301 u32 push_pull_mode:1;302 u32 eapd_pad_output_driver:2;303 u32 pll_source:1;304 u32 i2s_bclk_en:1;305 u32 i2s_bclk_invert:1;306 u32 pll_ref_clock:1;307 u32 class_d_shield_clk:1;308 u32 audio_pll_bypass_mode:1;309 u32 reserved:4;310 } r;311 u32 ulval;312};313 314#endif /* __CX2072X_H__ */315