163 lines · c
1/* SPDX-License-Identifier: GPL-2.0-only */2/*3 * es8311.c -- es8311 ALSA SoC audio driver4 *5 * Copyright (C) 2024 Matteo Martelli <matteomartelli3@gmail.com>6 *7 * Author: Matteo Martelli <matteomartelli3@gmail.com>8 */9 10#ifndef _ES8311_H11#define _ES8311_H12 13#include <linux/bitops.h>14 15#define ES8311_RESET 0x0016#define ES8311_RESET_CSM_ON BIT(7)17#define ES8311_RESET_MSC BIT(6)18#define ES8311_RESET_RST_MASK GENMASK(4, 0)19 20/* Clock Manager Registers */21#define ES8311_CLKMGR1 0x0122#define ES8311_CLKMGR1_MCLK_SEL BIT(7)23#define ES8311_CLKMGR1_MCLK_ON BIT(5)24#define ES8311_CLKMGR1_BCLK_ON BIT(4)25#define ES8311_CLKMGR1_CLKADC_ON_SHIFT 326#define ES8311_CLKMGR1_CLKDAC_ON_SHIFT 227#define ES8311_CLKMGR1_ANACLKADC_ON_SHIFT 128#define ES8311_CLKMGR1_ANACLKDAC_ON_SHIFT 029#define ES8311_CLKMGR2 0x0230#define ES8311_CLKMGR2_DIV_PRE_MASK GENMASK(7, 5)31#define ES8311_CLKMGR2_DIV_PRE_SHIFT 532#define ES8311_CLKMGR2_DIV_PRE_MAX 0x0733#define ES8311_CLKMGR2_MULT_PRE_MASK GENMASK(4, 3)34#define ES8311_CLKMGR2_MULT_PRE_SHIFT 335#define ES8311_CLKMGR3 0x0336#define ES8311_CLKMGR4 0x0437#define ES8311_CLKMGR5 0x0538#define ES8311_CLKMGR5_ADC_DIV_MASK GENMASK(7, 4)39#define ES8311_CLKMGR5_ADC_DIV_SHIFT 440#define ES8311_CLKMGR5_DAC_DIV_MASK GENMASK(3, 0)41#define ES8311_CLKMGR5_DAC_DIV_SHIFT 042#define ES8311_CLKMGR6 0x0643#define ES8311_CLKMGR6_BCLK_INV BIT(5)44#define ES8311_CLKMGR6_DIV_BCLK_MASK GENMASK(4, 0)45#define ES8311_CLKMGR7 0x0746#define ES8311_CLKMGR7_LRCLK_DIV_H_MASK GENMASK(3, 0)47#define ES8311_CLKMGR8 0x0848#define ES8311_CLKMGR_LRCLK_DIV_MAX 0x0FFF49 50/* SDP Mode Registers */51#define ES8311_SDP_IN 0x0952#define ES8311_SDP_IN_SEL_SHIFT 753#define ES8311_SDP_OUT 0x0A54/* Following values are the same for both SPD_IN and SDP_OUT */55#define ES8311_SDP_MUTE_SHIFT 656#define ES8311_SDP_LRP BIT(5)57#define ES8311_SDP_WL_MASK GENMASK(4, 2)58#define ES8311_SDP_WL_SHIFT 259#define ES8311_SDP_WL_24 0x0060#define ES8311_SDP_WL_20 0x0161#define ES8311_SDP_WL_18 0x0262#define ES8311_SDP_WL_16 0x0363#define ES8311_SDP_WL_32 0x0464#define ES8311_SDP_FMT_MASK GENMASK(1, 0)65#define ES8311_SDP_FMT_I2S 0x0066#define ES8311_SDP_FMT_LEFT_J 0x0167#define ES8311_SDP_FMT_DSP 0x0368 69/* System registers */70#define ES8311_SYS1 0x0B71#define ES8311_SYS2 0x0C72#define ES8311_SYS3 0x0D73#define ES8311_SYS3_PDN_ANA_SHIFT 774#define ES8311_SYS3_PDN_IBIASGEN_SHIFT 675#define ES8311_SYS3_PDN_ADCBIASGEN_SHIFT 576#define ES8311_SYS3_PDN_ADCVREFGEN_SHIFT 477#define ES8311_SYS3_PDN_DACVREFGEN_SHIFT 378#define ES8311_SYS3_PDN_VREF_SHIFT 279#define ES8311_SYS3_PDN_VMIDSEL_MASK GENMASK(1, 0)80#define ES8311_SYS3_PDN_VMIDSEL_POWER_DOWN 081#define ES8311_SYS3_PDN_VMIDSEL_STARTUP_NORMAL_SPEED 182#define ES8311_SYS3_PDN_VMIDSEL_NORMAL_OPERATION 283#define ES8311_SYS3_PDN_VMIDSEL_STARTUP_FAST_SPEED 384#define ES8311_SYS4 0x0E85#define ES8311_SYS4_PDN_PGA_SHIFT 686#define ES8311_SYS4_PDN_MOD_SHIFT 587#define ES8311_SYS5 0x0F88#define ES8311_SYS6 0x1089#define ES8311_SYS7 0x1190#define ES8311_SYS8 0x1291#define ES8311_SYS8_PDN_DAC_SHIFT 192#define ES8311_SYS9 0x1393#define ES8311_SYS9_HPSW_SHIFT 494#define ES8311_SYS10 0x1495#define ES8311_SYS10_DMIC_ON_SHIFT 696#define ES8311_SYS10_LINESEL_SHIFT 497#define ES8311_SYS10_PGAGAIN_SHIFT 098#define ES8311_SYS10_PGAGAIN_MAX 0x0A99 100/* ADC Registers*/101#define ES8311_ADC1 0x15102#define ES8311_ADC1_RAMPRATE_SHIFT 4103#define ES8311_ADC2 0x16104#define ES8311_ADC2_INV_SHIFT 4105#define ES8311_ADC2_SCALE_SHIFT 0106#define ES8311_ADC2_SCALE_MAX 0x07107#define ES8311_ADC3 0x17108#define ES8311_ADC3_VOLUME_SHIFT 0109#define ES8311_ADC3_VOLUME_MAX 0xFF110#define ES8311_ADC4 0x18111#define ES8311_ADC4_ALC_EN_SHIFT 7112#define ES8311_ADC4_AUTOMUTE_EN_SHIFT 6113#define ES8311_ADC4_ALC_WINSIZE_SHIFT 0114#define ES8311_ADC5 0x19115#define ES8311_ADC5_ALC_MAXLEVEL_SHIFT 4116#define ES8311_ADC5_ALC_MAXLEVEL_MAX 0x0F117#define ES8311_ADC5_ALC_MINLEVEL_SHIFT 0118#define ES8311_ADC5_ALC_MINLEVEL_MAX 0x0F119#define ES8311_ADC6 0x1A120#define ES8311_ADC6_AUTOMUTE_WS_SHIFT 4121#define ES8311_ADC6_AUTOMUTE_NG_SHIFT 0122#define ES8311_ADC6_AUTOMUTE_NG_MAX 0x0F123 124#define ES8311_ADC7 0x1B125#define ES8311_ADC7_AUTOMUTE_VOL_SHIFT 5126#define ES8311_ADC7_AUTOMUTE_VOL_MAX 0x07127#define ES8311_ADC8 0x1C128#define ES8311_ADC8_EQBYPASS_SHIFT 6129#define ES8311_ADC8_HPF_SHIFT 5130 131/* DAC Registers */132#define ES8311_DAC1 0x31133#define ES8311_DAC1_DAC_DSMMUTE BIT(6)134#define ES8311_DAC1_DAC_DEMMUTE BIT(5)135#define ES8311_DAC2 0x32136#define ES8311_DAC2_VOLUME_MAX 0xFF137#define ES8311_DAC3 0x33138#define ES8311_DAC4 0x34139#define ES8311_DAC4_DRC_EN_SHIFT 7140#define ES8311_DAC4_DRC_WINSIZE_SHIFT 0141#define ES8311_DAC5 0x35142#define ES8311_DAC5_DRC_MAXLEVEL_SHIFT 4143#define ES8311_DAC5_DRC_MAXLEVEL_MAX 0x0F144#define ES8311_DAC5_DRC_MINLEVEL_SHIFT 0145#define ES8311_DAC5_DRC_MINLEVEL_MAX 0x0F146#define ES8311_DAC6 0x37147#define ES8311_DAC6_RAMPRATE_SHIFT 4148#define ES8311_DAC6_EQBYPASS_SHIFT 3149 150/* GPIO Registers */151#define ES8311_GPIO 0x44152#define ES8311_GPIO_ADC2DAC_SEL_SHIFT 7153#define ES8311_GPIO_ADCDAT_SEL_SHIFT 4154 155/* Chip Info Registers */156#define ES8311_CHIPID1 0xFD /* 0x83 */157#define ES8311_CHIPID2 0xFE /* 0x11 */158#define ES8311_CHIPVER 0xFF159 160#define ES8311_REG_MAX 0xFF161 162#endif163