377 lines · c
1/* SPDX-License-Identifier: GPL-2.0-only */2/*3 * lm49453.h - LM49453 ALSA Soc Audio drive4 *5 * Copyright (c) 2012 Texas Instruments, Inc6 */7 8#ifndef _LM49453_H9#define _LM49453_H10 11#include <linux/bitops.h>12 13/* LM49453_P0 register space for page0 */14#define LM49453_P0_PMC_SETUP_REG 0x0015#define LM49453_P0_PLL_CLK_SEL1_REG 0x0116#define LM49453_P0_PLL_CLK_SEL2_REG 0x0217#define LM49453_P0_PMC_CLK_DIV_REG 0x0318#define LM49453_P0_HSDET_CLK_DIV_REG 0x0419#define LM49453_P0_DMIC_CLK_DIV_REG 0x0520#define LM49453_P0_ADC_CLK_DIV_REG 0x0621#define LM49453_P0_DAC_OT_CLK_DIV_REG 0x0722#define LM49453_P0_PLL_HF_M_REG 0x0823#define LM49453_P0_PLL_LF_M_REG 0x0924#define LM49453_P0_PLL_NL_REG 0x0A25#define LM49453_P0_PLL_N_MODL_REG 0x0B26#define LM49453_P0_PLL_N_MODH_REG 0x0C27#define LM49453_P0_PLL_P1_REG 0x0D28#define LM49453_P0_PLL_P2_REG 0x0E29#define LM49453_P0_FLL_REF_FREQL_REG 0x0F30#define LM49453_P0_FLL_REF_FREQH_REG 0x1031#define LM49453_P0_VCO_TARGETLL_REG 0x1132#define LM49453_P0_VCO_TARGETLH_REG 0x1233#define LM49453_P0_VCO_TARGETHL_REG 0x1334#define LM49453_P0_VCO_TARGETHH_REG 0x1435#define LM49453_P0_PLL_CONFIG_REG 0x1536#define LM49453_P0_DAC_CLK_SEL_REG 0x1637#define LM49453_P0_DAC_HP_CLK_DIV_REG 0x1738 39/* Analog Mixer Input Stages */40#define LM49453_P0_MICL_REG 0x2041#define LM49453_P0_MICR_REG 0x2142#define LM49453_P0_EP_REG 0x2443#define LM49453_P0_DIS_PKVL_FB_REG 0x2544 45/* Analog Mixer Output Stages */46#define LM49453_P0_ANALOG_MIXER_ADC_REG 0x2E47 48/*ADC or DAC */49#define LM49453_P0_ADC_DSP_REG 0x3050#define LM49453_P0_DAC_DSP_REG 0x3151 52/* EFFECTS ENABLES */53#define LM49453_P0_ADC_FX_ENABLES_REG 0x3354 55/* GPIO */56#define LM49453_P0_GPIO1_REG 0x3857#define LM49453_P0_GPIO2_REG 0x3958#define LM49453_P0_GPIO3_REG 0x3A59#define LM49453_P0_HAP_CTL_REG 0x3B60#define LM49453_P0_HAP_FREQ_PROG_LEFTL_REG 0x3C61#define LM49453_P0_HAP_FREQ_PROG_LEFTH_REG 0x3D62#define LM49453_P0_HAP_FREQ_PROG_RIGHTL_REG 0x3E63#define LM49453_P0_HAP_FREQ_PROG_RIGHTH_REG 0x3F64 65/* DIGITAL MIXER */66#define LM49453_P0_DMIX_CLK_SEL_REG 0x4067#define LM49453_P0_PORT1_RX_LVL1_REG 0x4168#define LM49453_P0_PORT1_RX_LVL2_REG 0x4269#define LM49453_P0_PORT2_RX_LVL_REG 0x4370#define LM49453_P0_PORT1_TX1_REG 0x4471#define LM49453_P0_PORT1_TX2_REG 0x4572#define LM49453_P0_PORT1_TX3_REG 0x4673#define LM49453_P0_PORT1_TX4_REG 0x4774#define LM49453_P0_PORT1_TX5_REG 0x4875#define LM49453_P0_PORT1_TX6_REG 0x4976#define LM49453_P0_PORT1_TX7_REG 0x4A77#define LM49453_P0_PORT1_TX8_REG 0x4B78#define LM49453_P0_PORT2_TX1_REG 0x4C79#define LM49453_P0_PORT2_TX2_REG 0x4D80#define LM49453_P0_STN_SEL_REG 0x4F81#define LM49453_P0_DACHPL1_REG 0x5082#define LM49453_P0_DACHPL2_REG 0x5183#define LM49453_P0_DACHPR1_REG 0x5284#define LM49453_P0_DACHPR2_REG 0x5385#define LM49453_P0_DACLOL1_REG 0x5486#define LM49453_P0_DACLOL2_REG 0x5587#define LM49453_P0_DACLOR1_REG 0x5688#define LM49453_P0_DACLOR2_REG 0x5789#define LM49453_P0_DACLSL1_REG 0x5890#define LM49453_P0_DACLSL2_REG 0x5991#define LM49453_P0_DACLSR1_REG 0x5A92#define LM49453_P0_DACLSR2_REG 0x5B93#define LM49453_P0_DACHAL1_REG 0x5C94#define LM49453_P0_DACHAL2_REG 0x5D95#define LM49453_P0_DACHAR1_REG 0x5E96#define LM49453_P0_DACHAR2_REG 0x5F97 98/* AUDIO PORT 1 (TDM) */99#define LM49453_P0_AUDIO_PORT1_BASIC_REG 0x60100#define LM49453_P0_AUDIO_PORT1_CLK_GEN1_REG 0x61101#define LM49453_P0_AUDIO_PORT1_CLK_GEN2_REG 0x62102#define LM49453_P0_AUDIO_PORT1_CLK_GEN3_REG 0x63103#define LM49453_P0_AUDIO_PORT1_SYNC_RATE_REG 0x64104#define LM49453_P0_AUDIO_PORT1_SYNC_SDO_SETUP_REG 0x65105#define LM49453_P0_AUDIO_PORT1_DATA_WIDTH_REG 0x66106#define LM49453_P0_AUDIO_PORT1_RX_MSB_REG 0x67107#define LM49453_P0_AUDIO_PORT1_TX_MSB_REG 0x68108#define LM49453_P0_AUDIO_PORT1_TDM_CHANNELS_REG 0x69109 110/* AUDIO PORT 2 */111#define LM49453_P0_AUDIO_PORT2_BASIC_REG 0x6A112#define LM49453_P0_AUDIO_PORT2_CLK_GEN1_REG 0x6B113#define LM49453_P0_AUDIO_PORT2_CLK_GEN2_REG 0x6C114#define LM49453_P0_AUDIO_PORT2_SYNC_GEN_REG 0x6D115#define LM49453_P0_AUDIO_PORT2_DATA_WIDTH_REG 0x6E116#define LM49453_P0_AUDIO_PORT2_RX_MODE_REG 0x6F117#define LM49453_P0_AUDIO_PORT2_TX_MODE_REG 0x70118 119/* SAMPLE RATE */120#define LM49453_P0_PORT1_SR_LSB_REG 0x79121#define LM49453_P0_PORT1_SR_MSB_REG 0x7A122#define LM49453_P0_PORT2_SR_LSB_REG 0x7B123#define LM49453_P0_PORT2_SR_MSB_REG 0x7C124 125/* EFFECTS - HPFs */126#define LM49453_P0_HPF_REG 0x80127 128/* EFFECTS ADC ALC */129#define LM49453_P0_ADC_ALC1_REG 0x82130#define LM49453_P0_ADC_ALC2_REG 0x83131#define LM49453_P0_ADC_ALC3_REG 0x84132#define LM49453_P0_ADC_ALC4_REG 0x85133#define LM49453_P0_ADC_ALC5_REG 0x86134#define LM49453_P0_ADC_ALC6_REG 0x87135#define LM49453_P0_ADC_ALC7_REG 0x88136#define LM49453_P0_ADC_ALC8_REG 0x89137#define LM49453_P0_DMIC1_LEVELL_REG 0x8A138#define LM49453_P0_DMIC1_LEVELR_REG 0x8B139#define LM49453_P0_DMIC2_LEVELL_REG 0x8C140#define LM49453_P0_DMIC2_LEVELR_REG 0x8D141#define LM49453_P0_ADC_LEVELL_REG 0x8E142#define LM49453_P0_ADC_LEVELR_REG 0x8F143#define LM49453_P0_DAC_HP_LEVELL_REG 0x90144#define LM49453_P0_DAC_HP_LEVELR_REG 0x91145#define LM49453_P0_DAC_LO_LEVELL_REG 0x92146#define LM49453_P0_DAC_LO_LEVELR_REG 0x93147#define LM49453_P0_DAC_LS_LEVELL_REG 0x94148#define LM49453_P0_DAC_LS_LEVELR_REG 0x95149#define LM49453_P0_DAC_HA_LEVELL_REG 0x96150#define LM49453_P0_DAC_HA_LEVELR_REG 0x97151#define LM49453_P0_SOFT_MUTE_REG 0x98152#define LM49453_P0_DMIC_MUTE_CFG_REG 0x99153#define LM49453_P0_ADC_MUTE_CFG_REG 0x9A154#define LM49453_P0_DAC_MUTE_CFG_REG 0x9B155 156/*DIGITAL MIC1 */157#define LM49453_P0_DIGITAL_MIC1_CONFIG_REG 0xB0158#define LM49453_P0_DIGITAL_MIC1_DATA_DELAYL_REG 0xB1159#define LM49453_P0_DIGITAL_MIC1_DATA_DELAYR_REG 0xB2160 161/*DIGITAL MIC2 */162#define LM49453_P0_DIGITAL_MIC2_CONFIG_REG 0xB3163#define LM49453_P0_DIGITAL_MIC2_DATA_DELAYL_REG 0xB4164#define LM49453_P0_DIGITAL_MIC2_DATA_DELAYR_REG 0xB5165 166/* ADC DECIMATOR */167#define LM49453_P0_ADC_DECIMATOR_REG 0xB6168 169/* DAC CONFIGURE */170#define LM49453_P0_DAC_CONFIG_REG 0xB7171 172/* SIDETONE */173#define LM49453_P0_STN_VOL_ADCL_REG 0xB8174#define LM49453_P0_STN_VOL_ADCR_REG 0xB9175#define LM49453_P0_STN_VOL_DMIC1L_REG 0xBA176#define LM49453_P0_STN_VOL_DMIC1R_REG 0xBB177#define LM49453_P0_STN_VOL_DMIC2L_REG 0xBC178#define LM49453_P0_STN_VOL_DMIC2R_REG 0xBD179 180/* ADC/DAC CLIPPING MONITORS (Read Only/Write to Clear) */181#define LM49453_P0_ADC_DEC_CLIP_REG 0xC2182#define LM49453_P0_ADC_HPF_CLIP_REG 0xC3183#define LM49453_P0_ADC_LVL_CLIP_REG 0xC4184#define LM49453_P0_DAC_LVL_CLIP_REG 0xC5185 186/* ADC ALC EFFECT MONITORS (Read Only) */187#define LM49453_P0_ADC_LVLMONL_REG 0xC8188#define LM49453_P0_ADC_LVLMONR_REG 0xC9189#define LM49453_P0_ADC_ALCMONL_REG 0xCA190#define LM49453_P0_ADC_ALCMONR_REG 0xCB191#define LM49453_P0_ADC_MUTED_REG 0xCC192#define LM49453_P0_DAC_MUTED_REG 0xCD193 194/* HEADSET DETECT */195#define LM49453_P0_HSD_PPB_LONG_CNT_LIMITL_REG 0xD0196#define LM49453_P0_HSD_PPB_LONG_CNT_LIMITR_REG 0xD1197#define LM49453_P0_HSD_PIN3_4_EX_LOOP_CNT_LIMITL_REG 0xD2198#define LM49453_P0_HSD_PIN3_4_EX_LOOP_CNT_LIMITH_REG 0xD3199#define LM49453_P0_HSD_TIMEOUT1_REG 0xD4200#define LM49453_P0_HSD_TIMEOUT2_REG 0xD5201#define LM49453_P0_HSD_TIMEOUT3_REG 0xD6202#define LM49453_P0_HSD_PIN3_4_CFG_REG 0xD7203#define LM49453_P0_HSD_IRQ1_REG 0xD8204#define LM49453_P0_HSD_IRQ2_REG 0xD9205#define LM49453_P0_HSD_IRQ3_REG 0xDA206#define LM49453_P0_HSD_IRQ4_REG 0xDB207#define LM49453_P0_HSD_IRQ_MASK1_REG 0xDC208#define LM49453_P0_HSD_IRQ_MASK2_REG 0xDD209#define LM49453_P0_HSD_IRQ_MASK3_REG 0xDE210#define LM49453_P0_HSD_R_HPLL_REG 0xE0211#define LM49453_P0_HSD_R_HPLH_REG 0xE1212#define LM49453_P0_HSD_R_HPLU_REG 0xE2213#define LM49453_P0_HSD_R_HPRL_REG 0xE3214#define LM49453_P0_HSD_R_HPRH_REG 0xE4215#define LM49453_P0_HSD_R_HPRU_REG 0xE5216#define LM49453_P0_HSD_VEL_L_FINALL_REG 0xE6217#define LM49453_P0_HSD_VEL_L_FINALH_REG 0xE7218#define LM49453_P0_HSD_VEL_L_FINALU_REG 0xE8219#define LM49453_P0_HSD_RO_FINALL_REG 0xE9220#define LM49453_P0_HSD_RO_FINALH_REG 0xEA221#define LM49453_P0_HSD_RO_FINALU_REG 0xEB222#define LM49453_P0_HSD_VMIC_BIAS_FINALL_REG 0xEC223#define LM49453_P0_HSD_VMIC_BIAS_FINALH_REG 0xED224#define LM49453_P0_HSD_VMIC_BIAS_FINALU_REG 0xEE225#define LM49453_P0_HSD_PIN_CONFIG_REG 0xEF226#define LM49453_P0_HSD_PLUG_DETECT_BB_IRQ_STATUS1_REG 0xF1227#define LM49453_P0_HSD_PLUG_DETECT_BB_IRQ_STATUS2_REG 0xF2228#define LM49453_P0_HSD_PLUG_DETECT_BB_IRQ_STATUS3_REG 0xF3229#define LM49453_P0_HSD_PLUG_DETECT_BB_IRQ_STATEL_REG 0xF4230#define LM49453_P0_HSD_PLUG_DETECT_BB_IRQ_STATEH_REG 0xF5231 232/* I/O PULLDOWN CONFIG */233#define LM49453_P0_PULL_CONFIG1_REG 0xF8234#define LM49453_P0_PULL_CONFIG2_REG 0xF9235#define LM49453_P0_PULL_CONFIG3_REG 0xFA236 237/* RESET */238#define LM49453_P0_RESET_REG 0xFE239 240/* PAGE */241#define LM49453_PAGE_REG 0xFF242 243#define LM49453_MAX_REGISTER (0xFF+1)244 245/* LM49453_P0_PMC_SETUP_REG (0x00h) */246#define LM49453_PMC_SETUP_CHIP_EN (BIT(1)|BIT(0))247#define LM49453_PMC_SETUP_PLL_EN BIT(2)248#define LM49453_PMC_SETUP_PLL_P2_EN BIT(3)249#define LM49453_PMC_SETUP_PLL_FLL BIT(4)250#define LM49453_PMC_SETUP_MCLK_OVER BIT(5)251#define LM49453_PMC_SETUP_RTC_CLK_OVER BIT(6)252#define LM49453_PMC_SETUP_CHIP_ACTIVE BIT(7)253 254/* Chip Enable bits */255#define LM49453_CHIP_EN_SHUTDOWN 0x00256#define LM49453_CHIP_EN 0x01257#define LM49453_CHIP_EN_HSD_DETECT 0x02258#define LM49453_CHIP_EN_INVALID_HSD 0x03259 260/* LM49453_P0_PLL_CLK_SEL1_REG (0x01h) */261#define LM49453_CLK_SEL1_MCLK_SEL 0x11262#define LM49453_CLK_SEL1_RTC_SEL 0x11263#define LM49453_CLK_SEL1_PORT1_SEL 0x10264#define LM49453_CLK_SEL1_PORT2_SEL 0x11265 266/* LM49453_P0_PLL_CLK_SEL2_REG (0x02h) */267#define LM49453_CLK_SEL2_ADC_CLK_SEL 0x38268 269/* LM49453_P0_FLL_REF_FREQL_REG (0x0F) */270#define LM49453_FLL_REF_FREQ_VAL 0x8ca0001271 272/* LM49453_P0_VCO_TARGETLL_REG (0x11) */273#define LM49453_VCO_TARGET_VAL 0x8ca0001274 275/* LM49453_P0_ADC_DSP_REG (0x30h) */276#define LM49453_ADC_DSP_ADC_MUTEL BIT(0)277#define LM49453_ADC_DSP_ADC_MUTER BIT(1)278#define LM49453_ADC_DSP_DMIC1_MUTEL BIT(2)279#define LM49453_ADC_DSP_DMIC1_MUTER BIT(3)280#define LM49453_ADC_DSP_DMIC2_MUTEL BIT(4)281#define LM49453_ADC_DSP_DMIC2_MUTER BIT(5)282#define LM49453_ADC_DSP_MUTE_ALL 0x3F283 284/* LM49453_P0_DAC_DSP_REG (0x31h) */285#define LM49453_DAC_DSP_MUTE_ALL 0xFF286 287/* LM49453_P0_AUDIO_PORT1_BASIC_REG (0x60h) */288#define LM49453_AUDIO_PORT1_BASIC_FMT_MASK (BIT(4)|BIT(3))289#define LM49453_AUDIO_PORT1_BASIC_CLK_MS BIT(3)290#define LM49453_AUDIO_PORT1_BASIC_SYNC_MS BIT(4)291 292/* LM49453_P0_RESET_REG (0xFEh) */293#define LM49453_RESET_REG_RST BIT(0)294 295/* Page select register bits (0xFF) */296#define LM49453_PAGE0_SELECT 0x0297#define LM49453_PAGE1_SELECT 0x1298 299/* LM49453_P0_HSD_PIN3_4_CFG_REG (Jack Pin config - 0xD7) */300#define LM49453_JACK_DISABLE 0x00301#define LM49453_JACK_CONFIG1 0x01302#define LM49453_JACK_CONFIG2 0x02303#define LM49453_JACK_CONFIG3 0x03304#define LM49453_JACK_CONFIG4 0x04305#define LM49453_JACK_CONFIG5 0x05306 307/* Page 1 REGISTERS */308 309/* SIDETONE */310#define LM49453_P1_SIDETONE_SA0L_REG 0x80311#define LM49453_P1_SIDETONE_SA0H_REG 0x81312#define LM49453_P1_SIDETONE_SAB0U_REG 0x82313#define LM49453_P1_SIDETONE_SB0L_REG 0x83314#define LM49453_P1_SIDETONE_SB0H_REG 0x84315#define LM49453_P1_SIDETONE_SH0L_REG 0x85316#define LM49453_P1_SIDETONE_SH0H_REG 0x86317#define LM49453_P1_SIDETONE_SH0U_REG 0x87318#define LM49453_P1_SIDETONE_SA1L_REG 0x88319#define LM49453_P1_SIDETONE_SA1H_REG 0x89320#define LM49453_P1_SIDETONE_SAB1U_REG 0x8A321#define LM49453_P1_SIDETONE_SB1L_REG 0x8B322#define LM49453_P1_SIDETONE_SB1H_REG 0x8C323#define LM49453_P1_SIDETONE_SH1L_REG 0x8D324#define LM49453_P1_SIDETONE_SH1H_REG 0x8E325#define LM49453_P1_SIDETONE_SH1U_REG 0x8F326#define LM49453_P1_SIDETONE_SA2L_REG 0x90327#define LM49453_P1_SIDETONE_SA2H_REG 0x91328#define LM49453_P1_SIDETONE_SAB2U_REG 0x92329#define LM49453_P1_SIDETONE_SB2L_REG 0x93330#define LM49453_P1_SIDETONE_SB2H_REG 0x94331#define LM49453_P1_SIDETONE_SH2L_REG 0x95332#define LM49453_P1_SIDETONE_SH2H_REG 0x96333#define LM49453_P1_SIDETONE_SH2U_REG 0x97334#define LM49453_P1_SIDETONE_SA3L_REG 0x98335#define LM49453_P1_SIDETONE_SA3H_REG 0x99336#define LM49453_P1_SIDETONE_SAB3U_REG 0x9A337#define LM49453_P1_SIDETONE_SB3L_REG 0x9B338#define LM49453_P1_SIDETONE_SB3H_REG 0x9C339#define LM49453_P1_SIDETONE_SH3L_REG 0x9D340#define LM49453_P1_SIDETONE_SH3H_REG 0x9E341#define LM49453_P1_SIDETONE_SH3U_REG 0x9F342#define LM49453_P1_SIDETONE_SA4L_REG 0xA0343#define LM49453_P1_SIDETONE_SA4H_REG 0xA1344#define LM49453_P1_SIDETONE_SAB4U_REG 0xA2345#define LM49453_P1_SIDETONE_SB4L_REG 0xA3346#define LM49453_P1_SIDETONE_SB4H_REG 0xA4347#define LM49453_P1_SIDETONE_SH4L_REG 0xA5348#define LM49453_P1_SIDETONE_SH4H_REG 0xA6349#define LM49453_P1_SIDETONE_SH4U_REG 0xA7350#define LM49453_P1_SIDETONE_SA5L_REG 0xA8351#define LM49453_P1_SIDETONE_SA5H_REG 0xA9352#define LM49453_P1_SIDETONE_SAB5U_REG 0xAA353#define LM49453_P1_SIDETONE_SB5L_REG 0xAB354#define LM49453_P1_SIDETONE_SB5H_REG 0xAC355#define LM49453_P1_SIDETONE_SH5L_REG 0xAD356#define LM49453_P1_SIDETONE_SH5H_REG 0xAE357#define LM49453_P1_SIDETONE_SH5U_REG 0xAF358 359/* CHARGE PUMP CONFIG */360#define LM49453_P1_CP_CONFIG1_REG 0xB0361#define LM49453_P1_CP_CONFIG2_REG 0xB1362#define LM49453_P1_CP_CONFIG3_REG 0xB2363#define LM49453_P1_CP_CONFIG4_REG 0xB3364#define LM49453_P1_CP_LA_VTH1L_REG 0xB4365#define LM49453_P1_CP_LA_VTH1M_REG 0xB5366#define LM49453_P1_CP_LA_VTH2L_REG 0xB6367#define LM49453_P1_CP_LA_VTH2M_REG 0xB7368#define LM49453_P1_CP_LA_VTH3L_REG 0xB8369#define LM49453_P1_CP_LA_VTH3H_REG 0xB9370#define LM49453_P1_CP_CLK_DIV_REG 0xBA371 372/* DAC */373#define LM49453_P1_DAC_CHOP_REG 0xC0374 375#define LM49453_CLK_SRC_MCLK 1376#endif377