1550 lines · c
1/* SPDX-License-Identifier: GPL-2.0-only */2/*3 * max98090.h -- MAX98090 ALSA SoC Audio driver4 *5 * Copyright 2011-2012 Maxim Integrated Products6 */7 8#ifndef _MAX98090_H9#define _MAX98090_H10 11/*12 * The default operating frequency for a DMIC attached to the codec.13 * This can be overridden by a device tree property.14 */15#define MAX98090_DEFAULT_DMIC_FREQ 250000016 17/*18 * MAX98090 Register Definitions19 */20 21#define M98090_REG_SOFTWARE_RESET 0x0022#define M98090_REG_DEVICE_STATUS 0x0123#define M98090_REG_JACK_STATUS 0x0224#define M98090_REG_INTERRUPT_S 0x0325#define M98090_REG_QUICK_SYSTEM_CLOCK 0x0426#define M98090_REG_QUICK_SAMPLE_RATE 0x0527#define M98090_REG_DAI_INTERFACE 0x0628#define M98090_REG_DAC_PATH 0x0729#define M98090_REG_MIC_DIRECT_TO_ADC 0x0830#define M98090_REG_LINE_TO_ADC 0x0931#define M98090_REG_ANALOG_MIC_LOOP 0x0A32#define M98090_REG_ANALOG_LINE_LOOP 0x0B33#define M98090_REG_RESERVED 0x0C34#define M98090_REG_LINE_INPUT_CONFIG 0x0D35#define M98090_REG_LINE_INPUT_LEVEL 0x0E36#define M98090_REG_INPUT_MODE 0x0F37#define M98090_REG_MIC1_INPUT_LEVEL 0x1038#define M98090_REG_MIC2_INPUT_LEVEL 0x1139#define M98090_REG_MIC_BIAS_VOLTAGE 0x1240#define M98090_REG_DIGITAL_MIC_ENABLE 0x1341#define M98090_REG_DIGITAL_MIC_CONFIG 0x1442#define M98090_REG_LEFT_ADC_MIXER 0x1543#define M98090_REG_RIGHT_ADC_MIXER 0x1644#define M98090_REG_LEFT_ADC_LEVEL 0x1745#define M98090_REG_RIGHT_ADC_LEVEL 0x1846#define M98090_REG_ADC_BIQUAD_LEVEL 0x1947#define M98090_REG_ADC_SIDETONE 0x1A48#define M98090_REG_SYSTEM_CLOCK 0x1B49#define M98090_REG_CLOCK_MODE 0x1C50#define M98090_REG_CLOCK_RATIO_NI_MSB 0x1D51#define M98090_REG_CLOCK_RATIO_NI_LSB 0x1E52#define M98090_REG_CLOCK_RATIO_MI_MSB 0x1F53#define M98090_REG_CLOCK_RATIO_MI_LSB 0x2054#define M98090_REG_MASTER_MODE 0x2155#define M98090_REG_INTERFACE_FORMAT 0x2256#define M98090_REG_TDM_CONTROL 0x2357#define M98090_REG_TDM_FORMAT 0x2458#define M98090_REG_IO_CONFIGURATION 0x2559#define M98090_REG_FILTER_CONFIG 0x2660#define M98090_REG_DAI_PLAYBACK_LEVEL 0x2761#define M98090_REG_DAI_PLAYBACK_LEVEL_EQ 0x2862#define M98090_REG_LEFT_HP_MIXER 0x2963#define M98090_REG_RIGHT_HP_MIXER 0x2A64#define M98090_REG_HP_CONTROL 0x2B65#define M98090_REG_LEFT_HP_VOLUME 0x2C66#define M98090_REG_RIGHT_HP_VOLUME 0x2D67#define M98090_REG_LEFT_SPK_MIXER 0x2E68#define M98090_REG_RIGHT_SPK_MIXER 0x2F69#define M98090_REG_SPK_CONTROL 0x3070#define M98090_REG_LEFT_SPK_VOLUME 0x3171#define M98090_REG_RIGHT_SPK_VOLUME 0x3272#define M98090_REG_DRC_TIMING 0x3373#define M98090_REG_DRC_COMPRESSOR 0x3474#define M98090_REG_DRC_EXPANDER 0x3575#define M98090_REG_DRC_GAIN 0x3676#define M98090_REG_RCV_LOUTL_MIXER 0x3777#define M98090_REG_RCV_LOUTL_CONTROL 0x3878#define M98090_REG_RCV_LOUTL_VOLUME 0x3979#define M98090_REG_LOUTR_MIXER 0x3A80#define M98090_REG_LOUTR_CONTROL 0x3B81#define M98090_REG_LOUTR_VOLUME 0x3C82#define M98090_REG_JACK_DETECT 0x3D83#define M98090_REG_INPUT_ENABLE 0x3E84#define M98090_REG_OUTPUT_ENABLE 0x3F85#define M98090_REG_LEVEL_CONTROL 0x4086#define M98090_REG_DSP_FILTER_ENABLE 0x4187#define M98090_REG_BIAS_CONTROL 0x4288#define M98090_REG_DAC_CONTROL 0x4389#define M98090_REG_ADC_CONTROL 0x4490#define M98090_REG_DEVICE_SHUTDOWN 0x4591#define M98090_REG_EQUALIZER_BASE 0x4692#define M98090_REG_RECORD_BIQUAD_BASE 0xAF93#define M98090_REG_DMIC3_VOLUME 0xBE94#define M98090_REG_DMIC4_VOLUME 0xBF95#define M98090_REG_DMIC34_BQ_PREATTEN 0xC096#define M98090_REG_RECORD_TDM_SLOT 0xC197#define M98090_REG_SAMPLE_RATE 0xC298#define M98090_REG_DMIC34_BIQUAD_BASE 0xC399#define M98090_REG_REVISION_ID 0xFF100 101#define M98090_REG_CNT (0xFF+1)102#define MAX98090_MAX_REGISTER 0xFF103 104/* MAX98090 Register Bit Fields */105 106/*107 * M98090_REG_SOFTWARE_RESET108 */109#define M98090_SWRESET_MASK (1<<7)110#define M98090_SWRESET_SHIFT 7111#define M98090_SWRESET_WIDTH 1112 113/*114 * M98090_REG_DEVICE_STATUS115 */116#define M98090_CLD_MASK (1<<7)117#define M98090_CLD_SHIFT 7118#define M98090_CLD_WIDTH 1119#define M98090_SLD_MASK (1<<6)120#define M98090_SLD_SHIFT 6121#define M98090_SLD_WIDTH 1122#define M98090_ULK_MASK (1<<5)123#define M98090_ULK_SHIFT 5124#define M98090_ULK_WIDTH 1125#define M98090_JDET_MASK (1<<2)126#define M98090_JDET_SHIFT 2127#define M98090_JDET_WIDTH 1128#define M98090_DRCACT_MASK (1<<1)129#define M98090_DRCACT_SHIFT 1130#define M98090_DRCACT_WIDTH 1131#define M98090_DRCCLP_MASK (1<<0)132#define M98090_DRCCLP_SHIFT 0133#define M98090_DRCCLP_WIDTH 1134 135/*136 * M98090_REG_JACK_STATUS137 */138#define M98090_LSNS_MASK (1<<2)139#define M98090_LSNS_SHIFT 2140#define M98090_LSNS_WIDTH 1141#define M98090_JKSNS_MASK (1<<1)142#define M98090_JKSNS_SHIFT 1143#define M98090_JKSNS_WIDTH 1144 145/*146 * M98090_REG_INTERRUPT_S147 */148#define M98090_ICLD_MASK (1<<7)149#define M98090_ICLD_SHIFT 7150#define M98090_ICLD_WIDTH 1151#define M98090_ISLD_MASK (1<<6)152#define M98090_ISLD_SHIFT 6153#define M98090_ISLD_WIDTH 1154#define M98090_IULK_MASK (1<<5)155#define M98090_IULK_SHIFT 5156#define M98090_IULK_WIDTH 1157#define M98090_IJDET_MASK (1<<2)158#define M98090_IJDET_SHIFT 2159#define M98090_IJDET_WIDTH 1160#define M98090_IDRCACT_MASK (1<<1)161#define M98090_IDRCACT_SHIFT 1162#define M98090_IDRCACT_WIDTH 1163#define M98090_IDRCCLP_MASK (1<<0)164#define M98090_IDRCCLP_SHIFT 0165#define M98090_IDRCCLP_WIDTH 1166 167/*168 * M98090_REG_QUICK_SYSTEM_CLOCK169 */170#define M98090_26M_MASK (1<<7)171#define M98090_26M_SHIFT 7172#define M98090_26M_WIDTH 1173#define M98090_19P2M_MASK (1<<6)174#define M98090_19P2M_SHIFT 6175#define M98090_19P2M_WIDTH 1176#define M98090_13M_MASK (1<<5)177#define M98090_13M_SHIFT 5178#define M98090_13M_WIDTH 1179#define M98090_12P288M_MASK (1<<4)180#define M98090_12P288M_SHIFT 4181#define M98090_12P288M_WIDTH 1182#define M98090_12M_MASK (1<<3)183#define M98090_12M_SHIFT 3184#define M98090_12M_WIDTH 1185#define M98090_11P2896M_MASK (1<<2)186#define M98090_11P2896M_SHIFT 2187#define M98090_11P2896M_WIDTH 1188#define M98090_256FS_MASK (1<<0)189#define M98090_256FS_SHIFT 0190#define M98090_256FS_WIDTH 1191#define M98090_CLK_ALL_SHIFT 0192#define M98090_CLK_ALL_WIDTH 8193#define M98090_CLK_ALL_NUM (1<<M98090_CLK_ALL_WIDTH)194 195/*196 * M98090_REG_QUICK_SAMPLE_RATE197 */198#define M98090_SR_96K_MASK (1<<5)199#define M98090_SR_96K_SHIFT 5200#define M98090_SR_96K_WIDTH 1201#define M98090_SR_32K_MASK (1<<4)202#define M98090_SR_32K_SHIFT 4203#define M98090_SR_32K_WIDTH 1204#define M98090_SR_48K_MASK (1<<3)205#define M98090_SR_48K_SHIFT 3206#define M98090_SR_48K_WIDTH 1207#define M98090_SR_44K1_MASK (1<<2)208#define M98090_SR_44K1_SHIFT 2209#define M98090_SR_44K1_WIDTH 1210#define M98090_SR_16K_MASK (1<<1)211#define M98090_SR_16K_SHIFT 1212#define M98090_SR_16K_WIDTH 1213#define M98090_SR_8K_MASK (1<<0)214#define M98090_SR_8K_SHIFT 0215#define M98090_SR_8K_WIDTH 1216#define M98090_SR_MASK 0x3F217#define M98090_SR_ALL_SHIFT 0218#define M98090_SR_ALL_WIDTH 8219#define M98090_SR_ALL_NUM (1<<M98090_SR_ALL_WIDTH)220 221/*222 * M98090_REG_DAI_INTERFACE223 */224#define M98090_RJ_M_MASK (1<<5)225#define M98090_RJ_M_SHIFT 5226#define M98090_RJ_M_WIDTH 1227#define M98090_RJ_S_MASK (1<<4)228#define M98090_RJ_S_SHIFT 4229#define M98090_RJ_S_WIDTH 1230#define M98090_LJ_M_MASK (1<<3)231#define M98090_LJ_M_SHIFT 3232#define M98090_LJ_M_WIDTH 1233#define M98090_LJ_S_MASK (1<<2)234#define M98090_LJ_S_SHIFT 2235#define M98090_LJ_S_WIDTH 1236#define M98090_I2S_M_MASK (1<<1)237#define M98090_I2S_M_SHIFT 1238#define M98090_I2S_M_WIDTH 1239#define M98090_I2S_S_MASK (1<<0)240#define M98090_I2S_S_SHIFT 0241#define M98090_I2S_S_WIDTH 1242#define M98090_DAI_ALL_SHIFT 0243#define M98090_DAI_ALL_WIDTH 8244#define M98090_DAI_ALL_NUM (1<<M98090_DAI_ALL_WIDTH)245 246/*247 * M98090_REG_DAC_PATH248 */249#define M98090_DIG2_HP_MASK (1<<7)250#define M98090_DIG2_HP_SHIFT 7251#define M98090_DIG2_HP_WIDTH 1252#define M98090_DIG2_EAR_MASK (1<<6)253#define M98090_DIG2_EAR_SHIFT 6254#define M98090_DIG2_EAR_WIDTH 1255#define M98090_DIG2_SPK_MASK (1<<5)256#define M98090_DIG2_SPK_SHIFT 5257#define M98090_DIG2_SPK_WIDTH 1258#define M98090_DIG2_LOUT_MASK (1<<4)259#define M98090_DIG2_LOUT_SHIFT 4260#define M98090_DIG2_LOUT_WIDTH 1261#define M98090_DIG2_ALL_SHIFT 0262#define M98090_DIG2_ALL_WIDTH 8263#define M98090_DIG2_ALL_NUM (1<<M98090_DIG2_ALL_WIDTH)264 265/*266 * M98090_REG_MIC_DIRECT_TO_ADC267 */268#define M98090_IN12_MIC1_MASK (1<<7)269#define M98090_IN12_MIC1_SHIFT 7270#define M98090_IN12_MIC1_WIDTH 1271#define M98090_IN34_MIC2_MASK (1<<6)272#define M98090_IN34_MIC2_SHIFT 6273#define M98090_IN34_MIC2_WIDTH 1274#define M98090_IN56_MIC1_MASK (1<<5)275#define M98090_IN56_MIC1_SHIFT 5276#define M98090_IN56_MIC1_WIDTH 1277#define M98090_IN56_MIC2_MASK (1<<4)278#define M98090_IN56_MIC2_SHIFT 4279#define M98090_IN56_MIC2_WIDTH 1280#define M98090_IN12_DADC_MASK (1<<3)281#define M98090_IN12_DADC_SHIFT 3282#define M98090_IN12_DADC_WIDTH 1283#define M98090_IN34_DADC_MASK (1<<2)284#define M98090_IN34_DADC_SHIFT 2285#define M98090_IN34_DADC_WIDTH 1286#define M98090_IN56_DADC_MASK (1<<1)287#define M98090_IN56_DADC_SHIFT 1288#define M98090_IN56_DADC_WIDTH 1289#define M98090_MIC_ALL_SHIFT 0290#define M98090_MIC_ALL_WIDTH 8291#define M98090_MIC_ALL_NUM (1<<M98090_MIC_ALL_WIDTH)292 293/*294 * M98090_REG_LINE_TO_ADC295 */296#define M98090_IN12S_AB_MASK (1<<7)297#define M98090_IN12S_AB_SHIFT 7298#define M98090_IN12S_AB_WIDTH 1299#define M98090_IN34S_AB_MASK (1<<6)300#define M98090_IN34S_AB_SHIFT 6301#define M98090_IN34S_AB_WIDTH 1302#define M98090_IN56S_AB_MASK (1<<5)303#define M98090_IN56S_AB_SHIFT 5304#define M98090_IN56S_AB_WIDTH 1305#define M98090_IN34D_A_MASK (1<<4)306#define M98090_IN34D_A_SHIFT 4307#define M98090_IN34D_A_WIDTH 1308#define M98090_IN56D_B_MASK (1<<3)309#define M98090_IN56D_B_SHIFT 3310#define M98090_IN56D_B_WIDTH 1311#define M98090_LINE_ALL_SHIFT 0312#define M98090_LINE_ALL_WIDTH 8313#define M98090_LINE_ALL_NUM (1<<M98090_LINE_ALL_WIDTH)314 315/*316 * M98090_REG_ANALOG_MIC_LOOP317 */318#define M98090_IN12_M1HPL_MASK (1<<7)319#define M98090_IN12_M1HPL_SHIFT 7320#define M98090_IN12_M1HPL_WIDTH 1321#define M98090_IN12_M1SPKL_MASK (1<<6)322#define M98090_IN12_M1SPKL_SHIFT 6323#define M98090_IN12_M1SPKL_WIDTH 1324#define M98090_IN12_M1EAR_MASK (1<<5)325#define M98090_IN12_M1EAR_SHIFT 5326#define M98090_IN12_M1EAR_WIDTH 1327#define M98090_IN12_M1LOUTL_MASK (1<<4)328#define M98090_IN12_M1LOUTL_SHIFT 4329#define M98090_IN12_M1LOUTL_WIDTH 1330#define M98090_IN34_M2HPR_MASK (1<<3)331#define M98090_IN34_M2HPR_SHIFT 3332#define M98090_IN34_M2HPR_WIDTH 1333#define M98090_IN34_M2SPKR_MASK (1<<2)334#define M98090_IN34_M2SPKR_SHIFT 2335#define M98090_IN34_M2SPKR_WIDTH 1336#define M98090_IN34_M2EAR_MASK (1<<1)337#define M98090_IN34_M2EAR_SHIFT 1338#define M98090_IN34_M2EAR_WIDTH 1339#define M98090_IN34_M2LOUTR_MASK (1<<0)340#define M98090_IN34_M2LOUTR_SHIFT 0341#define M98090_IN34_M2LOUTR_WIDTH 1342#define M98090_AMIC_ALL_SHIFT 0343#define M98090_AMIC_ALL_WIDTH 8344#define M98090_AMIC_ALL_NUM (1<<M98090_AMIC_ALL_WIDTH)345 346/*347 * M98090_REG_ANALOG_LINE_LOOP348 */349#define M98090_IN12S_ABHP_MASK (1<<7)350#define M98090_IN12S_ABHP_SHIFT 7351#define M98090_IN12S_ABHP_WIDTH 1352#define M98090_IN34D_ASPKL_MASK (1<<6)353#define M98090_IN34D_ASPKL_SHIFT 6354#define M98090_IN34D_ASPKL_WIDTH 1355#define M98090_IN34D_AEAR_MASK (1<<5)356#define M98090_IN34D_AEAR_SHIFT 5357#define M98090_IN34D_AEAR_WIDTH 1358#define M98090_IN12S_ABLOUT_MASK (1<<4)359#define M98090_IN12S_ABLOUT_SHIFT 4360#define M98090_IN12S_ABLOUT_WIDTH 1361#define M98090_IN34S_ABHP_MASK (1<<3)362#define M98090_IN34S_ABHP_SHIFT 3363#define M98090_IN34S_ABHP_WIDTH 1364#define M98090_IN56D_BSPKR_MASK (1<<2)365#define M98090_IN56D_BSPKR_SHIFT 2366#define M98090_IN56D_BSPKR_WIDTH 1367#define M98090_IN56D_BEAR_MASK (1<<1)368#define M98090_IN56D_BEAR_SHIFT 1369#define M98090_IN56D_BEAR_WIDTH 1370#define M98090_IN34S_ABLOUT_MASK (1<<0)371#define M98090_IN34S_ABLOUT_SHIFT 0372#define M98090_IN34S_ABLOUT_WIDTH 1373#define M98090_ALIN_ALL_SHIFT 0374#define M98090_ALIN_ALL_WIDTH 8375#define M98090_ALIN_ALL_NUM (1<<M98090_ALIN_ALL_WIDTH)376 377/*378 * M98090_REG_RESERVED379 */380 381/*382 * M98090_REG_LINE_INPUT_CONFIG383 */384#define M98090_IN34DIFF_MASK (1<<7)385#define M98090_IN34DIFF_SHIFT 7386#define M98090_IN34DIFF_WIDTH 1387#define M98090_IN56DIFF_MASK (1<<6)388#define M98090_IN56DIFF_SHIFT 6389#define M98090_IN56DIFF_WIDTH 1390#define M98090_IN1SEEN_MASK (1<<5)391#define M98090_IN1SEEN_SHIFT 5392#define M98090_IN1SEEN_WIDTH 1393#define M98090_IN2SEEN_MASK (1<<4)394#define M98090_IN2SEEN_SHIFT 4395#define M98090_IN2SEEN_WIDTH 1396#define M98090_IN3SEEN_MASK (1<<3)397#define M98090_IN3SEEN_SHIFT 3398#define M98090_IN3SEEN_WIDTH 1399#define M98090_IN4SEEN_MASK (1<<2)400#define M98090_IN4SEEN_SHIFT 2401#define M98090_IN4SEEN_WIDTH 1402#define M98090_IN5SEEN_MASK (1<<1)403#define M98090_IN5SEEN_SHIFT 1404#define M98090_IN5SEEN_WIDTH 1405#define M98090_IN6SEEN_MASK (1<<0)406#define M98090_IN6SEEN_SHIFT 0407#define M98090_IN6SEEN_WIDTH 1408 409/*410 * M98090_REG_LINE_INPUT_LEVEL411 */412#define M98090_MIXG135_MASK (1<<7)413#define M98090_MIXG135_SHIFT 7414#define M98090_MIXG135_WIDTH 1415#define M98090_MIXG135_NUM (1<<M98090_MIXG135_WIDTH)416#define M98090_MIXG246_MASK (1<<6)417#define M98090_MIXG246_SHIFT 6418#define M98090_MIXG246_WIDTH 1419#define M98090_MIXG246_NUM (1<<M98090_MIXG246_WIDTH)420#define M98090_LINAPGA_MASK (7<<3)421#define M98090_LINAPGA_SHIFT 3422#define M98090_LINAPGA_WIDTH 3423#define M98090_LINAPGA_NUM 6424#define M98090_LINBPGA_MASK (7<<0)425#define M98090_LINBPGA_SHIFT 0426#define M98090_LINBPGA_WIDTH 3427#define M98090_LINBPGA_NUM 6428 429/*430 * M98090_REG_INPUT_MODE431 */432#define M98090_EXTBUFA_MASK (1<<7)433#define M98090_EXTBUFA_SHIFT 7434#define M98090_EXTBUFA_WIDTH 1435#define M98090_EXTBUFA_NUM (1<<M98090_EXTBUFA_WIDTH)436#define M98090_EXTBUFB_MASK (1<<6)437#define M98090_EXTBUFB_SHIFT 6438#define M98090_EXTBUFB_WIDTH 1439#define M98090_EXTBUFB_NUM (1<<M98090_EXTBUFB_WIDTH)440#define M98090_EXTMIC_MASK (3<<0)441#define M98090_EXTMIC_SHIFT 0442#define M98090_EXTMIC1_SHIFT 0443#define M98090_EXTMIC2_SHIFT 1444#define M98090_EXTMIC_WIDTH 2445#define M98090_EXTMIC_NONE (0<<0)446#define M98090_EXTMIC_MIC1 (1<<0)447#define M98090_EXTMIC_MIC2 (2<<0)448 449/*450 * M98090_REG_MIC1_INPUT_LEVEL451 */452#define M98090_MIC_PA1EN_MASK (3<<5)453#define M98090_MIC_PA1EN_SHIFT 5454#define M98090_MIC_PA1EN_WIDTH 2455#define M98090_MIC_PA1EN_NUM 3456#define M98090_MIC_PGAM1_MASK (31<<0)457#define M98090_MIC_PGAM1_SHIFT 0458#define M98090_MIC_PGAM1_WIDTH 5459#define M98090_MIC_PGAM1_NUM 21460 461/*462 * M98090_REG_MIC2_INPUT_LEVEL463 */464#define M98090_MIC_PA2EN_MASK (3<<5)465#define M98090_MIC_PA2EN_SHIFT 5466#define M98090_MIC_PA2EN_WIDTH 2467#define M98090_MIC_PA2EN_NUM 3468#define M98090_MIC_PGAM2_MASK (31<<0)469#define M98090_MIC_PGAM2_SHIFT 0470#define M98090_MIC_PGAM2_WIDTH 5471#define M98090_MIC_PGAM2_NUM 21472 473/*474 * M98090_REG_MIC_BIAS_VOLTAGE475 */476#define M98090_MBVSEL_MASK (3<<0)477#define M98090_MBVSEL_SHIFT 0478#define M98090_MBVSEL_WIDTH 2479#define M98090_MBVSEL_2V8 (3<<0)480#define M98090_MBVSEL_2V55 (2<<0)481#define M98090_MBVSEL_2V4 (1<<0)482#define M98090_MBVSEL_2V2 (0<<0)483 484/*485 * M98090_REG_DIGITAL_MIC_ENABLE486 */487#define M98090_MICCLK_MASK (7<<4)488#define M98090_MICCLK_SHIFT 4489#define M98090_MICCLK_WIDTH 3490#define M98090_DIGMIC4_MASK (1<<3)491#define M98090_DIGMIC4_SHIFT 3492#define M98090_DIGMIC4_WIDTH 1493#define M98090_DIGMIC4_NUM (1<<M98090_DIGMIC4_WIDTH)494#define M98090_DIGMIC3_MASK (1<<2)495#define M98090_DIGMIC3_SHIFT 2496#define M98090_DIGMIC3_WIDTH 1497#define M98090_DIGMIC3_NUM (1<<M98090_DIGMIC3_WIDTH)498#define M98090_DIGMICR_MASK (1<<1)499#define M98090_DIGMICR_SHIFT 1500#define M98090_DIGMICR_WIDTH 1501#define M98090_DIGMICR_NUM (1<<M98090_DIGMICR_WIDTH)502#define M98090_DIGMICL_MASK (1<<0)503#define M98090_DIGMICL_SHIFT 0504#define M98090_DIGMICL_WIDTH 1505#define M98090_DIGMICL_NUM (1<<M98090_DIGMICL_WIDTH)506 507/*508 * M98090_REG_DIGITAL_MIC_CONFIG509 */510#define M98090_DMIC_COMP_MASK (15<<4)511#define M98090_DMIC_COMP_SHIFT 4512#define M98090_DMIC_COMP_WIDTH 4513#define M98090_DMIC_COMP_NUM (1<<M98090_DMIC_COMP_WIDTH)514#define M98090_DMIC_FREQ_MASK (3<<0)515#define M98090_DMIC_FREQ_SHIFT 0516#define M98090_DMIC_FREQ_WIDTH 2517 518/*519 * M98090_REG_LEFT_ADC_MIXER520 */521#define M98090_MIXADL_MIC2_MASK (1<<6)522#define M98090_MIXADL_MIC2_SHIFT 6523#define M98090_MIXADL_MIC2_WIDTH 1524#define M98090_MIXADL_MIC1_MASK (1<<5)525#define M98090_MIXADL_MIC1_SHIFT 5526#define M98090_MIXADL_MIC1_WIDTH 1527#define M98090_MIXADL_LINEB_MASK (1<<4)528#define M98090_MIXADL_LINEB_SHIFT 4529#define M98090_MIXADL_LINEB_WIDTH 1530#define M98090_MIXADL_LINEA_MASK (1<<3)531#define M98090_MIXADL_LINEA_SHIFT 3532#define M98090_MIXADL_LINEA_WIDTH 1533#define M98090_MIXADL_IN65DIFF_MASK (1<<2)534#define M98090_MIXADL_IN65DIFF_SHIFT 2535#define M98090_MIXADL_IN65DIFF_WIDTH 1536#define M98090_MIXADL_IN34DIFF_MASK (1<<1)537#define M98090_MIXADL_IN34DIFF_SHIFT 1538#define M98090_MIXADL_IN34DIFF_WIDTH 1539#define M98090_MIXADL_IN12DIFF_MASK (1<<0)540#define M98090_MIXADL_IN12DIFF_SHIFT 0541#define M98090_MIXADL_IN12DIFF_WIDTH 1542#define M98090_MIXADL_MASK (255<<0)543#define M98090_MIXADL_SHIFT 0544#define M98090_MIXADL_WIDTH 8545 546/*547 * M98090_REG_RIGHT_ADC_MIXER548 */549#define M98090_MIXADR_MIC2_MASK (1<<6)550#define M98090_MIXADR_MIC2_SHIFT 6551#define M98090_MIXADR_MIC2_WIDTH 1552#define M98090_MIXADR_MIC1_MASK (1<<5)553#define M98090_MIXADR_MIC1_SHIFT 5554#define M98090_MIXADR_MIC1_WIDTH 1555#define M98090_MIXADR_LINEB_MASK (1<<4)556#define M98090_MIXADR_LINEB_SHIFT 4557#define M98090_MIXADR_LINEB_WIDTH 1558#define M98090_MIXADR_LINEA_MASK (1<<3)559#define M98090_MIXADR_LINEA_SHIFT 3560#define M98090_MIXADR_LINEA_WIDTH 1561#define M98090_MIXADR_IN65DIFF_MASK (1<<2)562#define M98090_MIXADR_IN65DIFF_SHIFT 2563#define M98090_MIXADR_IN65DIFF_WIDTH 1564#define M98090_MIXADR_IN34DIFF_MASK (1<<1)565#define M98090_MIXADR_IN34DIFF_SHIFT 1566#define M98090_MIXADR_IN34DIFF_WIDTH 1567#define M98090_MIXADR_IN12DIFF_MASK (1<<0)568#define M98090_MIXADR_IN12DIFF_SHIFT 0569#define M98090_MIXADR_IN12DIFF_WIDTH 1570#define M98090_MIXADR_MASK (255<<0)571#define M98090_MIXADR_SHIFT 0572#define M98090_MIXADR_WIDTH 8573 574/*575 * M98090_REG_LEFT_ADC_LEVEL576 */577#define M98090_AVLG_MASK (7<<4)578#define M98090_AVLG_SHIFT 4579#define M98090_AVLG_WIDTH 3580#define M98090_AVLG_NUM (1<<M98090_AVLG_WIDTH)581#define M98090_AVL_MASK (15<<0)582#define M98090_AVL_SHIFT 0583#define M98090_AVL_WIDTH 4584#define M98090_AVL_NUM (1<<M98090_AVL_WIDTH)585 586/*587 * M98090_REG_RIGHT_ADC_LEVEL588 */589#define M98090_AVRG_MASK (7<<4)590#define M98090_AVRG_SHIFT 4591#define M98090_AVRG_WIDTH 3592#define M98090_AVRG_NUM (1<<M98090_AVRG_WIDTH)593#define M98090_AVR_MASK (15<<0)594#define M98090_AVR_SHIFT 0595#define M98090_AVR_WIDTH 4596#define M98090_AVR_NUM (1<<M98090_AVR_WIDTH)597 598/*599 * M98090_REG_ADC_BIQUAD_LEVEL600 */601#define M98090_AVBQ_MASK (15<<0)602#define M98090_AVBQ_SHIFT 0603#define M98090_AVBQ_WIDTH 4604#define M98090_AVBQ_NUM (1<<M98090_AVBQ_WIDTH)605 606/*607 * M98090_REG_ADC_SIDETONE608 */609#define M98090_DSTSR_MASK (1<<7)610#define M98090_DSTSR_SHIFT 7611#define M98090_DSTSR_WIDTH 1612#define M98090_DSTSL_MASK (1<<6)613#define M98090_DSTSL_SHIFT 6614#define M98090_DSTSL_WIDTH 1615#define M98090_DVST_MASK (31<<0)616#define M98090_DVST_SHIFT 0617#define M98090_DVST_WIDTH 5618#define M98090_DVST_NUM 31619 620/*621 * M98090_REG_SYSTEM_CLOCK622 */623#define M98090_PSCLK_MASK (3<<4)624#define M98090_PSCLK_SHIFT 4625#define M98090_PSCLK_WIDTH 2626#define M98090_PSCLK_DISABLED (0<<4)627#define M98090_PSCLK_DIV1 (1<<4)628#define M98090_PSCLK_DIV2 (2<<4)629#define M98090_PSCLK_DIV4 (3<<4)630 631/*632 * M98090_REG_CLOCK_MODE633 */634#define M98090_FREQ_MASK (15<<4)635#define M98090_FREQ_SHIFT 4636#define M98090_FREQ_WIDTH 4637#define M98090_USE_M1_MASK (1<<0)638#define M98090_USE_M1_SHIFT 0639#define M98090_USE_M1_WIDTH 1640#define M98090_USE_M1_NUM (1<<M98090_USE_M1_WIDTH)641 642/*643 * M98090_REG_CLOCK_RATIO_NI_MSB644 */645#define M98090_NI_HI_MASK (127<<0)646#define M98090_NI_HI_SHIFT 0647#define M98090_NI_HI_WIDTH 7648#define M98090_NI_HI_NUM (1<<M98090_NI_HI_WIDTH)649 650/*651 * M98090_REG_CLOCK_RATIO_NI_LSB652 */653#define M98090_NI_LO_MASK (255<<0)654#define M98090_NI_LO_SHIFT 0655#define M98090_NI_LO_WIDTH 8656#define M98090_NI_LO_NUM (1<<M98090_NI_LO_WIDTH)657 658/*659 * M98090_REG_CLOCK_RATIO_MI_MSB660 */661#define M98090_MI_HI_MASK (255<<0)662#define M98090_MI_HI_SHIFT 0663#define M98090_MI_HI_WIDTH 8664#define M98090_MI_HI_NUM (1<<M98090_MI_HI_WIDTH)665 666/*667 * M98090_REG_CLOCK_RATIO_MI_LSB668 */669#define M98090_MI_LO_MASK (255<<0)670#define M98090_MI_LO_SHIFT 0671#define M98090_MI_LO_WIDTH 8672#define M98090_MI_LO_NUM (1<<M98090_MI_LO_WIDTH)673 674/*675 * M98090_REG_MASTER_MODE676 */677#define M98090_MAS_MASK (1<<7)678#define M98090_MAS_SHIFT 7679#define M98090_MAS_WIDTH 1680#define M98090_BSEL_MASK (1<<0)681#define M98090_BSEL_SHIFT 0682#define M98090_BSEL_WIDTH 1683#define M98090_BSEL_32 (1<<0)684#define M98090_BSEL_48 (2<<0)685#define M98090_BSEL_64 (3<<0)686 687/*688 * M98090_REG_INTERFACE_FORMAT689 */690#define M98090_RJ_MASK (1<<5)691#define M98090_RJ_SHIFT 5692#define M98090_RJ_WIDTH 1693#define M98090_WCI_MASK (1<<4)694#define M98090_WCI_SHIFT 4695#define M98090_WCI_WIDTH 1696#define M98090_BCI_MASK (1<<3)697#define M98090_BCI_SHIFT 3698#define M98090_BCI_WIDTH 1699#define M98090_DLY_MASK (1<<2)700#define M98090_DLY_SHIFT 2701#define M98090_DLY_WIDTH 1702#define M98090_WS_MASK (3<<0)703#define M98090_WS_SHIFT 0704#define M98090_WS_WIDTH 2705#define M98090_WS_NUM (1<<M98090_WS_WIDTH)706 707/*708 * M98090_REG_TDM_CONTROL709 */710#define M98090_FSW_MASK (1<<1)711#define M98090_FSW_SHIFT 1712#define M98090_FSW_WIDTH 1713#define M98090_TDM_MASK (1<<0)714#define M98090_TDM_SHIFT 0715#define M98090_TDM_WIDTH 1716#define M98090_TDM_NUM (1<<M98090_TDM_WIDTH)717 718/*719 * M98090_REG_TDM_FORMAT720 */721#define M98090_TDM_SLOTL_MASK (3<<6)722#define M98090_TDM_SLOTL_SHIFT 6723#define M98090_TDM_SLOTL_WIDTH 2724#define M98090_TDM_SLOTL_NUM (1<<M98090_TDM_SLOTL_WIDTH)725#define M98090_TDM_SLOTR_MASK (3<<4)726#define M98090_TDM_SLOTR_SHIFT 4727#define M98090_TDM_SLOTR_WIDTH 2728#define M98090_TDM_SLOTR_NUM (1<<M98090_TDM_SLOTR_WIDTH)729#define M98090_TDM_SLOTDLY_MASK (15<<0)730#define M98090_TDM_SLOTDLY_SHIFT 0731#define M98090_TDM_SLOTDLY_WIDTH 4732#define M98090_TDM_SLOTDLY_NUM (1<<M98090_TDM_SLOTDLY_WIDTH)733 734/*735 * M98090_REG_IO_CONFIGURATION736 */737#define M98090_LTEN_MASK (1<<5)738#define M98090_LTEN_SHIFT 5739#define M98090_LTEN_WIDTH 1740#define M98090_LTEN_NUM (1<<M98090_LTEN_WIDTH)741#define M98090_LBEN_MASK (1<<4)742#define M98090_LBEN_SHIFT 4743#define M98090_LBEN_WIDTH 1744#define M98090_LBEN_NUM (1<<M98090_LBEN_WIDTH)745#define M98090_DMONO_MASK (1<<3)746#define M98090_DMONO_SHIFT 3747#define M98090_DMONO_WIDTH 1748#define M98090_DMONO_NUM (1<<M98090_DMONO_WIDTH)749#define M98090_HIZOFF_MASK (1<<2)750#define M98090_HIZOFF_SHIFT 2751#define M98090_HIZOFF_WIDTH 1752#define M98090_HIZOFF_NUM (1<<M98090_HIZOFF_WIDTH)753#define M98090_SDOEN_MASK (1<<1)754#define M98090_SDOEN_SHIFT 1755#define M98090_SDOEN_WIDTH 1756#define M98090_SDOEN_NUM (1<<M98090_SDOEN_WIDTH)757#define M98090_SDIEN_MASK (1<<0)758#define M98090_SDIEN_SHIFT 0759#define M98090_SDIEN_WIDTH 1760#define M98090_SDIEN_NUM (1<<M98090_SDIEN_WIDTH)761 762/*763 * M98090_REG_FILTER_CONFIG764 */765#define M98090_MODE_MASK (1<<7)766#define M98090_MODE_SHIFT 7767#define M98090_MODE_WIDTH 1768#define M98090_AHPF_MASK (1<<6)769#define M98090_AHPF_SHIFT 6770#define M98090_AHPF_WIDTH 1771#define M98090_AHPF_NUM (1<<M98090_AHPF_WIDTH)772#define M98090_DHPF_MASK (1<<5)773#define M98090_DHPF_SHIFT 5774#define M98090_DHPF_WIDTH 1775#define M98090_DHPF_NUM (1<<M98090_DHPF_WIDTH)776#define M98090_DHF_MASK (1<<4)777#define M98090_DHF_SHIFT 4778#define M98090_DHF_WIDTH 1779#define M98090_FLT_DMIC34MODE_MASK (1<<3)780#define M98090_FLT_DMIC34MODE_SHIFT 3781#define M98090_FLT_DMIC34MODE_WIDTH 1782#define M98090_FLT_DMIC34HPF_MASK (1<<2)783#define M98090_FLT_DMIC34HPF_SHIFT 2784#define M98090_FLT_DMIC34HPF_WIDTH 1785#define M98090_FLT_DMIC34HPF_NUM (1<<M98090_FLT_DMIC34HPF_WIDTH)786 787/*788 * M98090_REG_DAI_PLAYBACK_LEVEL789 */790#define M98090_DVM_MASK (1<<7)791#define M98090_DVM_SHIFT 7792#define M98090_DVM_WIDTH 1793#define M98090_DVG_MASK (3<<4)794#define M98090_DVG_SHIFT 4795#define M98090_DVG_WIDTH 2796#define M98090_DVG_NUM (1<<M98090_DVG_WIDTH)797#define M98090_DV_MASK (15<<0)798#define M98090_DV_SHIFT 0799#define M98090_DV_WIDTH 4800#define M98090_DV_NUM (1<<M98090_DV_WIDTH)801 802/*803 * M98090_REG_DAI_PLAYBACK_LEVEL_EQ804 */805#define M98090_EQCLPN_MASK (1<<4)806#define M98090_EQCLPN_SHIFT 4807#define M98090_EQCLPN_WIDTH 1808#define M98090_EQCLPN_NUM (1<<M98090_EQCLPN_WIDTH)809#define M98090_DVEQ_MASK (15<<0)810#define M98090_DVEQ_SHIFT 0811#define M98090_DVEQ_WIDTH 4812#define M98090_DVEQ_NUM (1<<M98090_DVEQ_WIDTH)813 814/*815 * M98090_REG_LEFT_HP_MIXER816 */817#define M98090_MIXHPL_MIC2_MASK (1<<5)818#define M98090_MIXHPL_MIC2_SHIFT 5819#define M98090_MIXHPL_MIC2_WIDTH 1820#define M98090_MIXHPL_MIC1_MASK (1<<4)821#define M98090_MIXHPL_MIC1_SHIFT 4822#define M98090_MIXHPL_MIC1_WIDTH 1823#define M98090_MIXHPL_LINEB_MASK (1<<3)824#define M98090_MIXHPL_LINEB_SHIFT 3825#define M98090_MIXHPL_LINEB_WIDTH 1826#define M98090_MIXHPL_LINEA_MASK (1<<2)827#define M98090_MIXHPL_LINEA_SHIFT 2828#define M98090_MIXHPL_LINEA_WIDTH 1829#define M98090_MIXHPL_DACR_MASK (1<<1)830#define M98090_MIXHPL_DACR_SHIFT 1831#define M98090_MIXHPL_DACR_WIDTH 1832#define M98090_MIXHPL_DACL_MASK (1<<0)833#define M98090_MIXHPL_DACL_SHIFT 0834#define M98090_MIXHPL_DACL_WIDTH 1835#define M98090_MIXHPL_MASK (63<<0)836#define M98090_MIXHPL_SHIFT 0837#define M98090_MIXHPL_WIDTH 6838 839/*840 * M98090_REG_RIGHT_HP_MIXER841 */842#define M98090_MIXHPR_MIC2_MASK (1<<5)843#define M98090_MIXHPR_MIC2_SHIFT 5844#define M98090_MIXHPR_MIC2_WIDTH 1845#define M98090_MIXHPR_MIC1_MASK (1<<4)846#define M98090_MIXHPR_MIC1_SHIFT 4847#define M98090_MIXHPR_MIC1_WIDTH 1848#define M98090_MIXHPR_LINEB_MASK (1<<3)849#define M98090_MIXHPR_LINEB_SHIFT 3850#define M98090_MIXHPR_LINEB_WIDTH 1851#define M98090_MIXHPR_LINEA_MASK (1<<2)852#define M98090_MIXHPR_LINEA_SHIFT 2853#define M98090_MIXHPR_LINEA_WIDTH 1854#define M98090_MIXHPR_DACR_MASK (1<<1)855#define M98090_MIXHPR_DACR_SHIFT 1856#define M98090_MIXHPR_DACR_WIDTH 1857#define M98090_MIXHPR_DACL_MASK (1<<0)858#define M98090_MIXHPR_DACL_SHIFT 0859#define M98090_MIXHPR_DACL_WIDTH 1860#define M98090_MIXHPR_MASK (63<<0)861#define M98090_MIXHPR_SHIFT 0862#define M98090_MIXHPR_WIDTH 6863 864/*865 * M98090_REG_HP_CONTROL866 */867#define M98090_MIXHPRSEL_MASK (1<<5)868#define M98090_MIXHPRSEL_SHIFT 5869#define M98090_MIXHPRSEL_WIDTH 1870#define M98090_MIXHPLSEL_MASK (1<<4)871#define M98090_MIXHPLSEL_SHIFT 4872#define M98090_MIXHPLSEL_WIDTH 1873#define M98090_MIXHPRG_MASK (3<<2)874#define M98090_MIXHPRG_SHIFT 2875#define M98090_MIXHPRG_WIDTH 2876#define M98090_MIXHPRG_NUM (1<<M98090_MIXHPRG_WIDTH)877#define M98090_MIXHPLG_MASK (3<<0)878#define M98090_MIXHPLG_SHIFT 0879#define M98090_MIXHPLG_WIDTH 2880#define M98090_MIXHPLG_NUM (1<<M98090_MIXHPLG_WIDTH)881 882/*883 * M98090_REG_LEFT_HP_VOLUME884 */885#define M98090_HPLM_MASK (1<<7)886#define M98090_HPLM_SHIFT 7887#define M98090_HPLM_WIDTH 1888#define M98090_HPVOLL_MASK (31<<0)889#define M98090_HPVOLL_SHIFT 0890#define M98090_HPVOLL_WIDTH 5891#define M98090_HPVOLL_NUM (1<<M98090_HPVOLL_WIDTH)892 893/*894 * M98090_REG_RIGHT_HP_VOLUME895 */896#define M98090_HPRM_MASK (1<<7)897#define M98090_HPRM_SHIFT 7898#define M98090_HPRM_WIDTH 1899#define M98090_HPVOLR_MASK (31<<0)900#define M98090_HPVOLR_SHIFT 0901#define M98090_HPVOLR_WIDTH 5902#define M98090_HPVOLR_NUM (1<<M98090_HPVOLR_WIDTH)903 904/*905 * M98090_REG_LEFT_SPK_MIXER906 */907#define M98090_MIXSPL_MIC2_MASK (1<<5)908#define M98090_MIXSPL_MIC2_SHIFT 5909#define M98090_MIXSPL_MIC2_WIDTH 1910#define M98090_MIXSPL_MIC1_MASK (1<<4)911#define M98090_MIXSPL_MIC1_SHIFT 4912#define M98090_MIXSPL_MIC1_WIDTH 1913#define M98090_MIXSPL_LINEB_MASK (1<<3)914#define M98090_MIXSPL_LINEB_SHIFT 3915#define M98090_MIXSPL_LINEB_WIDTH 1916#define M98090_MIXSPL_LINEA_MASK (1<<2)917#define M98090_MIXSPL_LINEA_SHIFT 2918#define M98090_MIXSPL_LINEA_WIDTH 1919#define M98090_MIXSPL_DACR_MASK (1<<1)920#define M98090_MIXSPL_DACR_SHIFT 1921#define M98090_MIXSPL_DACR_WIDTH 1922#define M98090_MIXSPL_DACL_MASK (1<<0)923#define M98090_MIXSPL_DACL_SHIFT 0924#define M98090_MIXSPL_DACL_WIDTH 1925#define M98090_MIXSPL_MASK (63<<0)926#define M98090_MIXSPL_SHIFT 0927#define M98090_MIXSPL_WIDTH 6928#define M98090_MIXSPR_DACR_MASK (1<<1)929#define M98090_MIXSPR_DACR_SHIFT 1930#define M98090_MIXSPR_DACR_WIDTH 1931 932 933/*934 * M98090_REG_RIGHT_SPK_MIXER935 */936#define M98090_SPK_SLAVE_MASK (1<<6)937#define M98090_SPK_SLAVE_SHIFT 6938#define M98090_SPK_SLAVE_WIDTH 1939#define M98090_MIXSPR_MIC2_MASK (1<<5)940#define M98090_MIXSPR_MIC2_SHIFT 5941#define M98090_MIXSPR_MIC2_WIDTH 1942#define M98090_MIXSPR_MIC1_MASK (1<<4)943#define M98090_MIXSPR_MIC1_SHIFT 4944#define M98090_MIXSPR_MIC1_WIDTH 1945#define M98090_MIXSPR_LINEB_MASK (1<<3)946#define M98090_MIXSPR_LINEB_SHIFT 3947#define M98090_MIXSPR_LINEB_WIDTH 1948#define M98090_MIXSPR_LINEA_MASK (1<<2)949#define M98090_MIXSPR_LINEA_SHIFT 2950#define M98090_MIXSPR_LINEA_WIDTH 1951#define M98090_MIXSPR_DACR_MASK (1<<1)952#define M98090_MIXSPR_DACR_SHIFT 1953#define M98090_MIXSPR_DACR_WIDTH 1954#define M98090_MIXSPR_DACL_MASK (1<<0)955#define M98090_MIXSPR_DACL_SHIFT 0956#define M98090_MIXSPR_DACL_WIDTH 1957#define M98090_MIXSPR_MASK (63<<0)958#define M98090_MIXSPR_SHIFT 0959#define M98090_MIXSPR_WIDTH 6960 961/*962 * M98090_REG_SPK_CONTROL963 */964#define M98090_MIXSPRG_MASK (3<<2)965#define M98090_MIXSPRG_SHIFT 2966#define M98090_MIXSPRG_WIDTH 2967#define M98090_MIXSPRG_NUM (1<<M98090_MIXSPRG_WIDTH)968#define M98090_MIXSPLG_MASK (3<<0)969#define M98090_MIXSPLG_SHIFT 0970#define M98090_MIXSPLG_WIDTH 2971#define M98090_MIXSPLG_NUM (1<<M98090_MIXSPLG_WIDTH)972 973/*974 * M98090_REG_LEFT_SPK_VOLUME975 */976#define M98090_SPLM_MASK (1<<7)977#define M98090_SPLM_SHIFT 7978#define M98090_SPLM_WIDTH 1979#define M98090_SPVOLL_MASK (63<<0)980#define M98090_SPVOLL_SHIFT 0981#define M98090_SPVOLL_WIDTH 6982#define M98090_SPVOLL_NUM 40983 984/*985 * M98090_REG_RIGHT_SPK_VOLUME986 */987#define M98090_SPRM_MASK (1<<7)988#define M98090_SPRM_SHIFT 7989#define M98090_SPRM_WIDTH 1990#define M98090_SPVOLR_MASK (63<<0)991#define M98090_SPVOLR_SHIFT 0992#define M98090_SPVOLR_WIDTH 6993#define M98090_SPVOLR_NUM 40994 995/*996 * M98090_REG_DRC_TIMING997 */998#define M98090_DRCEN_MASK (1<<7)999#define M98090_DRCEN_SHIFT 71000#define M98090_DRCEN_WIDTH 11001#define M98090_DRCEN_NUM (1<<M98090_DRCEN_WIDTH)1002#define M98090_DRCRLS_MASK (7<<4)1003#define M98090_DRCRLS_SHIFT 41004#define M98090_DRCRLS_WIDTH 31005#define M98090_DRCATK_MASK (7<<0)1006#define M98090_DRCATK_SHIFT 01007#define M98090_DRCATK_WIDTH 31008 1009/*1010 * M98090_REG_DRC_COMPRESSOR1011 */1012#define M98090_DRCCMP_MASK (7<<5)1013#define M98090_DRCCMP_SHIFT 51014#define M98090_DRCCMP_WIDTH 31015#define M98090_DRCTHC_MASK (31<<0)1016#define M98090_DRCTHC_SHIFT 01017#define M98090_DRCTHC_WIDTH 51018#define M98090_DRCTHC_NUM (1<<M98090_DRCTHC_WIDTH)1019 1020/*1021 * M98090_REG_DRC_EXPANDER1022 */1023#define M98090_DRCEXP_MASK (7<<5)1024#define M98090_DRCEXP_SHIFT 51025#define M98090_DRCEXP_WIDTH 31026#define M98090_DRCTHE_MASK (31<<0)1027#define M98090_DRCTHE_SHIFT 01028#define M98090_DRCTHE_WIDTH 51029#define M98090_DRCTHE_NUM (1<<M98090_DRCTHE_WIDTH)1030 1031/*1032 * M98090_REG_DRC_GAIN1033 */1034#define M98090_DRCG_MASK (31<<0)1035#define M98090_DRCG_SHIFT 01036#define M98090_DRCG_WIDTH 51037#define M98090_DRCG_NUM 131038 1039/*1040 * M98090_REG_RCV_LOUTL_MIXER1041 */1042#define M98090_MIXRCVL_MIC2_MASK (1<<5)1043#define M98090_MIXRCVL_MIC2_SHIFT 51044#define M98090_MIXRCVL_MIC2_WIDTH 11045#define M98090_MIXRCVL_MIC1_MASK (1<<4)1046#define M98090_MIXRCVL_MIC1_SHIFT 41047#define M98090_MIXRCVL_MIC1_WIDTH 11048#define M98090_MIXRCVL_LINEB_MASK (1<<3)1049#define M98090_MIXRCVL_LINEB_SHIFT 31050#define M98090_MIXRCVL_LINEB_WIDTH 11051#define M98090_MIXRCVL_LINEA_MASK (1<<2)1052#define M98090_MIXRCVL_LINEA_SHIFT 21053#define M98090_MIXRCVL_LINEA_WIDTH 11054#define M98090_MIXRCVL_DACR_MASK (1<<1)1055#define M98090_MIXRCVL_DACR_SHIFT 11056#define M98090_MIXRCVL_DACR_WIDTH 11057#define M98090_MIXRCVL_DACL_MASK (1<<0)1058#define M98090_MIXRCVL_DACL_SHIFT 01059#define M98090_MIXRCVL_DACL_WIDTH 11060#define M98090_MIXRCVL_MASK (63<<0)1061#define M98090_MIXRCVL_SHIFT 01062#define M98090_MIXRCVL_WIDTH 61063 1064/*1065 * M98090_REG_RCV_LOUTL_CONTROL1066 */1067#define M98090_MIXRCVLG_MASK (3<<0)1068#define M98090_MIXRCVLG_SHIFT 01069#define M98090_MIXRCVLG_WIDTH 21070#define M98090_MIXRCVLG_NUM (1<<M98090_MIXRCVLG_WIDTH)1071 1072/*1073 * M98090_REG_RCV_LOUTL_VOLUME1074 */1075#define M98090_RCVLM_MASK (1<<7)1076#define M98090_RCVLM_SHIFT 71077#define M98090_RCVLM_WIDTH 11078#define M98090_RCVLVOL_MASK (31<<0)1079#define M98090_RCVLVOL_SHIFT 01080#define M98090_RCVLVOL_WIDTH 51081#define M98090_RCVLVOL_NUM (1<<M98090_RCVLVOL_WIDTH)1082 1083/*1084 * M98090_REG_LOUTR_MIXER1085 */1086#define M98090_LINMOD_MASK (1<<7)1087#define M98090_LINMOD_SHIFT 71088#define M98090_LINMOD_WIDTH 11089#define M98090_MIXRCVR_MIC2_MASK (1<<5)1090#define M98090_MIXRCVR_MIC2_SHIFT 51091#define M98090_MIXRCVR_MIC2_WIDTH 11092#define M98090_MIXRCVR_MIC1_MASK (1<<4)1093#define M98090_MIXRCVR_MIC1_SHIFT 41094#define M98090_MIXRCVR_MIC1_WIDTH 11095#define M98090_MIXRCVR_LINEB_MASK (1<<3)1096#define M98090_MIXRCVR_LINEB_SHIFT 31097#define M98090_MIXRCVR_LINEB_WIDTH 11098#define M98090_MIXRCVR_LINEA_MASK (1<<2)1099#define M98090_MIXRCVR_LINEA_SHIFT 21100#define M98090_MIXRCVR_LINEA_WIDTH 11101#define M98090_MIXRCVR_DACR_MASK (1<<1)1102#define M98090_MIXRCVR_DACR_SHIFT 11103#define M98090_MIXRCVR_DACR_WIDTH 11104#define M98090_MIXRCVR_DACL_MASK (1<<0)1105#define M98090_MIXRCVR_DACL_SHIFT 01106#define M98090_MIXRCVR_DACL_WIDTH 11107#define M98090_MIXRCVR_MASK (63<<0)1108#define M98090_MIXRCVR_SHIFT 01109#define M98090_MIXRCVR_WIDTH 61110 1111/*1112 * M98090_REG_LOUTR_CONTROL1113 */1114#define M98090_MIXRCVRG_MASK (3<<0)1115#define M98090_MIXRCVRG_SHIFT 01116#define M98090_MIXRCVRG_WIDTH 21117#define M98090_MIXRCVRG_NUM (1<<M98090_MIXRCVRG_WIDTH)1118 1119/*1120 * M98090_REG_LOUTR_VOLUME1121 */1122#define M98090_RCVRM_MASK (1<<7)1123#define M98090_RCVRM_SHIFT 71124#define M98090_RCVRM_WIDTH 11125#define M98090_RCVRVOL_MASK (31<<0)1126#define M98090_RCVRVOL_SHIFT 01127#define M98090_RCVRVOL_WIDTH 51128#define M98090_RCVRVOL_NUM (1<<M98090_RCVRVOL_WIDTH)1129 1130/*1131 * M98090_REG_JACK_DETECT1132 */1133#define M98090_JDETEN_MASK (1<<7)1134#define M98090_JDETEN_SHIFT 71135#define M98090_JDETEN_WIDTH 11136#define M98090_JDWK_MASK (1<<6)1137#define M98090_JDWK_SHIFT 61138#define M98090_JDWK_WIDTH 11139#define M98090_JDEB_MASK (3<<0)1140#define M98090_JDEB_SHIFT 01141#define M98090_JDEB_WIDTH 21142#define M98090_JDEB_25MS (0<<0)1143#define M98090_JDEB_50MS (1<<0)1144#define M98090_JDEB_100MS (2<<0)1145#define M98090_JDEB_200MS (3<<0)1146 1147/*1148 * M98090_REG_INPUT_ENABLE1149 */1150#define M98090_MBEN_MASK (1<<4)1151#define M98090_MBEN_SHIFT 41152#define M98090_MBEN_WIDTH 11153#define M98090_LINEAEN_MASK (1<<3)1154#define M98090_LINEAEN_SHIFT 31155#define M98090_LINEAEN_WIDTH 11156#define M98090_LINEBEN_MASK (1<<2)1157#define M98090_LINEBEN_SHIFT 21158#define M98090_LINEBEN_WIDTH 11159#define M98090_ADREN_MASK (1<<1)1160#define M98090_ADREN_SHIFT 11161#define M98090_ADREN_WIDTH 11162#define M98090_ADLEN_MASK (1<<0)1163#define M98090_ADLEN_SHIFT 01164#define M98090_ADLEN_WIDTH 11165 1166/*1167 * M98090_REG_OUTPUT_ENABLE1168 */1169#define M98090_HPREN_MASK (1<<7)1170#define M98090_HPREN_SHIFT 71171#define M98090_HPREN_WIDTH 11172#define M98090_HPLEN_MASK (1<<6)1173#define M98090_HPLEN_SHIFT 61174#define M98090_HPLEN_WIDTH 11175#define M98090_SPREN_MASK (1<<5)1176#define M98090_SPREN_SHIFT 51177#define M98090_SPREN_WIDTH 11178#define M98090_SPLEN_MASK (1<<4)1179#define M98090_SPLEN_SHIFT 41180#define M98090_SPLEN_WIDTH 11181#define M98090_RCVLEN_MASK (1<<3)1182#define M98090_RCVLEN_SHIFT 31183#define M98090_RCVLEN_WIDTH 11184#define M98090_RCVREN_MASK (1<<2)1185#define M98090_RCVREN_SHIFT 21186#define M98090_RCVREN_WIDTH 11187#define M98090_DAREN_MASK (1<<1)1188#define M98090_DAREN_SHIFT 11189#define M98090_DAREN_WIDTH 11190#define M98090_DALEN_MASK (1<<0)1191#define M98090_DALEN_SHIFT 01192#define M98090_DALEN_WIDTH 11193 1194/*1195 * M98090_REG_LEVEL_CONTROL1196 */1197#define M98090_ZDENN_MASK (1<<2)1198#define M98090_ZDENN_SHIFT 21199#define M98090_ZDENN_WIDTH 11200#define M98090_ZDENN_NUM (1<<M98090_ZDENN_WIDTH)1201#define M98090_VS2ENN_MASK (1<<1)1202#define M98090_VS2ENN_SHIFT 11203#define M98090_VS2ENN_WIDTH 11204#define M98090_VS2ENN_NUM (1<<M98090_VS2ENN_WIDTH)1205#define M98090_VSENN_MASK (1<<0)1206#define M98090_VSENN_SHIFT 01207#define M98090_VSENN_WIDTH 11208#define M98090_VSENN_NUM (1<<M98090_VSENN_WIDTH)1209 1210/*1211 * M98090_REG_DSP_FILTER_ENABLE1212 */1213#define M98090_DMIC34BQEN_MASK (1<<4)1214#define M98090_DMIC34BQEN_SHIFT 41215#define M98090_DMIC34BQEN_WIDTH 11216#define M98090_DMIC34BQEN_NUM (1<<M98090_DMIC34BQEN_WIDTH)1217#define M98090_ADCBQEN_MASK (1<<3)1218#define M98090_ADCBQEN_SHIFT 31219#define M98090_ADCBQEN_WIDTH 11220#define M98090_ADCBQEN_NUM (1<<M98090_ADCBQEN_WIDTH)1221#define M98090_EQ3BANDEN_MASK (1<<2)1222#define M98090_EQ3BANDEN_SHIFT 21223#define M98090_EQ3BANDEN_WIDTH 11224#define M98090_EQ3BANDEN_NUM (1<<M98090_EQ3BANDEN_WIDTH)1225#define M98090_EQ5BANDEN_MASK (1<<1)1226#define M98090_EQ5BANDEN_SHIFT 11227#define M98090_EQ5BANDEN_WIDTH 11228#define M98090_EQ5BANDEN_NUM (1<<M98090_EQ5BANDEN_WIDTH)1229#define M98090_EQ7BANDEN_MASK (1<<0)1230#define M98090_EQ7BANDEN_SHIFT 01231#define M98090_EQ7BANDEN_WIDTH 11232#define M98090_EQ7BANDEN_NUM (1<<M98090_EQ7BANDEN_WIDTH)1233 1234/*1235 * M98090_REG_BIAS_CONTROL1236 */1237#define M98090_VCM_MODE_MASK (1<<0)1238#define M98090_VCM_MODE_SHIFT 01239#define M98090_VCM_MODE_WIDTH 11240#define M98090_VCM_MODE_NUM (1<<M98090_VCM_MODE_WIDTH)1241 1242/*1243 * M98090_REG_DAC_CONTROL1244 */1245#define M98090_PERFMODE_MASK (1<<1)1246#define M98090_PERFMODE_SHIFT 11247#define M98090_PERFMODE_WIDTH 11248#define M98090_PERFMODE_NUM (1<<M98090_PERFMODE_WIDTH)1249#define M98090_DACHP_MASK (1<<0)1250#define M98090_DACHP_SHIFT 01251#define M98090_DACHP_WIDTH 11252#define M98090_DACHP_NUM (1<<M98090_DACHP_WIDTH)1253 1254/*1255 * M98090_REG_ADC_CONTROL1256 */1257#define M98090_OSR128_MASK (1<<2)1258#define M98090_OSR128_SHIFT 21259#define M98090_OSR128_WIDTH 11260#define M98090_ADCDITHER_MASK (1<<1)1261#define M98090_ADCDITHER_SHIFT 11262#define M98090_ADCDITHER_WIDTH 11263#define M98090_ADCDITHER_NUM (1<<M98090_ADCDITHER_WIDTH)1264#define M98090_ADCHP_MASK (1<<0)1265#define M98090_ADCHP_SHIFT 01266#define M98090_ADCHP_WIDTH 11267#define M98090_ADCHP_NUM (1<<M98090_ADCHP_WIDTH)1268 1269/*1270 * M98090_REG_DEVICE_SHUTDOWN1271 */1272#define M98090_SHDNN_MASK (1<<7)1273#define M98090_SHDNN_SHIFT 71274#define M98090_SHDNN_WIDTH 11275 1276/*1277 * M98090_REG_EQUALIZER_BASE1278 */1279#define M98090_B0_1_HI_MASK (255<<0)1280#define M98090_B0_1_HI_SHIFT 01281#define M98090_B0_1_HI_WIDTH 81282#define M98090_B0_1_MID_MASK (255<<0)1283#define M98090_B0_1_MID_SHIFT 01284#define M98090_B0_1_MID_WIDTH 81285#define M98090_B0_1_LO_MASK (255<<0)1286#define M98090_B0_1_LO_SHIFT 01287#define M98090_B0_1_LO_WIDTH 81288#define M98090_B1_1_HI_MASK (255<<0)1289#define M98090_B1_1_HI_SHIFT 01290#define M98090_B1_1_HI_WIDTH 81291#define M98090_B1_1_MID_MASK (255<<0)1292#define M98090_B1_1_MID_SHIFT 01293#define M98090_B1_1_MID_WIDTH 81294#define M98090_B1_1_LO_MASK (255<<0)1295#define M98090_B1_1_LO_SHIFT 01296#define M98090_B1_1_LO_WIDTH 81297#define M98090_B2_1_HI_MASK (255<<0)1298#define M98090_B2_1_HI_SHIFT 01299#define M98090_B2_1_HI_WIDTH 81300#define M98090_B2_1_MID_MASK (255<<0)1301#define M98090_B2_1_MID_SHIFT 01302#define M98090_B2_1_MID_WIDTH 81303#define M98090_B2_1_LO_MASK (255<<0)1304#define M98090_B2_1_LO_SHIFT 01305#define M98090_B2_1_LO_WIDTH 81306#define M98090_A1_1_HI_MASK (255<<0)1307#define M98090_A1_1_HI_SHIFT 01308#define M98090_A1_1_HI_WIDTH 81309#define M98090_A1_1_MID_MASK (255<<0)1310#define M98090_A1_1_MID_SHIFT 01311#define M98090_A1_1_MID_WIDTH 81312#define M98090_A1_1_LO_MASK (255<<0)1313#define M98090_A1_1_LO_SHIFT 01314#define M98090_A1_1_LO_WIDTH 81315#define M98090_A2_1_HI_MASK (255<<0)1316#define M98090_A2_1_HI_SHIFT 01317#define M98090_A2_1_HI_WIDTH 81318#define M98090_A2_1_MID_MASK (255<<0)1319#define M98090_A2_1_MID_SHIFT 01320#define M98090_A2_1_MID_WIDTH 81321#define M98090_A2_1_LO_MASK (255<<0)1322#define M98090_A2_1_LO_SHIFT 01323#define M98090_A2_1_LO_WIDTH 81324 1325#define M98090_COEFS_PER_BAND 51326#define M98090_COEFS_BLK_SZ (M98090_COEFS_PER_BAND * 3)1327#define M98090_COEFS_MAX_SZ (M98090_COEFS_BLK_SZ * 7)1328 1329/*1330 * M98090_REG_RECORD_BIQUAD_BASE1331 */1332#define M98090_REC_B0_HI_MASK (255<<0)1333#define M98090_REC_B0_HI_SHIFT 01334#define M98090_REC_B0_HI_WIDTH 81335#define M98090_REC_B0_MID_MASK (255<<0)1336#define M98090_REC_B0_MID_SHIFT 01337#define M98090_REC_B0_MID_WIDTH 81338#define M98090_REC_B0_LO_MASK (255<<0)1339#define M98090_REC_B0_LO_SHIFT 01340#define M98090_REC_B0_LO_WIDTH 81341#define M98090_REC_B1_HI_MASK (255<<0)1342#define M98090_REC_B1_HI_SHIFT 01343#define M98090_REC_B1_HI_WIDTH 81344#define M98090_REC_B1_MID_MASK (255<<0)1345#define M98090_REC_B1_MID_SHIFT 01346#define M98090_REC_B1_MID_WIDTH 81347#define M98090_REC_B1_LO_MASK (255<<0)1348#define M98090_REC_B1_LO_SHIFT 01349#define M98090_REC_B1_LO_WIDTH 81350#define M98090_REC_B2_HI_MASK (255<<0)1351#define M98090_REC_B2_HI_SHIFT 01352#define M98090_REC_B2_HI_WIDTH 81353#define M98090_REC_B2_MID_MASK (255<<0)1354#define M98090_REC_B2_MID_SHIFT 01355#define M98090_REC_B2_MID_WIDTH 81356#define M98090_REC_B2_LO_MASK (255<<0)1357#define M98090_REC_B2_LO_SHIFT 01358#define M98090_REC_B2_LO_WIDTH 81359#define M98090_REC_A1_HI_MASK (255<<0)1360#define M98090_REC_A1_HI_SHIFT 01361#define M98090_REC_A1_HI_WIDTH 81362#define M98090_REC_A1_MID_MASK (255<<0)1363#define M98090_REC_A1_MID_SHIFT 01364#define M98090_REC_A1_MID_WIDTH 81365#define M98090_REC_A1_LO_MASK (255<<0)1366#define M98090_REC_A1_LO_SHIFT 01367#define M98090_REC_A1_LO_WIDTH 81368#define M98090_REC_A2_HI_MASK (255<<0)1369#define M98090_REC_A2_HI_SHIFT 01370#define M98090_REC_A2_HI_WIDTH 81371#define M98090_REC_A2_MID_MASK (255<<0)1372#define M98090_REC_A2_MID_SHIFT 01373#define M98090_REC_A2_MID_WIDTH 81374#define M98090_REC_A2_LO_MASK (255<<0)1375#define M98090_REC_A2_LO_SHIFT 01376#define M98090_REC_A2_LO_WIDTH 81377 1378/*1379 * M98090_REG_DMIC3_VOLUME1380 */1381#define M98090_DMIC_AV3G_MASK (7<<4)1382#define M98090_DMIC_AV3G_SHIFT 41383#define M98090_DMIC_AV3G_WIDTH 31384#define M98090_DMIC_AV3G_NUM (1<<M98090_DMIC_AV3G_WIDTH)1385#define M98090_DMIC_AV3_MASK (15<<0)1386#define M98090_DMIC_AV3_SHIFT 01387#define M98090_DMIC_AV3_WIDTH 41388#define M98090_DMIC_AV3_NUM (1<<M98090_DMIC_AV3_WIDTH)1389 1390/*1391 * M98090_REG_DMIC4_VOLUME1392 */1393#define M98090_DMIC_AV4G_MASK (7<<4)1394#define M98090_DMIC_AV4G_SHIFT 41395#define M98090_DMIC_AV4G_WIDTH 31396#define M98090_DMIC_AV4G_NUM (1<<M98090_DMIC_AV4G_WIDTH)1397#define M98090_DMIC_AV4_MASK (15<<0)1398#define M98090_DMIC_AV4_SHIFT 01399#define M98090_DMIC_AV4_WIDTH 41400#define M98090_DMIC_AV4_NUM (1<<M98090_DMIC_AV4_WIDTH)1401 1402/*1403 * M98090_REG_DMIC34_BQ_PREATTEN1404 */1405#define M98090_AV34BQ_MASK (15<<0)1406#define M98090_AV34BQ_SHIFT 01407#define M98090_AV34BQ_WIDTH 41408#define M98090_AV34BQ_NUM (1<<M98090_AV34BQ_WIDTH)1409 1410/*1411 * M98090_REG_RECORD_TDM_SLOT1412 */1413#define M98090_TDM_SLOTADCL_MASK (3<<6)1414#define M98090_TDM_SLOTADCL_SHIFT 61415#define M98090_TDM_SLOTADCL_WIDTH 21416#define M98090_TDM_SLOTADCL_NUM (1<<M98090_TDM_SLOTADCL_WIDTH)1417#define M98090_TDM_SLOTADCR_MASK (3<<4)1418#define M98090_TDM_SLOTADCR_SHIFT 41419#define M98090_TDM_SLOTADCR_WIDTH 21420#define M98090_TDM_SLOTADCR_NUM (1<<M98090_TDM_SLOTADCR_WIDTH)1421#define M98090_TDM_SLOTDMIC3_MASK (3<<2)1422#define M98090_TDM_SLOTDMIC3_SHIFT 21423#define M98090_TDM_SLOTDMIC3_WIDTH 21424#define M98090_TDM_SLOTDMIC3_NUM (1<<M98090_TDM_SLOTDMIC3_WIDTH)1425#define M98090_TDM_SLOTDMIC4_MASK (3<<0)1426#define M98090_TDM_SLOTDMIC4_SHIFT 01427#define M98090_TDM_SLOTDMIC4_WIDTH 21428#define M98090_TDM_SLOTDMIC4_NUM (1<<M98090_TDM_SLOTDMIC4_WIDTH)1429 1430/*1431 * M98090_REG_SAMPLE_RATE1432 */1433#define M98090_DMIC34_ZEROPAD_MASK (1<<4)1434#define M98090_DMIC34_ZEROPAD_SHIFT 41435#define M98090_DMIC34_ZEROPAD_WIDTH 11436#define M98090_DMIC34_ZEROPAD_NUM (1<<M98090_DIGMIC4_WIDTH)1437#define M98090_DMIC34_SRDIV_MASK (7<<0)1438#define M98090_DMIC34_SRDIV_SHIFT 01439#define M98090_DMIC34_SRDIV_WIDTH 31440 1441/*1442 * M98090_REG_DMIC34_BIQUAD_BASE1443 */1444#define M98090_DMIC34_B0_HI_MASK (255<<0)1445#define M98090_DMIC34_B0_HI_SHIFT 01446#define M98090_DMIC34_B0_HI_WIDTH 81447#define M98090_DMIC34_B0_MID_MASK (255<<0)1448#define M98090_DMIC34_B0_MID_SHIFT 01449#define M98090_DMIC34_B0_MID_WIDTH 81450#define M98090_DMIC34_B0_LO_MASK (255<<0)1451#define M98090_DMIC34_B0_LO_SHIFT 01452#define M98090_DMIC34_B0_LO_WIDTH 81453#define M98090_DMIC34_B1_HI_MASK (255<<0)1454#define M98090_DMIC34_B1_HI_SHIFT 01455#define M98090_DMIC34_B1_HI_WIDTH 81456#define M98090_DMIC34_B1_MID_MASK (255<<0)1457#define M98090_DMIC34_B1_MID_SHIFT 01458#define M98090_DMIC34_B1_MID_WIDTH 81459#define M98090_DMIC34_B1_LO_MASK (255<<0)1460#define M98090_DMIC34_B1_LO_SHIFT 01461#define M98090_DMIC34_B1_LO_WIDTH 81462#define M98090_DMIC34_B2_HI_MASK (255<<0)1463#define M98090_DMIC34_B2_HI_SHIFT 01464#define M98090_DMIC34_B2_HI_WIDTH 81465#define M98090_DMIC34_B2_MID_MASK (255<<0)1466#define M98090_DMIC34_B2_MID_SHIFT 01467#define M98090_DMIC34_B2_MID_WIDTH 81468#define M98090_DMIC34_B2_LO_MASK (255<<0)1469#define M98090_DMIC34_B2_LO_SHIFT 01470#define M98090_DMIC34_B2_LO_WIDTH 81471#define M98090_DMIC34_A1_HI_MASK (255<<0)1472#define M98090_DMIC34_A1_HI_SHIFT 01473#define M98090_DMIC34_A1_HI_WIDTH 81474#define M98090_DMIC34_A1_MID_MASK (255<<0)1475#define M98090_DMIC34_A1_MID_SHIFT 01476#define M98090_DMIC34_A1_MID_WIDTH 81477#define M98090_DMIC34_A1_LO_MASK (255<<0)1478#define M98090_DMIC34_A1_LO_SHIFT 01479#define M98090_DMIC34_A1_LO_WIDTH 81480#define M98090_DMIC34_A2_HI_MASK (255<<0)1481#define M98090_DMIC34_A2_HI_SHIFT 01482#define M98090_DMIC34_A2_HI_WIDTH 81483#define M98090_DMIC34_A2_MID_MASK (255<<0)1484#define M98090_DMIC34_A2_MID_SHIFT 01485#define M98090_DMIC34_A2_MID_WIDTH 81486#define M98090_DMIC34_A2_LO_MASK (255<<0)1487#define M98090_DMIC34_A2_LO_SHIFT 01488#define M98090_DMIC34_A2_LO_WIDTH 81489 1490#define M98090_JACK_STATE_NO_HEADSET 01491#define M98090_JACK_STATE_NO_HEADSET_2 11492#define M98090_JACK_STATE_HEADPHONE 21493#define M98090_JACK_STATE_HEADSET 31494 1495/*1496 * M98090_REG_REVISION_ID1497 */1498#define M98090_REVID_MASK (255<<0)1499#define M98090_REVID_SHIFT 01500#define M98090_REVID_WIDTH 81501#define M98090_REVID_NUM (1<<M98090_REVID_WIDTH)1502 1503/* Silicon revision number */1504#define M98090_REVA 0x401505#define M98091_REVA 0x501506 1507enum max98090_type {1508 MAX98090,1509 MAX98091,1510};1511 1512struct max98090_cdata {1513 unsigned int rate;1514 unsigned int fmt;1515};1516 1517struct max98090_priv {1518 struct regmap *regmap;1519 struct snd_soc_component *component;1520 enum max98090_type devtype;1521 struct max98090_pdata *pdata;1522 struct clk *mclk;1523 unsigned int sysclk;1524 unsigned int pclk;1525 unsigned int bclk;1526 unsigned int lrclk;1527 u32 dmic_freq;1528 struct max98090_cdata dai[1];1529 int jack_state;1530 struct delayed_work jack_work;1531 struct delayed_work pll_det_enable_work;1532 struct work_struct pll_det_disable_work;1533 struct snd_soc_jack *jack;1534 unsigned int dai_fmt;1535 int tdm_slots;1536 int tdm_lslot;1537 int tdm_rslot;1538 u8 lin_state;1539 unsigned int pa1en;1540 unsigned int pa2en;1541 unsigned int sidetone;1542 bool master;1543 bool shdn_pending;1544};1545 1546int max98090_mic_detect(struct snd_soc_component *component,1547 struct snd_soc_jack *jack);1548 1549#endif1550