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1/* SPDX-License-Identifier: GPL-2.0-only */2/* Copyright (c) 2020 Maxim Integrated */3 4#ifndef _MAX98373_SDW_H5#define _MAX98373_SDW_H6 7#include "max98373.h"8 9/* SoundWire Slave Control Port (SCP) */10#define MAX98373_R0040_SCP_INIT_STAT_1 0x004011#define MAX98373_R0041_SCP_INIT_MASK_1 0x004112#define MAX98373_R0042_SCP_INIT_STAT_2 0x004213#define MAX98373_R0044_SCP_CTRL 0x004414#define MAX98373_R0045_SCP_SYSTEM_CTRL 0x004515#define MAX98373_R0046_SCP_DEV_NUMBER 0x004616#define MAX98373_R0050_SCP_DEV_ID_0 0x005017#define MAX98373_R0051_SCP_DEV_ID_1 0x005118#define MAX98373_R0052_SCP_DEV_ID_2 0x005219#define MAX98373_R0053_SCP_DEV_ID_3 0x005320#define MAX98373_R0054_SCP_DEV_ID_4 0x005421#define MAX98373_R0055_SCP_DEV_ID_5 0x005522#define MAX98373_R0060_SCP_FRAME_CTLR 0x006023#define MAX98373_R0070_SCP_FRAME_CTLR 0x007024 25/* SoundWire Device Data Port (DP) */26/* Data Port 1 Registers */27#define MAX98373_R0100_DP1_INIT_STAT 0x010028#define MAX98373_R0101_DP1_INIT_MASK 0x010129#define MAX98373_R0102_DP1_PORT_CTRL 0x010230#define MAX98373_R0103_DP1_BLOCK_CTRL_1 0x010331#define MAX98373_R0104_DP1_PREPARE_STATUS 0x010432#define MAX98373_R0105_DP1_PREPARE_CTRL 0x010533/* Data Port 1 Bank 0 Registers */34#define MAX98373_R0120_DP1_CHANNEL_EN 0x012035#define MAX98373_R0122_DP1_SAMPLE_CTRL1 0x012236#define MAX98373_R0123_DP1_SAMPLE_CTRL2 0x012337#define MAX98373_R0124_DP1_OFFSET_CTRL1 0x012438#define MAX98373_R0125_DP1_OFFSET_CTRL2 0x012539#define MAX98373_R0126_DP1_HCTRL 0x012640#define MAX98373_R0127_DP1_BLOCK_CTRL3 0x012741/* Data Port 1 Bank 1 Registers */42#define MAX98373_R0130_DP1_CHANNEL_EN 0x013043#define MAX98373_R0132_DP1_SAMPLE_CTRL1 0x013244#define MAX98373_R0133_DP1_SAMPLE_CTRL2 0x013345#define MAX98373_R0134_DP1_OFFSET_CTRL1 0x013446#define MAX98373_R0135_DP1_OFFSET_CTRL2 0x013547#define MAX98373_R0136_DP1_HCTRL 0x013648#define MAX98373_R0137_DP1_BLOCK_CTRL3 0x013749/* Data Port 3 Registers */50#define MAX98373_R0300_DP3_INIT_STAT 0x030051#define MAX98373_R0301_DP3_INIT_MASK 0x030152#define MAX98373_R0302_DP3_PORT_CTRL 0x030253#define MAX98373_R0303_DP3_BLOCK_CTRL_1 0x030354#define MAX98373_R0304_DP3_PREPARE_STATUS 0x030455#define MAX98373_R0305_DP3_PREPARE_CTRL 0x030556/* Data Port 3 Bank 0 Registers */57#define MAX98373_R0320_DP3_CHANNEL_EN 0x032058#define MAX98373_R0322_DP3_SAMPLE_CTRL1 0x032259#define MAX98373_R0323_DP3_SAMPLE_CTRL2 0x032360#define MAX98373_R0324_DP3_OFFSET_CTRL1 0x032461#define MAX98373_R0325_DP3_OFFSET_CTRL2 0x032562#define MAX98373_R0326_DP3_HCTRL 0x032663#define MAX98373_R0327_DP3_BLOCK_CTRL3 0x032764/* Data Port 3 Bank 1 Registers */65#define MAX98373_R0330_DP3_CHANNEL_EN 0x033066#define MAX98373_R0332_DP3_SAMPLE_CTRL1 0x033267#define MAX98373_R0333_DP3_SAMPLE_CTRL2 0x033368#define MAX98373_R0334_DP3_OFFSET_CTRL1 0x033469#define MAX98373_R0335_DP3_OFFSET_CTRL2 0x033570#define MAX98373_R0336_DP3_HCTRL 0x033671#define MAX98373_R0337_DP3_BLOCK_CTRL3 0x033772#endif73