160 lines · c
1/* SPDX-License-Identifier: GPL-2.0 */2/*3 * Copyright (c) 2021, Maxim Integrated.4 */5 6#ifndef _MAX98520_H7#define _MAX98520_H8 9#define MAX98520_R2000_SW_RESET 0x200010#define MAX98520_R2001_STATUS_1 0x200111#define MAX98520_R2002_STATUS_2 0x200212#define MAX98520_R2020_THERM_WARN_THRESH 0x202013#define MAX98520_R2021_THERM_SHDN_THRESH 0x202114#define MAX98520_R2022_THERM_HYSTERESIS 0x202215#define MAX98520_R2023_THERM_FOLDBACK_SET 0x202316#define MAX98520_R2027_THERM_FOLDBACK_EN 0x202717#define MAX98520_R2030_CLK_MON_CTRL 0x203018#define MAX98520_R2037_ERR_MON_CTRL 0x203719#define MAX98520_R2040_PCM_MODE_CFG 0x204020#define MAX98520_R2041_PCM_CLK_SETUP 0x204121#define MAX98520_R2042_PCM_SR_SETUP 0x204222#define MAX98520_R2043_PCM_RX_SRC1 0x204323#define MAX98520_R2044_PCM_RX_SRC2 0x204424#define MAX98520_R204F_PCM_RX_EN 0x204F25#define MAX98520_R2090_AMP_VOL_CTRL 0x209026#define MAX98520_R2091_AMP_PATH_GAIN 0x209127#define MAX98520_R2092_AMP_DSP_CFG 0x209228#define MAX98520_R2094_SSM_CFG 0x209429#define MAX98520_R2095_AMP_CFG 0x209530#define MAX98520_R209F_AMP_EN 0x209F31#define MAX98520_R20B0_ADC_SR 0x20B032#define MAX98520_R20B1_ADC_RESOLUTION 0x20B133#define MAX98520_R20B2_ADC_PVDD0_CFG 0x20B234#define MAX98520_R20B3_ADC_THERMAL_CFG 0x20B335#define MAX98520_R20B4_ADC_READBACK_CTRL 0x20B436#define MAX98520_R20B5_ADC_READBACK_UPDATE 0x20B537#define MAX98520_R20B6_ADC_PVDD_READBACK_MSB 0x20B638#define MAX98520_R20B7_ADC_PVDD_READBACK_LSB 0x20B739#define MAX98520_R20B8_ADC_TEMP_READBACK_MSB 0x20B840#define MAX98520_R20B9_ADC_TEMP_READBACK_LSB 0x20B941#define MAX98520_R20BA_ADC_LOW_PVDD_READBACK_MSB 0x20BA42#define MAX98520_R20BB_ADC_LOW_READBACK_LSB 0x20BB43#define MAX98520_R20BC_ADC_HIGH_TEMP_READBACK_MSB 0x20BC44#define MAX98520_R20BD_ADC_HIGH_TEMP_READBACK_LSB 0x20BD45#define MAX98520_R20CF_MEAS_ADC_CFG 0x20CF46#define MAX98520_R20D0_DHT_CFG1 0x20D047#define MAX98520_R20D1_LIMITER_CFG1 0x20D148#define MAX98520_R20D2_LIMITER_CFG2 0x20D249#define MAX98520_R20D3_DHT_CFG2 0x20D350#define MAX98520_R20D4_DHT_CFG3 0x20D451#define MAX98520_R20D5_DHT_CFG4 0x20D552#define MAX98520_R20D6_DHT_HYSTERESIS_CFG 0x20D653#define MAX98520_R20D8_DHT_EN 0x20D854#define MAX98520_R210E_AUTO_RESTART_BEHAVIOR 0x210E55#define MAX98520_R210F_GLOBAL_EN 0x210F56#define MAX98520_R2161_BOOST_TM1 0x216157#define MAX98520_R2162_BOOST_TM2 0x216258#define MAX98520_R2163_BOOST_TM3 0x216359#define MAX98520_R21FF_REVISION_ID 0x21FF60 61/* MAX98520_R2030_CLK_MON_CTRL */62#define MAX98520_CMON_AUTORESTART_SHIFT (0)63 64/* MAX98520_R2037_ERR_MON_CTRL */65#define MAX98520_CTRL_CMON_EN_SHIFT (0)66 67/* MAX98520_R2040_PCM_MODE_CFG */68#define MAX98520_PCM_MODE_CFG_FORMAT_MASK (0x7 << 3)69#define MAX98520_PCM_MODE_CFG_FORMAT_SHIFT (3)70#define MAX98520_PCM_TX_CH_INTERLEAVE_MASK (0x1 << 2)71#define MAX98520_PCM_FORMAT_I2S (0x0 << 3)72#define MAX98520_PCM_FORMAT_LJ (0x1 << 3)73#define MAX98520_PCM_FORMAT_TDM_MODE0 (0x3 << 3)74#define MAX98520_PCM_FORMAT_TDM_MODE1 (0x4 << 3)75#define MAX98520_PCM_FORMAT_TDM_MODE2 (0x5 << 3)76#define MAX98520_PCM_MODE_CFG_CHANSZ_MASK (0x3 << 6)77#define MAX98520_PCM_MODE_CFG_CHANSZ_16 (0x1 << 6)78#define MAX98520_PCM_MODE_CFG_CHANSZ_24 (0x2 << 6)79#define MAX98520_PCM_MODE_CFG_CHANSZ_32 (0x3 << 6)80 81/* MAX98520_R2041_PCM_CLK_SETUP */82#define MAX98520_PCM_MODE_CFG_PCM_BCLKEDGE (0x1 << 4)83#define MAX98520_PCM_CLK_SETUP_BSEL_MASK (0xF << 0)84 85/* MAX98520_R2042_PCM_SR_SETUP */86#define MAX98520_PCM_SR_SHIFT (0)87#define MAX98520_IVADC_SR_SHIFT (4)88#define MAX98520_PCM_SR_MASK (0xF << MAX98520_PCM_SR_SHIFT)89#define MAX98520_IVADC_SR_MASK (0xF << MAX98520_IVADC_SR_SHIFT)90#define MAX98520_PCM_SR_8000 (0x0)91#define MAX98520_PCM_SR_11025 (0x1)92#define MAX98520_PCM_SR_12000 (0x2)93#define MAX98520_PCM_SR_16000 (0x3)94#define MAX98520_PCM_SR_22050 (0x4)95#define MAX98520_PCM_SR_24000 (0x5)96#define MAX98520_PCM_SR_32000 (0x6)97#define MAX98520_PCM_SR_44100 (0x7)98#define MAX98520_PCM_SR_48000 (0x8)99#define MAX98520_PCM_SR_88200 (0x9)100#define MAX98520_PCM_SR_96000 (0xA)101#define MAX98520_PCM_SR_176400 (0xB)102#define MAX98520_PCM_SR_192000 (0xC)103 104/* MAX98520_R2044_PCM_RX_SRC2 */105#define MAX98520_PCM_DMIX_CH1_SHIFT (0xF << 0)106#define MAX98520_PCM_DMIX_CH0_SRC_MASK (0xF << 0)107#define MAX98520_PCM_DMIX_CH1_SRC_MASK (0xF << MAX98520_PCM_DMIX_CH1_SHIFT)108 109/* MAX98520_R204F_PCM_RX_EN */110#define MAX98520_PCM_RX_EN_MASK (0x1 << 0)111#define MAX98520_PCM_RX_BYP_EN_MASK (0x1 << 1)112 113/* MAX98520_R2092_AMP_DSP_CFG */114#define MAX98520_DSP_SPK_DCBLK_EN_SHIFT (0)115#define MAX98520_DSP_SPK_DITH_EN_SHIFT (1)116#define MAX98520_DSP_SPK_INVERT_SHIFT (2)117#define MAX98520_DSP_SPK_VOL_RMPUP_SHIFT (3)118#define MAX98520_DSP_SPK_VOL_RMPDN_SHIFT (4)119#define MAX98520_DSP_SPK_SAFE_EN_SHIFT (5)120 121#define MAX98520_SPK_SAFE_EN_MASK (0x1 << MAX98520_DSP_SPK_SAFE_EN_SHIFT)122 123/* MAX98520_R2094_SSM_CFG */124#define MAX98520_SSM_EN_SHIFT (0)125#define MAX98520_SSM_MOD_SHIFT (1)126#define MAX98520_SSM_RCVR_MODE_SHIFT (3)127 128/* MAX98520_R2095_AMP_CFG */129#define MAX98520_CFG_DYN_MODE_SHIFT (4)130#define MAX98520_CFG_SPK_MODE_SHIFT (3)131 132/* MAX98520_R20D0_DHT_CFG1 */133#define MAX98520_DHT_VROT_PNT_SHIFT (0)134 135/* MAX98520_R20D1_LIMITER_CFG1 */136#define MAX98520_DHT_SUPPLY_HR_SHIFT (0)137 138/* MAX98520_R20D2_DHT_CFG2 */139#define MAX98520_DHT_LIMITER_MODE_SHIFT (0)140#define MAX98520_DHT_LIMITER_THRESHOLD_SHIFT (1)141 142/* MAX98520_R20D3_DHT_CFG2 */143#define MAX98520_DHT_MAX_ATTEN_SHIFT (0)144 145/* MAX98520_R20D6_DHT_HYSTERESIS_CFG */146#define MAX98520_DHT_HYSTERESIS_SWITCH_SHIFT (0)147#define MAX98520_DHT_HYSTERESIS_SHIFT (1)148 149/* MAX98520_R20B2_ADC_PVDD0_CFG, MAX98520_R20B3_ADC_THERMAL_CFG */150#define MAX98520_FLT_EN_SHIFT (4)151 152struct max98520_priv {153 struct regmap *regmap;154 struct gpio_desc *reset_gpio;155 unsigned int ch_size;156 bool tdm_mode;157};158#endif159 160