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1/* SPDX-License-Identifier: GPL-2.0-only */2/*3 * Copyright (C) 2011 LAPIS Semiconductor Co., Ltd.4 */5 6#ifndef ML26124_H7#define ML26124_H8 9/* Clock Control Register */10#define ML26124_SMPLING_RATE 0x0011#define ML26124_PLLNL 0x0212#define ML26124_PLLNH 0x0413#define ML26124_PLLML 0x0614#define ML26124_PLLMH 0x0815#define ML26124_PLLDIV 0x0a16#define ML26124_CLK_EN 0x0c17#define ML26124_CLK_CTL 0x0e18 19/* System Control Register */20#define ML26124_SW_RST 0x1021#define ML26124_REC_PLYBAK_RUN 0x1222#define ML26124_MIC_TIM 0x1423 24/* Power Mnagement Register */25#define ML26124_PW_REF_PW_MNG 0x2026#define ML26124_PW_IN_PW_MNG 0x2227#define ML26124_PW_DAC_PW_MNG 0x2428#define ML26124_PW_SPAMP_PW_MNG 0x2629#define ML26124_PW_LOUT_PW_MNG 0x2830#define ML26124_PW_VOUT_PW_MNG 0x2a31#define ML26124_PW_ZCCMP_PW_MNG 0x2e32 33/* Analog Reference Control Register */34#define ML26124_PW_MICBIAS_VOL 0x3035 36/* Input/Output Amplifier Control Register */37#define ML26124_PW_MIC_IN_VOL 0x3238#define ML26124_PW_MIC_BOST_VOL 0x3839#define ML26124_PW_SPK_AMP_VOL 0x3a40#define ML26124_PW_AMP_VOL_FUNC 0x4841#define ML26124_PW_AMP_VOL_FADE 0x4a42 43/* Analog Path Control Register */44#define ML26124_SPK_AMP_OUT 0x5445#define ML26124_MIC_IF_CTL 0x5a46#define ML26124_MIC_SELECT 0xe847 48/* Audio Interface Control Register */49#define ML26124_SAI_TRANS_CTL 0x6050#define ML26124_SAI_RCV_CTL 0x6251#define ML26124_SAI_MODE_SEL 0x6452 53/* DSP Control Register */54#define ML26124_FILTER_EN 0x6655#define ML26124_DVOL_CTL 0x6856#define ML26124_MIXER_VOL_CTL 0x6a57#define ML26124_RECORD_DIG_VOL 0x6c58#define ML26124_PLBAK_DIG_VOL 0x7059#define ML26124_DIGI_BOOST_VOL 0x7260#define ML26124_EQ_GAIN_BRAND0 0x7461#define ML26124_EQ_GAIN_BRAND1 0x7662#define ML26124_EQ_GAIN_BRAND2 0x7863#define ML26124_EQ_GAIN_BRAND3 0x7a64#define ML26124_EQ_GAIN_BRAND4 0x7c65#define ML26124_HPF2_CUTOFF 0x7e66#define ML26124_EQBRAND0_F0L 0x8067#define ML26124_EQBRAND0_F0H 0x8268#define ML26124_EQBRAND0_F1L 0x8469#define ML26124_EQBRAND0_F1H 0x8670#define ML26124_EQBRAND1_F0L 0x8871#define ML26124_EQBRAND1_F0H 0x8a72#define ML26124_EQBRAND1_F1L 0x8c73#define ML26124_EQBRAND1_F1H 0x8e74#define ML26124_EQBRAND2_F0L 0x9075#define ML26124_EQBRAND2_F0H 0x9276#define ML26124_EQBRAND2_F1L 0x9477#define ML26124_EQBRAND2_F1H 0x9678#define ML26124_EQBRAND3_F0L 0x9879#define ML26124_EQBRAND3_F0H 0x9a80#define ML26124_EQBRAND3_F1L 0x9c81#define ML26124_EQBRAND3_F1H 0x9e82#define ML26124_EQBRAND4_F0L 0xa083#define ML26124_EQBRAND4_F0H 0xa284#define ML26124_EQBRAND4_F1L 0xa485#define ML26124_EQBRAND4_F1H 0xa686 87/* ALC Control Register */88#define ML26124_ALC_MODE 0xb089#define ML26124_ALC_ATTACK_TIM 0xb290#define ML26124_ALC_DECAY_TIM 0xb491#define ML26124_ALC_HOLD_TIM 0xb692#define ML26124_ALC_TARGET_LEV 0xb893#define ML26124_ALC_MAXMIN_GAIN 0xba94#define ML26124_NOIS_GATE_THRSH 0xbc95#define ML26124_ALC_ZERO_TIMOUT 0xbe96 97/* Playback Limiter Control Register */98#define ML26124_PL_ATTACKTIME 0xc099#define ML26124_PL_DECAYTIME 0xc2100#define ML26124_PL_TARGETTIME 0xc4101#define ML26124_PL_MAXMIN_GAIN 0xc6102#define ML26124_PLYBAK_BOST_VOL 0xc8103#define ML26124_PL_0CROSS_TIMOUT 0xca104 105/* Video Amplifer Control Register */106#define ML26124_VIDEO_AMP_GAIN_CTL 0xd0107#define ML26124_VIDEO_AMP_SETUP1 0xd2108#define ML26124_VIDEO_AMP_CTL2 0xd4109 110/* Clock select for machine driver */111#define ML26124_USE_PLL 0112#define ML26124_USE_MCLKI_256FS 1113#define ML26124_USE_MCLKI_512FS 2114#define ML26124_USE_MCLKI_1024FS 3115 116/* Register Mask */117#define ML26124_R0_MASK 0xf118#define ML26124_R2_MASK 0xff119#define ML26124_R4_MASK 0x1120#define ML26124_R6_MASK 0xf121#define ML26124_R8_MASK 0x3f122#define ML26124_Ra_MASK 0x1f123#define ML26124_Rc_MASK 0x1f124#define ML26124_Re_MASK 0x7125#define ML26124_R10_MASK 0x1126#define ML26124_R12_MASK 0x17127#define ML26124_R14_MASK 0x3f128#define ML26124_R20_MASK 0x47129#define ML26124_R22_MASK 0xa130#define ML26124_R24_MASK 0x2131#define ML26124_R26_MASK 0x1f132#define ML26124_R28_MASK 0x2133#define ML26124_R2a_MASK 0x2134#define ML26124_R2e_MASK 0x2135#define ML26124_R30_MASK 0x7136#define ML26124_R32_MASK 0x3f137#define ML26124_R38_MASK 0x38138#define ML26124_R3a_MASK 0x3f139#define ML26124_R48_MASK 0x3140#define ML26124_R4a_MASK 0x7141#define ML26124_R54_MASK 0x2a142#define ML26124_R5a_MASK 0x3143#define ML26124_Re8_MASK 0x3144#define ML26124_R60_MASK 0xff145#define ML26124_R62_MASK 0xff146#define ML26124_R64_MASK 0x1147#define ML26124_R66_MASK 0xff148#define ML26124_R68_MASK 0x3b149#define ML26124_R6a_MASK 0xf3150#define ML26124_R6c_MASK 0xff151#define ML26124_R70_MASK 0xff152 153#define ML26124_MCLKEN BIT(0)154#define ML26124_PLLEN BIT(1)155#define ML26124_PLLOE BIT(2)156#define ML26124_MCLKOE BIT(3)157 158#define ML26124_BLT_ALL_ON 0x1f159#define ML26124_BLT_PREAMP_ON 0x13160 161#define ML26124_MICBEN_ON BIT(2)162 163enum ml26124_regs {164 ML26124_MCLK = 0,165};166 167enum ml26124_clk_in {168 ML26124_USE_PLLOUT = 0,169 ML26124_USE_MCLKI,170};171 172#endif173