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1/* SPDX-License-Identifier: GPL-2.0 */2/*3 * Copyright (C) 2020 MediaTek Inc.4 * Author: Argus Lin <argus.lin@mediatek.com>5 */6 7#ifndef _MT6359_H_8#define _MT6359_H_9 10/*************Register Bit Define*************/11#define MT6359_TOP0_ID 0x012#define MT6359_SMT_CON1 0x3213#define MT6359_DRV_CON2 0x3c14#define MT6359_DRV_CON3 0x3e15#define MT6359_DRV_CON4 0x4016#define MT6359_TOP_CKPDN_CON0 0x10c17#define MT6359_TOP_CKPDN_CON0_SET 0x10e18#define MT6359_TOP_CKPDN_CON0_CLR 0x11019#define MT6359_AUXADC_RQST0 0x110820#define MT6359_AUXADC_CON10 0x11a021#define MT6359_AUXADC_ACCDET 0x11ba22#define MT6359_LDO_VUSB_OP_EN 0x1d0c23#define MT6359_LDO_VUSB_OP_EN_SET 0x1d0e24#define MT6359_LDO_VUSB_OP_EN_CLR 0x1d1025#define MT6359_AUD_TOP_CKPDN_CON0 0x230c26#define MT6359_AUD_TOP_CKPDN_CON0_SET 0x230e27#define MT6359_AUD_TOP_CKPDN_CON0_CLR 0x231028#define MT6359_AUD_TOP_RST_CON0 0x232029#define MT6359_AUD_TOP_RST_CON0_SET 0x232230#define MT6359_AUD_TOP_RST_CON0_CLR 0x232431#define MT6359_AUD_TOP_INT_CON0 0x232832#define MT6359_AUD_TOP_INT_CON0_SET 0x232a33#define MT6359_AUD_TOP_INT_CON0_CLR 0x232c34#define MT6359_AUD_TOP_INT_MASK_CON0 0x232e35#define MT6359_AUD_TOP_INT_MASK_CON0_SET 0x233036#define MT6359_AUD_TOP_INT_MASK_CON0_CLR 0x233237#define MT6359_AUD_TOP_INT_STATUS0 0x233438#define MT6359_AFE_NCP_CFG2 0x24e239#define MT6359_AUDENC_DSN_ID 0x250040#define MT6359_AUDENC_DSN_REV0 0x250241#define MT6359_AUDENC_DSN_DBI 0x250442#define MT6359_AUDENC_DSN_FPI 0x250643#define MT6359_AUDENC_ANA_CON0 0x250844#define MT6359_AUDENC_ANA_CON1 0x250a45#define MT6359_AUDENC_ANA_CON2 0x250c46#define MT6359_AUDENC_ANA_CON3 0x250e47#define MT6359_AUDENC_ANA_CON4 0x251048#define MT6359_AUDENC_ANA_CON5 0x251249#define MT6359_AUDENC_ANA_CON6 0x251450#define MT6359_AUDENC_ANA_CON7 0x251651#define MT6359_AUDENC_ANA_CON8 0x251852#define MT6359_AUDENC_ANA_CON9 0x251a53#define MT6359_AUDENC_ANA_CON10 0x251c54#define MT6359_AUDENC_ANA_CON11 0x251e55#define MT6359_AUDENC_ANA_CON12 0x252056#define MT6359_AUDENC_ANA_CON13 0x252257#define MT6359_AUDENC_ANA_CON14 0x252458#define MT6359_AUDENC_ANA_CON15 0x252659#define MT6359_AUDENC_ANA_CON16 0x252860#define MT6359_AUDENC_ANA_CON17 0x252a61#define MT6359_AUDENC_ANA_CON18 0x252c62#define MT6359_AUDENC_ANA_CON19 0x252e63#define MT6359_AUDENC_ANA_CON20 0x253064#define MT6359_AUDENC_ANA_CON21 0x253265#define MT6359_AUDENC_ANA_CON22 0x253466#define MT6359_AUDENC_ANA_CON23 0x253667#define MT6359_AUDDEC_DSN_ID 0x258068#define MT6359_AUDDEC_DSN_REV0 0x258269#define MT6359_AUDDEC_DSN_DBI 0x258470#define MT6359_AUDDEC_DSN_FPI 0x258671#define MT6359_AUDDEC_ANA_CON0 0x258872#define MT6359_AUDDEC_ANA_CON1 0x258a73#define MT6359_AUDDEC_ANA_CON2 0x258c74#define MT6359_AUDDEC_ANA_CON3 0x258e75#define MT6359_AUDDEC_ANA_CON4 0x259076#define MT6359_AUDDEC_ANA_CON5 0x259277#define MT6359_AUDDEC_ANA_CON6 0x259478#define MT6359_AUDDEC_ANA_CON7 0x259679#define MT6359_AUDDEC_ANA_CON8 0x259880#define MT6359_AUDDEC_ANA_CON9 0x259a81#define MT6359_AUDDEC_ANA_CON10 0x259c82#define MT6359_AUDDEC_ANA_CON11 0x259e83#define MT6359_AUDDEC_ANA_CON12 0x25a084#define MT6359_AUDDEC_ANA_CON13 0x25a285#define MT6359_AUDDEC_ANA_CON14 0x25a486#define MT6359_ACCDET_DSN_DIG_ID 0x268087#define MT6359_ACCDET_DSN_DIG_REV0 0x268288#define MT6359_ACCDET_DSN_DBI 0x268489#define MT6359_ACCDET_DSN_FPI 0x268690#define MT6359_ACCDET_CON0 0x268891#define MT6359_ACCDET_CON1 0x268a92#define MT6359_ACCDET_CON2 0x268c93#define MT6359_ACCDET_CON3 0x268e94#define MT6359_ACCDET_CON4 0x269095#define MT6359_ACCDET_CON5 0x269296#define MT6359_ACCDET_CON6 0x269497#define MT6359_ACCDET_CON7 0x269698#define MT6359_ACCDET_CON8 0x269899#define MT6359_ACCDET_CON9 0x269a100#define MT6359_ACCDET_CON10 0x269c101#define MT6359_ACCDET_CON11 0x269e102#define MT6359_ACCDET_CON12 0x26a0103#define MT6359_ACCDET_CON13 0x26a2104#define MT6359_ACCDET_CON14 0x26a4105#define MT6359_ACCDET_CON15 0x26a6106#define MT6359_ACCDET_CON16 0x26a8107#define MT6359_ACCDET_CON17 0x26aa108#define MT6359_ACCDET_CON18 0x26ac109#define MT6359_ACCDET_CON19 0x26ae110#define MT6359_ACCDET_CON20 0x26b0111#define MT6359_ACCDET_CON21 0x26b2112#define MT6359_ACCDET_CON22 0x26b4113#define MT6359_ACCDET_CON23 0x26b6114#define MT6359_ACCDET_CON24 0x26b8115#define MT6359_ACCDET_CON25 0x26ba116#define MT6359_ACCDET_CON26 0x26bc117#define MT6359_ACCDET_CON27 0x26be118#define MT6359_ACCDET_CON28 0x26c0119#define MT6359_ACCDET_CON29 0x26c2120#define MT6359_ACCDET_CON30 0x26c4121#define MT6359_ACCDET_CON31 0x26c6122#define MT6359_ACCDET_CON32 0x26c8123#define MT6359_ACCDET_CON33 0x26ca124#define MT6359_ACCDET_CON34 0x26cc125#define MT6359_ACCDET_CON35 0x26ce126#define MT6359_ACCDET_CON36 0x26d0127#define MT6359_ACCDET_CON37 0x26d2128#define MT6359_ACCDET_CON38 0x26d4129#define MT6359_ACCDET_CON39 0x26d6130#define MT6359_ACCDET_CON40 0x26d8131 132#define TOP0_ANA_ID_ADDR \133 MT6359_TOP0_ID134#define TOP0_ANA_ID_SFT 0135#define TOP0_ANA_ID_MASK 0xFF136#define TOP0_ANA_ID_MASK_SFT (0xFF << 0)137#define AUXADC_RQST_CH0_ADDR \138 MT6359_AUXADC_RQST0139#define AUXADC_RQST_CH0_SFT 0140#define AUXADC_RQST_CH0_MASK 0x1141#define AUXADC_RQST_CH0_MASK_SFT (0x1 << 0)142#define AUXADC_ACCDET_ANASWCTRL_EN_ADDR \143 MT6359_AUXADC_CON15144#define AUXADC_ACCDET_ANASWCTRL_EN_SFT 6145#define AUXADC_ACCDET_ANASWCTRL_EN_MASK 0x1146#define AUXADC_ACCDET_ANASWCTRL_EN_MASK_SFT (0x1 << 6)147 148#define AUXADC_ACCDET_AUTO_SPL_ADDR \149 MT6359_AUXADC_ACCDET150#define AUXADC_ACCDET_AUTO_SPL_SFT 0151#define AUXADC_ACCDET_AUTO_SPL_MASK 0x1152#define AUXADC_ACCDET_AUTO_SPL_MASK_SFT (0x1 << 0)153#define AUXADC_ACCDET_AUTO_RQST_CLR_ADDR \154 MT6359_AUXADC_ACCDET155#define AUXADC_ACCDET_AUTO_RQST_CLR_SFT 1156#define AUXADC_ACCDET_AUTO_RQST_CLR_MASK 0x1157#define AUXADC_ACCDET_AUTO_RQST_CLR_MASK_SFT (0x1 << 1)158#define AUXADC_ACCDET_DIG1_RSV0_ADDR \159 MT6359_AUXADC_ACCDET160#define AUXADC_ACCDET_DIG1_RSV0_SFT 2161#define AUXADC_ACCDET_DIG1_RSV0_MASK 0x3F162#define AUXADC_ACCDET_DIG1_RSV0_MASK_SFT (0x3F << 2)163#define AUXADC_ACCDET_DIG0_RSV0_ADDR \164 MT6359_AUXADC_ACCDET165#define AUXADC_ACCDET_DIG0_RSV0_SFT 8166#define AUXADC_ACCDET_DIG0_RSV0_MASK 0xFF167#define AUXADC_ACCDET_DIG0_RSV0_MASK_SFT (0xFF << 8)168 169#define RG_ACCDET_CK_PDN_ADDR \170 MT6359_AUD_TOP_CKPDN_CON0171#define RG_ACCDET_CK_PDN_SFT 0172#define RG_ACCDET_CK_PDN_MASK 0x1173#define RG_ACCDET_CK_PDN_MASK_SFT (0x1 << 0)174 175#define RG_ACCDET_RST_ADDR \176 MT6359_AUD_TOP_RST_CON0177#define RG_ACCDET_RST_SFT 1178#define RG_ACCDET_RST_MASK 0x1179#define RG_ACCDET_RST_MASK_SFT (0x1 << 1)180#define BANK_ACCDET_SWRST_ADDR \181 MT6359_AUD_TOP_RST_BANK_CON0182#define BANK_ACCDET_SWRST_SFT 0183#define BANK_ACCDET_SWRST_MASK 0x1184#define BANK_ACCDET_SWRST_MASK_SFT (0x1 << 0)185 186#define RG_INT_EN_ACCDET_ADDR \187 MT6359_AUD_TOP_INT_CON0188#define RG_INT_EN_ACCDET_SFT 5189#define RG_INT_EN_ACCDET_MASK 0x1190#define RG_INT_EN_ACCDET_MASK_SFT (0x1 << 5)191#define RG_INT_EN_ACCDET_EINT0_ADDR \192 MT6359_AUD_TOP_INT_CON0193#define RG_INT_EN_ACCDET_EINT0_SFT 6194#define RG_INT_EN_ACCDET_EINT0_MASK 0x1195#define RG_INT_EN_ACCDET_EINT0_MASK_SFT (0x1 << 6)196#define RG_INT_EN_ACCDET_EINT1_ADDR \197 MT6359_AUD_TOP_INT_CON0198#define RG_INT_EN_ACCDET_EINT1_SFT 7199#define RG_INT_EN_ACCDET_EINT1_MASK 0x1200#define RG_INT_EN_ACCDET_EINT1_MASK_SFT (0x1 << 7)201 202#define RG_INT_MASK_ACCDET_ADDR \203 MT6359_AUD_TOP_INT_MASK_CON0204#define RG_INT_MASK_ACCDET_SFT 5205#define RG_INT_MASK_ACCDET_MASK 0x1206#define RG_INT_MASK_ACCDET_MASK_SFT (0x1 << 5)207#define RG_INT_MASK_ACCDET_EINT0_ADDR \208 MT6359_AUD_TOP_INT_MASK_CON0209#define RG_INT_MASK_ACCDET_EINT0_SFT 6210#define RG_INT_MASK_ACCDET_EINT0_MASK 0x1211#define RG_INT_MASK_ACCDET_EINT0_MASK_SFT (0x1 << 6)212#define RG_INT_MASK_ACCDET_EINT1_ADDR \213 MT6359_AUD_TOP_INT_MASK_CON0214#define RG_INT_MASK_ACCDET_EINT1_SFT 7215#define RG_INT_MASK_ACCDET_EINT1_MASK 0x1216#define RG_INT_MASK_ACCDET_EINT1_MASK_SFT (0x1 << 7)217 218#define RG_INT_STATUS_ACCDET_ADDR \219 MT6359_AUD_TOP_INT_STATUS0220#define RG_INT_STATUS_ACCDET_SFT 5221#define RG_INT_STATUS_ACCDET_MASK 0x1222#define RG_INT_STATUS_ACCDET_MASK_SFT (0x1 << 5)223#define RG_INT_STATUS_ACCDET_EINT0_ADDR \224 MT6359_AUD_TOP_INT_STATUS0225#define RG_INT_STATUS_ACCDET_EINT0_SFT 6226#define RG_INT_STATUS_ACCDET_EINT0_MASK 0x1227#define RG_INT_STATUS_ACCDET_EINT0_MASK_SFT (0x1 << 6)228#define RG_INT_STATUS_ACCDET_EINT1_ADDR \229 MT6359_AUD_TOP_INT_STATUS0230#define RG_INT_STATUS_ACCDET_EINT1_SFT 7231#define RG_INT_STATUS_ACCDET_EINT1_MASK 0x1232#define RG_INT_STATUS_ACCDET_EINT1_MASK_SFT (0x1 << 7)233 234#define RG_INT_RAW_STATUS_ACCDET_ADDR \235 MT6359_AUD_TOP_INT_RAW_STATUS0236#define RG_INT_RAW_STATUS_ACCDET_SFT 5237#define RG_INT_RAW_STATUS_ACCDET_MASK 0x1238#define RG_INT_RAW_STATUS_ACCDET_MASK_SFT (0x1 << 5)239#define RG_INT_RAW_STATUS_ACCDET_EINT0_ADDR \240 MT6359_AUD_TOP_INT_RAW_STATUS0241#define RG_INT_RAW_STATUS_ACCDET_EINT0_SFT 6242#define RG_INT_RAW_STATUS_ACCDET_EINT0_MASK 0x1243#define RG_INT_RAW_STATUS_ACCDET_EINT0_MASK_SFT (0x1 << 6)244#define RG_INT_RAW_STATUS_ACCDET_EINT1_ADDR \245 MT6359_AUD_TOP_INT_RAW_STATUS0246#define RG_INT_RAW_STATUS_ACCDET_EINT1_SFT 7247#define RG_INT_RAW_STATUS_ACCDET_EINT1_MASK 0x1248#define RG_INT_RAW_STATUS_ACCDET_EINT1_MASK_SFT (0x1 << 7)249 250#define RG_AUDACCDETMICBIAS0PULLLOW_ADDR \251 MT6359_AUDENC_ANA_CON18252#define RG_AUDACCDETMICBIAS0PULLLOW_SFT 0253#define RG_AUDACCDETMICBIAS0PULLLOW_MASK 0x1254#define RG_AUDACCDETMICBIAS0PULLLOW_MASK_SFT (0x1 << 0)255#define RG_AUDACCDETMICBIAS1PULLLOW_ADDR \256 MT6359_AUDENC_ANA_CON18257#define RG_AUDACCDETMICBIAS1PULLLOW_SFT 1258#define RG_AUDACCDETMICBIAS1PULLLOW_MASK 0x1259#define RG_AUDACCDETMICBIAS1PULLLOW_MASK_SFT (0x1 << 1)260#define RG_AUDACCDETMICBIAS2PULLLOW_ADDR \261 MT6359_AUDENC_ANA_CON18262#define RG_AUDACCDETMICBIAS2PULLLOW_SFT 2263#define RG_AUDACCDETMICBIAS2PULLLOW_MASK 0x1264#define RG_AUDACCDETMICBIAS2PULLLOW_MASK_SFT (0x1 << 2)265#define RG_AUDACCDETVIN1PULLLOW_ADDR \266 MT6359_AUDENC_ANA_CON18267#define RG_AUDACCDETVIN1PULLLOW_SFT 3268#define RG_AUDACCDETVIN1PULLLOW_MASK 0x1269#define RG_AUDACCDETVIN1PULLLOW_MASK_SFT (0x1 << 3)270#define RG_AUDACCDETVTHACAL_ADDR \271 MT6359_AUDENC_ANA_CON18272#define RG_AUDACCDETVTHACAL_SFT 4273#define RG_AUDACCDETVTHACAL_MASK 0x1274#define RG_AUDACCDETVTHACAL_MASK_SFT (0x1 << 4)275#define RG_AUDACCDETVTHBCAL_ADDR \276 MT6359_AUDENC_ANA_CON18277#define RG_AUDACCDETVTHBCAL_SFT 5278#define RG_AUDACCDETVTHBCAL_MASK 0x1279#define RG_AUDACCDETVTHBCAL_MASK_SFT (0x1 << 5)280#define RG_AUDACCDETTVDET_ADDR \281 MT6359_AUDENC_ANA_CON18282#define RG_AUDACCDETTVDET_SFT 6283#define RG_AUDACCDETTVDET_MASK 0x1284#define RG_AUDACCDETTVDET_MASK_SFT (0x1 << 6)285#define RG_ACCDETSEL_ADDR \286 MT6359_AUDENC_ANA_CON18287#define RG_ACCDETSEL_SFT 7288#define RG_ACCDETSEL_MASK 0x1289#define RG_ACCDETSEL_MASK_SFT (0x1 << 7)290 291#define RG_AUDPWDBMICBIAS1_ADDR \292 MT6359_AUDENC_ANA_CON16293#define RG_AUDPWDBMICBIAS1_SFT 0294#define RG_AUDPWDBMICBIAS1_MASK 0x1295#define RG_AUDPWDBMICBIAS1_MASK_SFT (0x1 << 0)296#define RG_AUDMICBIAS1BYPASSEN_ADDR \297 MT6359_AUDENC_ANA_CON16298#define RG_AUDMICBIAS1BYPASSEN_SFT 1299#define RG_AUDMICBIAS1BYPASSEN_MASK 0x1300#define RG_AUDMICBIAS1BYPASSEN_MASK_SFT (0x1 << 1)301#define RG_AUDMICBIAS1LOWPEN_ADDR \302 MT6359_AUDENC_ANA_CON16303#define RG_AUDMICBIAS1LOWPEN_SFT 2304#define RG_AUDMICBIAS1LOWPEN_MASK 0x1305#define RG_AUDMICBIAS1LOWPEN_MASK_SFT (0x1 << 2)306#define RG_AUDMICBIAS1VREF_ADDR \307 MT6359_AUDENC_ANA_CON16308#define RG_AUDMICBIAS1VREF_SFT 4309#define RG_AUDMICBIAS1VREF_MASK 0x7310#define RG_AUDMICBIAS1VREF_MASK_SFT (0x7 << 4)311#define RG_AUDMICBIAS1DCSW1PEN_ADDR \312 MT6359_AUDENC_ANA_CON16313#define RG_AUDMICBIAS1DCSW1PEN_SFT 8314#define RG_AUDMICBIAS1DCSW1PEN_MASK 0x1315#define RG_AUDMICBIAS1DCSW1PEN_MASK_SFT (0x1 << 8)316#define RG_AUDMICBIAS1DCSW1NEN_ADDR \317 MT6359_AUDENC_ANA_CON16318#define RG_AUDMICBIAS1DCSW1NEN_SFT 9319#define RG_AUDMICBIAS1DCSW1NEN_MASK 0x1320#define RG_AUDMICBIAS1DCSW1NEN_MASK_SFT (0x1 << 9)321#define RG_BANDGAPGEN_ADDR \322 MT6359_AUDENC_ANA_CON16323#define RG_BANDGAPGEN_SFT 10324#define RG_BANDGAPGEN_MASK 0x1325#define RG_BANDGAPGEN_MASK_SFT (0x1 << 10)326#define RG_AUDMICBIAS1HVEN_ADDR \327 MT6359_AUDENC_ANA_CON16328#define RG_AUDMICBIAS1HVEN_SFT 12329#define RG_AUDMICBIAS1HVEN_MASK 0x1330#define RG_AUDMICBIAS1HVEN_MASK_SFT (0x1 << 12)331#define RG_AUDMICBIAS1HVVREF_ADDR \332 MT6359_AUDENC_ANA_CON16333#define RG_AUDMICBIAS1HVVREF_SFT 13334#define RG_AUDMICBIAS1HVVREF_MASK 0x1335#define RG_AUDMICBIAS1HVVREF_MASK_SFT (0x1 << 13)336 337#define RG_EINT0NOHYS_ADDR \338 MT6359_AUDENC_ANA_CON18339#define RG_EINT0NOHYS_SFT 10340#define RG_EINT0NOHYS_MASK 0x1341#define RG_EINT0NOHYS_MASK_SFT (0x1 << 10)342#define RG_EINT0CONFIGACCDET_ADDR \343 MT6359_AUDENC_ANA_CON18344#define RG_EINT0CONFIGACCDET_SFT 11345#define RG_EINT0CONFIGACCDET_MASK 0x1346#define RG_EINT0CONFIGACCDET_MASK_SFT (0x1 << 11)347#define RG_EINT0HIRENB_ADDR \348 MT6359_AUDENC_ANA_CON18349#define RG_EINT0HIRENB_SFT 12350#define RG_EINT0HIRENB_MASK 0x1351#define RG_EINT0HIRENB_MASK_SFT (0x1 << 12)352#define RG_ACCDET2AUXRESBYPASS_ADDR \353 MT6359_AUDENC_ANA_CON18354#define RG_ACCDET2AUXRESBYPASS_SFT 13355#define RG_ACCDET2AUXRESBYPASS_MASK 0x1356#define RG_ACCDET2AUXRESBYPASS_MASK_SFT (0x1 << 13)357#define RG_ACCDET2AUXSWEN_ADDR \358 MT6359_AUDENC_ANA_CON18359#define RG_ACCDET2AUXSWEN_SFT 14360#define RG_ACCDET2AUXSWEN_MASK 0x1361#define RG_ACCDET2AUXSWEN_MASK_SFT (0x1 << 14)362#define RG_AUDACCDETMICBIAS3PULLLOW_ADDR \363 MT6359_AUDENC_ANA_CON18364#define RG_AUDACCDETMICBIAS3PULLLOW_SFT 15365#define RG_AUDACCDETMICBIAS3PULLLOW_MASK 0x1366#define RG_AUDACCDETMICBIAS3PULLLOW_MASK_SFT (0x1 << 15)367#define RG_EINT1CONFIGACCDET_ADDR \368 MT6359_AUDENC_ANA_CON19369#define RG_EINT1CONFIGACCDET_SFT 0370#define RG_EINT1CONFIGACCDET_MASK 0x1371#define RG_EINT1CONFIGACCDET_MASK_SFT (0x1 << 0)372#define RG_EINT1HIRENB_ADDR \373 MT6359_AUDENC_ANA_CON19374#define RG_EINT1HIRENB_SFT 1375#define RG_EINT1HIRENB_MASK 0x1376#define RG_EINT1HIRENB_MASK_SFT (0x1 << 1)377#define RG_EINT1NOHYS_ADDR \378 MT6359_AUDENC_ANA_CON19379#define RG_EINT1NOHYS_SFT 2380#define RG_EINT1NOHYS_MASK 0x1381#define RG_EINT1NOHYS_MASK_SFT (0x1 << 2)382#define RG_EINTCOMPVTH_ADDR \383 MT6359_AUDENC_ANA_CON19384#define RG_MTEST_EN_ADDR \385 MT6359_AUDENC_ANA_CON19386#define RG_MTEST_EN_SFT 8387#define RG_MTEST_EN_MASK 0x1388#define RG_MTEST_EN_MASK_SFT (0x1 << 8)389#define RG_MTEST_SEL_ADDR \390 MT6359_AUDENC_ANA_CON19391#define RG_MTEST_SEL_SFT 9392#define RG_MTEST_SEL_MASK 0x1393#define RG_MTEST_SEL_MASK_SFT (0x1 << 9)394#define RG_MTEST_CURRENT_ADDR \395 MT6359_AUDENC_ANA_CON19396#define RG_MTEST_CURRENT_SFT 10397#define RG_MTEST_CURRENT_MASK 0x1398#define RG_MTEST_CURRENT_MASK_SFT (0x1 << 10)399#define RG_ANALOGFDEN_ADDR \400 MT6359_AUDENC_ANA_CON19401#define RG_ANALOGFDEN_SFT 12402#define RG_ANALOGFDEN_MASK 0x1403#define RG_ANALOGFDEN_MASK_SFT (0x1 << 12)404#define RG_FDVIN1PPULLLOW_ADDR \405 MT6359_AUDENC_ANA_CON19406#define RG_FDVIN1PPULLLOW_SFT 13407#define RG_FDVIN1PPULLLOW_MASK 0x1408#define RG_FDVIN1PPULLLOW_MASK_SFT (0x1 << 13)409#define RG_FDEINT0TYPE_ADDR \410 MT6359_AUDENC_ANA_CON19411#define RG_FDEINT0TYPE_SFT 14412#define RG_FDEINT0TYPE_MASK 0x1413#define RG_FDEINT0TYPE_MASK_SFT (0x1 << 14)414#define RG_FDEINT1TYPE_ADDR \415 MT6359_AUDENC_ANA_CON19416#define RG_FDEINT1TYPE_SFT 15417#define RG_FDEINT1TYPE_MASK 0x1418#define RG_FDEINT1TYPE_MASK_SFT (0x1 << 15)419#define RG_EINT0CMPEN_ADDR \420 MT6359_AUDENC_ANA_CON20421#define RG_EINT0CMPEN_SFT 0422#define RG_EINT0CMPEN_MASK 0x1423#define RG_EINT0CMPEN_MASK_SFT (0x1 << 0)424#define RG_EINT0CMPMEN_ADDR \425 MT6359_AUDENC_ANA_CON20426#define RG_EINT0CMPMEN_SFT 1427#define RG_EINT0CMPMEN_MASK 0x1428#define RG_EINT0CMPMEN_MASK_SFT (0x1 << 1)429#define RG_EINT0EN_ADDR \430 MT6359_AUDENC_ANA_CON20431#define RG_EINT0EN_SFT 2432#define RG_EINT0EN_MASK 0x1433#define RG_EINT0EN_MASK_SFT (0x1 << 2)434#define RG_EINT0CEN_ADDR \435 MT6359_AUDENC_ANA_CON20436#define RG_EINT0CEN_SFT 3437#define RG_EINT0CEN_MASK 0x1438#define RG_EINT0CEN_MASK_SFT (0x1 << 3)439#define RG_EINT0INVEN_ADDR \440 MT6359_AUDENC_ANA_CON20441#define RG_EINT0INVEN_SFT 4442#define RG_EINT0INVEN_MASK 0x1443#define RG_EINT0INVEN_MASK_SFT (0x1 << 4)444#define RG_EINT0CTURBO_ADDR \445 MT6359_AUDENC_ANA_CON20446#define RG_EINT0CTURBO_SFT 5447#define RG_EINT0CTURBO_MASK 0x7448#define RG_EINT0CTURBO_MASK_SFT (0x7 << 5)449#define RG_EINT1CMPEN_ADDR \450 MT6359_AUDENC_ANA_CON20451#define RG_EINT1CMPEN_SFT 8452#define RG_EINT1CMPEN_MASK 0x1453#define RG_EINT1CMPEN_MASK_SFT (0x1 << 8)454#define RG_EINT1CMPMEN_ADDR \455 MT6359_AUDENC_ANA_CON20456#define RG_EINT1CMPMEN_SFT 9457#define RG_EINT1CMPMEN_MASK 0x1458#define RG_EINT1CMPMEN_MASK_SFT (0x1 << 9)459#define RG_EINT1EN_ADDR \460 MT6359_AUDENC_ANA_CON20461#define RG_EINT1EN_SFT 10462#define RG_EINT1EN_MASK 0x1463#define RG_EINT1EN_MASK_SFT (0x1 << 10)464#define RG_EINT1CEN_ADDR \465 MT6359_AUDENC_ANA_CON20466#define RG_EINT1CEN_SFT 11467#define RG_EINT1CEN_MASK 0x1468#define RG_EINT1CEN_MASK_SFT (0x1 << 11)469#define RG_EINT1INVEN_ADDR \470 MT6359_AUDENC_ANA_CON20471#define RG_EINT1INVEN_SFT 12472#define RG_EINT1INVEN_MASK 0x1473#define RG_EINT1INVEN_MASK_SFT (0x1 << 12)474#define RG_EINT1CTURBO_ADDR \475 MT6359_AUDENC_ANA_CON20476#define RG_EINT1CTURBO_SFT 13477#define RG_EINT1CTURBO_MASK 0x7478#define RG_EINT1CTURBO_MASK_SFT (0x7 << 13)479#define RG_ACCDETSPARE_ADDR \480 MT6359_AUDENC_ANA_CON21481 482#define ACCDET_ANA_ID_ADDR \483 MT6359_ACCDET_DSN_DIG_ID484#define ACCDET_ANA_ID_SFT 0485#define ACCDET_ANA_ID_MASK 0xFF486#define ACCDET_ANA_ID_MASK_SFT (0xFF << 0)487#define ACCDET_DIG_ID_ADDR \488 MT6359_ACCDET_DSN_DIG_ID489#define ACCDET_DIG_ID_SFT 8490#define ACCDET_DIG_ID_MASK 0xFF491#define ACCDET_DIG_ID_MASK_SFT (0xFF << 8)492#define ACCDET_ANA_MINOR_REV_ADDR \493 MT6359_ACCDET_DSN_DIG_REV0494#define ACCDET_ANA_MINOR_REV_SFT 0495#define ACCDET_ANA_MINOR_REV_MASK 0xF496#define ACCDET_ANA_MINOR_REV_MASK_SFT (0xF << 0)497#define ACCDET_ANA_MAJOR_REV_ADDR \498 MT6359_ACCDET_DSN_DIG_REV0499#define ACCDET_ANA_MAJOR_REV_SFT 4500#define ACCDET_ANA_MAJOR_REV_MASK 0xF501#define ACCDET_ANA_MAJOR_REV_MASK_SFT (0xF << 4)502#define ACCDET_DIG_MINOR_REV_ADDR \503 MT6359_ACCDET_DSN_DIG_REV0504#define ACCDET_DIG_MINOR_REV_SFT 8505#define ACCDET_DIG_MINOR_REV_MASK 0xF506#define ACCDET_DIG_MINOR_REV_MASK_SFT (0xF << 8)507#define ACCDET_DIG_MAJOR_REV_ADDR \508 MT6359_ACCDET_DSN_DIG_REV0509#define ACCDET_DIG_MAJOR_REV_SFT 12510#define ACCDET_DIG_MAJOR_REV_MASK 0xF511#define ACCDET_DIG_MAJOR_REV_MASK_SFT (0xF << 12)512#define ACCDET_DSN_CBS_ADDR \513 MT6359_ACCDET_DSN_DBI514#define ACCDET_DSN_CBS_SFT 0515#define ACCDET_DSN_CBS_MASK 0x3516#define ACCDET_DSN_CBS_MASK_SFT (0x3 << 0)517#define ACCDET_DSN_BIX_ADDR \518 MT6359_ACCDET_DSN_DBI519#define ACCDET_DSN_BIX_SFT 2520#define ACCDET_DSN_BIX_MASK 0x3521#define ACCDET_DSN_BIX_MASK_SFT (0x3 << 2)522#define ACCDET_ESP_ADDR \523 MT6359_ACCDET_DSN_DBI524#define ACCDET_ESP_SFT 8525#define ACCDET_ESP_MASK 0xFF526#define ACCDET_ESP_MASK_SFT (0xFF << 8)527#define ACCDET_DSN_FPI_ADDR \528 MT6359_ACCDET_DSN_FPI529#define ACCDET_DSN_FPI_SFT 0530#define ACCDET_DSN_FPI_MASK 0xFF531#define ACCDET_DSN_FPI_MASK_SFT (0xFF << 0)532#define ACCDET_AUXADC_SEL_ADDR \533 MT6359_ACCDET_CON0534#define ACCDET_AUXADC_SEL_SFT 0535#define ACCDET_AUXADC_SEL_MASK 0x1536#define ACCDET_AUXADC_SEL_MASK_SFT (0x1 << 0)537#define ACCDET_AUXADC_SW_ADDR \538 MT6359_ACCDET_CON0539#define ACCDET_AUXADC_SW_SFT 1540#define ACCDET_AUXADC_SW_MASK 0x1541#define ACCDET_AUXADC_SW_MASK_SFT (0x1 << 1)542#define ACCDET_TEST_AUXADC_ADDR \543 MT6359_ACCDET_CON0544#define ACCDET_TEST_AUXADC_SFT 2545#define ACCDET_TEST_AUXADC_MASK 0x1546#define ACCDET_TEST_AUXADC_MASK_SFT (0x1 << 2)547#define ACCDET_AUXADC_ANASWCTRL_SEL_ADDR \548 MT6359_ACCDET_CON0549#define ACCDET_AUXADC_ANASWCTRL_SEL_SFT 8550#define ACCDET_AUXADC_ANASWCTRL_SEL_MASK 0x1551#define ACCDET_AUXADC_ANASWCTRL_SEL_MASK_SFT (0x1 << 8)552#define AUDACCDETAUXADCSWCTRL_SEL_ADDR \553 MT6359_ACCDET_CON0554#define AUDACCDETAUXADCSWCTRL_SEL_SFT 9555#define AUDACCDETAUXADCSWCTRL_SEL_MASK 0x1556#define AUDACCDETAUXADCSWCTRL_SEL_MASK_SFT (0x1 << 9)557#define AUDACCDETAUXADCSWCTRL_SW_ADDR \558 MT6359_ACCDET_CON0559#define AUDACCDETAUXADCSWCTRL_SW_SFT 10560#define AUDACCDETAUXADCSWCTRL_SW_MASK 0x1561#define AUDACCDETAUXADCSWCTRL_SW_MASK_SFT (0x1 << 10)562#define ACCDET_TEST_ANA_ADDR \563 MT6359_ACCDET_CON0564#define ACCDET_TEST_ANA_SFT 11565#define ACCDET_TEST_ANA_MASK 0x1566#define ACCDET_TEST_ANA_MASK_SFT (0x1 << 11)567#define RG_AUDACCDETRSV_ADDR \568 MT6359_ACCDET_CON0569#define RG_AUDACCDETRSV_SFT 13570#define RG_AUDACCDETRSV_MASK 0x3571#define RG_AUDACCDETRSV_MASK_SFT (0x3 << 13)572#define ACCDET_SW_EN_ADDR \573 MT6359_ACCDET_CON1574#define ACCDET_SW_EN_SFT 0575#define ACCDET_SW_EN_MASK 0x1576#define ACCDET_SW_EN_MASK_SFT (0x1 << 0)577#define ACCDET_SEQ_INIT_ADDR \578 MT6359_ACCDET_CON1579#define ACCDET_SEQ_INIT_SFT 1580#define ACCDET_SEQ_INIT_MASK 0x1581#define ACCDET_SEQ_INIT_MASK_SFT (0x1 << 1)582#define ACCDET_EINT0_SW_EN_ADDR \583 MT6359_ACCDET_CON1584#define ACCDET_EINT0_SW_EN_SFT 2585#define ACCDET_EINT0_SW_EN_MASK 0x1586#define ACCDET_EINT0_SW_EN_MASK_SFT (0x1 << 2)587#define ACCDET_EINT0_SEQ_INIT_ADDR \588 MT6359_ACCDET_CON1589#define ACCDET_EINT0_SEQ_INIT_SFT 3590#define ACCDET_EINT0_SEQ_INIT_MASK 0x1591#define ACCDET_EINT0_SEQ_INIT_MASK_SFT (0x1 << 3)592#define ACCDET_EINT1_SW_EN_ADDR \593 MT6359_ACCDET_CON1594#define ACCDET_EINT1_SW_EN_SFT 4595#define ACCDET_EINT1_SW_EN_MASK 0x1596#define ACCDET_EINT1_SW_EN_MASK_SFT (0x1 << 4)597#define ACCDET_EINT1_SEQ_INIT_ADDR \598 MT6359_ACCDET_CON1599#define ACCDET_EINT1_SEQ_INIT_SFT 5600#define ACCDET_EINT1_SEQ_INIT_MASK 0x1601#define ACCDET_EINT1_SEQ_INIT_MASK_SFT (0x1 << 5)602#define ACCDET_EINT0_INVERTER_SW_EN_ADDR \603 MT6359_ACCDET_CON1604#define ACCDET_EINT0_INVERTER_SW_EN_SFT 6605#define ACCDET_EINT0_INVERTER_SW_EN_MASK 0x1606#define ACCDET_EINT0_INVERTER_SW_EN_MASK_SFT (0x1 << 6)607#define ACCDET_EINT0_INVERTER_SEQ_INIT_ADDR \608 MT6359_ACCDET_CON1609#define ACCDET_EINT0_INVERTER_SEQ_INIT_SFT 7610#define ACCDET_EINT0_INVERTER_SEQ_INIT_MASK 0x1611#define ACCDET_EINT0_INVERTER_SEQ_INIT_MASK_SFT (0x1 << 7)612#define ACCDET_EINT1_INVERTER_SW_EN_ADDR \613 MT6359_ACCDET_CON1614#define ACCDET_EINT1_INVERTER_SW_EN_SFT 8615#define ACCDET_EINT1_INVERTER_SW_EN_MASK 0x1616#define ACCDET_EINT1_INVERTER_SW_EN_MASK_SFT (0x1 << 8)617#define ACCDET_EINT1_INVERTER_SEQ_INIT_ADDR \618 MT6359_ACCDET_CON1619#define ACCDET_EINT1_INVERTER_SEQ_INIT_SFT 9620#define ACCDET_EINT1_INVERTER_SEQ_INIT_MASK 0x1621#define ACCDET_EINT1_INVERTER_SEQ_INIT_MASK_SFT (0x1 << 9)622#define ACCDET_EINT0_M_SW_EN_ADDR \623 MT6359_ACCDET_CON1624#define ACCDET_EINT0_M_SW_EN_SFT 10625#define ACCDET_EINT0_M_SW_EN_MASK 0x1626#define ACCDET_EINT0_M_SW_EN_MASK_SFT (0x1 << 10)627#define ACCDET_EINT1_M_SW_EN_ADDR \628 MT6359_ACCDET_CON1629#define ACCDET_EINT1_M_SW_EN_SFT 11630#define ACCDET_EINT1_M_SW_EN_MASK 0x1631#define ACCDET_EINT1_M_SW_EN_MASK_SFT (0x1 << 11)632#define ACCDET_EINT_M_DETECT_EN_ADDR \633 MT6359_ACCDET_CON1634#define ACCDET_EINT_M_DETECT_EN_SFT 12635#define ACCDET_EINT_M_DETECT_EN_MASK 0x1636#define ACCDET_EINT_M_DETECT_EN_MASK_SFT (0x1 << 12)637#define ACCDET_CMP_PWM_EN_ADDR \638 MT6359_ACCDET_CON2639#define ACCDET_CMP_PWM_EN_SFT 0640#define ACCDET_CMP_PWM_EN_MASK 0x1641#define ACCDET_CMP_PWM_EN_MASK_SFT (0x1 << 0)642#define ACCDET_VTH_PWM_EN_ADDR \643 MT6359_ACCDET_CON2644#define ACCDET_VTH_PWM_EN_SFT 1645#define ACCDET_VTH_PWM_EN_MASK 0x1646#define ACCDET_VTH_PWM_EN_MASK_SFT (0x1 << 1)647#define ACCDET_MBIAS_PWM_EN_ADDR \648 MT6359_ACCDET_CON2649#define ACCDET_MBIAS_PWM_EN_SFT 2650#define ACCDET_MBIAS_PWM_EN_MASK 0x1651#define ACCDET_MBIAS_PWM_EN_MASK_SFT (0x1 << 2)652#define ACCDET_EINT_EN_PWM_EN_ADDR \653 MT6359_ACCDET_CON2654#define ACCDET_EINT_EN_PWM_EN_SFT 3655#define ACCDET_EINT_EN_PWM_EN_MASK 0x1656#define ACCDET_EINT_EN_PWM_EN_MASK_SFT (0x1 << 3)657#define ACCDET_EINT_CMPEN_PWM_EN_ADDR \658 MT6359_ACCDET_CON2659#define ACCDET_EINT_CMPEN_PWM_EN_SFT 4660#define ACCDET_EINT_CMPEN_PWM_EN_MASK 0x1661#define ACCDET_EINT_CMPEN_PWM_EN_MASK_SFT (0x1 << 4)662#define ACCDET_EINT_CMPMEN_PWM_EN_ADDR \663 MT6359_ACCDET_CON2664#define ACCDET_EINT_CMPMEN_PWM_EN_SFT 5665#define ACCDET_EINT_CMPMEN_PWM_EN_MASK 0x1666#define ACCDET_EINT_CMPMEN_PWM_EN_MASK_SFT (0x1 << 5)667#define ACCDET_EINT_CTURBO_PWM_EN_ADDR \668 MT6359_ACCDET_CON2669#define ACCDET_EINT_CTURBO_PWM_EN_SFT 6670#define ACCDET_EINT_CTURBO_PWM_EN_MASK 0x1671#define ACCDET_EINT_CTURBO_PWM_EN_MASK_SFT (0x1 << 6)672#define ACCDET_CMP_PWM_IDLE_ADDR \673 MT6359_ACCDET_CON2674#define ACCDET_CMP_PWM_IDLE_SFT 8675#define ACCDET_CMP_PWM_IDLE_MASK 0x1676#define ACCDET_CMP_PWM_IDLE_MASK_SFT (0x1 << 8)677#define ACCDET_VTH_PWM_IDLE_ADDR \678 MT6359_ACCDET_CON2679#define ACCDET_VTH_PWM_IDLE_SFT 9680#define ACCDET_VTH_PWM_IDLE_MASK 0x1681#define ACCDET_VTH_PWM_IDLE_MASK_SFT (0x1 << 9)682#define ACCDET_MBIAS_PWM_IDLE_ADDR \683 MT6359_ACCDET_CON2684#define ACCDET_MBIAS_PWM_IDLE_SFT 10685#define ACCDET_MBIAS_PWM_IDLE_MASK 0x1686#define ACCDET_MBIAS_PWM_IDLE_MASK_SFT (0x1 << 10)687#define ACCDET_EINT0_CMPEN_PWM_IDLE_ADDR \688 MT6359_ACCDET_CON2689#define ACCDET_EINT0_CMPEN_PWM_IDLE_SFT 11690#define ACCDET_EINT0_CMPEN_PWM_IDLE_MASK 0x1691#define ACCDET_EINT0_CMPEN_PWM_IDLE_MASK_SFT (0x1 << 11)692#define ACCDET_EINT1_CMPEN_PWM_IDLE_ADDR \693 MT6359_ACCDET_CON2694#define ACCDET_EINT1_CMPEN_PWM_IDLE_SFT 12695#define ACCDET_EINT1_CMPEN_PWM_IDLE_MASK 0x1696#define ACCDET_EINT1_CMPEN_PWM_IDLE_MASK_SFT (0x1 << 12)697#define ACCDET_PWM_EN_SW_ADDR \698 MT6359_ACCDET_CON2699#define ACCDET_PWM_EN_SW_SFT 13700#define ACCDET_PWM_EN_SW_MASK 0x1701#define ACCDET_PWM_EN_SW_MASK_SFT (0x1 << 13)702#define ACCDET_PWM_EN_SEL_ADDR \703 MT6359_ACCDET_CON2704#define ACCDET_PWM_EN_SEL_SFT 14705#define ACCDET_PWM_EN_SEL_MASK 0x3706#define ACCDET_PWM_EN_SEL_MASK_SFT (0x3 << 14)707#define ACCDET_PWM_WIDTH_ADDR \708 MT6359_ACCDET_CON3709#define ACCDET_PWM_WIDTH_SFT 0710#define ACCDET_PWM_WIDTH_MASK 0xFFFF711#define ACCDET_PWM_WIDTH_MASK_SFT (0xFFFF << 0)712#define ACCDET_PWM_THRESH_ADDR \713 MT6359_ACCDET_CON4714#define ACCDET_PWM_THRESH_SFT 0715#define ACCDET_PWM_THRESH_MASK 0xFFFF716#define ACCDET_PWM_THRESH_MASK_SFT (0xFFFF << 0)717#define ACCDET_RISE_DELAY_ADDR \718 MT6359_ACCDET_CON5719#define ACCDET_RISE_DELAY_SFT 0720#define ACCDET_RISE_DELAY_MASK 0x7FFF721#define ACCDET_RISE_DELAY_MASK_SFT (0x7FFF << 0)722#define ACCDET_FALL_DELAY_ADDR \723 MT6359_ACCDET_CON5724#define ACCDET_FALL_DELAY_SFT 15725#define ACCDET_FALL_DELAY_MASK 0x1726#define ACCDET_FALL_DELAY_MASK_SFT (0x1 << 15)727#define ACCDET_EINT_CMPMEN_PWM_THRESH_ADDR \728 MT6359_ACCDET_CON6729#define ACCDET_EINT_CMPMEN_PWM_THRESH_SFT 0730#define ACCDET_EINT_CMPMEN_PWM_THRESH_MASK 0x7731#define ACCDET_EINT_CMPMEN_PWM_THRESH_MASK_SFT (0x7 << 0)732#define ACCDET_EINT_CMPMEN_PWM_WIDTH_ADDR \733 MT6359_ACCDET_CON6734#define ACCDET_EINT_CMPMEN_PWM_WIDTH_SFT 4735#define ACCDET_EINT_CMPMEN_PWM_WIDTH_MASK 0x7736#define ACCDET_EINT_CMPMEN_PWM_WIDTH_MASK_SFT (0x7 << 4)737#define ACCDET_EINT_EN_PWM_THRESH_ADDR \738 MT6359_ACCDET_CON7739#define ACCDET_EINT_EN_PWM_THRESH_SFT 0740#define ACCDET_EINT_EN_PWM_THRESH_MASK 0x7741#define ACCDET_EINT_EN_PWM_THRESH_MASK_SFT (0x7 << 0)742#define ACCDET_EINT_EN_PWM_WIDTH_ADDR \743 MT6359_ACCDET_CON7744#define ACCDET_EINT_EN_PWM_WIDTH_SFT 4745#define ACCDET_EINT_EN_PWM_WIDTH_MASK 0x3746#define ACCDET_EINT_EN_PWM_WIDTH_MASK_SFT (0x3 << 4)747#define ACCDET_EINT_CMPEN_PWM_THRESH_ADDR \748 MT6359_ACCDET_CON7749#define ACCDET_EINT_CMPEN_PWM_THRESH_SFT 8750#define ACCDET_EINT_CMPEN_PWM_THRESH_MASK 0x7751#define ACCDET_EINT_CMPEN_PWM_THRESH_MASK_SFT (0x7 << 8)752#define ACCDET_EINT_CMPEN_PWM_WIDTH_ADDR \753 MT6359_ACCDET_CON7754#define ACCDET_EINT_CMPEN_PWM_WIDTH_SFT 12755#define ACCDET_EINT_CMPEN_PWM_WIDTH_MASK 0x3756#define ACCDET_EINT_CMPEN_PWM_WIDTH_MASK_SFT (0x3 << 12)757#define ACCDET_DEBOUNCE0_ADDR \758 MT6359_ACCDET_CON8759#define ACCDET_DEBOUNCE0_SFT 0760#define ACCDET_DEBOUNCE0_MASK 0xFFFF761#define ACCDET_DEBOUNCE0_MASK_SFT (0xFFFF << 0)762#define ACCDET_DEBOUNCE1_ADDR \763 MT6359_ACCDET_CON9764#define ACCDET_DEBOUNCE1_SFT 0765#define ACCDET_DEBOUNCE1_MASK 0xFFFF766#define ACCDET_DEBOUNCE1_MASK_SFT (0xFFFF << 0)767#define ACCDET_DEBOUNCE2_ADDR \768 MT6359_ACCDET_CON10769#define ACCDET_DEBOUNCE2_SFT 0770#define ACCDET_DEBOUNCE2_MASK 0xFFFF771#define ACCDET_DEBOUNCE2_MASK_SFT (0xFFFF << 0)772#define ACCDET_DEBOUNCE3_ADDR \773 MT6359_ACCDET_CON11774#define ACCDET_DEBOUNCE3_SFT 0775#define ACCDET_DEBOUNCE3_MASK 0xFFFF776#define ACCDET_DEBOUNCE3_MASK_SFT (0xFFFF << 0)777#define ACCDET_CONNECT_AUXADC_TIME_DIG_ADDR \778 MT6359_ACCDET_CON12779#define ACCDET_CONNECT_AUXADC_TIME_DIG_SFT 0780#define ACCDET_CONNECT_AUXADC_TIME_DIG_MASK 0xFFFF781#define ACCDET_CONNECT_AUXADC_TIME_DIG_MASK_SFT (0xFFFF << 0)782#define ACCDET_CONNECT_AUXADC_TIME_ANA_ADDR \783 MT6359_ACCDET_CON13784#define ACCDET_CONNECT_AUXADC_TIME_ANA_SFT 0785#define ACCDET_CONNECT_AUXADC_TIME_ANA_MASK 0xFFFF786#define ACCDET_CONNECT_AUXADC_TIME_ANA_MASK_SFT (0xFFFF << 0)787#define ACCDET_EINT_DEBOUNCE0_ADDR \788 MT6359_ACCDET_CON14789#define ACCDET_EINT_DEBOUNCE0_SFT 0790#define ACCDET_EINT_DEBOUNCE0_MASK 0xF791#define ACCDET_EINT_DEBOUNCE0_MASK_SFT (0xF << 0)792#define ACCDET_EINT_DEBOUNCE1_ADDR \793 MT6359_ACCDET_CON14794#define ACCDET_EINT_DEBOUNCE1_SFT 4795#define ACCDET_EINT_DEBOUNCE1_MASK 0xF796#define ACCDET_EINT_DEBOUNCE1_MASK_SFT (0xF << 4)797#define ACCDET_EINT_DEBOUNCE2_ADDR \798 MT6359_ACCDET_CON14799#define ACCDET_EINT_DEBOUNCE2_SFT 8800#define ACCDET_EINT_DEBOUNCE2_MASK 0xF801#define ACCDET_EINT_DEBOUNCE2_MASK_SFT (0xF << 8)802#define ACCDET_EINT_DEBOUNCE3_ADDR \803 MT6359_ACCDET_CON14804#define ACCDET_EINT_DEBOUNCE3_SFT 12805#define ACCDET_EINT_DEBOUNCE3_MASK 0xF806#define ACCDET_EINT_DEBOUNCE3_MASK_SFT (0xF << 12)807#define ACCDET_EINT_INVERTER_DEBOUNCE_ADDR \808 MT6359_ACCDET_CON15809#define ACCDET_EINT_INVERTER_DEBOUNCE_SFT 0810#define ACCDET_EINT_INVERTER_DEBOUNCE_MASK 0xF811#define ACCDET_EINT_INVERTER_DEBOUNCE_MASK_SFT (0xF << 0)812#define ACCDET_IVAL_CUR_IN_ADDR \813 MT6359_ACCDET_CON16814#define ACCDET_IVAL_CUR_IN_SFT 0815#define ACCDET_IVAL_CUR_IN_MASK 0x3816#define ACCDET_IVAL_CUR_IN_MASK_SFT (0x3 << 0)817#define ACCDET_IVAL_SAM_IN_ADDR \818 MT6359_ACCDET_CON16819#define ACCDET_IVAL_SAM_IN_SFT 2820#define ACCDET_IVAL_SAM_IN_MASK 0x3821#define ACCDET_IVAL_SAM_IN_MASK_SFT (0x3 << 2)822#define ACCDET_IVAL_MEM_IN_ADDR \823 MT6359_ACCDET_CON16824#define ACCDET_IVAL_MEM_IN_SFT 4825#define ACCDET_IVAL_MEM_IN_MASK 0x3826#define ACCDET_IVAL_MEM_IN_MASK_SFT (0x3 << 4)827#define ACCDET_EINT_IVAL_CUR_IN_ADDR \828 MT6359_ACCDET_CON16829#define ACCDET_EINT_IVAL_CUR_IN_SFT 6830#define ACCDET_EINT_IVAL_CUR_IN_MASK 0x3831#define ACCDET_EINT_IVAL_CUR_IN_MASK_SFT (0x3 << 6)832#define ACCDET_EINT_IVAL_SAM_IN_ADDR \833 MT6359_ACCDET_CON16834#define ACCDET_EINT_IVAL_SAM_IN_SFT 8835#define ACCDET_EINT_IVAL_SAM_IN_MASK 0x3836#define ACCDET_EINT_IVAL_SAM_IN_MASK_SFT (0x3 << 8)837#define ACCDET_EINT_IVAL_MEM_IN_ADDR \838 MT6359_ACCDET_CON16839#define ACCDET_EINT_IVAL_MEM_IN_SFT 10840#define ACCDET_EINT_IVAL_MEM_IN_MASK 0x3841#define ACCDET_EINT_IVAL_MEM_IN_MASK_SFT (0x3 << 10)842#define ACCDET_IVAL_SEL_ADDR \843 MT6359_ACCDET_CON16844#define ACCDET_IVAL_SEL_SFT 12845#define ACCDET_IVAL_SEL_MASK 0x1846#define ACCDET_IVAL_SEL_MASK_SFT (0x1 << 12)847#define ACCDET_EINT_IVAL_SEL_ADDR \848 MT6359_ACCDET_CON16849#define ACCDET_EINT_IVAL_SEL_SFT 13850#define ACCDET_EINT_IVAL_SEL_MASK 0x1851#define ACCDET_EINT_IVAL_SEL_MASK_SFT (0x1 << 13)852#define ACCDET_EINT_INVERTER_IVAL_CUR_IN_ADDR \853 MT6359_ACCDET_CON17854#define ACCDET_EINT_INVERTER_IVAL_CUR_IN_SFT 0855#define ACCDET_EINT_INVERTER_IVAL_CUR_IN_MASK 0x1856#define ACCDET_EINT_INVERTER_IVAL_CUR_IN_MASK_SFT (0x1 << 0)857#define ACCDET_EINT_INVERTER_IVAL_SAM_IN_ADDR \858 MT6359_ACCDET_CON17859#define ACCDET_EINT_INVERTER_IVAL_SAM_IN_SFT 1860#define ACCDET_EINT_INVERTER_IVAL_SAM_IN_MASK 0x1861#define ACCDET_EINT_INVERTER_IVAL_SAM_IN_MASK_SFT (0x1 << 1)862#define ACCDET_EINT_INVERTER_IVAL_MEM_IN_ADDR \863 MT6359_ACCDET_CON17864#define ACCDET_EINT_INVERTER_IVAL_MEM_IN_SFT 2865#define ACCDET_EINT_INVERTER_IVAL_MEM_IN_MASK 0x1866#define ACCDET_EINT_INVERTER_IVAL_MEM_IN_MASK_SFT (0x1 << 2)867#define ACCDET_EINT_INVERTER_IVAL_SEL_ADDR \868 MT6359_ACCDET_CON17869#define ACCDET_EINT_INVERTER_IVAL_SEL_SFT 3870#define ACCDET_EINT_INVERTER_IVAL_SEL_MASK 0x1871#define ACCDET_EINT_INVERTER_IVAL_SEL_MASK_SFT (0x1 << 3)872#define ACCDET_IRQ_ADDR \873 MT6359_ACCDET_CON18874#define ACCDET_IRQ_SFT 0875#define ACCDET_IRQ_MASK 0x1876#define ACCDET_IRQ_MASK_SFT (0x1 << 0)877#define ACCDET_EINT0_IRQ_ADDR \878 MT6359_ACCDET_CON18879#define ACCDET_EINT0_IRQ_SFT 2880#define ACCDET_EINT0_IRQ_MASK 0x1881#define ACCDET_EINT0_IRQ_MASK_SFT (0x1 << 2)882#define ACCDET_EINT1_IRQ_ADDR \883 MT6359_ACCDET_CON18884#define ACCDET_EINT1_IRQ_SFT 3885#define ACCDET_EINT1_IRQ_MASK 0x1886#define ACCDET_EINT1_IRQ_MASK_SFT (0x1 << 3)887#define ACCDET_EINT_IN_INVERSE_ADDR \888 MT6359_ACCDET_CON18889#define ACCDET_EINT_IN_INVERSE_SFT 4890#define ACCDET_EINT_IN_INVERSE_MASK 0x1891#define ACCDET_EINT_IN_INVERSE_MASK_SFT (0x1 << 4)892#define ACCDET_IRQ_CLR_ADDR \893 MT6359_ACCDET_CON18894#define ACCDET_IRQ_CLR_SFT 8895#define ACCDET_IRQ_CLR_MASK 0x1896#define ACCDET_IRQ_CLR_MASK_SFT (0x1 << 8)897#define ACCDET_EINT0_IRQ_CLR_ADDR \898 MT6359_ACCDET_CON18899#define ACCDET_EINT0_IRQ_CLR_SFT 10900#define ACCDET_EINT0_IRQ_CLR_MASK 0x1901#define ACCDET_EINT0_IRQ_CLR_MASK_SFT (0x1 << 10)902#define ACCDET_EINT1_IRQ_CLR_ADDR \903 MT6359_ACCDET_CON18904#define ACCDET_EINT1_IRQ_CLR_SFT 11905#define ACCDET_EINT1_IRQ_CLR_MASK 0x1906#define ACCDET_EINT1_IRQ_CLR_MASK_SFT (0x1 << 11)907#define ACCDET_EINT_M_PLUG_IN_NUM_ADDR \908 MT6359_ACCDET_CON18909#define ACCDET_EINT_M_PLUG_IN_NUM_SFT 12910#define ACCDET_EINT_M_PLUG_IN_NUM_MASK 0x7911#define ACCDET_EINT_M_PLUG_IN_NUM_MASK_SFT (0x7 << 12)912#define ACCDET_DA_STABLE_ADDR \913 MT6359_ACCDET_CON19914#define ACCDET_DA_STABLE_SFT 0915#define ACCDET_DA_STABLE_MASK 0x1916#define ACCDET_DA_STABLE_MASK_SFT (0x1 << 0)917#define ACCDET_EINT0_EN_STABLE_ADDR \918 MT6359_ACCDET_CON19919#define ACCDET_EINT0_EN_STABLE_SFT 1920#define ACCDET_EINT0_EN_STABLE_MASK 0x1921#define ACCDET_EINT0_EN_STABLE_MASK_SFT (0x1 << 1)922#define ACCDET_EINT0_CMPEN_STABLE_ADDR \923 MT6359_ACCDET_CON19924#define ACCDET_EINT0_CMPEN_STABLE_SFT 2925#define ACCDET_EINT0_CMPEN_STABLE_MASK 0x1926#define ACCDET_EINT0_CMPEN_STABLE_MASK_SFT (0x1 << 2)927#define ACCDET_EINT0_CMPMEN_STABLE_ADDR \928 MT6359_ACCDET_CON19929#define ACCDET_EINT0_CMPMEN_STABLE_SFT 3930#define ACCDET_EINT0_CMPMEN_STABLE_MASK 0x1931#define ACCDET_EINT0_CMPMEN_STABLE_MASK_SFT (0x1 << 3)932#define ACCDET_EINT0_CTURBO_STABLE_ADDR \933 MT6359_ACCDET_CON19934#define ACCDET_EINT0_CTURBO_STABLE_SFT 4935#define ACCDET_EINT0_CTURBO_STABLE_MASK 0x1936#define ACCDET_EINT0_CTURBO_STABLE_MASK_SFT (0x1 << 4)937#define ACCDET_EINT0_CEN_STABLE_ADDR \938 MT6359_ACCDET_CON19939#define ACCDET_EINT0_CEN_STABLE_SFT 5940#define ACCDET_EINT0_CEN_STABLE_MASK 0x1941#define ACCDET_EINT0_CEN_STABLE_MASK_SFT (0x1 << 5)942#define ACCDET_EINT1_EN_STABLE_ADDR \943 MT6359_ACCDET_CON19944#define ACCDET_EINT1_EN_STABLE_SFT 6945#define ACCDET_EINT1_EN_STABLE_MASK 0x1946#define ACCDET_EINT1_EN_STABLE_MASK_SFT (0x1 << 6)947#define ACCDET_EINT1_CMPEN_STABLE_ADDR \948 MT6359_ACCDET_CON19949#define ACCDET_EINT1_CMPEN_STABLE_SFT 7950#define ACCDET_EINT1_CMPEN_STABLE_MASK 0x1951#define ACCDET_EINT1_CMPEN_STABLE_MASK_SFT (0x1 << 7)952#define ACCDET_EINT1_CMPMEN_STABLE_ADDR \953 MT6359_ACCDET_CON19954#define ACCDET_EINT1_CMPMEN_STABLE_SFT 8955#define ACCDET_EINT1_CMPMEN_STABLE_MASK 0x1956#define ACCDET_EINT1_CMPMEN_STABLE_MASK_SFT (0x1 << 8)957#define ACCDET_EINT1_CTURBO_STABLE_ADDR \958 MT6359_ACCDET_CON19959#define ACCDET_EINT1_CTURBO_STABLE_SFT 9960#define ACCDET_EINT1_CTURBO_STABLE_MASK 0x1961#define ACCDET_EINT1_CTURBO_STABLE_MASK_SFT (0x1 << 9)962#define ACCDET_EINT1_CEN_STABLE_ADDR \963 MT6359_ACCDET_CON19964#define ACCDET_EINT1_CEN_STABLE_SFT 10965#define ACCDET_EINT1_CEN_STABLE_MASK 0x1966#define ACCDET_EINT1_CEN_STABLE_MASK_SFT (0x1 << 10)967#define ACCDET_HWMODE_EN_ADDR \968 MT6359_ACCDET_CON20969#define ACCDET_HWMODE_EN_SFT 0970#define ACCDET_HWMODE_EN_MASK 0x1971#define ACCDET_HWMODE_EN_MASK_SFT (0x1 << 0)972#define ACCDET_HWMODE_SEL_ADDR \973 MT6359_ACCDET_CON20974#define ACCDET_HWMODE_SEL_SFT 1975#define ACCDET_HWMODE_SEL_MASK 0x3976#define ACCDET_HWMODE_SEL_MASK_SFT (0x3 << 1)977#define ACCDET_PLUG_OUT_DETECT_ADDR \978 MT6359_ACCDET_CON20979#define ACCDET_PLUG_OUT_DETECT_SFT 3980#define ACCDET_PLUG_OUT_DETECT_MASK 0x1981#define ACCDET_PLUG_OUT_DETECT_MASK_SFT (0x1 << 3)982#define ACCDET_EINT0_REVERSE_ADDR \983 MT6359_ACCDET_CON20984#define ACCDET_EINT0_REVERSE_SFT 4985#define ACCDET_EINT0_REVERSE_MASK 0x1986#define ACCDET_EINT0_REVERSE_MASK_SFT (0x1 << 4)987#define ACCDET_EINT1_REVERSE_ADDR \988 MT6359_ACCDET_CON20989#define ACCDET_EINT1_REVERSE_SFT 5990#define ACCDET_EINT1_REVERSE_MASK 0x1991#define ACCDET_EINT1_REVERSE_MASK_SFT (0x1 << 5)992#define ACCDET_EINT_HWMODE_EN_ADDR \993 MT6359_ACCDET_CON20994#define ACCDET_EINT_HWMODE_EN_SFT 8995#define ACCDET_EINT_HWMODE_EN_MASK 0x1996#define ACCDET_EINT_HWMODE_EN_MASK_SFT (0x1 << 8)997#define ACCDET_EINT_PLUG_OUT_BYPASS_DEB_ADDR \998 MT6359_ACCDET_CON20999#define ACCDET_EINT_PLUG_OUT_BYPASS_DEB_SFT 91000#define ACCDET_EINT_PLUG_OUT_BYPASS_DEB_MASK 0x11001#define ACCDET_EINT_PLUG_OUT_BYPASS_DEB_MASK_SFT (0x1 << 9)1002#define ACCDET_EINT_M_PLUG_IN_EN_ADDR \1003 MT6359_ACCDET_CON201004#define ACCDET_EINT_M_PLUG_IN_EN_SFT 101005#define ACCDET_EINT_M_PLUG_IN_EN_MASK 0x11006#define ACCDET_EINT_M_PLUG_IN_EN_MASK_SFT (0x1 << 10)1007#define ACCDET_EINT_M_HWMODE_EN_ADDR \1008 MT6359_ACCDET_CON201009#define ACCDET_EINT_M_HWMODE_EN_SFT 111010#define ACCDET_EINT_M_HWMODE_EN_MASK 0x11011#define ACCDET_EINT_M_HWMODE_EN_MASK_SFT (0x1 << 11)1012#define ACCDET_TEST_CMPEN_ADDR \1013 MT6359_ACCDET_CON211014#define ACCDET_TEST_CMPEN_SFT 01015#define ACCDET_TEST_CMPEN_MASK 0x11016#define ACCDET_TEST_CMPEN_MASK_SFT (0x1 << 0)1017#define ACCDET_TEST_VTHEN_ADDR \1018 MT6359_ACCDET_CON211019#define ACCDET_TEST_VTHEN_SFT 11020#define ACCDET_TEST_VTHEN_MASK 0x11021#define ACCDET_TEST_VTHEN_MASK_SFT (0x1 << 1)1022#define ACCDET_TEST_MBIASEN_ADDR \1023 MT6359_ACCDET_CON211024#define ACCDET_TEST_MBIASEN_SFT 21025#define ACCDET_TEST_MBIASEN_MASK 0x11026#define ACCDET_TEST_MBIASEN_MASK_SFT (0x1 << 2)1027#define ACCDET_EINT_TEST_EN_ADDR \1028 MT6359_ACCDET_CON211029#define ACCDET_EINT_TEST_EN_SFT 31030#define ACCDET_EINT_TEST_EN_MASK 0x11031#define ACCDET_EINT_TEST_EN_MASK_SFT (0x1 << 3)1032#define ACCDET_EINT_TEST_INVEN_ADDR \1033 MT6359_ACCDET_CON211034#define ACCDET_EINT_TEST_INVEN_SFT 41035#define ACCDET_EINT_TEST_INVEN_MASK 0x11036#define ACCDET_EINT_TEST_INVEN_MASK_SFT (0x1 << 4)1037#define ACCDET_EINT_TEST_CMPEN_ADDR \1038 MT6359_ACCDET_CON211039#define ACCDET_EINT_TEST_CMPEN_SFT 51040#define ACCDET_EINT_TEST_CMPEN_MASK 0x11041#define ACCDET_EINT_TEST_CMPEN_MASK_SFT (0x1 << 5)1042#define ACCDET_EINT_TEST_CMPMEN_ADDR \1043 MT6359_ACCDET_CON211044#define ACCDET_EINT_TEST_CMPMEN_SFT 61045#define ACCDET_EINT_TEST_CMPMEN_MASK 0x11046#define ACCDET_EINT_TEST_CMPMEN_MASK_SFT (0x1 << 6)1047#define ACCDET_EINT_TEST_CTURBO_ADDR \1048 MT6359_ACCDET_CON211049#define ACCDET_EINT_TEST_CTURBO_SFT 71050#define ACCDET_EINT_TEST_CTURBO_MASK 0x11051#define ACCDET_EINT_TEST_CTURBO_MASK_SFT (0x1 << 7)1052#define ACCDET_EINT_TEST_CEN_ADDR \1053 MT6359_ACCDET_CON211054#define ACCDET_EINT_TEST_CEN_SFT 81055#define ACCDET_EINT_TEST_CEN_MASK 0x11056#define ACCDET_EINT_TEST_CEN_MASK_SFT (0x1 << 8)1057#define ACCDET_TEST_B_ADDR \1058 MT6359_ACCDET_CON211059#define ACCDET_TEST_B_SFT 91060#define ACCDET_TEST_B_MASK 0x11061#define ACCDET_TEST_B_MASK_SFT (0x1 << 9)1062#define ACCDET_TEST_A_ADDR \1063 MT6359_ACCDET_CON211064#define ACCDET_TEST_A_SFT 101065#define ACCDET_TEST_A_MASK 0x11066#define ACCDET_TEST_A_MASK_SFT (0x1 << 10)1067#define ACCDET_EINT_TEST_CMPOUT_ADDR \1068 MT6359_ACCDET_CON211069#define ACCDET_EINT_TEST_CMPOUT_SFT 111070#define ACCDET_EINT_TEST_CMPOUT_MASK 0x11071#define ACCDET_EINT_TEST_CMPOUT_MASK_SFT (0x1 << 11)1072#define ACCDET_EINT_TEST_CMPMOUT_ADDR \1073 MT6359_ACCDET_CON211074#define ACCDET_EINT_TEST_CMPMOUT_SFT 121075#define ACCDET_EINT_TEST_CMPMOUT_MASK 0x11076#define ACCDET_EINT_TEST_CMPMOUT_MASK_SFT (0x1 << 12)1077#define ACCDET_EINT_TEST_INVOUT_ADDR \1078 MT6359_ACCDET_CON211079#define ACCDET_EINT_TEST_INVOUT_SFT 131080#define ACCDET_EINT_TEST_INVOUT_MASK 0x11081#define ACCDET_EINT_TEST_INVOUT_MASK_SFT (0x1 << 13)1082#define ACCDET_CMPEN_SEL_ADDR \1083 MT6359_ACCDET_CON221084#define ACCDET_CMPEN_SEL_SFT 01085#define ACCDET_CMPEN_SEL_MASK 0x11086#define ACCDET_CMPEN_SEL_MASK_SFT (0x1 << 0)1087#define ACCDET_VTHEN_SEL_ADDR \1088 MT6359_ACCDET_CON221089#define ACCDET_VTHEN_SEL_SFT 11090#define ACCDET_VTHEN_SEL_MASK 0x11091#define ACCDET_VTHEN_SEL_MASK_SFT (0x1 << 1)1092#define ACCDET_MBIASEN_SEL_ADDR \1093 MT6359_ACCDET_CON221094#define ACCDET_MBIASEN_SEL_SFT 21095#define ACCDET_MBIASEN_SEL_MASK 0x11096#define ACCDET_MBIASEN_SEL_MASK_SFT (0x1 << 2)1097#define ACCDET_EINT_EN_SEL_ADDR \1098 MT6359_ACCDET_CON221099#define ACCDET_EINT_EN_SEL_SFT 31100#define ACCDET_EINT_EN_SEL_MASK 0x11101#define ACCDET_EINT_EN_SEL_MASK_SFT (0x1 << 3)1102#define ACCDET_EINT_INVEN_SEL_ADDR \1103 MT6359_ACCDET_CON221104#define ACCDET_EINT_INVEN_SEL_SFT 41105#define ACCDET_EINT_INVEN_SEL_MASK 0x11106#define ACCDET_EINT_INVEN_SEL_MASK_SFT (0x1 << 4)1107#define ACCDET_EINT_CMPEN_SEL_ADDR \1108 MT6359_ACCDET_CON221109#define ACCDET_EINT_CMPEN_SEL_SFT 51110#define ACCDET_EINT_CMPEN_SEL_MASK 0x11111#define ACCDET_EINT_CMPEN_SEL_MASK_SFT (0x1 << 5)1112#define ACCDET_EINT_CMPMEN_SEL_ADDR \1113 MT6359_ACCDET_CON221114#define ACCDET_EINT_CMPMEN_SEL_SFT 61115#define ACCDET_EINT_CMPMEN_SEL_MASK 0x11116#define ACCDET_EINT_CMPMEN_SEL_MASK_SFT (0x1 << 6)1117#define ACCDET_EINT_CTURBO_SEL_ADDR \1118 MT6359_ACCDET_CON221119#define ACCDET_EINT_CTURBO_SEL_SFT 71120#define ACCDET_EINT_CTURBO_SEL_MASK 0x11121#define ACCDET_EINT_CTURBO_SEL_MASK_SFT (0x1 << 7)1122#define ACCDET_B_SEL_ADDR \1123 MT6359_ACCDET_CON221124#define ACCDET_B_SEL_SFT 91125#define ACCDET_B_SEL_MASK 0x11126#define ACCDET_B_SEL_MASK_SFT (0x1 << 9)1127#define ACCDET_A_SEL_ADDR \1128 MT6359_ACCDET_CON221129#define ACCDET_A_SEL_SFT 101130#define ACCDET_A_SEL_MASK 0x11131#define ACCDET_A_SEL_MASK_SFT (0x1 << 10)1132#define ACCDET_EINT_CMPOUT_SEL_ADDR \1133 MT6359_ACCDET_CON221134#define ACCDET_EINT_CMPOUT_SEL_SFT 111135#define ACCDET_EINT_CMPOUT_SEL_MASK 0x11136#define ACCDET_EINT_CMPOUT_SEL_MASK_SFT (0x1 << 11)1137#define ACCDET_EINT_CMPMOUT_SEL_ADDR \1138 MT6359_ACCDET_CON221139#define ACCDET_EINT_CMPMOUT_SEL_SFT 121140#define ACCDET_EINT_CMPMOUT_SEL_MASK 0x11141#define ACCDET_EINT_CMPMOUT_SEL_MASK_SFT (0x1 << 12)1142#define ACCDET_EINT_INVOUT_SEL_ADDR \1143 MT6359_ACCDET_CON221144#define ACCDET_EINT_INVOUT_SEL_SFT 131145#define ACCDET_EINT_INVOUT_SEL_MASK 0x11146#define ACCDET_EINT_INVOUT_SEL_MASK_SFT (0x1 << 13)1147#define ACCDET_CMPEN_SW_ADDR \1148 MT6359_ACCDET_CON231149#define ACCDET_CMPEN_SW_SFT 01150#define ACCDET_CMPEN_SW_MASK 0x11151#define ACCDET_CMPEN_SW_MASK_SFT (0x1 << 0)1152#define ACCDET_VTHEN_SW_ADDR \1153 MT6359_ACCDET_CON231154#define ACCDET_VTHEN_SW_SFT 11155#define ACCDET_VTHEN_SW_MASK 0x11156#define ACCDET_VTHEN_SW_MASK_SFT (0x1 << 1)1157#define ACCDET_MBIASEN_SW_ADDR \1158 MT6359_ACCDET_CON231159#define ACCDET_MBIASEN_SW_SFT 21160#define ACCDET_MBIASEN_SW_MASK 0x11161#define ACCDET_MBIASEN_SW_MASK_SFT (0x1 << 2)1162#define ACCDET_EINT0_EN_SW_ADDR \1163 MT6359_ACCDET_CON231164#define ACCDET_EINT0_EN_SW_SFT 31165#define ACCDET_EINT0_EN_SW_MASK 0x11166#define ACCDET_EINT0_EN_SW_MASK_SFT (0x1 << 3)1167#define ACCDET_EINT0_INVEN_SW_ADDR \1168 MT6359_ACCDET_CON231169#define ACCDET_EINT0_INVEN_SW_SFT 41170#define ACCDET_EINT0_INVEN_SW_MASK 0x11171#define ACCDET_EINT0_INVEN_SW_MASK_SFT (0x1 << 4)1172#define ACCDET_EINT0_CMPEN_SW_ADDR \1173 MT6359_ACCDET_CON231174#define ACCDET_EINT0_CMPEN_SW_SFT 51175#define ACCDET_EINT0_CMPEN_SW_MASK 0x11176#define ACCDET_EINT0_CMPEN_SW_MASK_SFT (0x1 << 5)1177#define ACCDET_EINT0_CMPMEN_SW_ADDR \1178 MT6359_ACCDET_CON231179#define ACCDET_EINT0_CMPMEN_SW_SFT 61180#define ACCDET_EINT0_CMPMEN_SW_MASK 0x11181#define ACCDET_EINT0_CMPMEN_SW_MASK_SFT (0x1 << 6)1182#define ACCDET_EINT0_CTURBO_SW_ADDR \1183 MT6359_ACCDET_CON231184#define ACCDET_EINT0_CTURBO_SW_SFT 71185#define ACCDET_EINT0_CTURBO_SW_MASK 0x11186#define ACCDET_EINT0_CTURBO_SW_MASK_SFT (0x1 << 7)1187#define ACCDET_EINT1_EN_SW_ADDR \1188 MT6359_ACCDET_CON231189#define ACCDET_EINT1_EN_SW_SFT 81190#define ACCDET_EINT1_EN_SW_MASK 0x11191#define ACCDET_EINT1_EN_SW_MASK_SFT (0x1 << 8)1192#define ACCDET_EINT1_INVEN_SW_ADDR \1193 MT6359_ACCDET_CON231194#define ACCDET_EINT1_INVEN_SW_SFT 91195#define ACCDET_EINT1_INVEN_SW_MASK 0x11196#define ACCDET_EINT1_INVEN_SW_MASK_SFT (0x1 << 9)1197#define ACCDET_EINT1_CMPEN_SW_ADDR \1198 MT6359_ACCDET_CON231199#define ACCDET_EINT1_CMPEN_SW_SFT 101200#define ACCDET_EINT1_CMPEN_SW_MASK 0x11201#define ACCDET_EINT1_CMPEN_SW_MASK_SFT (0x1 << 10)1202#define ACCDET_EINT1_CMPMEN_SW_ADDR \1203 MT6359_ACCDET_CON231204#define ACCDET_EINT1_CMPMEN_SW_SFT 111205#define ACCDET_EINT1_CMPMEN_SW_MASK 0x11206#define ACCDET_EINT1_CMPMEN_SW_MASK_SFT (0x1 << 11)1207#define ACCDET_EINT1_CTURBO_SW_ADDR \1208 MT6359_ACCDET_CON231209#define ACCDET_EINT1_CTURBO_SW_SFT 121210#define ACCDET_EINT1_CTURBO_SW_MASK 0x11211#define ACCDET_EINT1_CTURBO_SW_MASK_SFT (0x1 << 12)1212#define ACCDET_B_SW_ADDR \1213 MT6359_ACCDET_CON241214#define ACCDET_B_SW_SFT 01215#define ACCDET_B_SW_MASK 0x11216#define ACCDET_B_SW_MASK_SFT (0x1 << 0)1217#define ACCDET_A_SW_ADDR \1218 MT6359_ACCDET_CON241219#define ACCDET_A_SW_SFT 11220#define ACCDET_A_SW_MASK 0x11221#define ACCDET_A_SW_MASK_SFT (0x1 << 1)1222#define ACCDET_EINT0_CMPOUT_SW_ADDR \1223 MT6359_ACCDET_CON241224#define ACCDET_EINT0_CMPOUT_SW_SFT 21225#define ACCDET_EINT0_CMPOUT_SW_MASK 0x11226#define ACCDET_EINT0_CMPOUT_SW_MASK_SFT (0x1 << 2)1227#define ACCDET_EINT0_CMPMOUT_SW_ADDR \1228 MT6359_ACCDET_CON241229#define ACCDET_EINT0_CMPMOUT_SW_SFT 31230#define ACCDET_EINT0_CMPMOUT_SW_MASK 0x11231#define ACCDET_EINT0_CMPMOUT_SW_MASK_SFT (0x1 << 3)1232#define ACCDET_EINT0_INVOUT_SW_ADDR \1233 MT6359_ACCDET_CON241234#define ACCDET_EINT0_INVOUT_SW_SFT 41235#define ACCDET_EINT0_INVOUT_SW_MASK 0x11236#define ACCDET_EINT0_INVOUT_SW_MASK_SFT (0x1 << 4)1237#define ACCDET_EINT1_CMPOUT_SW_ADDR \1238 MT6359_ACCDET_CON241239#define ACCDET_EINT1_CMPOUT_SW_SFT 51240#define ACCDET_EINT1_CMPOUT_SW_MASK 0x11241#define ACCDET_EINT1_CMPOUT_SW_MASK_SFT (0x1 << 5)1242#define ACCDET_EINT1_CMPMOUT_SW_ADDR \1243 MT6359_ACCDET_CON241244#define ACCDET_EINT1_CMPMOUT_SW_SFT 61245#define ACCDET_EINT1_CMPMOUT_SW_MASK 0x11246#define ACCDET_EINT1_CMPMOUT_SW_MASK_SFT (0x1 << 6)1247#define ACCDET_EINT1_INVOUT_SW_ADDR \1248 MT6359_ACCDET_CON241249#define ACCDET_EINT1_INVOUT_SW_SFT 71250#define ACCDET_EINT1_INVOUT_SW_MASK 0x11251#define ACCDET_EINT1_INVOUT_SW_MASK_SFT (0x1 << 7)1252#define AD_AUDACCDETCMPOB_ADDR \1253 MT6359_ACCDET_CON251254#define AD_AUDACCDETCMPOB_SFT 01255#define AD_AUDACCDETCMPOB_MASK 0x11256#define AD_AUDACCDETCMPOB_MASK_SFT (0x1 << 0)1257#define AD_AUDACCDETCMPOA_ADDR \1258 MT6359_ACCDET_CON251259#define AD_AUDACCDETCMPOA_SFT 11260#define AD_AUDACCDETCMPOA_MASK 0x11261#define AD_AUDACCDETCMPOA_MASK_SFT (0x1 << 1)1262#define ACCDET_CUR_IN_ADDR \1263 MT6359_ACCDET_CON251264#define ACCDET_CUR_IN_SFT 21265#define ACCDET_CUR_IN_MASK 0x31266#define ACCDET_CUR_IN_MASK_SFT (0x3 << 2)1267#define ACCDET_SAM_IN_ADDR \1268 MT6359_ACCDET_CON251269#define ACCDET_SAM_IN_SFT 41270#define ACCDET_SAM_IN_MASK 0x31271#define ACCDET_SAM_IN_MASK_SFT (0x3 << 4)1272#define ACCDET_MEM_IN_ADDR \1273 MT6359_ACCDET_CON251274#define ACCDET_MEM_IN_SFT 61275#define ACCDET_MEM_IN_MASK 0x31276#define ACCDET_MEM_IN_MASK_SFT (0x3 << 6)1277#define ACCDET_STATE_ADDR \1278 MT6359_ACCDET_CON251279#define ACCDET_STATE_SFT 81280#define ACCDET_STATE_MASK 0x71281#define ACCDET_STATE_MASK_SFT (0x7 << 8)1282#define DA_AUDACCDETMBIASCLK_ADDR \1283 MT6359_ACCDET_CON251284#define DA_AUDACCDETMBIASCLK_SFT 121285#define DA_AUDACCDETMBIASCLK_MASK 0x11286#define DA_AUDACCDETMBIASCLK_MASK_SFT (0x1 << 12)1287#define DA_AUDACCDETVTHCLK_ADDR \1288 MT6359_ACCDET_CON251289#define DA_AUDACCDETVTHCLK_SFT 131290#define DA_AUDACCDETVTHCLK_MASK 0x11291#define DA_AUDACCDETVTHCLK_MASK_SFT (0x1 << 13)1292#define DA_AUDACCDETCMPCLK_ADDR \1293 MT6359_ACCDET_CON251294#define DA_AUDACCDETCMPCLK_SFT 141295#define DA_AUDACCDETCMPCLK_MASK 0x11296#define DA_AUDACCDETCMPCLK_MASK_SFT (0x1 << 14)1297#define DA_AUDACCDETAUXADCSWCTRL_ADDR \1298 MT6359_ACCDET_CON251299#define DA_AUDACCDETAUXADCSWCTRL_SFT 151300#define DA_AUDACCDETAUXADCSWCTRL_MASK 0x11301#define DA_AUDACCDETAUXADCSWCTRL_MASK_SFT (0x1 << 15)1302#define AD_EINT0CMPMOUT_ADDR \1303 MT6359_ACCDET_CON261304#define AD_EINT0CMPMOUT_SFT 01305#define AD_EINT0CMPMOUT_MASK 0x11306#define AD_EINT0CMPMOUT_MASK_SFT (0x1 << 0)1307#define AD_EINT0CMPOUT_ADDR \1308 MT6359_ACCDET_CON261309#define AD_EINT0CMPOUT_SFT 11310#define AD_EINT0CMPOUT_MASK 0x11311#define AD_EINT0CMPOUT_MASK_SFT (0x1 << 1)1312#define ACCDET_EINT0_CUR_IN_ADDR \1313 MT6359_ACCDET_CON261314#define ACCDET_EINT0_CUR_IN_SFT 21315#define ACCDET_EINT0_CUR_IN_MASK 0x31316#define ACCDET_EINT0_CUR_IN_MASK_SFT (0x3 << 2)1317#define ACCDET_EINT0_SAM_IN_ADDR \1318 MT6359_ACCDET_CON261319#define ACCDET_EINT0_SAM_IN_SFT 41320#define ACCDET_EINT0_SAM_IN_MASK 0x31321#define ACCDET_EINT0_SAM_IN_MASK_SFT (0x3 << 4)1322#define ACCDET_EINT0_MEM_IN_ADDR \1323 MT6359_ACCDET_CON261324#define ACCDET_EINT0_MEM_IN_SFT 61325#define ACCDET_EINT0_MEM_IN_MASK 0x31326#define ACCDET_EINT0_MEM_IN_MASK_SFT (0x3 << 6)1327#define ACCDET_EINT0_STATE_ADDR \1328 MT6359_ACCDET_CON261329#define ACCDET_EINT0_STATE_SFT 81330#define ACCDET_EINT0_STATE_MASK 0x71331#define ACCDET_EINT0_STATE_MASK_SFT (0x7 << 8)1332#define DA_EINT0CMPEN_ADDR \1333 MT6359_ACCDET_CON261334#define DA_EINT0CMPEN_SFT 131335#define DA_EINT0CMPEN_MASK 0x11336#define DA_EINT0CMPEN_MASK_SFT (0x1 << 13)1337#define DA_EINT0CMPMEN_ADDR \1338 MT6359_ACCDET_CON261339#define DA_EINT0CMPMEN_SFT 141340#define DA_EINT0CMPMEN_MASK 0x11341#define DA_EINT0CMPMEN_MASK_SFT (0x1 << 14)1342#define DA_EINT0CTURBO_ADDR \1343 MT6359_ACCDET_CON261344#define DA_EINT0CTURBO_SFT 151345#define DA_EINT0CTURBO_MASK 0x11346#define DA_EINT0CTURBO_MASK_SFT (0x1 << 15)1347#define AD_EINT1CMPMOUT_ADDR \1348 MT6359_ACCDET_CON271349#define AD_EINT1CMPMOUT_SFT 01350#define AD_EINT1CMPMOUT_MASK 0x11351#define AD_EINT1CMPMOUT_MASK_SFT (0x1 << 0)1352#define AD_EINT1CMPOUT_ADDR \1353 MT6359_ACCDET_CON271354#define AD_EINT1CMPOUT_SFT 11355#define AD_EINT1CMPOUT_MASK 0x11356#define AD_EINT1CMPOUT_MASK_SFT (0x1 << 1)1357#define ACCDET_EINT1_CUR_IN_ADDR \1358 MT6359_ACCDET_CON271359#define ACCDET_EINT1_CUR_IN_SFT 21360#define ACCDET_EINT1_CUR_IN_MASK 0x31361#define ACCDET_EINT1_CUR_IN_MASK_SFT (0x3 << 2)1362#define ACCDET_EINT1_SAM_IN_ADDR \1363 MT6359_ACCDET_CON271364#define ACCDET_EINT1_SAM_IN_SFT 41365#define ACCDET_EINT1_SAM_IN_MASK 0x31366#define ACCDET_EINT1_SAM_IN_MASK_SFT (0x3 << 4)1367#define ACCDET_EINT1_MEM_IN_ADDR \1368 MT6359_ACCDET_CON271369#define ACCDET_EINT1_MEM_IN_SFT 61370#define ACCDET_EINT1_MEM_IN_MASK 0x31371#define ACCDET_EINT1_MEM_IN_MASK_SFT (0x3 << 6)1372#define ACCDET_EINT1_STATE_ADDR \1373 MT6359_ACCDET_CON271374#define ACCDET_EINT1_STATE_SFT 81375#define ACCDET_EINT1_STATE_MASK 0x71376#define ACCDET_EINT1_STATE_MASK_SFT (0x7 << 8)1377#define DA_EINT1CMPEN_ADDR \1378 MT6359_ACCDET_CON271379#define DA_EINT1CMPEN_SFT 131380#define DA_EINT1CMPEN_MASK 0x11381#define DA_EINT1CMPEN_MASK_SFT (0x1 << 13)1382#define DA_EINT1CMPMEN_ADDR \1383 MT6359_ACCDET_CON271384#define DA_EINT1CMPMEN_SFT 141385#define DA_EINT1CMPMEN_MASK 0x11386#define DA_EINT1CMPMEN_MASK_SFT (0x1 << 14)1387#define DA_EINT1CTURBO_ADDR \1388 MT6359_ACCDET_CON271389#define DA_EINT1CTURBO_SFT 151390#define DA_EINT1CTURBO_MASK 0x11391#define DA_EINT1CTURBO_MASK_SFT (0x1 << 15)1392#define AD_EINT0INVOUT_ADDR \1393 MT6359_ACCDET_CON281394#define AD_EINT0INVOUT_SFT 01395#define AD_EINT0INVOUT_MASK 0x11396#define AD_EINT0INVOUT_MASK_SFT (0x1 << 0)1397#define ACCDET_EINT0_INVERTER_CUR_IN_ADDR \1398 MT6359_ACCDET_CON281399#define ACCDET_EINT0_INVERTER_CUR_IN_SFT 11400#define ACCDET_EINT0_INVERTER_CUR_IN_MASK 0x11401#define ACCDET_EINT0_INVERTER_CUR_IN_MASK_SFT (0x1 << 1)1402#define ACCDET_EINT0_INVERTER_SAM_IN_ADDR \1403 MT6359_ACCDET_CON281404#define ACCDET_EINT0_INVERTER_SAM_IN_SFT 21405#define ACCDET_EINT0_INVERTER_SAM_IN_MASK 0x11406#define ACCDET_EINT0_INVERTER_SAM_IN_MASK_SFT (0x1 << 2)1407#define ACCDET_EINT0_INVERTER_MEM_IN_ADDR \1408 MT6359_ACCDET_CON281409#define ACCDET_EINT0_INVERTER_MEM_IN_SFT 31410#define ACCDET_EINT0_INVERTER_MEM_IN_MASK 0x11411#define ACCDET_EINT0_INVERTER_MEM_IN_MASK_SFT (0x1 << 3)1412#define ACCDET_EINT0_INVERTER_STATE_ADDR \1413 MT6359_ACCDET_CON281414#define ACCDET_EINT0_INVERTER_STATE_SFT 81415#define ACCDET_EINT0_INVERTER_STATE_MASK 0x71416#define ACCDET_EINT0_INVERTER_STATE_MASK_SFT (0x7 << 8)1417#define DA_EINT0EN_ADDR \1418 MT6359_ACCDET_CON281419#define DA_EINT0EN_SFT 121420#define DA_EINT0EN_MASK 0x11421#define DA_EINT0EN_MASK_SFT (0x1 << 12)1422#define DA_EINT0INVEN_ADDR \1423 MT6359_ACCDET_CON281424#define DA_EINT0INVEN_SFT 131425#define DA_EINT0INVEN_MASK 0x11426#define DA_EINT0INVEN_MASK_SFT (0x1 << 13)1427#define DA_EINT0CEN_ADDR \1428 MT6359_ACCDET_CON281429#define DA_EINT0CEN_SFT 141430#define DA_EINT0CEN_MASK 0x11431#define DA_EINT0CEN_MASK_SFT (0x1 << 14)1432#define AD_EINT1INVOUT_ADDR \1433 MT6359_ACCDET_CON291434#define AD_EINT1INVOUT_SFT 01435#define AD_EINT1INVOUT_MASK 0x11436#define AD_EINT1INVOUT_MASK_SFT (0x1 << 0)1437#define ACCDET_EINT1_INVERTER_CUR_IN_ADDR \1438 MT6359_ACCDET_CON291439#define ACCDET_EINT1_INVERTER_CUR_IN_SFT 11440#define ACCDET_EINT1_INVERTER_CUR_IN_MASK 0x11441#define ACCDET_EINT1_INVERTER_CUR_IN_MASK_SFT (0x1 << 1)1442#define ACCDET_EINT1_INVERTER_SAM_IN_ADDR \1443 MT6359_ACCDET_CON291444#define ACCDET_EINT1_INVERTER_SAM_IN_SFT 21445#define ACCDET_EINT1_INVERTER_SAM_IN_MASK 0x11446#define ACCDET_EINT1_INVERTER_SAM_IN_MASK_SFT (0x1 << 2)1447#define ACCDET_EINT1_INVERTER_MEM_IN_ADDR \1448 MT6359_ACCDET_CON291449#define ACCDET_EINT1_INVERTER_MEM_IN_SFT 31450#define ACCDET_EINT1_INVERTER_MEM_IN_MASK 0x11451#define ACCDET_EINT1_INVERTER_MEM_IN_MASK_SFT (0x1 << 3)1452#define ACCDET_EINT1_INVERTER_STATE_ADDR \1453 MT6359_ACCDET_CON291454#define ACCDET_EINT1_INVERTER_STATE_SFT 81455#define ACCDET_EINT1_INVERTER_STATE_MASK 0x71456#define ACCDET_EINT1_INVERTER_STATE_MASK_SFT (0x7 << 8)1457#define DA_EINT1EN_ADDR \1458 MT6359_ACCDET_CON291459#define DA_EINT1EN_SFT 121460#define DA_EINT1EN_MASK 0x11461#define DA_EINT1EN_MASK_SFT (0x1 << 12)1462#define DA_EINT1INVEN_ADDR \1463 MT6359_ACCDET_CON291464#define DA_EINT1INVEN_SFT 131465#define DA_EINT1INVEN_MASK 0x11466#define DA_EINT1INVEN_MASK_SFT (0x1 << 13)1467#define DA_EINT1CEN_ADDR \1468 MT6359_ACCDET_CON291469#define DA_EINT1CEN_SFT 141470#define DA_EINT1CEN_MASK 0x11471#define DA_EINT1CEN_MASK_SFT (0x1 << 14)1472#define ACCDET_EN_ADDR \1473 MT6359_ACCDET_CON301474#define ACCDET_EN_SFT 01475#define ACCDET_EN_MASK 0x11476#define ACCDET_EN_MASK_SFT (0x1 << 0)1477#define ACCDET_EINT0_EN_ADDR \1478 MT6359_ACCDET_CON301479#define ACCDET_EINT0_EN_SFT 11480#define ACCDET_EINT0_EN_MASK 0x11481#define ACCDET_EINT0_EN_MASK_SFT (0x1 << 1)1482#define ACCDET_EINT1_EN_ADDR \1483 MT6359_ACCDET_CON301484#define ACCDET_EINT1_EN_SFT 21485#define ACCDET_EINT1_EN_MASK 0x11486#define ACCDET_EINT1_EN_MASK_SFT (0x1 << 2)1487#define ACCDET_EINT0_M_EN_ADDR \1488 MT6359_ACCDET_CON301489#define ACCDET_EINT0_M_EN_SFT 31490#define ACCDET_EINT0_M_EN_MASK 0x11491#define ACCDET_EINT0_M_EN_MASK_SFT (0x1 << 3)1492#define ACCDET_EINT0_DETECT_MOISTURE_ADDR \1493 MT6359_ACCDET_CON301494#define ACCDET_EINT0_DETECT_MOISTURE_SFT 41495#define ACCDET_EINT0_DETECT_MOISTURE_MASK 0x11496#define ACCDET_EINT0_DETECT_MOISTURE_MASK_SFT (0x1 << 4)1497#define ACCDET_EINT0_PLUG_IN_ADDR \1498 MT6359_ACCDET_CON301499#define ACCDET_EINT0_PLUG_IN_SFT 51500#define ACCDET_EINT0_PLUG_IN_MASK 0x11501#define ACCDET_EINT0_PLUG_IN_MASK_SFT (0x1 << 5)1502#define ACCDET_EINT0_M_PLUG_IN_ADDR \1503 MT6359_ACCDET_CON301504#define ACCDET_EINT0_M_PLUG_IN_SFT 61505#define ACCDET_EINT0_M_PLUG_IN_MASK 0x11506#define ACCDET_EINT0_M_PLUG_IN_MASK_SFT (0x1 << 6)1507#define ACCDET_EINT1_M_EN_ADDR \1508 MT6359_ACCDET_CON301509#define ACCDET_EINT1_M_EN_SFT 71510#define ACCDET_EINT1_M_EN_MASK 0x11511#define ACCDET_EINT1_M_EN_MASK_SFT (0x1 << 7)1512#define ACCDET_EINT1_DETECT_MOISTURE_ADDR \1513 MT6359_ACCDET_CON301514#define ACCDET_EINT1_DETECT_MOISTURE_SFT 81515#define ACCDET_EINT1_DETECT_MOISTURE_MASK 0x11516#define ACCDET_EINT1_DETECT_MOISTURE_MASK_SFT (0x1 << 8)1517#define ACCDET_EINT1_PLUG_IN_ADDR \1518 MT6359_ACCDET_CON301519#define ACCDET_EINT1_PLUG_IN_SFT 91520#define ACCDET_EINT1_PLUG_IN_MASK 0x11521#define ACCDET_EINT1_PLUG_IN_MASK_SFT (0x1 << 9)1522#define ACCDET_EINT1_M_PLUG_IN_ADDR \1523 MT6359_ACCDET_CON301524#define ACCDET_EINT1_M_PLUG_IN_SFT 101525#define ACCDET_EINT1_M_PLUG_IN_MASK 0x11526#define ACCDET_EINT1_M_PLUG_IN_MASK_SFT (0x1 << 10)1527#define ACCDET_CUR_DEB_ADDR \1528 MT6359_ACCDET_CON311529#define ACCDET_CUR_DEB_SFT 01530#define ACCDET_CUR_DEB_MASK 0xFFFF1531#define ACCDET_CUR_DEB_MASK_SFT (0xFFFF << 0)1532#define ACCDET_EINT0_CUR_DEB_ADDR \1533 MT6359_ACCDET_CON321534#define ACCDET_EINT0_CUR_DEB_SFT 01535#define ACCDET_EINT0_CUR_DEB_MASK 0x7FFF1536#define ACCDET_EINT0_CUR_DEB_MASK_SFT (0x7FFF << 0)1537#define ACCDET_EINT1_CUR_DEB_ADDR \1538 MT6359_ACCDET_CON331539#define ACCDET_EINT1_CUR_DEB_SFT 01540#define ACCDET_EINT1_CUR_DEB_MASK 0x7FFF1541#define ACCDET_EINT1_CUR_DEB_MASK_SFT (0x7FFF << 0)1542#define ACCDET_EINT0_INVERTER_CUR_DEB_ADDR \1543 MT6359_ACCDET_CON341544#define ACCDET_EINT0_INVERTER_CUR_DEB_SFT 01545#define ACCDET_EINT0_INVERTER_CUR_DEB_MASK 0x7FFF1546#define ACCDET_EINT0_INVERTER_CUR_DEB_MASK_SFT (0x7FFF << 0)1547#define ACCDET_EINT1_INVERTER_CUR_DEB_ADDR \1548 MT6359_ACCDET_CON351549#define ACCDET_EINT1_INVERTER_CUR_DEB_SFT 01550#define ACCDET_EINT1_INVERTER_CUR_DEB_MASK 0x7FFF1551#define ACCDET_EINT1_INVERTER_CUR_DEB_MASK_SFT (0x7FFF << 0)1552#define AD_AUDACCDETCMPOB_MON_ADDR \1553 MT6359_ACCDET_CON361554#define AD_AUDACCDETCMPOB_MON_SFT 01555#define AD_AUDACCDETCMPOB_MON_MASK 0x11556#define AD_AUDACCDETCMPOB_MON_MASK_SFT (0x1 << 0)1557#define AD_AUDACCDETCMPOA_MON_ADDR \1558 MT6359_ACCDET_CON361559#define AD_AUDACCDETCMPOA_MON_SFT 11560#define AD_AUDACCDETCMPOA_MON_MASK 0x11561#define AD_AUDACCDETCMPOA_MON_MASK_SFT (0x1 << 1)1562#define AD_EINT0CMPMOUT_MON_ADDR \1563 MT6359_ACCDET_CON361564#define AD_EINT0CMPMOUT_MON_SFT 21565#define AD_EINT0CMPMOUT_MON_MASK 0x11566#define AD_EINT0CMPMOUT_MON_MASK_SFT (0x1 << 2)1567#define AD_EINT0CMPOUT_MON_ADDR \1568 MT6359_ACCDET_CON361569#define AD_EINT0CMPOUT_MON_SFT 31570#define AD_EINT0CMPOUT_MON_MASK 0x11571#define AD_EINT0CMPOUT_MON_MASK_SFT (0x1 << 3)1572#define AD_EINT0INVOUT_MON_ADDR \1573 MT6359_ACCDET_CON361574#define AD_EINT0INVOUT_MON_SFT 41575#define AD_EINT0INVOUT_MON_MASK 0x11576#define AD_EINT0INVOUT_MON_MASK_SFT (0x1 << 4)1577#define AD_EINT1CMPMOUT_MON_ADDR \1578 MT6359_ACCDET_CON361579#define AD_EINT1CMPMOUT_MON_SFT 51580#define AD_EINT1CMPMOUT_MON_MASK 0x11581#define AD_EINT1CMPMOUT_MON_MASK_SFT (0x1 << 5)1582#define AD_EINT1CMPOUT_MON_ADDR \1583 MT6359_ACCDET_CON361584#define AD_EINT1CMPOUT_MON_SFT 61585#define AD_EINT1CMPOUT_MON_MASK 0x11586#define AD_EINT1CMPOUT_MON_MASK_SFT (0x1 << 6)1587#define AD_EINT1INVOUT_MON_ADDR \1588 MT6359_ACCDET_CON361589#define AD_EINT1INVOUT_MON_SFT 71590#define AD_EINT1INVOUT_MON_MASK 0x11591#define AD_EINT1INVOUT_MON_MASK_SFT (0x1 << 7)1592#define DA_AUDACCDETCMPCLK_MON_ADDR \1593 MT6359_ACCDET_CON371594#define DA_AUDACCDETCMPCLK_MON_SFT 01595#define DA_AUDACCDETCMPCLK_MON_MASK 0x11596#define DA_AUDACCDETCMPCLK_MON_MASK_SFT (0x1 << 0)1597#define DA_AUDACCDETVTHCLK_MON_ADDR \1598 MT6359_ACCDET_CON371599#define DA_AUDACCDETVTHCLK_MON_SFT 11600#define DA_AUDACCDETVTHCLK_MON_MASK 0x11601#define DA_AUDACCDETVTHCLK_MON_MASK_SFT (0x1 << 1)1602#define DA_AUDACCDETMBIASCLK_MON_ADDR \1603 MT6359_ACCDET_CON371604#define DA_AUDACCDETMBIASCLK_MON_SFT 21605#define DA_AUDACCDETMBIASCLK_MON_MASK 0x11606#define DA_AUDACCDETMBIASCLK_MON_MASK_SFT (0x1 << 2)1607#define DA_AUDACCDETAUXADCSWCTRL_MON_ADDR \1608 MT6359_ACCDET_CON371609#define DA_AUDACCDETAUXADCSWCTRL_MON_SFT 31610#define DA_AUDACCDETAUXADCSWCTRL_MON_MASK 0x11611#define DA_AUDACCDETAUXADCSWCTRL_MON_MASK_SFT (0x1 << 3)1612#define DA_EINT0CTURBO_MON_ADDR \1613 MT6359_ACCDET_CON381614#define DA_EINT0CTURBO_MON_SFT 01615#define DA_EINT0CTURBO_MON_MASK 0x11616#define DA_EINT0CTURBO_MON_MASK_SFT (0x1 << 0)1617#define DA_EINT0CMPMEN_MON_ADDR \1618 MT6359_ACCDET_CON381619#define DA_EINT0CMPMEN_MON_SFT 11620#define DA_EINT0CMPMEN_MON_MASK 0x11621#define DA_EINT0CMPMEN_MON_MASK_SFT (0x1 << 1)1622#define DA_EINT0CMPEN_MON_ADDR \1623 MT6359_ACCDET_CON381624#define DA_EINT0CMPEN_MON_SFT 21625#define DA_EINT0CMPEN_MON_MASK 0x11626#define DA_EINT0CMPEN_MON_MASK_SFT (0x1 << 2)1627#define DA_EINT0INVEN_MON_ADDR \1628 MT6359_ACCDET_CON381629#define DA_EINT0INVEN_MON_SFT 31630#define DA_EINT0INVEN_MON_MASK 0x11631#define DA_EINT0INVEN_MON_MASK_SFT (0x1 << 3)1632#define DA_EINT0CEN_MON_ADDR \1633 MT6359_ACCDET_CON381634#define DA_EINT0CEN_MON_SFT 41635#define DA_EINT0CEN_MON_MASK 0x11636#define DA_EINT0CEN_MON_MASK_SFT (0x1 << 4)1637#define DA_EINT0EN_MON_ADDR \1638 MT6359_ACCDET_CON381639#define DA_EINT0EN_MON_SFT 51640#define DA_EINT0EN_MON_MASK 0x11641#define DA_EINT0EN_MON_MASK_SFT (0x1 << 5)1642#define DA_EINT1CTURBO_MON_ADDR \1643 MT6359_ACCDET_CON381644#define DA_EINT1CTURBO_MON_SFT 81645#define DA_EINT1CTURBO_MON_MASK 0x11646#define DA_EINT1CTURBO_MON_MASK_SFT (0x1 << 8)1647#define DA_EINT1CMPMEN_MON_ADDR \1648 MT6359_ACCDET_CON381649#define DA_EINT1CMPMEN_MON_SFT 91650#define DA_EINT1CMPMEN_MON_MASK 0x11651#define DA_EINT1CMPMEN_MON_MASK_SFT (0x1 << 9)1652#define DA_EINT1CMPEN_MON_ADDR \1653 MT6359_ACCDET_CON381654#define DA_EINT1CMPEN_MON_SFT 101655#define DA_EINT1CMPEN_MON_MASK 0x11656#define DA_EINT1CMPEN_MON_MASK_SFT (0x1 << 10)1657#define DA_EINT1INVEN_MON_ADDR \1658 MT6359_ACCDET_CON381659#define DA_EINT1INVEN_MON_SFT 111660#define DA_EINT1INVEN_MON_MASK 0x11661#define DA_EINT1INVEN_MON_MASK_SFT (0x1 << 11)1662#define DA_EINT1CEN_MON_ADDR \1663 MT6359_ACCDET_CON381664#define DA_EINT1CEN_MON_SFT 121665#define DA_EINT1CEN_MON_MASK 0x11666#define DA_EINT1CEN_MON_MASK_SFT (0x1 << 12)1667#define DA_EINT1EN_MON_ADDR \1668 MT6359_ACCDET_CON381669#define DA_EINT1EN_MON_SFT 131670#define DA_EINT1EN_MON_MASK 0x11671#define DA_EINT1EN_MON_MASK_SFT (0x1 << 13)1672#define ACCDET_EINT0_M_PLUG_IN_COUNT_ADDR \1673 MT6359_ACCDET_CON391674#define ACCDET_EINT0_M_PLUG_IN_COUNT_SFT 01675#define ACCDET_EINT0_M_PLUG_IN_COUNT_MASK 0x71676#define ACCDET_EINT0_M_PLUG_IN_COUNT_MASK_SFT (0x7 << 0)1677#define ACCDET_EINT1_M_PLUG_IN_COUNT_ADDR \1678 MT6359_ACCDET_CON391679#define ACCDET_EINT1_M_PLUG_IN_COUNT_SFT 41680#define ACCDET_EINT1_M_PLUG_IN_COUNT_MASK 0x71681#define ACCDET_EINT1_M_PLUG_IN_COUNT_MASK_SFT (0x7 << 4)1682#define ACCDET_MON_FLAG_EN_ADDR \1683 MT6359_ACCDET_CON401684#define ACCDET_MON_FLAG_EN_SFT 01685#define ACCDET_MON_FLAG_EN_MASK 0x11686#define ACCDET_MON_FLAG_EN_MASK_SFT (0x1 << 0)1687#define ACCDET_MON_FLAG_SEL_ADDR \1688 MT6359_ACCDET_CON401689#define ACCDET_MON_FLAG_SEL_SFT 41690#define ACCDET_MON_FLAG_SEL_MASK 0xF1691#define ACCDET_MON_FLAG_SEL_MASK_SFT (0xF << 4)1692 1693#define RG_AUDPWDBMICBIAS0_ADDR \1694 MT6359_AUDENC_ANA_CON151695#define RG_AUDPWDBMICBIAS0_SFT 01696#define RG_AUDPWDBMICBIAS0_MASK 0x11697#define RG_AUDPWDBMICBIAS0_MASK_SFT (0x1 << 0)1698#define RG_AUDPREAMPLON_ADDR \1699 MT6359_AUDENC_ANA_CON01700#define RG_AUDPREAMPLON_SFT 01701#define RG_AUDPREAMPLON_MASK 0x11702#define RG_AUDPREAMPLON_MASK_SFT (0x1 << 0)1703#define RG_CLKSQ_EN_ADDR \1704 MT6359_AUDENC_ANA_CON231705#define RG_CLKSQ_EN_SFT 01706#define RG_CLKSQ_EN_MASK 0x11707#define RG_CLKSQ_EN_MASK_SFT (0x1 << 0)1708#define RG_RTC32K_CK_PDN_ADDR \1709 MT6359_TOP_CKPDN_CON01710#define RG_RTC32K_CK_PDN_SFT 151711#define RG_RTC32K_CK_PDN_MASK 0x11712#define RG_RTC32K_CK_PDN_MASK_SFT (0x1 << 15)1713#define RG_HPLOUTPUTSTBENH_VAUDP32_ADDR \1714 MT6359_AUDDEC_ANA_CON21715#define RG_HPLOUTPUTSTBENH_VAUDP32_SFT 01716#define RG_HPLOUTPUTSTBENH_VAUDP32_MASK 0x71717#define RG_HPLOUTPUTSTBENH_VAUDP32_MASK_SFT (0x7 << 0)1718#define AUXADC_RQST_CH5_ADDR \1719 MT6359_AUXADC_RQST01720#define AUXADC_RQST_CH5_SFT 51721#define AUXADC_RQST_CH5_MASK 0x11722#define AUXADC_RQST_CH5_MASK_SFT (0x1 << 5)1723#define RG_LDO_VUSB_HW0_OP_EN_ADDR \1724 MT6359_LDO_VUSB_OP_EN1725#define RG_LDO_VUSB_HW0_OP_EN_SFT 01726#define RG_LDO_VUSB_HW0_OP_EN_MASK 0x11727#define RG_LDO_VUSB_HW0_OP_EN_MASK_SFT (0x1 << 0)1728#define RG_HPROUTPUTSTBENH_VAUDP32_ADDR \1729 MT6359_AUDDEC_ANA_CON21730#define RG_HPROUTPUTSTBENH_VAUDP32_SFT 41731#define RG_HPROUTPUTSTBENH_VAUDP32_MASK 0x71732#define RG_HPROUTPUTSTBENH_VAUDP32_MASK_SFT (0x7 << 4)1733#define RG_NCP_PDDIS_EN_ADDR \1734 MT6359_AFE_NCP_CFG21735#define RG_NCP_PDDIS_EN_SFT 01736#define RG_NCP_PDDIS_EN_MASK 0x11737#define RG_NCP_PDDIS_EN_MASK_SFT (0x1 << 0)1738#define RG_SCK32K_CK_PDN_ADDR \1739 MT6359_TOP_CKPDN_CON01740#define RG_SCK32K_CK_PDN_SFT 01741#define RG_SCK32K_CK_PDN_MASK 0x11742#define RG_SCK32K_CK_PDN_MASK_SFT (0x1 << 0)1743/* AUDENC_ANA_CON18: */1744#define RG_ACCDET_MODE_ANA11_MODE1 (0x000F)1745#define RG_ACCDET_MODE_ANA11_MODE2 (0x008F)1746#define RG_ACCDET_MODE_ANA11_MODE6 (0x008F)1747 1748/* AUXADC_ADC5: Auxadc CH5 read data */1749#define AUXADC_DATA_RDY_CH5 BIT(15)1750#define AUXADC_DATA_PROCEED_CH5 BIT(15)1751#define AUXADC_DATA_MASK (0x0FFF)1752 1753/* AUXADC_RQST0_SET: Auxadc CH5 request, relevant 0x07EC */1754#define AUXADC_RQST_CH5_SET BIT(5)1755/* AUXADC_RQST0_CLR: Auxadc CH5 request, relevant 0x07EC */1756#define AUXADC_RQST_CH5_CLR BIT(5)1757 1758#define ACCDET_CALI_MASK0 (0xFF)1759#define ACCDET_CALI_MASK1 (0xFF << 8)1760#define ACCDET_CALI_MASK2 (0xFF)1761#define ACCDET_CALI_MASK3 (0xFF << 8)1762#define ACCDET_CALI_MASK4 (0xFF)1763 1764#define ACCDET_EINT_IRQ_B2_B3 (0x03 << ACCDET_EINT0_IRQ_SFT)1765 1766/* ACCDET_CON25: RO, accdet FSM state,etc.*/1767#define ACCDET_STATE_MEM_IN_OFFSET (ACCDET_MEM_IN_SFT)1768#define ACCDET_STATE_AB_MASK (0x03)1769#define ACCDET_STATE_AB_00 (0x00)1770#define ACCDET_STATE_AB_01 (0x01)1771#define ACCDET_STATE_AB_10 (0x02)1772#define ACCDET_STATE_AB_11 (0x03)1773 1774/* ACCDET_CON19 */1775#define ACCDET_EINT0_STABLE_VAL ((ACCDET_DA_STABLE_MASK_SFT) | \1776 (ACCDET_EINT0_EN_STABLE_MASK_SFT) | \1777 (ACCDET_EINT0_CMPEN_STABLE_MASK_SFT) | \1778 (ACCDET_EINT0_CEN_STABLE_MASK_SFT))1779 1780#define ACCDET_EINT1_STABLE_VAL ((ACCDET_DA_STABLE_MASK_SFT) | \1781 (ACCDET_EINT1_EN_STABLE_MASK_SFT) | \1782 (ACCDET_EINT1_CMPEN_STABLE_MASK_SFT) | \1783 (ACCDET_EINT1_CEN_STABLE_MASK_SFT))1784/* The following are used for mt6359.c */1785/* MT6359_DCXO_CW12 */1786#define RG_XO_AUDIO_EN_M_SFT 131787 1788/* AUD_TOP_CKPDN_CON0 */1789#define RG_VOW13M_CK_PDN_SFT 131790#define RG_VOW13M_CK_PDN_MASK 0x11791#define RG_VOW13M_CK_PDN_MASK_SFT (0x1 << 13)1792#define RG_VOW32K_CK_PDN_SFT 121793#define RG_VOW32K_CK_PDN_MASK 0x11794#define RG_VOW32K_CK_PDN_MASK_SFT (0x1 << 12)1795#define RG_AUD_INTRP_CK_PDN_SFT 81796#define RG_AUD_INTRP_CK_PDN_MASK 0x11797#define RG_AUD_INTRP_CK_PDN_MASK_SFT (0x1 << 8)1798#define RG_PAD_AUD_CLK_MISO_CK_PDN_SFT 71799#define RG_PAD_AUD_CLK_MISO_CK_PDN_MASK 0x11800#define RG_PAD_AUD_CLK_MISO_CK_PDN_MASK_SFT (0x1 << 7)1801#define RG_AUDNCP_CK_PDN_SFT 61802#define RG_AUDNCP_CK_PDN_MASK 0x11803#define RG_AUDNCP_CK_PDN_MASK_SFT (0x1 << 6)1804#define RG_ZCD13M_CK_PDN_SFT 51805#define RG_ZCD13M_CK_PDN_MASK 0x11806#define RG_ZCD13M_CK_PDN_MASK_SFT (0x1 << 5)1807#define RG_AUDIF_CK_PDN_SFT 21808#define RG_AUDIF_CK_PDN_MASK 0x11809#define RG_AUDIF_CK_PDN_MASK_SFT (0x1 << 2)1810#define RG_AUD_CK_PDN_SFT 11811#define RG_AUD_CK_PDN_MASK 0x11812#define RG_AUD_CK_PDN_MASK_SFT (0x1 << 1)1813#define RG_ACCDET_CK_PDN_SFT 01814#define RG_ACCDET_CK_PDN_MASK 0x11815#define RG_ACCDET_CK_PDN_MASK_SFT (0x1 << 0)1816 1817/* AUD_TOP_CKPDN_CON0_SET */1818#define RG_AUD_TOP_CKPDN_CON0_SET_SFT 01819#define RG_AUD_TOP_CKPDN_CON0_SET_MASK 0x3fff1820#define RG_AUD_TOP_CKPDN_CON0_SET_MASK_SFT (0x3fff << 0)1821 1822/* AUD_TOP_CKPDN_CON0_CLR */1823#define RG_AUD_TOP_CKPDN_CON0_CLR_SFT 01824#define RG_AUD_TOP_CKPDN_CON0_CLR_MASK 0x3fff1825#define RG_AUD_TOP_CKPDN_CON0_CLR_MASK_SFT (0x3fff << 0)1826 1827/* AUD_TOP_CKSEL_CON0 */1828#define RG_AUDIF_CK_CKSEL_SFT 31829#define RG_AUDIF_CK_CKSEL_MASK 0x11830#define RG_AUDIF_CK_CKSEL_MASK_SFT (0x1 << 3)1831#define RG_AUD_CK_CKSEL_SFT 21832#define RG_AUD_CK_CKSEL_MASK 0x11833#define RG_AUD_CK_CKSEL_MASK_SFT (0x1 << 2)1834 1835/* AUD_TOP_CKSEL_CON0_SET */1836#define RG_AUD_TOP_CKSEL_CON0_SET_SFT 01837#define RG_AUD_TOP_CKSEL_CON0_SET_MASK 0xf1838#define RG_AUD_TOP_CKSEL_CON0_SET_MASK_SFT (0xf << 0)1839 1840/* AUD_TOP_CKSEL_CON0_CLR */1841#define RG_AUD_TOP_CKSEL_CON0_CLR_SFT 01842#define RG_AUD_TOP_CKSEL_CON0_CLR_MASK 0xf1843#define RG_AUD_TOP_CKSEL_CON0_CLR_MASK_SFT (0xf << 0)1844 1845/* AUD_TOP_CKTST_CON0 */1846#define RG_VOW13M_CK_TSTSEL_SFT 91847#define RG_VOW13M_CK_TSTSEL_MASK 0x11848#define RG_VOW13M_CK_TSTSEL_MASK_SFT (0x1 << 9)1849#define RG_VOW13M_CK_TST_DIS_SFT 81850#define RG_VOW13M_CK_TST_DIS_MASK 0x11851#define RG_VOW13M_CK_TST_DIS_MASK_SFT (0x1 << 8)1852#define RG_AUD26M_CK_TSTSEL_SFT 41853#define RG_AUD26M_CK_TSTSEL_MASK 0x11854#define RG_AUD26M_CK_TSTSEL_MASK_SFT (0x1 << 4)1855#define RG_AUDIF_CK_TSTSEL_SFT 31856#define RG_AUDIF_CK_TSTSEL_MASK 0x11857#define RG_AUDIF_CK_TSTSEL_MASK_SFT (0x1 << 3)1858#define RG_AUD_CK_TSTSEL_SFT 21859#define RG_AUD_CK_TSTSEL_MASK 0x11860#define RG_AUD_CK_TSTSEL_MASK_SFT (0x1 << 2)1861#define RG_AUD26M_CK_TST_DIS_SFT 01862#define RG_AUD26M_CK_TST_DIS_MASK 0x11863#define RG_AUD26M_CK_TST_DIS_MASK_SFT (0x1 << 0)1864 1865/* AUD_TOP_CLK_HWEN_CON0 */1866#define RG_AUD_INTRP_CK_PDN_HWEN_SFT 01867#define RG_AUD_INTRP_CK_PDN_HWEN_MASK 0x11868#define RG_AUD_INTRP_CK_PDN_HWEN_MASK_SFT (0x1 << 0)1869 1870/* AUD_TOP_CLK_HWEN_CON0_SET */1871#define RG_AUD_INTRP_CK_PND_HWEN_CON0_SET_SFT 01872#define RG_AUD_INTRP_CK_PND_HWEN_CON0_SET_MASK 0xffff1873#define RG_AUD_INTRP_CK_PND_HWEN_CON0_SET_MASK_SFT (0xffff << 0)1874 1875/* AUD_TOP_CLK_HWEN_CON0_CLR */1876#define RG_AUD_INTRP_CLK_PDN_HWEN_CON0_CLR_SFT 01877#define RG_AUD_INTRP_CLK_PDN_HWEN_CON0_CLR_MASK 0xffff1878#define RG_AUD_INTRP_CLK_PDN_HWEN_CON0_CLR_MASK_SFT (0xffff << 0)1879 1880/* AUD_TOP_RST_CON0 */1881#define RG_AUDNCP_RST_SFT 31882#define RG_AUDNCP_RST_MASK 0x11883#define RG_AUDNCP_RST_MASK_SFT (0x1 << 3)1884#define RG_ZCD_RST_SFT 21885#define RG_ZCD_RST_MASK 0x11886#define RG_ZCD_RST_MASK_SFT (0x1 << 2)1887#define RG_ACCDET_RST_SFT 11888#define RG_ACCDET_RST_MASK 0x11889#define RG_ACCDET_RST_MASK_SFT (0x1 << 1)1890#define RG_AUDIO_RST_SFT 01891#define RG_AUDIO_RST_MASK 0x11892#define RG_AUDIO_RST_MASK_SFT (0x1 << 0)1893 1894/* AUD_TOP_RST_CON0_SET */1895#define RG_AUD_TOP_RST_CON0_SET_SFT 01896#define RG_AUD_TOP_RST_CON0_SET_MASK 0xf1897#define RG_AUD_TOP_RST_CON0_SET_MASK_SFT (0xf << 0)1898 1899/* AUD_TOP_RST_CON0_CLR */1900#define RG_AUD_TOP_RST_CON0_CLR_SFT 01901#define RG_AUD_TOP_RST_CON0_CLR_MASK 0xf1902#define RG_AUD_TOP_RST_CON0_CLR_MASK_SFT (0xf << 0)1903 1904/* AUD_TOP_RST_BANK_CON0 */1905#define BANK_AUDZCD_SWRST_SFT 21906#define BANK_AUDZCD_SWRST_MASK 0x11907#define BANK_AUDZCD_SWRST_MASK_SFT (0x1 << 2)1908#define BANK_AUDIO_SWRST_SFT 11909#define BANK_AUDIO_SWRST_MASK 0x11910#define BANK_AUDIO_SWRST_MASK_SFT (0x1 << 1)1911#define BANK_ACCDET_SWRST_SFT 01912#define BANK_ACCDET_SWRST_MASK 0x11913#define BANK_ACCDET_SWRST_MASK_SFT (0x1 << 0)1914 1915/* AFE_UL_DL_CON0 */1916#define AFE_UL_LR_SWAP_SFT 151917#define AFE_UL_LR_SWAP_MASK 0x11918#define AFE_UL_LR_SWAP_MASK_SFT (0x1 << 15)1919#define AFE_DL_LR_SWAP_SFT 141920#define AFE_DL_LR_SWAP_MASK 0x11921#define AFE_DL_LR_SWAP_MASK_SFT (0x1 << 14)1922#define AFE_ON_SFT 01923#define AFE_ON_MASK 0x11924#define AFE_ON_MASK_SFT (0x1 << 0)1925 1926/* AFE_DL_SRC2_CON0_L */1927#define DL_2_SRC_ON_TMP_CTL_PRE_SFT 01928#define DL_2_SRC_ON_TMP_CTL_PRE_MASK 0x11929#define DL_2_SRC_ON_TMP_CTL_PRE_MASK_SFT (0x1 << 0)1930 1931/* AFE_UL_SRC_CON0_H */1932#define C_DIGMIC_PHASE_SEL_CH1_CTL_SFT 111933#define C_DIGMIC_PHASE_SEL_CH1_CTL_MASK 0x71934#define C_DIGMIC_PHASE_SEL_CH1_CTL_MASK_SFT (0x7 << 11)1935#define C_DIGMIC_PHASE_SEL_CH2_CTL_SFT 81936#define C_DIGMIC_PHASE_SEL_CH2_CTL_MASK 0x71937#define C_DIGMIC_PHASE_SEL_CH2_CTL_MASK_SFT (0x7 << 8)1938#define C_TWO_DIGITAL_MIC_CTL_SFT 71939#define C_TWO_DIGITAL_MIC_CTL_MASK 0x11940#define C_TWO_DIGITAL_MIC_CTL_MASK_SFT (0x1 << 7)1941 1942/* AFE_UL_SRC_CON0_L */1943#define DMIC_LOW_POWER_MODE_CTL_SFT 141944#define DMIC_LOW_POWER_MODE_CTL_MASK 0x31945#define DMIC_LOW_POWER_MODE_CTL_MASK_SFT (0x3 << 14)1946#define DIGMIC_4P33M_SEL_CTL_SFT 61947#define DIGMIC_4P33M_SEL_CTL_MASK 0x11948#define DIGMIC_4P33M_SEL_CTL_MASK_SFT (0x1 << 6)1949#define DIGMIC_3P25M_1P625M_SEL_CTL_SFT 51950#define DIGMIC_3P25M_1P625M_SEL_CTL_MASK 0x11951#define DIGMIC_3P25M_1P625M_SEL_CTL_MASK_SFT (0x1 << 5)1952#define UL_LOOP_BACK_MODE_CTL_SFT 21953#define UL_LOOP_BACK_MODE_CTL_MASK 0x11954#define UL_LOOP_BACK_MODE_CTL_MASK_SFT (0x1 << 2)1955#define UL_SDM_3_LEVEL_CTL_SFT 11956#define UL_SDM_3_LEVEL_CTL_MASK 0x11957#define UL_SDM_3_LEVEL_CTL_MASK_SFT (0x1 << 1)1958#define UL_SRC_ON_TMP_CTL_SFT 01959#define UL_SRC_ON_TMP_CTL_MASK 0x11960#define UL_SRC_ON_TMP_CTL_MASK_SFT (0x1 << 0)1961 1962/* AFE_ADDA6_L_SRC_CON0_H */1963#define ADDA6_C_DIGMIC_PHASE_SEL_CH1_CTL_SFT 111964#define ADDA6_C_DIGMIC_PHASE_SEL_CH1_CTL_MASK 0x71965#define ADDA6_C_DIGMIC_PHASE_SEL_CH1_CTL_MASK_SFT (0x7 << 11)1966#define ADDA6_C_DIGMIC_PHASE_SEL_CH2_CTL_SFT 81967#define ADDA6_C_DIGMIC_PHASE_SEL_CH2_CTL_MASK 0x71968#define ADDA6_C_DIGMIC_PHASE_SEL_CH2_CTL_MASK_SFT (0x7 << 8)1969#define ADDA6_C_TWO_DIGITAL_MIC_CTL_SFT 71970#define ADDA6_C_TWO_DIGITAL_MIC_CTL_MASK 0x11971#define ADDA6_C_TWO_DIGITAL_MIC_CTL_MASK_SFT (0x1 << 7)1972 1973/* AFE_ADDA6_UL_SRC_CON0_L */1974#define ADDA6_DMIC_LOW_POWER_MODE_CTL_SFT 141975#define ADDA6_DMIC_LOW_POWER_MODE_CTL_MASK 0x31976#define ADDA6_DMIC_LOW_POWER_MODE_CTL_MASK_SFT (0x3 << 14)1977#define ADDA6_DIGMIC_4P33M_SEL_CTL_SFT 61978#define ADDA6_DIGMIC_4P33M_SEL_CTL_MASK 0x11979#define ADDA6_DIGMIC_4P33M_SEL_CTL_MASK_SFT (0x1 << 6)1980#define ADDA6_DIGMIC_3P25M_1P625M_SEL_CTL_SFT 51981#define ADDA6_DIGMIC_3P25M_1P625M_SEL_CTL_MASK 0x11982#define ADDA6_DIGMIC_3P25M_1P625M_SEL_CTL_MASK_SFT (0x1 << 5)1983#define ADDA6_UL_LOOP_BACK_MODE_CTL_SFT 21984#define ADDA6_UL_LOOP_BACK_MODE_CTL_MASK 0x11985#define ADDA6_UL_LOOP_BACK_MODE_CTL_MASK_SFT (0x1 << 2)1986#define ADDA6_UL_SDM_3_LEVEL_CTL_SFT 11987#define ADDA6_UL_SDM_3_LEVEL_CTL_MASK 0x11988#define ADDA6_UL_SDM_3_LEVEL_CTL_MASK_SFT (0x1 << 1)1989#define ADDA6_UL_SRC_ON_TMP_CTL_SFT 01990#define ADDA6_UL_SRC_ON_TMP_CTL_MASK 0x11991#define ADDA6_UL_SRC_ON_TMP_CTL_MASK_SFT (0x1 << 0)1992 1993/* AFE_TOP_CON0 */1994#define ADDA6_MTKAIF_SINE_ON_SFT 41995#define ADDA6_MTKAIF_SINE_ON_MASK 0x11996#define ADDA6_MTKAIF_SINE_ON_MASK_SFT (0x1 << 4)1997#define ADDA6_UL_SINE_ON_SFT 31998#define ADDA6_UL_SINE_ON_MASK 0x11999#define ADDA6_UL_SINE_ON_MASK_SFT (0x1 << 3)2000#define MTKAIF_SINE_ON_SFT 22001#define MTKAIF_SINE_ON_MASK 0x12002#define MTKAIF_SINE_ON_MASK_SFT (0x1 << 2)2003#define UL_SINE_ON_SFT 12004#define UL_SINE_ON_MASK 0x12005#define UL_SINE_ON_MASK_SFT (0x1 << 1)2006#define DL_SINE_ON_SFT 02007#define DL_SINE_ON_MASK 0x12008#define DL_SINE_ON_MASK_SFT (0x1 << 0)2009 2010/* AUDIO_TOP_CON0 */2011#define PDN_AFE_CTL_SFT 72012#define PDN_AFE_CTL_MASK 0x12013#define PDN_AFE_CTL_MASK_SFT (0x1 << 7)2014#define PDN_DAC_CTL_SFT 62015#define PDN_DAC_CTL_MASK 0x12016#define PDN_DAC_CTL_MASK_SFT (0x1 << 6)2017#define PDN_ADC_CTL_SFT 52018#define PDN_ADC_CTL_MASK 0x12019#define PDN_ADC_CTL_MASK_SFT (0x1 << 5)2020#define PDN_ADDA6_ADC_CTL_SFT 42021#define PDN_ADDA6_ADC_CTL_MASK 0x12022#define PDN_ADDA6_ADC_CTL_MASK_SFT (0x1 << 4)2023#define PDN_I2S_DL_CTL_SFT 32024#define PDN_I2S_DL_CTL_MASK 0x12025#define PDN_I2S_DL_CTL_MASK_SFT (0x1 << 3)2026#define PWR_CLK_DIS_CTL_SFT 22027#define PWR_CLK_DIS_CTL_MASK 0x12028#define PWR_CLK_DIS_CTL_MASK_SFT (0x1 << 2)2029#define PDN_AFE_TESTMODEL_CTL_SFT 12030#define PDN_AFE_TESTMODEL_CTL_MASK 0x12031#define PDN_AFE_TESTMODEL_CTL_MASK_SFT (0x1 << 1)2032#define PDN_RESERVED_SFT 02033#define PDN_RESERVED_MASK 0x12034#define PDN_RESERVED_MASK_SFT (0x1 << 0)2035 2036/* AFE_MON_DEBUG0 */2037#define AUDIO_SYS_TOP_MON_SWAP_SFT 142038#define AUDIO_SYS_TOP_MON_SWAP_MASK 0x32039#define AUDIO_SYS_TOP_MON_SWAP_MASK_SFT (0x3 << 14)2040#define AUDIO_SYS_TOP_MON_SEL_SFT 82041#define AUDIO_SYS_TOP_MON_SEL_MASK 0x1f2042#define AUDIO_SYS_TOP_MON_SEL_MASK_SFT (0x1f << 8)2043#define AFE_MON_SEL_SFT 02044#define AFE_MON_SEL_MASK 0xff2045#define AFE_MON_SEL_MASK_SFT (0xff << 0)2046 2047/* AFUNC_AUD_CON0 */2048#define CCI_AUD_ANACK_SEL_SFT 152049#define CCI_AUD_ANACK_SEL_MASK 0x12050#define CCI_AUD_ANACK_SEL_MASK_SFT (0x1 << 15)2051#define CCI_AUDIO_FIFO_WPTR_SFT 122052#define CCI_AUDIO_FIFO_WPTR_MASK 0x72053#define CCI_AUDIO_FIFO_WPTR_MASK_SFT (0x7 << 12)2054#define CCI_SCRAMBLER_CG_EN_SFT 112055#define CCI_SCRAMBLER_CG_EN_MASK 0x12056#define CCI_SCRAMBLER_CG_EN_MASK_SFT (0x1 << 11)2057#define CCI_LCH_INV_SFT 102058#define CCI_LCH_INV_MASK 0x12059#define CCI_LCH_INV_MASK_SFT (0x1 << 10)2060#define CCI_RAND_EN_SFT 92061#define CCI_RAND_EN_MASK 0x12062#define CCI_RAND_EN_MASK_SFT (0x1 << 9)2063#define CCI_SPLT_SCRMB_CLK_ON_SFT 82064#define CCI_SPLT_SCRMB_CLK_ON_MASK 0x12065#define CCI_SPLT_SCRMB_CLK_ON_MASK_SFT (0x1 << 8)2066#define CCI_SPLT_SCRMB_ON_SFT 72067#define CCI_SPLT_SCRMB_ON_MASK 0x12068#define CCI_SPLT_SCRMB_ON_MASK_SFT (0x1 << 7)2069#define CCI_AUD_IDAC_TEST_EN_SFT 62070#define CCI_AUD_IDAC_TEST_EN_MASK 0x12071#define CCI_AUD_IDAC_TEST_EN_MASK_SFT (0x1 << 6)2072#define CCI_ZERO_PAD_DISABLE_SFT 52073#define CCI_ZERO_PAD_DISABLE_MASK 0x12074#define CCI_ZERO_PAD_DISABLE_MASK_SFT (0x1 << 5)2075#define CCI_AUD_SPLIT_TEST_EN_SFT 42076#define CCI_AUD_SPLIT_TEST_EN_MASK 0x12077#define CCI_AUD_SPLIT_TEST_EN_MASK_SFT (0x1 << 4)2078#define CCI_AUD_SDM_MUTEL_SFT 32079#define CCI_AUD_SDM_MUTEL_MASK 0x12080#define CCI_AUD_SDM_MUTEL_MASK_SFT (0x1 << 3)2081#define CCI_AUD_SDM_MUTER_SFT 22082#define CCI_AUD_SDM_MUTER_MASK 0x12083#define CCI_AUD_SDM_MUTER_MASK_SFT (0x1 << 2)2084#define CCI_AUD_SDM_7BIT_SEL_SFT 12085#define CCI_AUD_SDM_7BIT_SEL_MASK 0x12086#define CCI_AUD_SDM_7BIT_SEL_MASK_SFT (0x1 << 1)2087#define CCI_SCRAMBLER_EN_SFT 02088#define CCI_SCRAMBLER_EN_MASK 0x12089#define CCI_SCRAMBLER_EN_MASK_SFT (0x1 << 0)2090 2091/* AFUNC_AUD_CON1 */2092#define AUD_SDM_TEST_L_SFT 82093#define AUD_SDM_TEST_L_MASK 0xff2094#define AUD_SDM_TEST_L_MASK_SFT (0xff << 8)2095#define AUD_SDM_TEST_R_SFT 02096#define AUD_SDM_TEST_R_MASK 0xff2097#define AUD_SDM_TEST_R_MASK_SFT (0xff << 0)2098 2099/* AFUNC_AUD_CON2 */2100#define CCI_AUD_DAC_ANA_MUTE_SFT 72101#define CCI_AUD_DAC_ANA_MUTE_MASK 0x12102#define CCI_AUD_DAC_ANA_MUTE_MASK_SFT (0x1 << 7)2103#define CCI_AUD_DAC_ANA_RSTB_SEL_SFT 62104#define CCI_AUD_DAC_ANA_RSTB_SEL_MASK 0x12105#define CCI_AUD_DAC_ANA_RSTB_SEL_MASK_SFT (0x1 << 6)2106#define CCI_AUDIO_FIFO_CLKIN_INV_SFT 42107#define CCI_AUDIO_FIFO_CLKIN_INV_MASK 0x12108#define CCI_AUDIO_FIFO_CLKIN_INV_MASK_SFT (0x1 << 4)2109#define CCI_AUDIO_FIFO_ENABLE_SFT 32110#define CCI_AUDIO_FIFO_ENABLE_MASK 0x12111#define CCI_AUDIO_FIFO_ENABLE_MASK_SFT (0x1 << 3)2112#define CCI_ACD_MODE_SFT 22113#define CCI_ACD_MODE_MASK 0x12114#define CCI_ACD_MODE_MASK_SFT (0x1 << 2)2115#define CCI_AFIFO_CLK_PWDB_SFT 12116#define CCI_AFIFO_CLK_PWDB_MASK 0x12117#define CCI_AFIFO_CLK_PWDB_MASK_SFT (0x1 << 1)2118#define CCI_ACD_FUNC_RSTB_SFT 02119#define CCI_ACD_FUNC_RSTB_MASK 0x12120#define CCI_ACD_FUNC_RSTB_MASK_SFT (0x1 << 0)2121 2122/* AFUNC_AUD_CON3 */2123#define SDM_ANA13M_TESTCK_SEL_SFT 152124#define SDM_ANA13M_TESTCK_SEL_MASK 0x12125#define SDM_ANA13M_TESTCK_SEL_MASK_SFT (0x1 << 15)2126#define SDM_ANA13M_TESTCK_SRC_SEL_SFT 122127#define SDM_ANA13M_TESTCK_SRC_SEL_MASK 0x72128#define SDM_ANA13M_TESTCK_SRC_SEL_MASK_SFT (0x7 << 12)2129#define SDM_TESTCK_SRC_SEL_SFT 82130#define SDM_TESTCK_SRC_SEL_MASK 0x72131#define SDM_TESTCK_SRC_SEL_MASK_SFT (0x7 << 8)2132#define DIGMIC_TESTCK_SRC_SEL_SFT 42133#define DIGMIC_TESTCK_SRC_SEL_MASK 0x72134#define DIGMIC_TESTCK_SRC_SEL_MASK_SFT (0x7 << 4)2135#define DIGMIC_TESTCK_SEL_SFT 02136#define DIGMIC_TESTCK_SEL_MASK 0x12137#define DIGMIC_TESTCK_SEL_MASK_SFT (0x1 << 0)2138 2139/* AFUNC_AUD_CON4 */2140#define UL_FIFO_WCLK_INV_SFT 82141#define UL_FIFO_WCLK_INV_MASK 0x12142#define UL_FIFO_WCLK_INV_MASK_SFT (0x1 << 8)2143#define UL_FIFO_DIGMIC_WDATA_TESTSRC_SEL_SFT 62144#define UL_FIFO_DIGMIC_WDATA_TESTSRC_SEL_MASK 0x12145#define UL_FIFO_DIGMIC_WDATA_TESTSRC_SEL_MASK_SFT (0x1 << 6)2146#define UL_FIFO_WDATA_TESTEN_SFT 52147#define UL_FIFO_WDATA_TESTEN_MASK 0x12148#define UL_FIFO_WDATA_TESTEN_MASK_SFT (0x1 << 5)2149#define UL_FIFO_WDATA_TESTSRC_SEL_SFT 42150#define UL_FIFO_WDATA_TESTSRC_SEL_MASK 0x12151#define UL_FIFO_WDATA_TESTSRC_SEL_MASK_SFT (0x1 << 4)2152#define UL_FIFO_WCLK_6P5M_TESTCK_SEL_SFT 32153#define UL_FIFO_WCLK_6P5M_TESTCK_SEL_MASK 0x12154#define UL_FIFO_WCLK_6P5M_TESTCK_SEL_MASK_SFT (0x1 << 3)2155#define UL_FIFO_WCLK_6P5M_TESTCK_SRC_SEL_SFT 02156#define UL_FIFO_WCLK_6P5M_TESTCK_SRC_SEL_MASK 0x72157#define UL_FIFO_WCLK_6P5M_TESTCK_SRC_SEL_MASK_SFT (0x7 << 0)2158 2159/* AFUNC_AUD_CON5 */2160#define R_AUD_DAC_POS_LARGE_MONO_SFT 82161#define R_AUD_DAC_POS_LARGE_MONO_MASK 0xff2162#define R_AUD_DAC_POS_LARGE_MONO_MASK_SFT (0xff << 8)2163#define R_AUD_DAC_NEG_LARGE_MONO_SFT 02164#define R_AUD_DAC_NEG_LARGE_MONO_MASK 0xff2165#define R_AUD_DAC_NEG_LARGE_MONO_MASK_SFT (0xff << 0)2166 2167/* AFUNC_AUD_CON6 */2168#define R_AUD_DAC_POS_SMALL_MONO_SFT 122169#define R_AUD_DAC_POS_SMALL_MONO_MASK 0xf2170#define R_AUD_DAC_POS_SMALL_MONO_MASK_SFT (0xf << 12)2171#define R_AUD_DAC_NEG_SMALL_MONO_SFT 82172#define R_AUD_DAC_NEG_SMALL_MONO_MASK 0xf2173#define R_AUD_DAC_NEG_SMALL_MONO_MASK_SFT (0xf << 8)2174#define R_AUD_DAC_POS_TINY_MONO_SFT 62175#define R_AUD_DAC_POS_TINY_MONO_MASK 0x32176#define R_AUD_DAC_POS_TINY_MONO_MASK_SFT (0x3 << 6)2177#define R_AUD_DAC_NEG_TINY_MONO_SFT 42178#define R_AUD_DAC_NEG_TINY_MONO_MASK 0x32179#define R_AUD_DAC_NEG_TINY_MONO_MASK_SFT (0x3 << 4)2180#define R_AUD_DAC_MONO_SEL_SFT 32181#define R_AUD_DAC_MONO_SEL_MASK 0x12182#define R_AUD_DAC_MONO_SEL_MASK_SFT (0x1 << 3)2183#define R_AUD_DAC_3TH_SEL_SFT 12184#define R_AUD_DAC_3TH_SEL_MASK 0x12185#define R_AUD_DAC_3TH_SEL_MASK_SFT (0x1 << 1)2186#define R_AUD_DAC_SW_RSTB_SFT 02187#define R_AUD_DAC_SW_RSTB_MASK 0x12188#define R_AUD_DAC_SW_RSTB_MASK_SFT (0x1 << 0)2189 2190/* AFUNC_AUD_CON7 */2191#define UL2_DIGMIC_TESTCK_SRC_SEL_SFT 102192#define UL2_DIGMIC_TESTCK_SRC_SEL_MASK 0x72193#define UL2_DIGMIC_TESTCK_SRC_SEL_MASK_SFT (0x7 << 10)2194#define UL2_DIGMIC_TESTCK_SEL_SFT 92195#define UL2_DIGMIC_TESTCK_SEL_MASK 0x12196#define UL2_DIGMIC_TESTCK_SEL_MASK_SFT (0x1 << 9)2197#define UL2_FIFO_WCLK_INV_SFT 82198#define UL2_FIFO_WCLK_INV_MASK 0x12199#define UL2_FIFO_WCLK_INV_MASK_SFT (0x1 << 8)2200#define UL2_FIFO_DIGMIC_WDATA_TESTSRC_SEL_SFT 62201#define UL2_FIFO_DIGMIC_WDATA_TESTSRC_SEL_MASK 0x12202#define UL2_FIFO_DIGMIC_WDATA_TESTSRC_SEL_MASK_SFT (0x1 << 6)2203#define UL2_FIFO_WDATA_TESTEN_SFT 52204#define UL2_FIFO_WDATA_TESTEN_MASK 0x12205#define UL2_FIFO_WDATA_TESTEN_MASK_SFT (0x1 << 5)2206#define UL2_FIFO_WDATA_TESTSRC_SEL_SFT 42207#define UL2_FIFO_WDATA_TESTSRC_SEL_MASK 0x12208#define UL2_FIFO_WDATA_TESTSRC_SEL_MASK_SFT (0x1 << 4)2209#define UL2_FIFO_WCLK_6P5M_TESTCK_SEL_SFT 32210#define UL2_FIFO_WCLK_6P5M_TESTCK_SEL_MASK 0x12211#define UL2_FIFO_WCLK_6P5M_TESTCK_SEL_MASK_SFT (0x1 << 3)2212#define UL2_FIFO_WCLK_6P5M_TESTCK_SRC_SEL_SFT 02213#define UL2_FIFO_WCLK_6P5M_TESTCK_SRC_SEL_MASK 0x72214#define UL2_FIFO_WCLK_6P5M_TESTCK_SRC_SEL_MASK_SFT (0x7 << 0)2215 2216/* AFUNC_AUD_CON8 */2217#define SPLITTER2_DITHER_EN_SFT 92218#define SPLITTER2_DITHER_EN_MASK 0x12219#define SPLITTER2_DITHER_EN_MASK_SFT (0x1 << 9)2220#define SPLITTER1_DITHER_EN_SFT 82221#define SPLITTER1_DITHER_EN_MASK 0x12222#define SPLITTER1_DITHER_EN_MASK_SFT (0x1 << 8)2223#define SPLITTER2_DITHER_GAIN_SFT 42224#define SPLITTER2_DITHER_GAIN_MASK 0xf2225#define SPLITTER2_DITHER_GAIN_MASK_SFT (0xf << 4)2226#define SPLITTER1_DITHER_GAIN_SFT 02227#define SPLITTER1_DITHER_GAIN_MASK 0xf2228#define SPLITTER1_DITHER_GAIN_MASK_SFT (0xf << 0)2229 2230/* AFUNC_AUD_CON9 */2231#define CCI_AUD_ANACK_SEL_2ND_SFT 152232#define CCI_AUD_ANACK_SEL_2ND_MASK 0x12233#define CCI_AUD_ANACK_SEL_2ND_MASK_SFT (0x1 << 15)2234#define CCI_AUDIO_FIFO_WPTR_2ND_SFT 122235#define CCI_AUDIO_FIFO_WPTR_2ND_MASK 0x72236#define CCI_AUDIO_FIFO_WPTR_2ND_MASK_SFT (0x7 << 12)2237#define CCI_SCRAMBLER_CG_EN_2ND_SFT 112238#define CCI_SCRAMBLER_CG_EN_2ND_MASK 0x12239#define CCI_SCRAMBLER_CG_EN_2ND_MASK_SFT (0x1 << 11)2240#define CCI_LCH_INV_2ND_SFT 102241#define CCI_LCH_INV_2ND_MASK 0x12242#define CCI_LCH_INV_2ND_MASK_SFT (0x1 << 10)2243#define CCI_RAND_EN_2ND_SFT 92244#define CCI_RAND_EN_2ND_MASK 0x12245#define CCI_RAND_EN_2ND_MASK_SFT (0x1 << 9)2246#define CCI_SPLT_SCRMB_CLK_ON_2ND_SFT 82247#define CCI_SPLT_SCRMB_CLK_ON_2ND_MASK 0x12248#define CCI_SPLT_SCRMB_CLK_ON_2ND_MASK_SFT (0x1 << 8)2249#define CCI_SPLT_SCRMB_ON_2ND_SFT 72250#define CCI_SPLT_SCRMB_ON_2ND_MASK 0x12251#define CCI_SPLT_SCRMB_ON_2ND_MASK_SFT (0x1 << 7)2252#define CCI_AUD_IDAC_TEST_EN_2ND_SFT 62253#define CCI_AUD_IDAC_TEST_EN_2ND_MASK 0x12254#define CCI_AUD_IDAC_TEST_EN_2ND_MASK_SFT (0x1 << 6)2255#define CCI_ZERO_PAD_DISABLE_2ND_SFT 52256#define CCI_ZERO_PAD_DISABLE_2ND_MASK 0x12257#define CCI_ZERO_PAD_DISABLE_2ND_MASK_SFT (0x1 << 5)2258#define CCI_AUD_SPLIT_TEST_EN_2ND_SFT 42259#define CCI_AUD_SPLIT_TEST_EN_2ND_MASK 0x12260#define CCI_AUD_SPLIT_TEST_EN_2ND_MASK_SFT (0x1 << 4)2261#define CCI_AUD_SDM_MUTEL_2ND_SFT 32262#define CCI_AUD_SDM_MUTEL_2ND_MASK 0x12263#define CCI_AUD_SDM_MUTEL_2ND_MASK_SFT (0x1 << 3)2264#define CCI_AUD_SDM_MUTER_2ND_SFT 22265#define CCI_AUD_SDM_MUTER_2ND_MASK 0x12266#define CCI_AUD_SDM_MUTER_2ND_MASK_SFT (0x1 << 2)2267#define CCI_AUD_SDM_7BIT_SEL_2ND_SFT 12268#define CCI_AUD_SDM_7BIT_SEL_2ND_MASK 0x12269#define CCI_AUD_SDM_7BIT_SEL_2ND_MASK_SFT (0x1 << 1)2270#define CCI_SCRAMBLER_EN_2ND_SFT 02271#define CCI_SCRAMBLER_EN_2ND_MASK 0x12272#define CCI_SCRAMBLER_EN_2ND_MASK_SFT (0x1 << 0)2273 2274/* AFUNC_AUD_CON10 */2275#define AUD_SDM_TEST_L_2ND_SFT 82276#define AUD_SDM_TEST_L_2ND_MASK 0xff2277#define AUD_SDM_TEST_L_2ND_MASK_SFT (0xff << 8)2278#define AUD_SDM_TEST_R_2ND_SFT 02279#define AUD_SDM_TEST_R_2ND_MASK 0xff2280#define AUD_SDM_TEST_R_2ND_MASK_SFT (0xff << 0)2281 2282/* AFUNC_AUD_CON11 */2283#define CCI_AUD_DAC_ANA_MUTE_2ND_SFT 72284#define CCI_AUD_DAC_ANA_MUTE_2ND_MASK 0x12285#define CCI_AUD_DAC_ANA_MUTE_2ND_MASK_SFT (0x1 << 7)2286#define CCI_AUD_DAC_ANA_RSTB_SEL_2ND_SFT 62287#define CCI_AUD_DAC_ANA_RSTB_SEL_2ND_MASK 0x12288#define CCI_AUD_DAC_ANA_RSTB_SEL_2ND_MASK_SFT (0x1 << 6)2289#define CCI_AUDIO_FIFO_CLKIN_INV_2ND_SFT 42290#define CCI_AUDIO_FIFO_CLKIN_INV_2ND_MASK 0x12291#define CCI_AUDIO_FIFO_CLKIN_INV_2ND_MASK_SFT (0x1 << 4)2292#define CCI_AUDIO_FIFO_ENABLE_2ND_SFT 32293#define CCI_AUDIO_FIFO_ENABLE_2ND_MASK 0x12294#define CCI_AUDIO_FIFO_ENABLE_2ND_MASK_SFT (0x1 << 3)2295#define CCI_ACD_MODE_2ND_SFT 22296#define CCI_ACD_MODE_2ND_MASK 0x12297#define CCI_ACD_MODE_2ND_MASK_SFT (0x1 << 2)2298#define CCI_AFIFO_CLK_PWDB_2ND_SFT 12299#define CCI_AFIFO_CLK_PWDB_2ND_MASK 0x12300#define CCI_AFIFO_CLK_PWDB_2ND_MASK_SFT (0x1 << 1)2301#define CCI_ACD_FUNC_RSTB_2ND_SFT 02302#define CCI_ACD_FUNC_RSTB_2ND_MASK 0x12303#define CCI_ACD_FUNC_RSTB_2ND_MASK_SFT (0x1 << 0)2304 2305/* AFUNC_AUD_CON12 */2306#define SPLITTER2_DITHER_EN_2ND_SFT 92307#define SPLITTER2_DITHER_EN_2ND_MASK 0x12308#define SPLITTER2_DITHER_EN_2ND_MASK_SFT (0x1 << 9)2309#define SPLITTER1_DITHER_EN_2ND_SFT 82310#define SPLITTER1_DITHER_EN_2ND_MASK 0x12311#define SPLITTER1_DITHER_EN_2ND_MASK_SFT (0x1 << 8)2312#define SPLITTER2_DITHER_GAIN_2ND_SFT 42313#define SPLITTER2_DITHER_GAIN_2ND_MASK 0xf2314#define SPLITTER2_DITHER_GAIN_2ND_MASK_SFT (0xf << 4)2315#define SPLITTER1_DITHER_GAIN_2ND_SFT 02316#define SPLITTER1_DITHER_GAIN_2ND_MASK 0xf2317#define SPLITTER1_DITHER_GAIN_2ND_MASK_SFT (0xf << 0)2318 2319/* AFUNC_AUD_MON0 */2320#define AUD_SCR_OUT_L_SFT 82321#define AUD_SCR_OUT_L_MASK 0xff2322#define AUD_SCR_OUT_L_MASK_SFT (0xff << 8)2323#define AUD_SCR_OUT_R_SFT 02324#define AUD_SCR_OUT_R_MASK 0xff2325#define AUD_SCR_OUT_R_MASK_SFT (0xff << 0)2326 2327/* AFUNC_AUD_MON1 */2328#define AUD_SCR_OUT_L_2ND_SFT 82329#define AUD_SCR_OUT_L_2ND_MASK 0xff2330#define AUD_SCR_OUT_L_2ND_MASK_SFT (0xff << 8)2331#define AUD_SCR_OUT_R_2ND_SFT 02332#define AUD_SCR_OUT_R_2ND_MASK 0xff2333#define AUD_SCR_OUT_R_2ND_MASK_SFT (0xff << 0)2334 2335/* AUDRC_TUNE_MON0 */2336#define ASYNC_TEST_OUT_BCK_SFT 152337#define ASYNC_TEST_OUT_BCK_MASK 0x12338#define ASYNC_TEST_OUT_BCK_MASK_SFT (0x1 << 15)2339#define RGS_AUDRCTUNE1READ_SFT 82340#define RGS_AUDRCTUNE1READ_MASK 0x1f2341#define RGS_AUDRCTUNE1READ_MASK_SFT (0x1f << 8)2342#define RGS_AUDRCTUNE0READ_SFT 02343#define RGS_AUDRCTUNE0READ_MASK 0x1f2344#define RGS_AUDRCTUNE0READ_MASK_SFT (0x1f << 0)2345 2346/* AFE_ADDA_MTKAIF_FIFO_CFG0 */2347#define AFE_RESERVED_SFT 12348#define AFE_RESERVED_MASK 0x7fff2349#define AFE_RESERVED_MASK_SFT (0x7fff << 1)2350#define RG_MTKAIF_RXIF_FIFO_INTEN_SFT 02351#define RG_MTKAIF_RXIF_FIFO_INTEN_MASK 0x12352#define RG_MTKAIF_RXIF_FIFO_INTEN_MASK_SFT (0x1 << 0)2353 2354/* AFE_ADDA_MTKAIF_FIFO_LOG_MON1 */2355#define MTKAIF_RXIF_WR_FULL_STATUS_SFT 12356#define MTKAIF_RXIF_WR_FULL_STATUS_MASK 0x12357#define MTKAIF_RXIF_WR_FULL_STATUS_MASK_SFT (0x1 << 1)2358#define MTKAIF_RXIF_RD_EMPTY_STATUS_SFT 02359#define MTKAIF_RXIF_RD_EMPTY_STATUS_MASK 0x12360#define MTKAIF_RXIF_RD_EMPTY_STATUS_MASK_SFT (0x1 << 0)2361 2362/* AFE_ADDA_MTKAIF_MON0 */2363#define MTKAIFTX_V3_SYNC_OUT_SFT 152364#define MTKAIFTX_V3_SYNC_OUT_MASK 0x12365#define MTKAIFTX_V3_SYNC_OUT_MASK_SFT (0x1 << 15)2366#define MTKAIFTX_V3_SDATA_OUT3_SFT 142367#define MTKAIFTX_V3_SDATA_OUT3_MASK 0x12368#define MTKAIFTX_V3_SDATA_OUT3_MASK_SFT (0x1 << 14)2369#define MTKAIFTX_V3_SDATA_OUT2_SFT 132370#define MTKAIFTX_V3_SDATA_OUT2_MASK 0x12371#define MTKAIFTX_V3_SDATA_OUT2_MASK_SFT (0x1 << 13)2372#define MTKAIFTX_V3_SDATA_OUT1_SFT 122373#define MTKAIFTX_V3_SDATA_OUT1_MASK 0x12374#define MTKAIFTX_V3_SDATA_OUT1_MASK_SFT (0x1 << 12)2375#define MTKAIF_RXIF_FIFO_STATUS_SFT 02376#define MTKAIF_RXIF_FIFO_STATUS_MASK 0xfff2377#define MTKAIF_RXIF_FIFO_STATUS_MASK_SFT (0xfff << 0)2378 2379/* AFE_ADDA_MTKAIF_MON1 */2380#define MTKAIFRX_V3_SYNC_IN_SFT 152381#define MTKAIFRX_V3_SYNC_IN_MASK 0x12382#define MTKAIFRX_V3_SYNC_IN_MASK_SFT (0x1 << 15)2383#define MTKAIFRX_V3_SDATA_IN3_SFT 142384#define MTKAIFRX_V3_SDATA_IN3_MASK 0x12385#define MTKAIFRX_V3_SDATA_IN3_MASK_SFT (0x1 << 14)2386#define MTKAIFRX_V3_SDATA_IN2_SFT 132387#define MTKAIFRX_V3_SDATA_IN2_MASK 0x12388#define MTKAIFRX_V3_SDATA_IN2_MASK_SFT (0x1 << 13)2389#define MTKAIFRX_V3_SDATA_IN1_SFT 122390#define MTKAIFRX_V3_SDATA_IN1_MASK 0x12391#define MTKAIFRX_V3_SDATA_IN1_MASK_SFT (0x1 << 12)2392#define MTKAIF_RXIF_SEARCH_FAIL_FLAG_SFT 112393#define MTKAIF_RXIF_SEARCH_FAIL_FLAG_MASK 0x12394#define MTKAIF_RXIF_SEARCH_FAIL_FLAG_MASK_SFT (0x1 << 11)2395#define MTKAIF_RXIF_INVALID_FLAG_SFT 82396#define MTKAIF_RXIF_INVALID_FLAG_MASK 0x12397#define MTKAIF_RXIF_INVALID_FLAG_MASK_SFT (0x1 << 8)2398#define MTKAIF_RXIF_INVALID_CYCLE_SFT 02399#define MTKAIF_RXIF_INVALID_CYCLE_MASK 0xff2400#define MTKAIF_RXIF_INVALID_CYCLE_MASK_SFT (0xff << 0)2401 2402/* AFE_ADDA_MTKAIF_MON2 */2403#define MTKAIF_TXIF_IN_CH2_SFT 82404#define MTKAIF_TXIF_IN_CH2_MASK 0xff2405#define MTKAIF_TXIF_IN_CH2_MASK_SFT (0xff << 8)2406#define MTKAIF_TXIF_IN_CH1_SFT 02407#define MTKAIF_TXIF_IN_CH1_MASK 0xff2408#define MTKAIF_TXIF_IN_CH1_MASK_SFT (0xff << 0)2409 2410/* AFE_ADDA6_MTKAIF_MON3 */2411#define ADDA6_MTKAIF_TXIF_IN_CH2_SFT 82412#define ADDA6_MTKAIF_TXIF_IN_CH2_MASK 0xff2413#define ADDA6_MTKAIF_TXIF_IN_CH2_MASK_SFT (0xff << 8)2414#define ADDA6_MTKAIF_TXIF_IN_CH1_SFT 02415#define ADDA6_MTKAIF_TXIF_IN_CH1_MASK 0xff2416#define ADDA6_MTKAIF_TXIF_IN_CH1_MASK_SFT (0xff << 0)2417 2418/* AFE_ADDA_MTKAIF_MON4 */2419#define MTKAIF_RXIF_OUT_CH2_SFT 82420#define MTKAIF_RXIF_OUT_CH2_MASK 0xff2421#define MTKAIF_RXIF_OUT_CH2_MASK_SFT (0xff << 8)2422#define MTKAIF_RXIF_OUT_CH1_SFT 02423#define MTKAIF_RXIF_OUT_CH1_MASK 0xff2424#define MTKAIF_RXIF_OUT_CH1_MASK_SFT (0xff << 0)2425 2426/* AFE_ADDA_MTKAIF_MON5 */2427#define MTKAIF_RXIF_OUT_CH3_SFT 02428#define MTKAIF_RXIF_OUT_CH3_MASK 0xff2429#define MTKAIF_RXIF_OUT_CH3_MASK_SFT (0xff << 0)2430 2431/* AFE_ADDA_MTKAIF_CFG0 */2432#define RG_MTKAIF_RXIF_CLKINV_SFT 152433#define RG_MTKAIF_RXIF_CLKINV_MASK 0x12434#define RG_MTKAIF_RXIF_CLKINV_MASK_SFT (0x1 << 15)2435#define RG_ADDA6_MTKAIF_TXIF_PROTOCOL2_SFT 92436#define RG_ADDA6_MTKAIF_TXIF_PROTOCOL2_MASK 0x12437#define RG_ADDA6_MTKAIF_TXIF_PROTOCOL2_MASK_SFT (0x1 << 9)2438#define RG_MTKAIF_RXIF_PROTOCOL2_SFT 82439#define RG_MTKAIF_RXIF_PROTOCOL2_MASK 0x12440#define RG_MTKAIF_RXIF_PROTOCOL2_MASK_SFT (0x1 << 8)2441#define RG_MTKAIF_BYPASS_SRC_MODE_SFT 62442#define RG_MTKAIF_BYPASS_SRC_MODE_MASK 0x32443#define RG_MTKAIF_BYPASS_SRC_MODE_MASK_SFT (0x3 << 6)2444#define RG_MTKAIF_BYPASS_SRC_TEST_SFT 52445#define RG_MTKAIF_BYPASS_SRC_TEST_MASK 0x12446#define RG_MTKAIF_BYPASS_SRC_TEST_MASK_SFT (0x1 << 5)2447#define RG_MTKAIF_TXIF_PROTOCOL2_SFT 42448#define RG_MTKAIF_TXIF_PROTOCOL2_MASK 0x12449#define RG_MTKAIF_TXIF_PROTOCOL2_MASK_SFT (0x1 << 4)2450#define RG_ADDA6_MTKAIF_PMIC_TXIF_8TO5_SFT 32451#define RG_ADDA6_MTKAIF_PMIC_TXIF_8TO5_MASK 0x12452#define RG_ADDA6_MTKAIF_PMIC_TXIF_8TO5_MASK_SFT (0x1 << 3)2453#define RG_MTKAIF_PMIC_TXIF_8TO5_SFT 22454#define RG_MTKAIF_PMIC_TXIF_8TO5_MASK 0x12455#define RG_MTKAIF_PMIC_TXIF_8TO5_MASK_SFT (0x1 << 2)2456#define RG_MTKAIF_LOOPBACK_TEST2_SFT 12457#define RG_MTKAIF_LOOPBACK_TEST2_MASK 0x12458#define RG_MTKAIF_LOOPBACK_TEST2_MASK_SFT (0x1 << 1)2459#define RG_MTKAIF_LOOPBACK_TEST1_SFT 02460#define RG_MTKAIF_LOOPBACK_TEST1_MASK 0x12461#define RG_MTKAIF_LOOPBACK_TEST1_MASK_SFT (0x1 << 0)2462 2463/* AFE_ADDA_MTKAIF_RX_CFG0 */2464#define RG_MTKAIF_RXIF_VOICE_MODE_SFT 122465#define RG_MTKAIF_RXIF_VOICE_MODE_MASK 0xf2466#define RG_MTKAIF_RXIF_VOICE_MODE_MASK_SFT (0xf << 12)2467#define RG_MTKAIF_RXIF_DATA_BIT_SFT 82468#define RG_MTKAIF_RXIF_DATA_BIT_MASK 0x72469#define RG_MTKAIF_RXIF_DATA_BIT_MASK_SFT (0x7 << 8)2470#define RG_MTKAIF_RXIF_FIFO_RSP_SFT 42471#define RG_MTKAIF_RXIF_FIFO_RSP_MASK 0x72472#define RG_MTKAIF_RXIF_FIFO_RSP_MASK_SFT (0x7 << 4)2473#define RG_MTKAIF_RXIF_DETECT_ON_SFT 32474#define RG_MTKAIF_RXIF_DETECT_ON_MASK 0x12475#define RG_MTKAIF_RXIF_DETECT_ON_MASK_SFT (0x1 << 3)2476#define RG_MTKAIF_RXIF_DATA_MODE_SFT 02477#define RG_MTKAIF_RXIF_DATA_MODE_MASK 0x12478#define RG_MTKAIF_RXIF_DATA_MODE_MASK_SFT (0x1 << 0)2479 2480/* AFE_ADDA_MTKAIF_RX_CFG1 */2481#define RG_MTKAIF_RXIF_SYNC_SEARCH_TABLE_SFT 122482#define RG_MTKAIF_RXIF_SYNC_SEARCH_TABLE_MASK 0xf2483#define RG_MTKAIF_RXIF_SYNC_SEARCH_TABLE_MASK_SFT (0xf << 12)2484#define RG_MTKAIF_RXIF_INVALID_SYNC_CHECK_ROUND_SFT 82485#define RG_MTKAIF_RXIF_INVALID_SYNC_CHECK_ROUND_MASK 0xf2486#define RG_MTKAIF_RXIF_INVALID_SYNC_CHECK_ROUND_MASK_SFT (0xf << 8)2487#define RG_MTKAIF_RXIF_SYNC_CHECK_ROUND_SFT 42488#define RG_MTKAIF_RXIF_SYNC_CHECK_ROUND_MASK 0xf2489#define RG_MTKAIF_RXIF_SYNC_CHECK_ROUND_MASK_SFT (0xf << 4)2490#define RG_MTKAIF_RXIF_VOICE_MODE_PROTOCOL2_SFT 02491#define RG_MTKAIF_RXIF_VOICE_MODE_PROTOCOL2_MASK 0xf2492#define RG_MTKAIF_RXIF_VOICE_MODE_PROTOCOL2_MASK_SFT (0xf << 0)2493 2494/* AFE_ADDA_MTKAIF_RX_CFG2 */2495#define RG_MTKAIF_RXIF_P2_INPUT_SEL_SFT 152496#define RG_MTKAIF_RXIF_P2_INPUT_SEL_MASK 0x12497#define RG_MTKAIF_RXIF_P2_INPUT_SEL_MASK_SFT (0x1 << 15)2498#define RG_MTKAIF_RXIF_SYNC_WORD2_DISABLE_SFT 142499#define RG_MTKAIF_RXIF_SYNC_WORD2_DISABLE_MASK 0x12500#define RG_MTKAIF_RXIF_SYNC_WORD2_DISABLE_MASK_SFT (0x1 << 14)2501#define RG_MTKAIF_RXIF_SYNC_WORD1_DISABLE_SFT 132502#define RG_MTKAIF_RXIF_SYNC_WORD1_DISABLE_MASK 0x12503#define RG_MTKAIF_RXIF_SYNC_WORD1_DISABLE_MASK_SFT (0x1 << 13)2504#define RG_MTKAIF_RXIF_CLEAR_SYNC_FAIL_SFT 122505#define RG_MTKAIF_RXIF_CLEAR_SYNC_FAIL_MASK 0x12506#define RG_MTKAIF_RXIF_CLEAR_SYNC_FAIL_MASK_SFT (0x1 << 12)2507#define RG_MTKAIF_RXIF_SYNC_CNT_TABLE_SFT 02508#define RG_MTKAIF_RXIF_SYNC_CNT_TABLE_MASK 0xfff2509#define RG_MTKAIF_RXIF_SYNC_CNT_TABLE_MASK_SFT (0xfff << 0)2510 2511/* AFE_ADDA_MTKAIF_RX_CFG3 */2512#define RG_MTKAIF_RXIF_LOOPBACK_USE_NLE_SFT 72513#define RG_MTKAIF_RXIF_LOOPBACK_USE_NLE_MASK 0x12514#define RG_MTKAIF_RXIF_LOOPBACK_USE_NLE_MASK_SFT (0x1 << 7)2515#define RG_MTKAIF_RXIF_FIFO_RSP_PROTOCOL2_SFT 42516#define RG_MTKAIF_RXIF_FIFO_RSP_PROTOCOL2_MASK 0x72517#define RG_MTKAIF_RXIF_FIFO_RSP_PROTOCOL2_MASK_SFT (0x7 << 4)2518#define RG_MTKAIF_RXIF_DETECT_ON_PROTOCOL2_SFT 32519#define RG_MTKAIF_RXIF_DETECT_ON_PROTOCOL2_MASK 0x12520#define RG_MTKAIF_RXIF_DETECT_ON_PROTOCOL2_MASK_SFT (0x1 << 3)2521 2522/* AFE_ADDA_MTKAIF_SYNCWORD_CFG0 */2523#define RG_MTKAIF_RX_SYNC_WORD2_SFT 42524#define RG_MTKAIF_RX_SYNC_WORD2_MASK 0x72525#define RG_MTKAIF_RX_SYNC_WORD2_MASK_SFT (0x7 << 4)2526#define RG_MTKAIF_RX_SYNC_WORD1_SFT 02527#define RG_MTKAIF_RX_SYNC_WORD1_MASK 0x72528#define RG_MTKAIF_RX_SYNC_WORD1_MASK_SFT (0x7 << 0)2529 2530/* AFE_ADDA_MTKAIF_SYNCWORD_CFG1 */2531#define RG_ADDA6_MTKAIF_TX_SYNC_WORD2_SFT 122532#define RG_ADDA6_MTKAIF_TX_SYNC_WORD2_MASK 0x72533#define RG_ADDA6_MTKAIF_TX_SYNC_WORD2_MASK_SFT (0x7 << 12)2534#define RG_ADDA6_MTKAIF_TX_SYNC_WORD1_SFT 82535#define RG_ADDA6_MTKAIF_TX_SYNC_WORD1_MASK 0x72536#define RG_ADDA6_MTKAIF_TX_SYNC_WORD1_MASK_SFT (0x7 << 8)2537#define RG_ADDA_MTKAIF_TX_SYNC_WORD2_SFT 42538#define RG_ADDA_MTKAIF_TX_SYNC_WORD2_MASK 0x72539#define RG_ADDA_MTKAIF_TX_SYNC_WORD2_MASK_SFT (0x7 << 4)2540#define RG_ADDA_MTKAIF_TX_SYNC_WORD1_SFT 02541#define RG_ADDA_MTKAIF_TX_SYNC_WORD1_MASK 0x72542#define RG_ADDA_MTKAIF_TX_SYNC_WORD1_MASK_SFT (0x7 << 0)2543 2544/* AFE_SGEN_CFG0 */2545#define SGEN_AMP_DIV_CH1_CTL_SFT 122546#define SGEN_AMP_DIV_CH1_CTL_MASK 0xf2547#define SGEN_AMP_DIV_CH1_CTL_MASK_SFT (0xf << 12)2548#define SGEN_DAC_EN_CTL_SFT 72549#define SGEN_DAC_EN_CTL_MASK 0x12550#define SGEN_DAC_EN_CTL_MASK_SFT (0x1 << 7)2551#define SGEN_MUTE_SW_CTL_SFT 62552#define SGEN_MUTE_SW_CTL_MASK 0x12553#define SGEN_MUTE_SW_CTL_MASK_SFT (0x1 << 6)2554#define R_AUD_SDM_MUTE_L_SFT 52555#define R_AUD_SDM_MUTE_L_MASK 0x12556#define R_AUD_SDM_MUTE_L_MASK_SFT (0x1 << 5)2557#define R_AUD_SDM_MUTE_R_SFT 42558#define R_AUD_SDM_MUTE_R_MASK 0x12559#define R_AUD_SDM_MUTE_R_MASK_SFT (0x1 << 4)2560#define R_AUD_SDM_MUTE_L_2ND_SFT 32561#define R_AUD_SDM_MUTE_L_2ND_MASK 0x12562#define R_AUD_SDM_MUTE_L_2ND_MASK_SFT (0x1 << 3)2563#define R_AUD_SDM_MUTE_R_2ND_SFT 22564#define R_AUD_SDM_MUTE_R_2ND_MASK 0x12565#define R_AUD_SDM_MUTE_R_2ND_MASK_SFT (0x1 << 2)2566 2567/* AFE_SGEN_CFG1 */2568#define C_SGEN_RCH_INV_5BIT_SFT 152569#define C_SGEN_RCH_INV_5BIT_MASK 0x12570#define C_SGEN_RCH_INV_5BIT_MASK_SFT (0x1 << 15)2571#define C_SGEN_RCH_INV_8BIT_SFT 142572#define C_SGEN_RCH_INV_8BIT_MASK 0x12573#define C_SGEN_RCH_INV_8BIT_MASK_SFT (0x1 << 14)2574#define SGEN_FREQ_DIV_CH1_CTL_SFT 02575#define SGEN_FREQ_DIV_CH1_CTL_MASK 0x1f2576#define SGEN_FREQ_DIV_CH1_CTL_MASK_SFT (0x1f << 0)2577 2578/* AFE_ADC_ASYNC_FIFO_CFG */2579#define RG_UL_ASYNC_FIFO_SOFT_RST_EN_SFT 52580#define RG_UL_ASYNC_FIFO_SOFT_RST_EN_MASK 0x12581#define RG_UL_ASYNC_FIFO_SOFT_RST_EN_MASK_SFT (0x1 << 5)2582#define RG_UL_ASYNC_FIFO_SOFT_RST_SFT 42583#define RG_UL_ASYNC_FIFO_SOFT_RST_MASK 0x12584#define RG_UL_ASYNC_FIFO_SOFT_RST_MASK_SFT (0x1 << 4)2585#define RG_AMIC_UL_ADC_CLK_SEL_SFT 12586#define RG_AMIC_UL_ADC_CLK_SEL_MASK 0x12587#define RG_AMIC_UL_ADC_CLK_SEL_MASK_SFT (0x1 << 1)2588 2589/* AFE_ADC_ASYNC_FIFO_CFG1 */2590#define RG_UL2_ASYNC_FIFO_SOFT_RST_EN_SFT 52591#define RG_UL2_ASYNC_FIFO_SOFT_RST_EN_MASK 0x12592#define RG_UL2_ASYNC_FIFO_SOFT_RST_EN_MASK_SFT (0x1 << 5)2593#define RG_UL2_ASYNC_FIFO_SOFT_RST_SFT 42594#define RG_UL2_ASYNC_FIFO_SOFT_RST_MASK 0x12595#define RG_UL2_ASYNC_FIFO_SOFT_RST_MASK_SFT (0x1 << 4)2596 2597/* AFE_DCCLK_CFG0 */2598#define DCCLK_DIV_SFT 52599#define DCCLK_DIV_MASK 0x7ff2600#define DCCLK_DIV_MASK_SFT (0x7ff << 5)2601#define DCCLK_INV_SFT 42602#define DCCLK_INV_MASK 0x12603#define DCCLK_INV_MASK_SFT (0x1 << 4)2604#define DCCLK_REF_CK_SEL_SFT 22605#define DCCLK_REF_CK_SEL_MASK 0x32606#define DCCLK_REF_CK_SEL_MASK_SFT (0x3 << 2)2607#define DCCLK_PDN_SFT 12608#define DCCLK_PDN_MASK 0x12609#define DCCLK_PDN_MASK_SFT (0x1 << 1)2610#define DCCLK_GEN_ON_SFT 02611#define DCCLK_GEN_ON_MASK 0x12612#define DCCLK_GEN_ON_MASK_SFT (0x1 << 0)2613 2614/* AFE_DCCLK_CFG1 */2615#define RESYNC_SRC_SEL_SFT 102616#define RESYNC_SRC_SEL_MASK 0x32617#define RESYNC_SRC_SEL_MASK_SFT (0x3 << 10)2618#define RESYNC_SRC_CK_INV_SFT 92619#define RESYNC_SRC_CK_INV_MASK 0x12620#define RESYNC_SRC_CK_INV_MASK_SFT (0x1 << 9)2621#define DCCLK_RESYNC_BYPASS_SFT 82622#define DCCLK_RESYNC_BYPASS_MASK 0x12623#define DCCLK_RESYNC_BYPASS_MASK_SFT (0x1 << 8)2624#define DCCLK_PHASE_SEL_SFT 42625#define DCCLK_PHASE_SEL_MASK 0xf2626#define DCCLK_PHASE_SEL_MASK_SFT (0xf << 4)2627 2628/* AUDIO_DIG_CFG */2629#define RG_AUD_PAD_TOP_DAT_MISO2_LOOPBACK_SFT 152630#define RG_AUD_PAD_TOP_DAT_MISO2_LOOPBACK_MASK 0x12631#define RG_AUD_PAD_TOP_DAT_MISO2_LOOPBACK_MASK_SFT (0x1 << 15)2632#define RG_AUD_PAD_TOP_PHASE_MODE2_SFT 82633#define RG_AUD_PAD_TOP_PHASE_MODE2_MASK 0x7f2634#define RG_AUD_PAD_TOP_PHASE_MODE2_MASK_SFT (0x7f << 8)2635#define RG_AUD_PAD_TOP_DAT_MISO_LOOPBACK_SFT 72636#define RG_AUD_PAD_TOP_DAT_MISO_LOOPBACK_MASK 0x12637#define RG_AUD_PAD_TOP_DAT_MISO_LOOPBACK_MASK_SFT (0x1 << 7)2638#define RG_AUD_PAD_TOP_PHASE_MODE_SFT 02639#define RG_AUD_PAD_TOP_PHASE_MODE_MASK 0x7f2640#define RG_AUD_PAD_TOP_PHASE_MODE_MASK_SFT (0x7f << 0)2641 2642/* AUDIO_DIG_CFG1 */2643#define RG_AUD_PAD_TOP_DAT_MISO3_LOOPBACK_SFT 72644#define RG_AUD_PAD_TOP_DAT_MISO3_LOOPBACK_MASK 0x12645#define RG_AUD_PAD_TOP_DAT_MISO3_LOOPBACK_MASK_SFT (0x1 << 7)2646#define RG_AUD_PAD_TOP_PHASE_MODE3_SFT 02647#define RG_AUD_PAD_TOP_PHASE_MODE3_MASK 0x7f2648#define RG_AUD_PAD_TOP_PHASE_MODE3_MASK_SFT (0x7f << 0)2649 2650/* AFE_AUD_PAD_TOP */2651#define RG_AUD_PAD_TOP_TX_FIFO_RSP_SFT 122652#define RG_AUD_PAD_TOP_TX_FIFO_RSP_MASK 0x72653#define RG_AUD_PAD_TOP_TX_FIFO_RSP_MASK_SFT (0x7 << 12)2654#define RG_AUD_PAD_TOP_MTKAIF_CLK_PROTOCOL2_SFT 112655#define RG_AUD_PAD_TOP_MTKAIF_CLK_PROTOCOL2_MASK 0x12656#define RG_AUD_PAD_TOP_MTKAIF_CLK_PROTOCOL2_MASK_SFT (0x1 << 11)2657#define RG_AUD_PAD_TOP_TX_FIFO_ON_SFT 82658#define RG_AUD_PAD_TOP_TX_FIFO_ON_MASK 0x12659#define RG_AUD_PAD_TOP_TX_FIFO_ON_MASK_SFT (0x1 << 8)2660 2661/* AFE_AUD_PAD_TOP_MON */2662#define ADDA_AUD_PAD_TOP_MON_SFT 02663#define ADDA_AUD_PAD_TOP_MON_MASK 0xffff2664#define ADDA_AUD_PAD_TOP_MON_MASK_SFT (0xffff << 0)2665 2666/* AFE_AUD_PAD_TOP_MON1 */2667#define ADDA_AUD_PAD_TOP_MON1_SFT 02668#define ADDA_AUD_PAD_TOP_MON1_MASK 0xffff2669#define ADDA_AUD_PAD_TOP_MON1_MASK_SFT (0xffff << 0)2670 2671/* AFE_AUD_PAD_TOP_MON2 */2672#define ADDA_AUD_PAD_TOP_MON2_SFT 02673#define ADDA_AUD_PAD_TOP_MON2_MASK 0xffff2674#define ADDA_AUD_PAD_TOP_MON2_MASK_SFT (0xffff << 0)2675 2676/* AFE_DL_NLE_CFG */2677#define NLE_RCH_HPGAIN_SEL_SFT 102678#define NLE_RCH_HPGAIN_SEL_MASK 0x12679#define NLE_RCH_HPGAIN_SEL_MASK_SFT (0x1 << 10)2680#define NLE_RCH_CH_SEL_SFT 92681#define NLE_RCH_CH_SEL_MASK 0x12682#define NLE_RCH_CH_SEL_MASK_SFT (0x1 << 9)2683#define NLE_RCH_ON_SFT 82684#define NLE_RCH_ON_MASK 0x12685#define NLE_RCH_ON_MASK_SFT (0x1 << 8)2686#define NLE_LCH_HPGAIN_SEL_SFT 22687#define NLE_LCH_HPGAIN_SEL_MASK 0x12688#define NLE_LCH_HPGAIN_SEL_MASK_SFT (0x1 << 2)2689#define NLE_LCH_CH_SEL_SFT 12690#define NLE_LCH_CH_SEL_MASK 0x12691#define NLE_LCH_CH_SEL_MASK_SFT (0x1 << 1)2692#define NLE_LCH_ON_SFT 02693#define NLE_LCH_ON_MASK 0x12694#define NLE_LCH_ON_MASK_SFT (0x1 << 0)2695 2696/* AFE_DL_NLE_MON */2697#define NLE_MONITOR_SFT 02698#define NLE_MONITOR_MASK 0x3fff2699#define NLE_MONITOR_MASK_SFT (0x3fff << 0)2700 2701/* AFE_CG_EN_MON */2702#define CK_CG_EN_MON_SFT 02703#define CK_CG_EN_MON_MASK 0x3f2704#define CK_CG_EN_MON_MASK_SFT (0x3f << 0)2705 2706/* AFE_MIC_ARRAY_CFG */2707#define RG_AMIC_ADC1_SOURCE_SEL_SFT 102708#define RG_AMIC_ADC1_SOURCE_SEL_MASK 0x32709#define RG_AMIC_ADC1_SOURCE_SEL_MASK_SFT (0x3 << 10)2710#define RG_AMIC_ADC2_SOURCE_SEL_SFT 82711#define RG_AMIC_ADC2_SOURCE_SEL_MASK 0x32712#define RG_AMIC_ADC2_SOURCE_SEL_MASK_SFT (0x3 << 8)2713#define RG_AMIC_ADC3_SOURCE_SEL_SFT 62714#define RG_AMIC_ADC3_SOURCE_SEL_MASK 0x32715#define RG_AMIC_ADC3_SOURCE_SEL_MASK_SFT (0x3 << 6)2716#define RG_DMIC_ADC1_SOURCE_SEL_SFT 42717#define RG_DMIC_ADC1_SOURCE_SEL_MASK 0x32718#define RG_DMIC_ADC1_SOURCE_SEL_MASK_SFT (0x3 << 4)2719#define RG_DMIC_ADC2_SOURCE_SEL_SFT 22720#define RG_DMIC_ADC2_SOURCE_SEL_MASK 0x32721#define RG_DMIC_ADC2_SOURCE_SEL_MASK_SFT (0x3 << 2)2722#define RG_DMIC_ADC3_SOURCE_SEL_SFT 02723#define RG_DMIC_ADC3_SOURCE_SEL_MASK 0x32724#define RG_DMIC_ADC3_SOURCE_SEL_MASK_SFT (0x3 << 0)2725 2726/* AFE_CHOP_CFG0 */2727#define RG_CHOP_DIV_SEL_SFT 42728#define RG_CHOP_DIV_SEL_MASK 0x1f2729#define RG_CHOP_DIV_SEL_MASK_SFT (0x1f << 4)2730#define RG_CHOP_DIV_EN_SFT 02731#define RG_CHOP_DIV_EN_MASK 0x12732#define RG_CHOP_DIV_EN_MASK_SFT (0x1 << 0)2733 2734/* AFE_MTKAIF_MUX_CFG */2735#define RG_ADDA6_EN_SEL_SFT 122736#define RG_ADDA6_EN_SEL_MASK 0x12737#define RG_ADDA6_EN_SEL_MASK_SFT (0x1 << 12)2738#define RG_ADDA6_CH2_SEL_SFT 102739#define RG_ADDA6_CH2_SEL_MASK 0x32740#define RG_ADDA6_CH2_SEL_MASK_SFT (0x3 << 10)2741#define RG_ADDA6_CH1_SEL_SFT 82742#define RG_ADDA6_CH1_SEL_MASK 0x32743#define RG_ADDA6_CH1_SEL_MASK_SFT (0x3 << 8)2744#define RG_ADDA_EN_SEL_SFT 42745#define RG_ADDA_EN_SEL_MASK 0x12746#define RG_ADDA_EN_SEL_MASK_SFT (0x1 << 4)2747#define RG_ADDA_CH2_SEL_SFT 22748#define RG_ADDA_CH2_SEL_MASK 0x32749#define RG_ADDA_CH2_SEL_MASK_SFT (0x3 << 2)2750#define RG_ADDA_CH1_SEL_SFT 02751#define RG_ADDA_CH1_SEL_MASK 0x32752#define RG_ADDA_CH1_SEL_MASK_SFT (0x3 << 0)2753 2754/* AFE_PMIC_NEWIF_CFG3 */2755#define RG_UP8X_SYNC_WORD_SFT 02756#define RG_UP8X_SYNC_WORD_MASK 0xffff2757#define RG_UP8X_SYNC_WORD_MASK_SFT (0xffff << 0)2758 2759/* AFE_NCP_CFG0 */2760#define RG_NCP_CK1_VALID_CNT_SFT 92761#define RG_NCP_CK1_VALID_CNT_MASK 0x7f2762#define RG_NCP_CK1_VALID_CNT_MASK_SFT (0x7f << 9)2763#define RG_NCP_ADITH_SFT 82764#define RG_NCP_ADITH_MASK 0x12765#define RG_NCP_ADITH_MASK_SFT (0x1 << 8)2766#define RG_NCP_DITHER_EN_SFT 72767#define RG_NCP_DITHER_EN_MASK 0x12768#define RG_NCP_DITHER_EN_MASK_SFT (0x1 << 7)2769#define RG_NCP_DITHER_FIXED_CK0_ACK1_2P_SFT 42770#define RG_NCP_DITHER_FIXED_CK0_ACK1_2P_MASK 0x72771#define RG_NCP_DITHER_FIXED_CK0_ACK1_2P_MASK_SFT (0x7 << 4)2772#define RG_NCP_DITHER_FIXED_CK0_ACK2_2P_SFT 12773#define RG_NCP_DITHER_FIXED_CK0_ACK2_2P_MASK 0x72774#define RG_NCP_DITHER_FIXED_CK0_ACK2_2P_MASK_SFT (0x7 << 1)2775#define RG_NCP_ON_SFT 02776#define RG_NCP_ON_MASK 0x12777#define RG_NCP_ON_MASK_SFT (0x1 << 0)2778 2779/* AFE_NCP_CFG1 */2780#define RG_XY_VAL_CFG_EN_SFT 152781#define RG_XY_VAL_CFG_EN_MASK 0x12782#define RG_XY_VAL_CFG_EN_MASK_SFT (0x1 << 15)2783#define RG_X_VAL_CFG_SFT 82784#define RG_X_VAL_CFG_MASK 0x7f2785#define RG_X_VAL_CFG_MASK_SFT (0x7f << 8)2786#define RG_Y_VAL_CFG_SFT 02787#define RG_Y_VAL_CFG_MASK 0x7f2788#define RG_Y_VAL_CFG_MASK_SFT (0x7f << 0)2789 2790/* AFE_NCP_CFG2 */2791#define RG_NCP_NONCLK_SET_SFT 12792#define RG_NCP_NONCLK_SET_MASK 0x12793#define RG_NCP_NONCLK_SET_MASK_SFT (0x1 << 1)2794#define RG_NCP_PDDIS_EN_SFT 02795#define RG_NCP_PDDIS_EN_MASK 0x12796#define RG_NCP_PDDIS_EN_MASK_SFT (0x1 << 0)2797 2798/* AUDENC_ANA_CON0 */2799#define RG_AUDPREAMPLON_SFT 02800#define RG_AUDPREAMPLON_MASK 0x12801#define RG_AUDPREAMPLON_MASK_SFT (0x1 << 0)2802#define RG_AUDPREAMPLDCCEN_SFT 12803#define RG_AUDPREAMPLDCCEN_MASK 0x12804#define RG_AUDPREAMPLDCCEN_MASK_SFT (0x1 << 1)2805#define RG_AUDPREAMPLDCPRECHARGE_SFT 22806#define RG_AUDPREAMPLDCPRECHARGE_MASK 0x12807#define RG_AUDPREAMPLDCPRECHARGE_MASK_SFT (0x1 << 2)2808#define RG_AUDPREAMPLPGATEST_SFT 32809#define RG_AUDPREAMPLPGATEST_MASK 0x12810#define RG_AUDPREAMPLPGATEST_MASK_SFT (0x1 << 3)2811#define RG_AUDPREAMPLVSCALE_SFT 42812#define RG_AUDPREAMPLVSCALE_MASK 0x32813#define RG_AUDPREAMPLVSCALE_MASK_SFT (0x3 << 4)2814#define RG_AUDPREAMPLINPUTSEL_SFT 62815#define RG_AUDPREAMPLINPUTSEL_MASK 0x32816#define RG_AUDPREAMPLINPUTSEL_MASK_SFT (0x3 << 6)2817#define RG_AUDPREAMPLGAIN_SFT 82818#define RG_AUDPREAMPLGAIN_MASK 0x72819#define RG_AUDPREAMPLGAIN_MASK_SFT (0x7 << 8)2820#define RG_BULKL_VCM_EN_SFT 112821#define RG_BULKL_VCM_EN_MASK 0x12822#define RG_BULKL_VCM_EN_MASK_SFT (0x1 << 11)2823#define RG_AUDADCLPWRUP_SFT 122824#define RG_AUDADCLPWRUP_MASK 0x12825#define RG_AUDADCLPWRUP_MASK_SFT (0x1 << 12)2826#define RG_AUDADCLINPUTSEL_SFT 132827#define RG_AUDADCLINPUTSEL_MASK 0x32828#define RG_AUDADCLINPUTSEL_MASK_SFT (0x3 << 13)2829 2830/* AUDENC_ANA_CON1 */2831#define RG_AUDPREAMPRON_SFT 02832#define RG_AUDPREAMPRON_MASK 0x12833#define RG_AUDPREAMPRON_MASK_SFT (0x1 << 0)2834#define RG_AUDPREAMPRDCCEN_SFT 12835#define RG_AUDPREAMPRDCCEN_MASK 0x12836#define RG_AUDPREAMPRDCCEN_MASK_SFT (0x1 << 1)2837#define RG_AUDPREAMPRDCPRECHARGE_SFT 22838#define RG_AUDPREAMPRDCPRECHARGE_MASK 0x12839#define RG_AUDPREAMPRDCPRECHARGE_MASK_SFT (0x1 << 2)2840#define RG_AUDPREAMPRPGATEST_SFT 32841#define RG_AUDPREAMPRPGATEST_MASK 0x12842#define RG_AUDPREAMPRPGATEST_MASK_SFT (0x1 << 3)2843#define RG_AUDPREAMPRVSCALE_SFT 42844#define RG_AUDPREAMPRVSCALE_MASK 0x32845#define RG_AUDPREAMPRVSCALE_MASK_SFT (0x3 << 4)2846#define RG_AUDPREAMPRINPUTSEL_SFT 62847#define RG_AUDPREAMPRINPUTSEL_MASK 0x32848#define RG_AUDPREAMPRINPUTSEL_MASK_SFT (0x3 << 6)2849#define RG_AUDPREAMPRGAIN_SFT 82850#define RG_AUDPREAMPRGAIN_MASK 0x72851#define RG_AUDPREAMPRGAIN_MASK_SFT (0x7 << 8)2852#define RG_BULKR_VCM_EN_SFT 112853#define RG_BULKR_VCM_EN_MASK 0x12854#define RG_BULKR_VCM_EN_MASK_SFT (0x1 << 11)2855#define RG_AUDADCRPWRUP_SFT 122856#define RG_AUDADCRPWRUP_MASK 0x12857#define RG_AUDADCRPWRUP_MASK_SFT (0x1 << 12)2858#define RG_AUDADCRINPUTSEL_SFT 132859#define RG_AUDADCRINPUTSEL_MASK 0x32860#define RG_AUDADCRINPUTSEL_MASK_SFT (0x3 << 13)2861 2862/* AUDENC_ANA_CON2 */2863#define RG_AUDPREAMP3ON_SFT 02864#define RG_AUDPREAMP3ON_MASK 0x12865#define RG_AUDPREAMP3ON_MASK_SFT (0x1 << 0)2866#define RG_AUDPREAMP3DCCEN_SFT 12867#define RG_AUDPREAMP3DCCEN_MASK 0x12868#define RG_AUDPREAMP3DCCEN_MASK_SFT (0x1 << 1)2869#define RG_AUDPREAMP3DCPRECHARGE_SFT 22870#define RG_AUDPREAMP3DCPRECHARGE_MASK 0x12871#define RG_AUDPREAMP3DCPRECHARGE_MASK_SFT (0x1 << 2)2872#define RG_AUDPREAMP3PGATEST_SFT 32873#define RG_AUDPREAMP3PGATEST_MASK 0x12874#define RG_AUDPREAMP3PGATEST_MASK_SFT (0x1 << 3)2875#define RG_AUDPREAMP3VSCALE_SFT 42876#define RG_AUDPREAMP3VSCALE_MASK 0x32877#define RG_AUDPREAMP3VSCALE_MASK_SFT (0x3 << 4)2878#define RG_AUDPREAMP3INPUTSEL_SFT 62879#define RG_AUDPREAMP3INPUTSEL_MASK 0x32880#define RG_AUDPREAMP3INPUTSEL_MASK_SFT (0x3 << 6)2881#define RG_AUDPREAMP3GAIN_SFT 82882#define RG_AUDPREAMP3GAIN_MASK 0x72883#define RG_AUDPREAMP3GAIN_MASK_SFT (0x7 << 8)2884#define RG_BULK3_VCM_EN_SFT 112885#define RG_BULK3_VCM_EN_MASK 0x12886#define RG_BULK3_VCM_EN_MASK_SFT (0x1 << 11)2887#define RG_AUDADC3PWRUP_SFT 122888#define RG_AUDADC3PWRUP_MASK 0x12889#define RG_AUDADC3PWRUP_MASK_SFT (0x1 << 12)2890#define RG_AUDADC3INPUTSEL_SFT 132891#define RG_AUDADC3INPUTSEL_MASK 0x32892#define RG_AUDADC3INPUTSEL_MASK_SFT (0x3 << 13)2893 2894/* AUDENC_ANA_CON3 */2895#define RG_AUDULHALFBIAS_SFT 02896#define RG_AUDULHALFBIAS_MASK 0x12897#define RG_AUDULHALFBIAS_MASK_SFT (0x1 << 0)2898#define RG_AUDGLBVOWLPWEN_SFT 12899#define RG_AUDGLBVOWLPWEN_MASK 0x12900#define RG_AUDGLBVOWLPWEN_MASK_SFT (0x1 << 1)2901#define RG_AUDPREAMPLPEN_SFT 22902#define RG_AUDPREAMPLPEN_MASK 0x12903#define RG_AUDPREAMPLPEN_MASK_SFT (0x1 << 2)2904#define RG_AUDADC1STSTAGELPEN_SFT 32905#define RG_AUDADC1STSTAGELPEN_MASK 0x12906#define RG_AUDADC1STSTAGELPEN_MASK_SFT (0x1 << 3)2907#define RG_AUDADC2NDSTAGELPEN_SFT 42908#define RG_AUDADC2NDSTAGELPEN_MASK 0x12909#define RG_AUDADC2NDSTAGELPEN_MASK_SFT (0x1 << 4)2910#define RG_AUDADCFLASHLPEN_SFT 52911#define RG_AUDADCFLASHLPEN_MASK 0x12912#define RG_AUDADCFLASHLPEN_MASK_SFT (0x1 << 5)2913#define RG_AUDPREAMPIDDTEST_SFT 62914#define RG_AUDPREAMPIDDTEST_MASK 0x32915#define RG_AUDPREAMPIDDTEST_MASK_SFT (0x3 << 6)2916#define RG_AUDADC1STSTAGEIDDTEST_SFT 82917#define RG_AUDADC1STSTAGEIDDTEST_MASK 0x32918#define RG_AUDADC1STSTAGEIDDTEST_MASK_SFT (0x3 << 8)2919#define RG_AUDADC2NDSTAGEIDDTEST_SFT 102920#define RG_AUDADC2NDSTAGEIDDTEST_MASK 0x32921#define RG_AUDADC2NDSTAGEIDDTEST_MASK_SFT (0x3 << 10)2922#define RG_AUDADCREFBUFIDDTEST_SFT 122923#define RG_AUDADCREFBUFIDDTEST_MASK 0x32924#define RG_AUDADCREFBUFIDDTEST_MASK_SFT (0x3 << 12)2925#define RG_AUDADCFLASHIDDTEST_SFT 142926#define RG_AUDADCFLASHIDDTEST_MASK 0x32927#define RG_AUDADCFLASHIDDTEST_MASK_SFT (0x3 << 14)2928 2929/* AUDENC_ANA_CON4 */2930#define RG_AUDRULHALFBIAS_SFT 02931#define RG_AUDRULHALFBIAS_MASK 0x12932#define RG_AUDRULHALFBIAS_MASK_SFT (0x1 << 0)2933#define RG_AUDGLBRVOWLPWEN_SFT 12934#define RG_AUDGLBRVOWLPWEN_MASK 0x12935#define RG_AUDGLBRVOWLPWEN_MASK_SFT (0x1 << 1)2936#define RG_AUDRPREAMPLPEN_SFT 22937#define RG_AUDRPREAMPLPEN_MASK 0x12938#define RG_AUDRPREAMPLPEN_MASK_SFT (0x1 << 2)2939#define RG_AUDRADC1STSTAGELPEN_SFT 32940#define RG_AUDRADC1STSTAGELPEN_MASK 0x12941#define RG_AUDRADC1STSTAGELPEN_MASK_SFT (0x1 << 3)2942#define RG_AUDRADC2NDSTAGELPEN_SFT 42943#define RG_AUDRADC2NDSTAGELPEN_MASK 0x12944#define RG_AUDRADC2NDSTAGELPEN_MASK_SFT (0x1 << 4)2945#define RG_AUDRADCFLASHLPEN_SFT 52946#define RG_AUDRADCFLASHLPEN_MASK 0x12947#define RG_AUDRADCFLASHLPEN_MASK_SFT (0x1 << 5)2948#define RG_AUDRPREAMPIDDTEST_SFT 62949#define RG_AUDRPREAMPIDDTEST_MASK 0x32950#define RG_AUDRPREAMPIDDTEST_MASK_SFT (0x3 << 6)2951#define RG_AUDRADC1STSTAGEIDDTEST_SFT 82952#define RG_AUDRADC1STSTAGEIDDTEST_MASK 0x32953#define RG_AUDRADC1STSTAGEIDDTEST_MASK_SFT (0x3 << 8)2954#define RG_AUDRADC2NDSTAGEIDDTEST_SFT 102955#define RG_AUDRADC2NDSTAGEIDDTEST_MASK 0x32956#define RG_AUDRADC2NDSTAGEIDDTEST_MASK_SFT (0x3 << 10)2957#define RG_AUDRADCREFBUFIDDTEST_SFT 122958#define RG_AUDRADCREFBUFIDDTEST_MASK 0x32959#define RG_AUDRADCREFBUFIDDTEST_MASK_SFT (0x3 << 12)2960#define RG_AUDRADCFLASHIDDTEST_SFT 142961#define RG_AUDRADCFLASHIDDTEST_MASK 0x32962#define RG_AUDRADCFLASHIDDTEST_MASK_SFT (0x3 << 14)2963 2964/* AUDENC_ANA_CON5 */2965#define RG_AUDADCCLKRSTB_SFT 02966#define RG_AUDADCCLKRSTB_MASK 0x12967#define RG_AUDADCCLKRSTB_MASK_SFT (0x1 << 0)2968#define RG_AUDADCCLKSEL_SFT 12969#define RG_AUDADCCLKSEL_MASK 0x32970#define RG_AUDADCCLKSEL_MASK_SFT (0x3 << 1)2971#define RG_AUDADCCLKSOURCE_SFT 32972#define RG_AUDADCCLKSOURCE_MASK 0x32973#define RG_AUDADCCLKSOURCE_MASK_SFT (0x3 << 3)2974#define RG_AUDADCCLKGENMODE_SFT 52975#define RG_AUDADCCLKGENMODE_MASK 0x32976#define RG_AUDADCCLKGENMODE_MASK_SFT (0x3 << 5)2977#define RG_AUDPREAMP_ACCFS_SFT 72978#define RG_AUDPREAMP_ACCFS_MASK 0x12979#define RG_AUDPREAMP_ACCFS_MASK_SFT (0x1 << 7)2980#define RG_AUDPREAMPAAFEN_SFT 82981#define RG_AUDPREAMPAAFEN_MASK 0x12982#define RG_AUDPREAMPAAFEN_MASK_SFT (0x1 << 8)2983#define RG_DCCVCMBUFLPMODSEL_SFT 92984#define RG_DCCVCMBUFLPMODSEL_MASK 0x12985#define RG_DCCVCMBUFLPMODSEL_MASK_SFT (0x1 << 9)2986#define RG_DCCVCMBUFLPSWEN_SFT 102987#define RG_DCCVCMBUFLPSWEN_MASK 0x12988#define RG_DCCVCMBUFLPSWEN_MASK_SFT (0x1 << 10)2989#define RG_AUDSPAREPGA_SFT 112990#define RG_AUDSPAREPGA_MASK 0x1f2991#define RG_AUDSPAREPGA_MASK_SFT (0x1f << 11)2992 2993/* AUDENC_ANA_CON6 */2994#define RG_AUDADC1STSTAGESDENB_SFT 02995#define RG_AUDADC1STSTAGESDENB_MASK 0x12996#define RG_AUDADC1STSTAGESDENB_MASK_SFT (0x1 << 0)2997#define RG_AUDADC2NDSTAGERESET_SFT 12998#define RG_AUDADC2NDSTAGERESET_MASK 0x12999#define RG_AUDADC2NDSTAGERESET_MASK_SFT (0x1 << 1)3000#define RG_AUDADC3RDSTAGERESET_SFT 23001#define RG_AUDADC3RDSTAGERESET_MASK 0x13002#define RG_AUDADC3RDSTAGERESET_MASK_SFT (0x1 << 2)3003#define RG_AUDADCFSRESET_SFT 33004#define RG_AUDADCFSRESET_MASK 0x13005#define RG_AUDADCFSRESET_MASK_SFT (0x1 << 3)3006#define RG_AUDADCWIDECM_SFT 43007#define RG_AUDADCWIDECM_MASK 0x13008#define RG_AUDADCWIDECM_MASK_SFT (0x1 << 4)3009#define RG_AUDADCNOPATEST_SFT 53010#define RG_AUDADCNOPATEST_MASK 0x13011#define RG_AUDADCNOPATEST_MASK_SFT (0x1 << 5)3012#define RG_AUDADCBYPASS_SFT 63013#define RG_AUDADCBYPASS_MASK 0x13014#define RG_AUDADCBYPASS_MASK_SFT (0x1 << 6)3015#define RG_AUDADCFFBYPASS_SFT 73016#define RG_AUDADCFFBYPASS_MASK 0x13017#define RG_AUDADCFFBYPASS_MASK_SFT (0x1 << 7)3018#define RG_AUDADCDACFBCURRENT_SFT 83019#define RG_AUDADCDACFBCURRENT_MASK 0x13020#define RG_AUDADCDACFBCURRENT_MASK_SFT (0x1 << 8)3021#define RG_AUDADCDACIDDTEST_SFT 93022#define RG_AUDADCDACIDDTEST_MASK 0x33023#define RG_AUDADCDACIDDTEST_MASK_SFT (0x3 << 9)3024#define RG_AUDADCDACNRZ_SFT 113025#define RG_AUDADCDACNRZ_MASK 0x13026#define RG_AUDADCDACNRZ_MASK_SFT (0x1 << 11)3027#define RG_AUDADCNODEM_SFT 123028#define RG_AUDADCNODEM_MASK 0x13029#define RG_AUDADCNODEM_MASK_SFT (0x1 << 12)3030#define RG_AUDADCDACTEST_SFT 133031#define RG_AUDADCDACTEST_MASK 0x13032#define RG_AUDADCDACTEST_MASK_SFT (0x1 << 13)3033#define RG_AUDADCDAC0P25FS_SFT 143034#define RG_AUDADCDAC0P25FS_MASK 0x13035#define RG_AUDADCDAC0P25FS_MASK_SFT (0x1 << 14)3036#define RG_AUDADCRDAC0P25FS_SFT 153037#define RG_AUDADCRDAC0P25FS_MASK 0x13038#define RG_AUDADCRDAC0P25FS_MASK_SFT (0x1 << 15)3039 3040/* AUDENC_ANA_CON7 */3041#define RG_AUDADCTESTDATA_SFT 03042#define RG_AUDADCTESTDATA_MASK 0xffff3043#define RG_AUDADCTESTDATA_MASK_SFT (0xffff << 0)3044 3045/* AUDENC_ANA_CON8 */3046#define RG_AUDRCTUNEL_SFT 03047#define RG_AUDRCTUNEL_MASK 0x1f3048#define RG_AUDRCTUNEL_MASK_SFT (0x1f << 0)3049#define RG_AUDRCTUNELSEL_SFT 53050#define RG_AUDRCTUNELSEL_MASK 0x13051#define RG_AUDRCTUNELSEL_MASK_SFT (0x1 << 5)3052#define RG_AUDRCTUNER_SFT 83053#define RG_AUDRCTUNER_MASK 0x1f3054#define RG_AUDRCTUNER_MASK_SFT (0x1f << 8)3055#define RG_AUDRCTUNERSEL_SFT 133056#define RG_AUDRCTUNERSEL_MASK 0x13057#define RG_AUDRCTUNERSEL_MASK_SFT (0x1 << 13)3058 3059/* AUDENC_ANA_CON9 */3060#define RG_AUD3CTUNEL_SFT 03061#define RG_AUD3CTUNEL_MASK 0x1f3062#define RG_AUD3CTUNEL_MASK_SFT (0x1f << 0)3063#define RG_AUD3CTUNELSEL_SFT 53064#define RG_AUD3CTUNELSEL_MASK 0x13065#define RG_AUD3CTUNELSEL_MASK_SFT (0x1 << 5)3066#define RGS_AUDRCTUNE3READ_SFT 63067#define RGS_AUDRCTUNE3READ_MASK 0x1f3068#define RGS_AUDRCTUNE3READ_MASK_SFT (0x1f << 6)3069#define RG_AUD3SPARE_SFT 113070#define RG_AUD3SPARE_MASK 0x1f3071#define RG_AUD3SPARE_MASK_SFT (0x1f << 11)3072 3073/* AUDENC_ANA_CON10 */3074#define RGS_AUDRCTUNELREAD_SFT 03075#define RGS_AUDRCTUNELREAD_MASK 0x1f3076#define RGS_AUDRCTUNELREAD_MASK_SFT (0x1f << 0)3077#define RGS_AUDRCTUNERREAD_SFT 83078#define RGS_AUDRCTUNERREAD_MASK 0x1f3079#define RGS_AUDRCTUNERREAD_MASK_SFT (0x1f << 8)3080 3081/* AUDENC_ANA_CON11 */3082#define RG_AUDSPAREVA30_SFT 03083#define RG_AUDSPAREVA30_MASK 0xff3084#define RG_AUDSPAREVA30_MASK_SFT (0xff << 0)3085#define RG_AUDSPAREVA18_SFT 83086#define RG_AUDSPAREVA18_MASK 0xff3087#define RG_AUDSPAREVA18_MASK_SFT (0xff << 8)3088 3089/* AUDENC_ANA_CON12 */3090#define RG_AUDPGA_DECAP_SFT 03091#define RG_AUDPGA_DECAP_MASK 0x13092#define RG_AUDPGA_DECAP_MASK_SFT (0x1 << 0)3093#define RG_AUDPGA_CAPRA_SFT 13094#define RG_AUDPGA_CAPRA_MASK 0x13095#define RG_AUDPGA_CAPRA_MASK_SFT (0x1 << 1)3096#define RG_AUDPGA_ACCCMP_SFT 23097#define RG_AUDPGA_ACCCMP_MASK 0x13098#define RG_AUDPGA_ACCCMP_MASK_SFT (0x1 << 2)3099#define RG_AUDENC_SPARE2_SFT 33100#define RG_AUDENC_SPARE2_MASK 0x1fff3101#define RG_AUDENC_SPARE2_MASK_SFT (0x1fff << 3)3102 3103/* AUDENC_ANA_CON13 */3104#define RG_AUDDIGMICEN_SFT 03105#define RG_AUDDIGMICEN_MASK 0x13106#define RG_AUDDIGMICEN_MASK_SFT (0x1 << 0)3107#define RG_AUDDIGMICBIAS_SFT 13108#define RG_AUDDIGMICBIAS_MASK 0x33109#define RG_AUDDIGMICBIAS_MASK_SFT (0x3 << 1)3110#define RG_DMICHPCLKEN_SFT 33111#define RG_DMICHPCLKEN_MASK 0x13112#define RG_DMICHPCLKEN_MASK_SFT (0x1 << 3)3113#define RG_AUDDIGMICPDUTY_SFT 43114#define RG_AUDDIGMICPDUTY_MASK 0x33115#define RG_AUDDIGMICPDUTY_MASK_SFT (0x3 << 4)3116#define RG_AUDDIGMICNDUTY_SFT 63117#define RG_AUDDIGMICNDUTY_MASK 0x33118#define RG_AUDDIGMICNDUTY_MASK_SFT (0x3 << 6)3119#define RG_DMICMONEN_SFT 83120#define RG_DMICMONEN_MASK 0x13121#define RG_DMICMONEN_MASK_SFT (0x1 << 8)3122#define RG_DMICMONSEL_SFT 93123#define RG_DMICMONSEL_MASK 0x73124#define RG_DMICMONSEL_MASK_SFT (0x7 << 9)3125 3126/* AUDENC_ANA_CON14 */3127#define RG_AUDDIGMIC1EN_SFT 03128#define RG_AUDDIGMIC1EN_MASK 0x13129#define RG_AUDDIGMIC1EN_MASK_SFT (0x1 << 0)3130#define RG_AUDDIGMICBIAS1_SFT 13131#define RG_AUDDIGMICBIAS1_MASK 0x33132#define RG_AUDDIGMICBIAS1_MASK_SFT (0x3 << 1)3133#define RG_DMIC1HPCLKEN_SFT 33134#define RG_DMIC1HPCLKEN_MASK 0x13135#define RG_DMIC1HPCLKEN_MASK_SFT (0x1 << 3)3136#define RG_AUDDIGMIC1PDUTY_SFT 43137#define RG_AUDDIGMIC1PDUTY_MASK 0x33138#define RG_AUDDIGMIC1PDUTY_MASK_SFT (0x3 << 4)3139#define RG_AUDDIGMIC1NDUTY_SFT 63140#define RG_AUDDIGMIC1NDUTY_MASK 0x33141#define RG_AUDDIGMIC1NDUTY_MASK_SFT (0x3 << 6)3142#define RG_DMIC1MONEN_SFT 83143#define RG_DMIC1MONEN_MASK 0x13144#define RG_DMIC1MONEN_MASK_SFT (0x1 << 8)3145#define RG_DMIC1MONSEL_SFT 93146#define RG_DMIC1MONSEL_MASK 0x73147#define RG_DMIC1MONSEL_MASK_SFT (0x7 << 9)3148#define RG_AUDSPAREVMIC_SFT 123149#define RG_AUDSPAREVMIC_MASK 0xf3150#define RG_AUDSPAREVMIC_MASK_SFT (0xf << 12)3151 3152/* AUDENC_ANA_CON15 */3153#define RG_AUDPWDBMICBIAS0_SFT 03154#define RG_AUDPWDBMICBIAS0_MASK 0x13155#define RG_AUDPWDBMICBIAS0_MASK_SFT (0x1 << 0)3156#define RG_AUDMICBIAS0BYPASSEN_SFT 13157#define RG_AUDMICBIAS0BYPASSEN_MASK 0x13158#define RG_AUDMICBIAS0BYPASSEN_MASK_SFT (0x1 << 1)3159#define RG_AUDMICBIAS0LOWPEN_SFT 23160#define RG_AUDMICBIAS0LOWPEN_MASK 0x13161#define RG_AUDMICBIAS0LOWPEN_MASK_SFT (0x1 << 2)3162#define RG_AUDPWDBMICBIAS3_SFT 33163#define RG_AUDPWDBMICBIAS3_MASK 0x13164#define RG_AUDPWDBMICBIAS3_MASK_SFT (0x1 << 3)3165#define RG_AUDMICBIAS0VREF_SFT 43166#define RG_AUDMICBIAS0VREF_MASK 0x73167#define RG_AUDMICBIAS0VREF_MASK_SFT (0x7 << 4)3168#define RG_AUDMICBIAS0DCSW0P1EN_SFT 83169#define RG_AUDMICBIAS0DCSW0P1EN_MASK 0x13170#define RG_AUDMICBIAS0DCSW0P1EN_MASK_SFT (0x1 << 8)3171#define RG_AUDMICBIAS0DCSW0P2EN_SFT 93172#define RG_AUDMICBIAS0DCSW0P2EN_MASK 0x13173#define RG_AUDMICBIAS0DCSW0P2EN_MASK_SFT (0x1 << 9)3174#define RG_AUDMICBIAS0DCSW0NEN_SFT 103175#define RG_AUDMICBIAS0DCSW0NEN_MASK 0x13176#define RG_AUDMICBIAS0DCSW0NEN_MASK_SFT (0x1 << 10)3177#define RG_AUDMICBIAS0DCSW2P1EN_SFT 123178#define RG_AUDMICBIAS0DCSW2P1EN_MASK 0x13179#define RG_AUDMICBIAS0DCSW2P1EN_MASK_SFT (0x1 << 12)3180#define RG_AUDMICBIAS0DCSW2P2EN_SFT 133181#define RG_AUDMICBIAS0DCSW2P2EN_MASK 0x13182#define RG_AUDMICBIAS0DCSW2P2EN_MASK_SFT (0x1 << 13)3183#define RG_AUDMICBIAS0DCSW2NEN_SFT 143184#define RG_AUDMICBIAS0DCSW2NEN_MASK 0x13185#define RG_AUDMICBIAS0DCSW2NEN_MASK_SFT (0x1 << 14)3186 3187/* AUDENC_ANA_CON16 */3188#define RG_AUDPWDBMICBIAS1_SFT 03189#define RG_AUDPWDBMICBIAS1_MASK 0x13190#define RG_AUDPWDBMICBIAS1_MASK_SFT (0x1 << 0)3191#define RG_AUDMICBIAS1BYPASSEN_SFT 13192#define RG_AUDMICBIAS1BYPASSEN_MASK 0x13193#define RG_AUDMICBIAS1BYPASSEN_MASK_SFT (0x1 << 1)3194#define RG_AUDMICBIAS1LOWPEN_SFT 23195#define RG_AUDMICBIAS1LOWPEN_MASK 0x13196#define RG_AUDMICBIAS1LOWPEN_MASK_SFT (0x1 << 2)3197#define RG_AUDMICBIAS1VREF_SFT 43198#define RG_AUDMICBIAS1VREF_MASK 0x73199#define RG_AUDMICBIAS1VREF_MASK_SFT (0x7 << 4)3200#define RG_AUDMICBIAS1DCSW1PEN_SFT 83201#define RG_AUDMICBIAS1DCSW1PEN_MASK 0x13202#define RG_AUDMICBIAS1DCSW1PEN_MASK_SFT (0x1 << 8)3203#define RG_AUDMICBIAS1DCSW1NEN_SFT 93204#define RG_AUDMICBIAS1DCSW1NEN_MASK 0x13205#define RG_AUDMICBIAS1DCSW1NEN_MASK_SFT (0x1 << 9)3206#define RG_BANDGAPGEN_SFT 103207#define RG_BANDGAPGEN_MASK 0x13208#define RG_BANDGAPGEN_MASK_SFT (0x1 << 10)3209#define RG_AUDMICBIAS1HVEN_SFT 123210#define RG_AUDMICBIAS1HVEN_MASK 0x13211#define RG_AUDMICBIAS1HVEN_MASK_SFT (0x1 << 12)3212#define RG_AUDMICBIAS1HVVREF_SFT 133213#define RG_AUDMICBIAS1HVVREF_MASK 0x13214#define RG_AUDMICBIAS1HVVREF_MASK_SFT (0x1 << 13)3215 3216/* AUDENC_ANA_CON17 */3217#define RG_AUDPWDBMICBIAS2_SFT 03218#define RG_AUDPWDBMICBIAS2_MASK 0x13219#define RG_AUDPWDBMICBIAS2_MASK_SFT (0x1 << 0)3220#define RG_AUDMICBIAS2BYPASSEN_SFT 13221#define RG_AUDMICBIAS2BYPASSEN_MASK 0x13222#define RG_AUDMICBIAS2BYPASSEN_MASK_SFT (0x1 << 1)3223#define RG_AUDMICBIAS2LOWPEN_SFT 23224#define RG_AUDMICBIAS2LOWPEN_MASK 0x13225#define RG_AUDMICBIAS2LOWPEN_MASK_SFT (0x1 << 2)3226#define RG_AUDMICBIAS2VREF_SFT 43227#define RG_AUDMICBIAS2VREF_MASK 0x73228#define RG_AUDMICBIAS2VREF_MASK_SFT (0x7 << 4)3229#define RG_AUDMICBIAS2DCSW3P1EN_SFT 83230#define RG_AUDMICBIAS2DCSW3P1EN_MASK 0x13231#define RG_AUDMICBIAS2DCSW3P1EN_MASK_SFT (0x1 << 8)3232#define RG_AUDMICBIAS2DCSW3P2EN_SFT 93233#define RG_AUDMICBIAS2DCSW3P2EN_MASK 0x13234#define RG_AUDMICBIAS2DCSW3P2EN_MASK_SFT (0x1 << 9)3235#define RG_AUDMICBIAS2DCSW3NEN_SFT 103236#define RG_AUDMICBIAS2DCSW3NEN_MASK 0x13237#define RG_AUDMICBIAS2DCSW3NEN_MASK_SFT (0x1 << 10)3238#define RG_AUDMICBIASSPARE_SFT 123239#define RG_AUDMICBIASSPARE_MASK 0xf3240#define RG_AUDMICBIASSPARE_MASK_SFT (0xf << 12)3241 3242/* AUDENC_ANA_CON18 */3243#define RG_AUDACCDETMICBIAS0PULLLOW_SFT 03244#define RG_AUDACCDETMICBIAS0PULLLOW_MASK 0x13245#define RG_AUDACCDETMICBIAS0PULLLOW_MASK_SFT (0x1 << 0)3246#define RG_AUDACCDETMICBIAS1PULLLOW_SFT 13247#define RG_AUDACCDETMICBIAS1PULLLOW_MASK 0x13248#define RG_AUDACCDETMICBIAS1PULLLOW_MASK_SFT (0x1 << 1)3249#define RG_AUDACCDETMICBIAS2PULLLOW_SFT 23250#define RG_AUDACCDETMICBIAS2PULLLOW_MASK 0x13251#define RG_AUDACCDETMICBIAS2PULLLOW_MASK_SFT (0x1 << 2)3252#define RG_AUDACCDETVIN1PULLLOW_SFT 33253#define RG_AUDACCDETVIN1PULLLOW_MASK 0x13254#define RG_AUDACCDETVIN1PULLLOW_MASK_SFT (0x1 << 3)3255#define RG_AUDACCDETVTHACAL_SFT 43256#define RG_AUDACCDETVTHACAL_MASK 0x13257#define RG_AUDACCDETVTHACAL_MASK_SFT (0x1 << 4)3258#define RG_AUDACCDETVTHBCAL_SFT 53259#define RG_AUDACCDETVTHBCAL_MASK 0x13260#define RG_AUDACCDETVTHBCAL_MASK_SFT (0x1 << 5)3261#define RG_AUDACCDETTVDET_SFT 63262#define RG_AUDACCDETTVDET_MASK 0x13263#define RG_AUDACCDETTVDET_MASK_SFT (0x1 << 6)3264#define RG_ACCDETSEL_SFT 73265#define RG_ACCDETSEL_MASK 0x13266#define RG_ACCDETSEL_MASK_SFT (0x1 << 7)3267#define RG_SWBUFMODSEL_SFT 83268#define RG_SWBUFMODSEL_MASK 0x13269#define RG_SWBUFMODSEL_MASK_SFT (0x1 << 8)3270#define RG_SWBUFSWEN_SFT 93271#define RG_SWBUFSWEN_MASK 0x13272#define RG_SWBUFSWEN_MASK_SFT (0x1 << 9)3273#define RG_EINT0NOHYS_SFT 103274#define RG_EINT0NOHYS_MASK 0x13275#define RG_EINT0NOHYS_MASK_SFT (0x1 << 10)3276#define RG_EINT0CONFIGACCDET_SFT 113277#define RG_EINT0CONFIGACCDET_MASK 0x13278#define RG_EINT0CONFIGACCDET_MASK_SFT (0x1 << 11)3279#define RG_EINT0HIRENB_SFT 123280#define RG_EINT0HIRENB_MASK 0x13281#define RG_EINT0HIRENB_MASK_SFT (0x1 << 12)3282#define RG_ACCDET2AUXRESBYPASS_SFT 133283#define RG_ACCDET2AUXRESBYPASS_MASK 0x13284#define RG_ACCDET2AUXRESBYPASS_MASK_SFT (0x1 << 13)3285#define RG_ACCDET2AUXSWEN_SFT 143286#define RG_ACCDET2AUXSWEN_MASK 0x13287#define RG_ACCDET2AUXSWEN_MASK_SFT (0x1 << 14)3288#define RG_AUDACCDETMICBIAS3PULLLOW_SFT 153289#define RG_AUDACCDETMICBIAS3PULLLOW_MASK 0x13290#define RG_AUDACCDETMICBIAS3PULLLOW_MASK_SFT (0x1 << 15)3291 3292/* AUDENC_ANA_CON19 */3293#define RG_EINT1CONFIGACCDET_SFT 03294#define RG_EINT1CONFIGACCDET_MASK 0x13295#define RG_EINT1CONFIGACCDET_MASK_SFT (0x1 << 0)3296#define RG_EINT1HIRENB_SFT 13297#define RG_EINT1HIRENB_MASK 0x13298#define RG_EINT1HIRENB_MASK_SFT (0x1 << 1)3299#define RG_EINT1NOHYS_SFT 23300#define RG_EINT1NOHYS_MASK 0x13301#define RG_EINT1NOHYS_MASK_SFT (0x1 << 2)3302#define RG_EINTCOMPVTH_SFT 43303#define RG_EINTCOMPVTH_MASK 0xf3304#define RG_EINTCOMPVTH_MASK_SFT (0xf << 4)3305#define RG_MTEST_EN_SFT 83306#define RG_MTEST_EN_MASK 0x13307#define RG_MTEST_EN_MASK_SFT (0x1 << 8)3308#define RG_MTEST_SEL_SFT 93309#define RG_MTEST_SEL_MASK 0x13310#define RG_MTEST_SEL_MASK_SFT (0x1 << 9)3311#define RG_MTEST_CURRENT_SFT 103312#define RG_MTEST_CURRENT_MASK 0x13313#define RG_MTEST_CURRENT_MASK_SFT (0x1 << 10)3314#define RG_ANALOGFDEN_SFT 123315#define RG_ANALOGFDEN_MASK 0x13316#define RG_ANALOGFDEN_MASK_SFT (0x1 << 12)3317#define RG_FDVIN1PPULLLOW_SFT 133318#define RG_FDVIN1PPULLLOW_MASK 0x13319#define RG_FDVIN1PPULLLOW_MASK_SFT (0x1 << 13)3320#define RG_FDEINT0TYPE_SFT 143321#define RG_FDEINT0TYPE_MASK 0x13322#define RG_FDEINT0TYPE_MASK_SFT (0x1 << 14)3323#define RG_FDEINT1TYPE_SFT 153324#define RG_FDEINT1TYPE_MASK 0x13325#define RG_FDEINT1TYPE_MASK_SFT (0x1 << 15)3326 3327/* AUDENC_ANA_CON20 */3328#define RG_EINT0CMPEN_SFT 03329#define RG_EINT0CMPEN_MASK 0x13330#define RG_EINT0CMPEN_MASK_SFT (0x1 << 0)3331#define RG_EINT0CMPMEN_SFT 13332#define RG_EINT0CMPMEN_MASK 0x13333#define RG_EINT0CMPMEN_MASK_SFT (0x1 << 1)3334#define RG_EINT0EN_SFT 23335#define RG_EINT0EN_MASK 0x13336#define RG_EINT0EN_MASK_SFT (0x1 << 2)3337#define RG_EINT0CEN_SFT 33338#define RG_EINT0CEN_MASK 0x13339#define RG_EINT0CEN_MASK_SFT (0x1 << 3)3340#define RG_EINT0INVEN_SFT 43341#define RG_EINT0INVEN_MASK 0x13342#define RG_EINT0INVEN_MASK_SFT (0x1 << 4)3343#define RG_EINT0CTURBO_SFT 53344#define RG_EINT0CTURBO_MASK 0x73345#define RG_EINT0CTURBO_MASK_SFT (0x7 << 5)3346#define RG_EINT1CMPEN_SFT 83347#define RG_EINT1CMPEN_MASK 0x13348#define RG_EINT1CMPEN_MASK_SFT (0x1 << 8)3349#define RG_EINT1CMPMEN_SFT 93350#define RG_EINT1CMPMEN_MASK 0x13351#define RG_EINT1CMPMEN_MASK_SFT (0x1 << 9)3352#define RG_EINT1EN_SFT 103353#define RG_EINT1EN_MASK 0x13354#define RG_EINT1EN_MASK_SFT (0x1 << 10)3355#define RG_EINT1CEN_SFT 113356#define RG_EINT1CEN_MASK 0x13357#define RG_EINT1CEN_MASK_SFT (0x1 << 11)3358#define RG_EINT1INVEN_SFT 123359#define RG_EINT1INVEN_MASK 0x13360#define RG_EINT1INVEN_MASK_SFT (0x1 << 12)3361#define RG_EINT1CTURBO_SFT 133362#define RG_EINT1CTURBO_MASK 0x73363#define RG_EINT1CTURBO_MASK_SFT (0x7 << 13)3364 3365/* AUDENC_ANA_CON21 */3366#define RG_ACCDETSPARE_SFT 03367#define RG_ACCDETSPARE_MASK 0xffff3368#define RG_ACCDETSPARE_MASK_SFT (0xffff << 0)3369 3370/* AUDENC_ANA_CON22 */3371#define RG_AUDENCSPAREVA30_SFT 03372#define RG_AUDENCSPAREVA30_MASK 0xff3373#define RG_AUDENCSPAREVA30_MASK_SFT (0xff << 0)3374#define RG_AUDENCSPAREVA18_SFT 83375#define RG_AUDENCSPAREVA18_MASK 0xff3376#define RG_AUDENCSPAREVA18_MASK_SFT (0xff << 8)3377 3378/* AUDENC_ANA_CON23 */3379#define RG_CLKSQ_EN_SFT 03380#define RG_CLKSQ_EN_MASK 0x13381#define RG_CLKSQ_EN_MASK_SFT (0x1 << 0)3382#define RG_CLKSQ_IN_SEL_TEST_SFT 13383#define RG_CLKSQ_IN_SEL_TEST_MASK 0x13384#define RG_CLKSQ_IN_SEL_TEST_MASK_SFT (0x1 << 1)3385#define RG_CM_REFGENSEL_SFT 23386#define RG_CM_REFGENSEL_MASK 0x13387#define RG_CM_REFGENSEL_MASK_SFT (0x1 << 2)3388#define RG_AUDIO_VOW_EN_SFT 33389#define RG_AUDIO_VOW_EN_MASK 0x13390#define RG_AUDIO_VOW_EN_MASK_SFT (0x1 << 3)3391#define RG_CLKSQ_EN_VOW_SFT 43392#define RG_CLKSQ_EN_VOW_MASK 0x13393#define RG_CLKSQ_EN_VOW_MASK_SFT (0x1 << 4)3394#define RG_CLKAND_EN_VOW_SFT 53395#define RG_CLKAND_EN_VOW_MASK 0x13396#define RG_CLKAND_EN_VOW_MASK_SFT (0x1 << 5)3397#define RG_VOWCLK_SEL_EN_VOW_SFT 63398#define RG_VOWCLK_SEL_EN_VOW_MASK 0x13399#define RG_VOWCLK_SEL_EN_VOW_MASK_SFT (0x1 << 6)3400#define RG_SPARE_VOW_SFT 73401#define RG_SPARE_VOW_MASK 0x73402#define RG_SPARE_VOW_MASK_SFT (0x7 << 7)3403 3404/* AUDDEC_ANA_CON0 */3405#define RG_AUDDACLPWRUP_VAUDP32_SFT 03406#define RG_AUDDACLPWRUP_VAUDP32_MASK 0x13407#define RG_AUDDACLPWRUP_VAUDP32_MASK_SFT (0x1 << 0)3408#define RG_AUDDACRPWRUP_VAUDP32_SFT 13409#define RG_AUDDACRPWRUP_VAUDP32_MASK 0x13410#define RG_AUDDACRPWRUP_VAUDP32_MASK_SFT (0x1 << 1)3411#define RG_AUD_DAC_PWR_UP_VA32_SFT 23412#define RG_AUD_DAC_PWR_UP_VA32_MASK 0x13413#define RG_AUD_DAC_PWR_UP_VA32_MASK_SFT (0x1 << 2)3414#define RG_AUD_DAC_PWL_UP_VA32_SFT 33415#define RG_AUD_DAC_PWL_UP_VA32_MASK 0x13416#define RG_AUD_DAC_PWL_UP_VA32_MASK_SFT (0x1 << 3)3417#define RG_AUDHPLPWRUP_VAUDP32_SFT 43418#define RG_AUDHPLPWRUP_VAUDP32_MASK 0x13419#define RG_AUDHPLPWRUP_VAUDP32_MASK_SFT (0x1 << 4)3420#define RG_AUDHPRPWRUP_VAUDP32_SFT 53421#define RG_AUDHPRPWRUP_VAUDP32_MASK 0x13422#define RG_AUDHPRPWRUP_VAUDP32_MASK_SFT (0x1 << 5)3423#define RG_AUDHPLPWRUP_IBIAS_VAUDP32_SFT 63424#define RG_AUDHPLPWRUP_IBIAS_VAUDP32_MASK 0x13425#define RG_AUDHPLPWRUP_IBIAS_VAUDP32_MASK_SFT (0x1 << 6)3426#define RG_AUDHPRPWRUP_IBIAS_VAUDP32_SFT 73427#define RG_AUDHPRPWRUP_IBIAS_VAUDP32_MASK 0x13428#define RG_AUDHPRPWRUP_IBIAS_VAUDP32_MASK_SFT (0x1 << 7)3429#define RG_AUDHPLMUXINPUTSEL_VAUDP32_SFT 83430#define RG_AUDHPLMUXINPUTSEL_VAUDP32_MASK 0x33431#define RG_AUDHPLMUXINPUTSEL_VAUDP32_MASK_SFT (0x3 << 8)3432#define RG_AUDHPRMUXINPUTSEL_VAUDP32_SFT 103433#define RG_AUDHPRMUXINPUTSEL_VAUDP32_MASK 0x33434#define RG_AUDHPRMUXINPUTSEL_VAUDP32_MASK_SFT (0x3 << 10)3435#define RG_AUDHPLSCDISABLE_VAUDP32_SFT 123436#define RG_AUDHPLSCDISABLE_VAUDP32_MASK 0x13437#define RG_AUDHPLSCDISABLE_VAUDP32_MASK_SFT (0x1 << 12)3438#define RG_AUDHPRSCDISABLE_VAUDP32_SFT 133439#define RG_AUDHPRSCDISABLE_VAUDP32_MASK 0x13440#define RG_AUDHPRSCDISABLE_VAUDP32_MASK_SFT (0x1 << 13)3441#define RG_AUDHPLBSCCURRENT_VAUDP32_SFT 143442#define RG_AUDHPLBSCCURRENT_VAUDP32_MASK 0x13443#define RG_AUDHPLBSCCURRENT_VAUDP32_MASK_SFT (0x1 << 14)3444#define RG_AUDHPRBSCCURRENT_VAUDP32_SFT 153445#define RG_AUDHPRBSCCURRENT_VAUDP32_MASK 0x13446#define RG_AUDHPRBSCCURRENT_VAUDP32_MASK_SFT (0x1 << 15)3447 3448/* AUDDEC_ANA_CON1 */3449#define RG_AUDHPLOUTPWRUP_VAUDP32_SFT 03450#define RG_AUDHPLOUTPWRUP_VAUDP32_MASK 0x13451#define RG_AUDHPLOUTPWRUP_VAUDP32_MASK_SFT (0x1 << 0)3452#define RG_AUDHPROUTPWRUP_VAUDP32_SFT 13453#define RG_AUDHPROUTPWRUP_VAUDP32_MASK 0x13454#define RG_AUDHPROUTPWRUP_VAUDP32_MASK_SFT (0x1 << 1)3455#define RG_AUDHPLOUTAUXPWRUP_VAUDP32_SFT 23456#define RG_AUDHPLOUTAUXPWRUP_VAUDP32_MASK 0x13457#define RG_AUDHPLOUTAUXPWRUP_VAUDP32_MASK_SFT (0x1 << 2)3458#define RG_AUDHPROUTAUXPWRUP_VAUDP32_SFT 33459#define RG_AUDHPROUTAUXPWRUP_VAUDP32_MASK 0x13460#define RG_AUDHPROUTAUXPWRUP_VAUDP32_MASK_SFT (0x1 << 3)3461#define RG_HPLAUXFBRSW_EN_VAUDP32_SFT 43462#define RG_HPLAUXFBRSW_EN_VAUDP32_MASK 0x13463#define RG_HPLAUXFBRSW_EN_VAUDP32_MASK_SFT (0x1 << 4)3464#define RG_HPRAUXFBRSW_EN_VAUDP32_SFT 53465#define RG_HPRAUXFBRSW_EN_VAUDP32_MASK 0x13466#define RG_HPRAUXFBRSW_EN_VAUDP32_MASK_SFT (0x1 << 5)3467#define RG_HPLSHORT2HPLAUX_EN_VAUDP32_SFT 63468#define RG_HPLSHORT2HPLAUX_EN_VAUDP32_MASK 0x13469#define RG_HPLSHORT2HPLAUX_EN_VAUDP32_MASK_SFT (0x1 << 6)3470#define RG_HPRSHORT2HPRAUX_EN_VAUDP32_SFT 73471#define RG_HPRSHORT2HPRAUX_EN_VAUDP32_MASK 0x13472#define RG_HPRSHORT2HPRAUX_EN_VAUDP32_MASK_SFT (0x1 << 7)3473#define RG_HPLOUTSTGCTRL_VAUDP32_SFT 83474#define RG_HPLOUTSTGCTRL_VAUDP32_MASK 0x73475#define RG_HPLOUTSTGCTRL_VAUDP32_MASK_SFT (0x7 << 8)3476#define RG_HPROUTSTGCTRL_VAUDP32_SFT 123477#define RG_HPROUTSTGCTRL_VAUDP32_MASK 0x73478#define RG_HPROUTSTGCTRL_VAUDP32_MASK_SFT (0x7 << 12)3479 3480/* AUDDEC_ANA_CON2 */3481#define RG_HPLOUTPUTSTBENH_VAUDP32_SFT 03482#define RG_HPLOUTPUTSTBENH_VAUDP32_MASK 0x73483#define RG_HPLOUTPUTSTBENH_VAUDP32_MASK_SFT (0x7 << 0)3484#define RG_HPROUTPUTSTBENH_VAUDP32_SFT 43485#define RG_HPROUTPUTSTBENH_VAUDP32_MASK 0x73486#define RG_HPROUTPUTSTBENH_VAUDP32_MASK_SFT (0x7 << 4)3487#define RG_AUDHPSTARTUP_VAUDP32_SFT 73488#define RG_AUDHPSTARTUP_VAUDP32_MASK 0x13489#define RG_AUDHPSTARTUP_VAUDP32_MASK_SFT (0x1 << 7)3490#define RG_AUDREFN_DERES_EN_VAUDP32_SFT 83491#define RG_AUDREFN_DERES_EN_VAUDP32_MASK 0x13492#define RG_AUDREFN_DERES_EN_VAUDP32_MASK_SFT (0x1 << 8)3493#define RG_HPINPUTSTBENH_VAUDP32_SFT 93494#define RG_HPINPUTSTBENH_VAUDP32_MASK 0x13495#define RG_HPINPUTSTBENH_VAUDP32_MASK_SFT (0x1 << 9)3496#define RG_HPINPUTRESET0_VAUDP32_SFT 103497#define RG_HPINPUTRESET0_VAUDP32_MASK 0x13498#define RG_HPINPUTRESET0_VAUDP32_MASK_SFT (0x1 << 10)3499#define RG_HPOUTPUTRESET0_VAUDP32_SFT 113500#define RG_HPOUTPUTRESET0_VAUDP32_MASK 0x13501#define RG_HPOUTPUTRESET0_VAUDP32_MASK_SFT (0x1 << 11)3502#define RG_HPPSHORT2VCM_VAUDP32_SFT 123503#define RG_HPPSHORT2VCM_VAUDP32_MASK 0x73504#define RG_HPPSHORT2VCM_VAUDP32_MASK_SFT (0x7 << 12)3505#define RG_AUDHPTRIM_EN_VAUDP32_SFT 153506#define RG_AUDHPTRIM_EN_VAUDP32_MASK 0x13507#define RG_AUDHPTRIM_EN_VAUDP32_MASK_SFT (0x1 << 15)3508 3509/* AUDDEC_ANA_CON3 */3510#define RG_AUDHPLTRIM_VAUDP32_SFT 03511#define RG_AUDHPLTRIM_VAUDP32_MASK 0x1f3512#define RG_AUDHPLTRIM_VAUDP32_MASK_SFT (0x1f << 0)3513#define RG_AUDHPLFINETRIM_VAUDP32_SFT 53514#define RG_AUDHPLFINETRIM_VAUDP32_MASK 0x73515#define RG_AUDHPLFINETRIM_VAUDP32_MASK_SFT (0x7 << 5)3516#define RG_AUDHPRTRIM_VAUDP32_SFT 83517#define RG_AUDHPRTRIM_VAUDP32_MASK 0x1f3518#define RG_AUDHPRTRIM_VAUDP32_MASK_SFT (0x1f << 8)3519#define RG_AUDHPRFINETRIM_VAUDP32_SFT 133520#define RG_AUDHPRFINETRIM_VAUDP32_MASK 0x73521#define RG_AUDHPRFINETRIM_VAUDP32_MASK_SFT (0x7 << 13)3522 3523/* AUDDEC_ANA_CON4 */3524#define RG_AUDHPDIFFINPBIASADJ_VAUDP32_SFT 03525#define RG_AUDHPDIFFINPBIASADJ_VAUDP32_MASK 0x73526#define RG_AUDHPDIFFINPBIASADJ_VAUDP32_MASK_SFT (0x7 << 0)3527#define RG_AUDHPLFCOMPRESSEL_VAUDP32_SFT 43528#define RG_AUDHPLFCOMPRESSEL_VAUDP32_MASK 0x73529#define RG_AUDHPLFCOMPRESSEL_VAUDP32_MASK_SFT (0x7 << 4)3530#define RG_AUDHPHFCOMPRESSEL_VAUDP32_SFT 83531#define RG_AUDHPHFCOMPRESSEL_VAUDP32_MASK 0x73532#define RG_AUDHPHFCOMPRESSEL_VAUDP32_MASK_SFT (0x7 << 8)3533#define RG_AUDHPHFCOMPBUFGAINSEL_VAUDP32_SFT 123534#define RG_AUDHPHFCOMPBUFGAINSEL_VAUDP32_MASK 0x33535#define RG_AUDHPHFCOMPBUFGAINSEL_VAUDP32_MASK_SFT (0x3 << 12)3536#define RG_AUDHPCOMP_EN_VAUDP32_SFT 153537#define RG_AUDHPCOMP_EN_VAUDP32_MASK 0x13538#define RG_AUDHPCOMP_EN_VAUDP32_MASK_SFT (0x1 << 15)3539 3540/* AUDDEC_ANA_CON5 */3541#define RG_AUDHPDECMGAINADJ_VAUDP32_SFT 03542#define RG_AUDHPDECMGAINADJ_VAUDP32_MASK 0x73543#define RG_AUDHPDECMGAINADJ_VAUDP32_MASK_SFT (0x7 << 0)3544#define RG_AUDHPDEDMGAINADJ_VAUDP32_SFT 43545#define RG_AUDHPDEDMGAINADJ_VAUDP32_MASK 0x73546#define RG_AUDHPDEDMGAINADJ_VAUDP32_MASK_SFT (0x7 << 4)3547 3548/* AUDDEC_ANA_CON6 */3549#define RG_AUDHSPWRUP_VAUDP32_SFT 03550#define RG_AUDHSPWRUP_VAUDP32_MASK 0x13551#define RG_AUDHSPWRUP_VAUDP32_MASK_SFT (0x1 << 0)3552#define RG_AUDHSPWRUP_IBIAS_VAUDP32_SFT 13553#define RG_AUDHSPWRUP_IBIAS_VAUDP32_MASK 0x13554#define RG_AUDHSPWRUP_IBIAS_VAUDP32_MASK_SFT (0x1 << 1)3555#define RG_AUDHSMUXINPUTSEL_VAUDP32_SFT 23556#define RG_AUDHSMUXINPUTSEL_VAUDP32_MASK 0x33557#define RG_AUDHSMUXINPUTSEL_VAUDP32_MASK_SFT (0x3 << 2)3558#define RG_AUDHSSCDISABLE_VAUDP32_SFT 43559#define RG_AUDHSSCDISABLE_VAUDP32_MASK 0x13560#define RG_AUDHSSCDISABLE_VAUDP32_MASK_SFT (0x1 << 4)3561#define RG_AUDHSBSCCURRENT_VAUDP32_SFT 53562#define RG_AUDHSBSCCURRENT_VAUDP32_MASK 0x13563#define RG_AUDHSBSCCURRENT_VAUDP32_MASK_SFT (0x1 << 5)3564#define RG_AUDHSSTARTUP_VAUDP32_SFT 63565#define RG_AUDHSSTARTUP_VAUDP32_MASK 0x13566#define RG_AUDHSSTARTUP_VAUDP32_MASK_SFT (0x1 << 6)3567#define RG_HSOUTPUTSTBENH_VAUDP32_SFT 73568#define RG_HSOUTPUTSTBENH_VAUDP32_MASK 0x13569#define RG_HSOUTPUTSTBENH_VAUDP32_MASK_SFT (0x1 << 7)3570#define RG_HSINPUTSTBENH_VAUDP32_SFT 83571#define RG_HSINPUTSTBENH_VAUDP32_MASK 0x13572#define RG_HSINPUTSTBENH_VAUDP32_MASK_SFT (0x1 << 8)3573#define RG_HSINPUTRESET0_VAUDP32_SFT 93574#define RG_HSINPUTRESET0_VAUDP32_MASK 0x13575#define RG_HSINPUTRESET0_VAUDP32_MASK_SFT (0x1 << 9)3576#define RG_HSOUTPUTRESET0_VAUDP32_SFT 103577#define RG_HSOUTPUTRESET0_VAUDP32_MASK 0x13578#define RG_HSOUTPUTRESET0_VAUDP32_MASK_SFT (0x1 << 10)3579#define RG_HSOUT_SHORTVCM_VAUDP32_SFT 113580#define RG_HSOUT_SHORTVCM_VAUDP32_MASK 0x13581#define RG_HSOUT_SHORTVCM_VAUDP32_MASK_SFT (0x1 << 11)3582 3583/* AUDDEC_ANA_CON7 */3584#define RG_AUDLOLPWRUP_VAUDP32_SFT 03585#define RG_AUDLOLPWRUP_VAUDP32_MASK 0x13586#define RG_AUDLOLPWRUP_VAUDP32_MASK_SFT (0x1 << 0)3587#define RG_AUDLOLPWRUP_IBIAS_VAUDP32_SFT 13588#define RG_AUDLOLPWRUP_IBIAS_VAUDP32_MASK 0x13589#define RG_AUDLOLPWRUP_IBIAS_VAUDP32_MASK_SFT (0x1 << 1)3590#define RG_AUDLOLMUXINPUTSEL_VAUDP32_SFT 23591#define RG_AUDLOLMUXINPUTSEL_VAUDP32_MASK 0x33592#define RG_AUDLOLMUXINPUTSEL_VAUDP32_MASK_SFT (0x3 << 2)3593#define RG_AUDLOLSCDISABLE_VAUDP32_SFT 43594#define RG_AUDLOLSCDISABLE_VAUDP32_MASK 0x13595#define RG_AUDLOLSCDISABLE_VAUDP32_MASK_SFT (0x1 << 4)3596#define RG_AUDLOLBSCCURRENT_VAUDP32_SFT 53597#define RG_AUDLOLBSCCURRENT_VAUDP32_MASK 0x13598#define RG_AUDLOLBSCCURRENT_VAUDP32_MASK_SFT (0x1 << 5)3599#define RG_AUDLOSTARTUP_VAUDP32_SFT 63600#define RG_AUDLOSTARTUP_VAUDP32_MASK 0x13601#define RG_AUDLOSTARTUP_VAUDP32_MASK_SFT (0x1 << 6)3602#define RG_LOINPUTSTBENH_VAUDP32_SFT 73603#define RG_LOINPUTSTBENH_VAUDP32_MASK 0x13604#define RG_LOINPUTSTBENH_VAUDP32_MASK_SFT (0x1 << 7)3605#define RG_LOOUTPUTSTBENH_VAUDP32_SFT 83606#define RG_LOOUTPUTSTBENH_VAUDP32_MASK 0x13607#define RG_LOOUTPUTSTBENH_VAUDP32_MASK_SFT (0x1 << 8)3608#define RG_LOINPUTRESET0_VAUDP32_SFT 93609#define RG_LOINPUTRESET0_VAUDP32_MASK 0x13610#define RG_LOINPUTRESET0_VAUDP32_MASK_SFT (0x1 << 9)3611#define RG_LOOUTPUTRESET0_VAUDP32_SFT 103612#define RG_LOOUTPUTRESET0_VAUDP32_MASK 0x13613#define RG_LOOUTPUTRESET0_VAUDP32_MASK_SFT (0x1 << 10)3614#define RG_LOOUT_SHORTVCM_VAUDP32_SFT 113615#define RG_LOOUT_SHORTVCM_VAUDP32_MASK 0x13616#define RG_LOOUT_SHORTVCM_VAUDP32_MASK_SFT (0x1 << 11)3617#define RG_AUDDACTPWRUP_VAUDP32_SFT 123618#define RG_AUDDACTPWRUP_VAUDP32_MASK 0x13619#define RG_AUDDACTPWRUP_VAUDP32_MASK_SFT (0x1 << 12)3620#define RG_AUD_DAC_PWT_UP_VA32_SFT 133621#define RG_AUD_DAC_PWT_UP_VA32_MASK 0x13622#define RG_AUD_DAC_PWT_UP_VA32_MASK_SFT (0x1 << 13)3623 3624/* AUDDEC_ANA_CON8 */3625#define RG_AUDTRIMBUF_INPUTMUXSEL_VAUDP32_SFT 03626#define RG_AUDTRIMBUF_INPUTMUXSEL_VAUDP32_MASK 0xf3627#define RG_AUDTRIMBUF_INPUTMUXSEL_VAUDP32_MASK_SFT (0xf << 0)3628#define RG_AUDTRIMBUF_GAINSEL_VAUDP32_SFT 43629#define RG_AUDTRIMBUF_GAINSEL_VAUDP32_MASK 0x33630#define RG_AUDTRIMBUF_GAINSEL_VAUDP32_MASK_SFT (0x3 << 4)3631#define RG_AUDTRIMBUF_EN_VAUDP32_SFT 63632#define RG_AUDTRIMBUF_EN_VAUDP32_MASK 0x13633#define RG_AUDTRIMBUF_EN_VAUDP32_MASK_SFT (0x1 << 6)3634#define RG_AUDHPSPKDET_INPUTMUXSEL_VAUDP32_SFT 83635#define RG_AUDHPSPKDET_INPUTMUXSEL_VAUDP32_MASK 0x33636#define RG_AUDHPSPKDET_INPUTMUXSEL_VAUDP32_MASK_SFT (0x3 << 8)3637#define RG_AUDHPSPKDET_OUTPUTMUXSEL_VAUDP32_SFT 103638#define RG_AUDHPSPKDET_OUTPUTMUXSEL_VAUDP32_MASK 0x33639#define RG_AUDHPSPKDET_OUTPUTMUXSEL_VAUDP32_MASK_SFT (0x3 << 10)3640#define RG_AUDHPSPKDET_EN_VAUDP32_SFT 123641#define RG_AUDHPSPKDET_EN_VAUDP32_MASK 0x13642#define RG_AUDHPSPKDET_EN_VAUDP32_MASK_SFT (0x1 << 12)3643 3644/* AUDDEC_ANA_CON9 */3645#define RG_ABIDEC_RSVD0_VA32_SFT 03646#define RG_ABIDEC_RSVD0_VA32_MASK 0xff3647#define RG_ABIDEC_RSVD0_VA32_MASK_SFT (0xff << 0)3648#define RG_ABIDEC_RSVD0_VAUDP32_SFT 83649#define RG_ABIDEC_RSVD0_VAUDP32_MASK 0xff3650#define RG_ABIDEC_RSVD0_VAUDP32_MASK_SFT (0xff << 8)3651 3652/* AUDDEC_ANA_CON10 */3653#define RG_ABIDEC_RSVD1_VAUDP32_SFT 03654#define RG_ABIDEC_RSVD1_VAUDP32_MASK 0xff3655#define RG_ABIDEC_RSVD1_VAUDP32_MASK_SFT (0xff << 0)3656#define RG_ABIDEC_RSVD2_VAUDP32_SFT 83657#define RG_ABIDEC_RSVD2_VAUDP32_MASK 0xff3658#define RG_ABIDEC_RSVD2_VAUDP32_MASK_SFT (0xff << 8)3659 3660/* AUDDEC_ANA_CON11 */3661#define RG_AUDZCDMUXSEL_VAUDP32_SFT 03662#define RG_AUDZCDMUXSEL_VAUDP32_MASK 0x73663#define RG_AUDZCDMUXSEL_VAUDP32_MASK_SFT (0x7 << 0)3664#define RG_AUDZCDCLKSEL_VAUDP32_SFT 33665#define RG_AUDZCDCLKSEL_VAUDP32_MASK 0x13666#define RG_AUDZCDCLKSEL_VAUDP32_MASK_SFT (0x1 << 3)3667#define RG_AUDBIASADJ_0_VAUDP32_SFT 73668#define RG_AUDBIASADJ_0_VAUDP32_MASK 0x1ff3669#define RG_AUDBIASADJ_0_VAUDP32_MASK_SFT (0x1ff << 7)3670 3671/* AUDDEC_ANA_CON12 */3672#define RG_AUDBIASADJ_1_VAUDP32_SFT 03673#define RG_AUDBIASADJ_1_VAUDP32_MASK 0xff3674#define RG_AUDBIASADJ_1_VAUDP32_MASK_SFT (0xff << 0)3675#define RG_AUDIBIASPWRDN_VAUDP32_SFT 83676#define RG_AUDIBIASPWRDN_VAUDP32_MASK 0x13677#define RG_AUDIBIASPWRDN_VAUDP32_MASK_SFT (0x1 << 8)3678 3679/* AUDDEC_ANA_CON13 */3680#define RG_RSTB_DECODER_VA32_SFT 03681#define RG_RSTB_DECODER_VA32_MASK 0x13682#define RG_RSTB_DECODER_VA32_MASK_SFT (0x1 << 0)3683#define RG_SEL_DECODER_96K_VA32_SFT 13684#define RG_SEL_DECODER_96K_VA32_MASK 0x13685#define RG_SEL_DECODER_96K_VA32_MASK_SFT (0x1 << 1)3686#define RG_SEL_DELAY_VCORE_SFT 23687#define RG_SEL_DELAY_VCORE_MASK 0x13688#define RG_SEL_DELAY_VCORE_MASK_SFT (0x1 << 2)3689#define RG_AUDGLB_PWRDN_VA32_SFT 43690#define RG_AUDGLB_PWRDN_VA32_MASK 0x13691#define RG_AUDGLB_PWRDN_VA32_MASK_SFT (0x1 << 4)3692#define RG_AUDGLB_LP_VOW_EN_VA32_SFT 53693#define RG_AUDGLB_LP_VOW_EN_VA32_MASK 0x13694#define RG_AUDGLB_LP_VOW_EN_VA32_MASK_SFT (0x1 << 5)3695#define RG_AUDGLB_LP2_VOW_EN_VA32_SFT 63696#define RG_AUDGLB_LP2_VOW_EN_VA32_MASK 0x13697#define RG_AUDGLB_LP2_VOW_EN_VA32_MASK_SFT (0x1 << 6)3698 3699/* AUDDEC_ANA_CON14 */3700#define RG_LCLDO_DEC_EN_VA32_SFT 03701#define RG_LCLDO_DEC_EN_VA32_MASK 0x13702#define RG_LCLDO_DEC_EN_VA32_MASK_SFT (0x1 << 0)3703#define RG_LCLDO_DEC_PDDIS_EN_VA18_SFT 13704#define RG_LCLDO_DEC_PDDIS_EN_VA18_MASK 0x13705#define RG_LCLDO_DEC_PDDIS_EN_VA18_MASK_SFT (0x1 << 1)3706#define RG_LCLDO_DEC_REMOTE_SENSE_VA18_SFT 23707#define RG_LCLDO_DEC_REMOTE_SENSE_VA18_MASK 0x13708#define RG_LCLDO_DEC_REMOTE_SENSE_VA18_MASK_SFT (0x1 << 2)3709#define RG_NVREG_EN_VAUDP32_SFT 43710#define RG_NVREG_EN_VAUDP32_MASK 0x13711#define RG_NVREG_EN_VAUDP32_MASK_SFT (0x1 << 4)3712#define RG_NVREG_PULL0V_VAUDP32_SFT 53713#define RG_NVREG_PULL0V_VAUDP32_MASK 0x13714#define RG_NVREG_PULL0V_VAUDP32_MASK_SFT (0x1 << 5)3715#define RG_AUDPMU_RSVD_VA18_SFT 83716#define RG_AUDPMU_RSVD_VA18_MASK 0xff3717#define RG_AUDPMU_RSVD_VA18_MASK_SFT (0xff << 8)3718 3719/* MT6359_ZCD_CON0 */3720#define RG_AUDZCDENABLE_SFT 03721#define RG_AUDZCDENABLE_MASK 0x13722#define RG_AUDZCDENABLE_MASK_SFT (0x1 << 0)3723#define RG_AUDZCDGAINSTEPTIME_SFT 13724#define RG_AUDZCDGAINSTEPTIME_MASK 0x73725#define RG_AUDZCDGAINSTEPTIME_MASK_SFT (0x7 << 1)3726#define RG_AUDZCDGAINSTEPSIZE_SFT 43727#define RG_AUDZCDGAINSTEPSIZE_MASK 0x33728#define RG_AUDZCDGAINSTEPSIZE_MASK_SFT (0x3 << 4)3729#define RG_AUDZCDTIMEOUTMODESEL_SFT 63730#define RG_AUDZCDTIMEOUTMODESEL_MASK 0x13731#define RG_AUDZCDTIMEOUTMODESEL_MASK_SFT (0x1 << 6)3732 3733/* MT6359_ZCD_CON1 */3734#define RG_AUDLOLGAIN_SFT 03735#define RG_AUDLOLGAIN_MASK 0x1f3736#define RG_AUDLOLGAIN_MASK_SFT (0x1f << 0)3737#define RG_AUDLORGAIN_SFT 73738#define RG_AUDLORGAIN_MASK 0x1f3739#define RG_AUDLORGAIN_MASK_SFT (0x1f << 7)3740 3741/* MT6359_ZCD_CON2 */3742#define RG_AUDHPLGAIN_SFT 03743#define RG_AUDHPLGAIN_MASK 0x1f3744#define RG_AUDHPLGAIN_MASK_SFT (0x1f << 0)3745#define RG_AUDHPRGAIN_SFT 73746#define RG_AUDHPRGAIN_MASK 0x1f3747#define RG_AUDHPRGAIN_MASK_SFT (0x1f << 7)3748 3749/* MT6359_ZCD_CON3 */3750#define RG_AUDHSGAIN_SFT 03751#define RG_AUDHSGAIN_MASK 0x1f3752#define RG_AUDHSGAIN_MASK_SFT (0x1f << 0)3753 3754/* MT6359_ZCD_CON4 */3755#define RG_AUDIVLGAIN_SFT 03756#define RG_AUDIVLGAIN_MASK 0x73757#define RG_AUDIVLGAIN_MASK_SFT (0x7 << 0)3758#define RG_AUDIVRGAIN_SFT 83759#define RG_AUDIVRGAIN_MASK 0x73760#define RG_AUDIVRGAIN_MASK_SFT (0x7 << 8)3761 3762/* MT6359_ZCD_CON5 */3763#define RG_AUDINTGAIN1_SFT 03764#define RG_AUDINTGAIN1_MASK 0x3f3765#define RG_AUDINTGAIN1_MASK_SFT (0x3f << 0)3766#define RG_AUDINTGAIN2_SFT 83767#define RG_AUDINTGAIN2_MASK 0x3f3768#define RG_AUDINTGAIN2_MASK_SFT (0x3f << 8)3769 3770/* audio register */3771#define MT6359_GPIO_DIR0 0x883772#define MT6359_GPIO_DIR0_SET 0x8a3773#define MT6359_GPIO_DIR0_CLR 0x8c3774#define MT6359_GPIO_DIR1 0x8e3775#define MT6359_GPIO_DIR1_SET 0x903776#define MT6359_GPIO_DIR1_CLR 0x923777 3778#define MT6359_DCXO_CW11 0x7a63779#define MT6359_DCXO_CW12 0x7a83780 3781#define MT6359_GPIO_MODE0 0xcc3782#define MT6359_GPIO_MODE0_SET 0xce3783#define MT6359_GPIO_MODE0_CLR 0xd03784#define MT6359_GPIO_MODE1 0xd23785#define MT6359_GPIO_MODE1_SET 0xd43786#define MT6359_GPIO_MODE1_CLR 0xd63787#define MT6359_GPIO_MODE2 0xd83788#define MT6359_GPIO_MODE2_SET 0xda3789#define MT6359_GPIO_MODE2_CLR 0xdc3790#define MT6359_GPIO_MODE3 0xde3791#define MT6359_GPIO_MODE3_SET 0xe03792#define MT6359_GPIO_MODE3_CLR 0xe23793#define MT6359_GPIO_MODE4 0xe43794#define MT6359_GPIO_MODE4_SET 0xe63795#define MT6359_GPIO_MODE4_CLR 0xe83796 3797#define MT6359_AUD_TOP_ID 0x23003798#define MT6359_AUD_TOP_REV0 0x23023799#define MT6359_AUD_TOP_DBI 0x23043800#define MT6359_AUD_TOP_DXI 0x23063801#define MT6359_AUD_TOP_CKPDN_TPM0 0x23083802#define MT6359_AUD_TOP_CKPDN_TPM1 0x230a3803#define MT6359_AUD_TOP_CKPDN_CON0 0x230c3804#define MT6359_AUD_TOP_CKPDN_CON0_SET 0x230e3805#define MT6359_AUD_TOP_CKPDN_CON0_CLR 0x23103806#define MT6359_AUD_TOP_CKSEL_CON0 0x23123807#define MT6359_AUD_TOP_CKSEL_CON0_SET 0x23143808#define MT6359_AUD_TOP_CKSEL_CON0_CLR 0x23163809#define MT6359_AUD_TOP_CKTST_CON0 0x23183810#define MT6359_AUD_TOP_CLK_HWEN_CON0 0x231a3811#define MT6359_AUD_TOP_CLK_HWEN_CON0_SET 0x231c3812#define MT6359_AUD_TOP_CLK_HWEN_CON0_CLR 0x231e3813#define MT6359_AUD_TOP_RST_CON0 0x23203814#define MT6359_AUD_TOP_RST_CON0_SET 0x23223815#define MT6359_AUD_TOP_RST_CON0_CLR 0x23243816#define MT6359_AUD_TOP_RST_BANK_CON0 0x23263817#define MT6359_AUD_TOP_INT_CON0 0x23283818#define MT6359_AUD_TOP_INT_CON0_SET 0x232a3819#define MT6359_AUD_TOP_INT_CON0_CLR 0x232c3820#define MT6359_AUD_TOP_INT_MASK_CON0 0x232e3821#define MT6359_AUD_TOP_INT_MASK_CON0_SET 0x23303822#define MT6359_AUD_TOP_INT_MASK_CON0_CLR 0x23323823#define MT6359_AUD_TOP_INT_STATUS0 0x23343824#define MT6359_AUD_TOP_INT_RAW_STATUS0 0x23363825#define MT6359_AUD_TOP_INT_MISC_CON0 0x23383826#define MT6359_AUD_TOP_MON_CON0 0x233a3827#define MT6359_AUDIO_DIG_DSN_ID 0x23803828#define MT6359_AUDIO_DIG_DSN_REV0 0x23823829#define MT6359_AUDIO_DIG_DSN_DBI 0x23843830#define MT6359_AUDIO_DIG_DSN_DXI 0x23863831#define MT6359_AFE_UL_DL_CON0 0x23883832#define MT6359_AFE_DL_SRC2_CON0_L 0x238a3833#define MT6359_AFE_UL_SRC_CON0_H 0x238c3834#define MT6359_AFE_UL_SRC_CON0_L 0x238e3835#define MT6359_AFE_ADDA6_L_SRC_CON0_H 0x23903836#define MT6359_AFE_ADDA6_UL_SRC_CON0_L 0x23923837#define MT6359_AFE_TOP_CON0 0x23943838#define MT6359_AUDIO_TOP_CON0 0x23963839#define MT6359_AFE_MON_DEBUG0 0x23983840#define MT6359_AFUNC_AUD_CON0 0x239a3841#define MT6359_AFUNC_AUD_CON1 0x239c3842#define MT6359_AFUNC_AUD_CON2 0x239e3843#define MT6359_AFUNC_AUD_CON3 0x23a03844#define MT6359_AFUNC_AUD_CON4 0x23a23845#define MT6359_AFUNC_AUD_CON5 0x23a43846#define MT6359_AFUNC_AUD_CON6 0x23a63847#define MT6359_AFUNC_AUD_CON7 0x23a83848#define MT6359_AFUNC_AUD_CON8 0x23aa3849#define MT6359_AFUNC_AUD_CON9 0x23ac3850#define MT6359_AFUNC_AUD_CON10 0x23ae3851#define MT6359_AFUNC_AUD_CON11 0x23b03852#define MT6359_AFUNC_AUD_CON12 0x23b23853#define MT6359_AFUNC_AUD_MON0 0x23b43854#define MT6359_AFUNC_AUD_MON1 0x23b63855#define MT6359_AUDRC_TUNE_MON0 0x23b83856#define MT6359_AFE_ADDA_MTKAIF_FIFO_CFG0 0x23ba3857#define MT6359_AFE_ADDA_MTKAIF_FIFO_LOG_MON1 0x23bc3858#define MT6359_AFE_ADDA_MTKAIF_MON0 0x23be3859#define MT6359_AFE_ADDA_MTKAIF_MON1 0x23c03860#define MT6359_AFE_ADDA_MTKAIF_MON2 0x23c23861#define MT6359_AFE_ADDA6_MTKAIF_MON3 0x23c43862#define MT6359_AFE_ADDA_MTKAIF_MON4 0x23c63863#define MT6359_AFE_ADDA_MTKAIF_MON5 0x23c83864#define MT6359_AFE_ADDA_MTKAIF_CFG0 0x23ca3865#define MT6359_AFE_ADDA_MTKAIF_RX_CFG0 0x23cc3866#define MT6359_AFE_ADDA_MTKAIF_RX_CFG1 0x23ce3867#define MT6359_AFE_ADDA_MTKAIF_RX_CFG2 0x23d03868#define MT6359_AFE_ADDA_MTKAIF_RX_CFG3 0x23d23869#define MT6359_AFE_ADDA_MTKAIF_SYNCWORD_CFG0 0x23d43870#define MT6359_AFE_ADDA_MTKAIF_SYNCWORD_CFG1 0x23d63871#define MT6359_AFE_SGEN_CFG0 0x23d83872#define MT6359_AFE_SGEN_CFG1 0x23da3873#define MT6359_AFE_ADC_ASYNC_FIFO_CFG 0x23dc3874#define MT6359_AFE_ADC_ASYNC_FIFO_CFG1 0x23de3875#define MT6359_AFE_DCCLK_CFG0 0x23e03876#define MT6359_AFE_DCCLK_CFG1 0x23e23877#define MT6359_AUDIO_DIG_CFG 0x23e43878#define MT6359_AUDIO_DIG_CFG1 0x23e63879#define MT6359_AFE_AUD_PAD_TOP 0x23e83880#define MT6359_AFE_AUD_PAD_TOP_MON 0x23ea3881#define MT6359_AFE_AUD_PAD_TOP_MON1 0x23ec3882#define MT6359_AFE_AUD_PAD_TOP_MON2 0x23ee3883#define MT6359_AFE_DL_NLE_CFG 0x23f03884#define MT6359_AFE_DL_NLE_MON 0x23f23885#define MT6359_AFE_CG_EN_MON 0x23f43886#define MT6359_AFE_MIC_ARRAY_CFG 0x23f63887#define MT6359_AFE_CHOP_CFG0 0x23f83888#define MT6359_AFE_MTKAIF_MUX_CFG 0x23fa3889#define MT6359_AUDIO_DIG_2ND_DSN_ID 0x24003890#define MT6359_AUDIO_DIG_2ND_DSN_REV0 0x24023891#define MT6359_AUDIO_DIG_2ND_DSN_DBI 0x24043892#define MT6359_AUDIO_DIG_2ND_DSN_DXI 0x24063893#define MT6359_AFE_PMIC_NEWIF_CFG3 0x24083894#define MT6359_AUDIO_DIG_3RD_DSN_ID 0x24803895#define MT6359_AUDIO_DIG_3RD_DSN_REV0 0x24823896#define MT6359_AUDIO_DIG_3RD_DSN_DBI 0x24843897#define MT6359_AUDIO_DIG_3RD_DSN_DXI 0x24863898#define MT6359_AFE_NCP_CFG0 0x24de3899#define MT6359_AFE_NCP_CFG1 0x24e03900#define MT6359_AFE_NCP_CFG2 0x24e23901#define MT6359_AUDENC_DSN_ID 0x25003902#define MT6359_AUDENC_DSN_REV0 0x25023903#define MT6359_AUDENC_DSN_DBI 0x25043904#define MT6359_AUDENC_DSN_FPI 0x25063905#define MT6359_AUDENC_ANA_CON0 0x25083906#define MT6359_AUDENC_ANA_CON1 0x250a3907#define MT6359_AUDENC_ANA_CON2 0x250c3908#define MT6359_AUDENC_ANA_CON3 0x250e3909#define MT6359_AUDENC_ANA_CON4 0x25103910#define MT6359_AUDENC_ANA_CON5 0x25123911#define MT6359_AUDENC_ANA_CON6 0x25143912#define MT6359_AUDENC_ANA_CON7 0x25163913#define MT6359_AUDENC_ANA_CON8 0x25183914#define MT6359_AUDENC_ANA_CON9 0x251a3915#define MT6359_AUDENC_ANA_CON10 0x251c3916#define MT6359_AUDENC_ANA_CON11 0x251e3917#define MT6359_AUDENC_ANA_CON12 0x25203918#define MT6359_AUDENC_ANA_CON13 0x25223919#define MT6359_AUDENC_ANA_CON14 0x25243920#define MT6359_AUDENC_ANA_CON15 0x25263921#define MT6359_AUDENC_ANA_CON16 0x25283922#define MT6359_AUDENC_ANA_CON17 0x252a3923#define MT6359_AUDENC_ANA_CON18 0x252c3924#define MT6359_AUDENC_ANA_CON19 0x252e3925#define MT6359_AUDENC_ANA_CON20 0x25303926#define MT6359_AUDENC_ANA_CON21 0x25323927#define MT6359_AUDENC_ANA_CON22 0x25343928#define MT6359_AUDENC_ANA_CON23 0x25363929#define MT6359_AUDDEC_DSN_ID 0x25803930#define MT6359_AUDDEC_DSN_REV0 0x25823931#define MT6359_AUDDEC_DSN_DBI 0x25843932#define MT6359_AUDDEC_DSN_FPI 0x25863933#define MT6359_AUDDEC_ANA_CON0 0x25883934#define MT6359_AUDDEC_ANA_CON1 0x258a3935#define MT6359_AUDDEC_ANA_CON2 0x258c3936#define MT6359_AUDDEC_ANA_CON3 0x258e3937#define MT6359_AUDDEC_ANA_CON4 0x25903938#define MT6359_AUDDEC_ANA_CON5 0x25923939#define MT6359_AUDDEC_ANA_CON6 0x25943940#define MT6359_AUDDEC_ANA_CON7 0x25963941#define MT6359_AUDDEC_ANA_CON8 0x25983942#define MT6359_AUDDEC_ANA_CON9 0x259a3943#define MT6359_AUDDEC_ANA_CON10 0x259c3944#define MT6359_AUDDEC_ANA_CON11 0x259e3945#define MT6359_AUDDEC_ANA_CON12 0x25a03946#define MT6359_AUDDEC_ANA_CON13 0x25a23947#define MT6359_AUDDEC_ANA_CON14 0x25a43948#define MT6359_AUDZCD_DSN_ID 0x26003949#define MT6359_AUDZCD_DSN_REV0 0x26023950#define MT6359_AUDZCD_DSN_DBI 0x26043951#define MT6359_AUDZCD_DSN_FPI 0x26063952#define MT6359_ZCD_CON0 0x26083953#define MT6359_ZCD_CON1 0x260a3954#define MT6359_ZCD_CON2 0x260c3955#define MT6359_ZCD_CON3 0x260e3956#define MT6359_ZCD_CON4 0x26103957#define MT6359_ZCD_CON5 0x26123958#define MT6359_ACCDET_DSN_DIG_ID 0x26803959#define MT6359_ACCDET_DSN_DIG_REV0 0x26823960#define MT6359_ACCDET_DSN_DBI 0x26843961#define MT6359_ACCDET_DSN_FPI 0x26863962#define MT6359_ACCDET_CON0 0x26883963#define MT6359_ACCDET_CON1 0x268a3964#define MT6359_ACCDET_CON2 0x268c3965#define MT6359_ACCDET_CON3 0x268e3966#define MT6359_ACCDET_CON4 0x26903967#define MT6359_ACCDET_CON5 0x26923968#define MT6359_ACCDET_CON6 0x26943969#define MT6359_ACCDET_CON7 0x26963970#define MT6359_ACCDET_CON8 0x26983971#define MT6359_ACCDET_CON9 0x269a3972#define MT6359_ACCDET_CON10 0x269c3973#define MT6359_ACCDET_CON11 0x269e3974#define MT6359_ACCDET_CON12 0x26a03975#define MT6359_ACCDET_CON13 0x26a23976#define MT6359_ACCDET_CON14 0x26a43977#define MT6359_ACCDET_CON15 0x26a63978#define MT6359_ACCDET_CON16 0x26a83979#define MT6359_ACCDET_CON17 0x26aa3980#define MT6359_ACCDET_CON18 0x26ac3981#define MT6359_ACCDET_CON19 0x26ae3982#define MT6359_ACCDET_CON20 0x26b03983#define MT6359_ACCDET_CON21 0x26b23984#define MT6359_ACCDET_CON22 0x26b43985#define MT6359_ACCDET_CON23 0x26b63986#define MT6359_ACCDET_CON24 0x26b83987#define MT6359_ACCDET_CON25 0x26ba3988#define MT6359_ACCDET_CON26 0x26bc3989#define MT6359_ACCDET_CON27 0x26be3990#define MT6359_ACCDET_CON28 0x26c03991#define MT6359_ACCDET_CON29 0x26c23992#define MT6359_ACCDET_CON30 0x26c43993#define MT6359_ACCDET_CON31 0x26c63994#define MT6359_ACCDET_CON32 0x26c83995#define MT6359_ACCDET_CON33 0x26ca3996#define MT6359_ACCDET_CON34 0x26cc3997#define MT6359_ACCDET_CON35 0x26ce3998#define MT6359_ACCDET_CON36 0x26d03999#define MT6359_ACCDET_CON37 0x26d24000#define MT6359_ACCDET_CON38 0x26d44001#define MT6359_ACCDET_CON39 0x26d64002#define MT6359_ACCDET_CON40 0x26d84003#define MT6359_MAX_REGISTER MT6359_ZCD_CON54004 4005/* dl bias */4006#define DRBIAS_MASK 0x74007#define DRBIAS_HP_SFT (RG_AUDBIASADJ_0_VAUDP32_SFT + 0)4008#define DRBIAS_HP_MASK_SFT (DRBIAS_MASK << DRBIAS_HP_SFT)4009#define DRBIAS_HS_SFT (RG_AUDBIASADJ_0_VAUDP32_SFT + 3)4010#define DRBIAS_HS_MASK_SFT (DRBIAS_MASK << DRBIAS_HS_SFT)4011#define DRBIAS_LO_SFT (RG_AUDBIASADJ_0_VAUDP32_SFT + 6)4012#define DRBIAS_LO_MASK_SFT (DRBIAS_MASK << DRBIAS_LO_SFT)4013#define IBIAS_MASK 0x34014#define IBIAS_HP_SFT (RG_AUDBIASADJ_1_VAUDP32_SFT + 0)4015#define IBIAS_HP_MASK_SFT (IBIAS_MASK << IBIAS_HP_SFT)4016#define IBIAS_HS_SFT (RG_AUDBIASADJ_1_VAUDP32_SFT + 2)4017#define IBIAS_HS_MASK_SFT (IBIAS_MASK << IBIAS_HS_SFT)4018#define IBIAS_LO_SFT (RG_AUDBIASADJ_1_VAUDP32_SFT + 4)4019#define IBIAS_LO_MASK_SFT (IBIAS_MASK << IBIAS_LO_SFT)4020#define IBIAS_ZCD_SFT (RG_AUDBIASADJ_1_VAUDP32_SFT + 6)4021#define IBIAS_ZCD_MASK_SFT (IBIAS_MASK << IBIAS_ZCD_SFT)4022 4023/* dl gain */4024#define DL_GAIN_N_10DB_REG (DL_GAIN_N_10DB << 7 | DL_GAIN_N_10DB)4025#define DL_GAIN_N_22DB_REG (DL_GAIN_N_22DB << 7 | DL_GAIN_N_22DB)4026#define DL_GAIN_N_40DB_REG (DL_GAIN_N_40DB << 7 | DL_GAIN_N_40DB)4027#define DL_GAIN_REG_MASK 0x0f9f4028 4029/* mic type mux */4030#define MT_SOC_ENUM_EXT_ID(xname, xenum, xhandler_get, xhandler_put, id) \4031{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .device = id,\4032 .info = snd_soc_info_enum_double, \4033 .get = xhandler_get, .put = xhandler_put, \4034 .private_value = (unsigned long)&(xenum) }4035 4036enum {4037 MT6359_MTKAIF_PROTOCOL_1 = 0,4038 MT6359_MTKAIF_PROTOCOL_2,4039 MT6359_MTKAIF_PROTOCOL_2_CLK_P2,4040};4041 4042enum {4043 MT6359_AIF_1 = 0, /* dl: hp, rcv, hp+lo */4044 MT6359_AIF_2, /* dl: lo only */4045 MT6359_AIF_NUM,4046};4047 4048enum {4049 AUDIO_ANALOG_VOLUME_HSOUTL,4050 AUDIO_ANALOG_VOLUME_HSOUTR,4051 AUDIO_ANALOG_VOLUME_HPOUTL,4052 AUDIO_ANALOG_VOLUME_HPOUTR,4053 AUDIO_ANALOG_VOLUME_LINEOUTL,4054 AUDIO_ANALOG_VOLUME_LINEOUTR,4055 AUDIO_ANALOG_VOLUME_MICAMP1,4056 AUDIO_ANALOG_VOLUME_MICAMP2,4057 AUDIO_ANALOG_VOLUME_MICAMP3,4058 AUDIO_ANALOG_VOLUME_TYPE_MAX4059};4060 4061enum {4062 MUX_MIC_TYPE_0, /* ain0, micbias 0 */4063 MUX_MIC_TYPE_1, /* ain1, micbias 1 */4064 MUX_MIC_TYPE_2, /* ain2/3, micbias 2 */4065 MUX_PGA_L,4066 MUX_PGA_R,4067 MUX_PGA_3,4068 MUX_HP,4069 MUX_NUM,4070};4071 4072enum {4073 DEVICE_HP,4074 DEVICE_LO,4075 DEVICE_RCV,4076 DEVICE_MIC1,4077 DEVICE_MIC2,4078 DEVICE_NUM4079};4080 4081enum {4082 HP_GAIN_CTL_ZCD = 0,4083 HP_GAIN_CTL_NLE,4084 HP_GAIN_CTL_NUM,4085};4086 4087enum {4088 HP_MUX_OPEN = 0,4089 HP_MUX_HPSPK,4090 HP_MUX_HP,4091 HP_MUX_TEST_MODE,4092 HP_MUX_HP_IMPEDANCE,4093 HP_MUX_MASK = 0x7,4094};4095 4096enum {4097 RCV_MUX_OPEN = 0,4098 RCV_MUX_MUTE,4099 RCV_MUX_VOICE_PLAYBACK,4100 RCV_MUX_TEST_MODE,4101 RCV_MUX_MASK = 0x3,4102};4103 4104enum {4105 LO_MUX_OPEN = 0,4106 LO_MUX_L_DAC,4107 LO_MUX_3RD_DAC,4108 LO_MUX_TEST_MODE,4109 LO_MUX_MASK = 0x3,4110};4111 4112/* Supply widget subseq */4113enum {4114 /* common */4115 SUPPLY_SEQ_CLK_BUF,4116 SUPPLY_SEQ_AUD_GLB,4117 SUPPLY_SEQ_HP_PULL_DOWN,4118 SUPPLY_SEQ_CLKSQ,4119 SUPPLY_SEQ_ADC_CLKGEN,4120 SUPPLY_SEQ_TOP_CK,4121 SUPPLY_SEQ_TOP_CK_LAST,4122 SUPPLY_SEQ_DCC_CLK,4123 SUPPLY_SEQ_MIC_BIAS,4124 SUPPLY_SEQ_DMIC,4125 SUPPLY_SEQ_AUD_TOP,4126 SUPPLY_SEQ_AUD_TOP_LAST,4127 SUPPLY_SEQ_DL_SDM_FIFO_CLK,4128 SUPPLY_SEQ_DL_SDM,4129 SUPPLY_SEQ_DL_NCP,4130 SUPPLY_SEQ_AFE,4131 /* playback */4132 SUPPLY_SEQ_DL_SRC,4133 SUPPLY_SEQ_DL_ESD_RESIST,4134 SUPPLY_SEQ_HP_DAMPING_OFF_RESET_CMFB,4135 SUPPLY_SEQ_HP_MUTE,4136 SUPPLY_SEQ_DL_LDO_REMOTE_SENSE,4137 SUPPLY_SEQ_DL_LDO,4138 SUPPLY_SEQ_DL_NV,4139 SUPPLY_SEQ_HP_ANA_TRIM,4140 SUPPLY_SEQ_DL_IBIST,4141 /* capture */4142 SUPPLY_SEQ_UL_PGA,4143 SUPPLY_SEQ_UL_ADC,4144 SUPPLY_SEQ_UL_MTKAIF,4145 SUPPLY_SEQ_UL_SRC_DMIC,4146 SUPPLY_SEQ_UL_SRC,4147};4148 4149enum {4150 CH_L = 0,4151 CH_R,4152 NUM_CH,4153};4154 4155enum {4156 DRBIAS_4UA = 0,4157 DRBIAS_5UA,4158 DRBIAS_6UA,4159 DRBIAS_7UA,4160 DRBIAS_8UA,4161 DRBIAS_9UA,4162 DRBIAS_10UA,4163 DRBIAS_11UA,4164};4165 4166enum {4167 IBIAS_4UA = 0,4168 IBIAS_5UA,4169 IBIAS_6UA,4170 IBIAS_7UA,4171};4172 4173enum {4174 IBIAS_ZCD_3UA = 0,4175 IBIAS_ZCD_4UA,4176 IBIAS_ZCD_5UA,4177 IBIAS_ZCD_6UA,4178};4179 4180enum {4181 MIC_BIAS_1P7 = 0,4182 MIC_BIAS_1P8,4183 MIC_BIAS_1P9,4184 MIC_BIAS_2P0,4185 MIC_BIAS_2P1,4186 MIC_BIAS_2P5,4187 MIC_BIAS_2P6,4188 MIC_BIAS_2P7,4189};4190 4191/* dl pga gain */4192enum {4193 DL_GAIN_8DB = 0,4194 DL_GAIN_0DB = 8,4195 DL_GAIN_N_1DB = 9,4196 DL_GAIN_N_10DB = 18,4197 DL_GAIN_N_22DB = 30,4198 DL_GAIN_N_40DB = 0x1f,4199};4200 4201/* Mic Type MUX */4202enum {4203 MIC_TYPE_MUX_IDLE = 0,4204 MIC_TYPE_MUX_ACC,4205 MIC_TYPE_MUX_DMIC,4206 MIC_TYPE_MUX_DCC,4207 MIC_TYPE_MUX_DCC_ECM_DIFF,4208 MIC_TYPE_MUX_DCC_ECM_SINGLE,4209};4210 4211/* UL SRC MUX */4212enum {4213 UL_SRC_MUX_AMIC = 0,4214 UL_SRC_MUX_DMIC,4215};4216 4217/* MISO MUX */4218enum {4219 MISO_MUX_UL1_CH1 = 0,4220 MISO_MUX_UL1_CH2,4221 MISO_MUX_UL2_CH1,4222 MISO_MUX_UL2_CH2,4223};4224 4225/* DMIC MUX */4226enum {4227 DMIC_MUX_DMIC_DATA0 = 0,4228 DMIC_MUX_DMIC_DATA1_L,4229 DMIC_MUX_DMIC_DATA1_L_1,4230 DMIC_MUX_DMIC_DATA1_R,4231};4232 4233/* ADC L MUX */4234enum {4235 ADC_MUX_IDLE = 0,4236 ADC_MUX_AIN0,4237 ADC_MUX_PREAMPLIFIER,4238 ADC_MUX_IDLE1,4239};4240 4241/* PGA L MUX */4242enum {4243 PGA_L_MUX_NONE = 0,4244 PGA_L_MUX_AIN0,4245 PGA_L_MUX_AIN1,4246};4247 4248/* PGA R MUX */4249enum {4250 PGA_R_MUX_NONE = 0,4251 PGA_R_MUX_AIN2,4252 PGA_R_MUX_AIN3,4253 PGA_R_MUX_AIN0,4254};4255 4256/* PGA 3 MUX */4257enum {4258 PGA_3_MUX_NONE = 0,4259 PGA_3_MUX_AIN3,4260 PGA_3_MUX_AIN2,4261};4262 4263struct mt6359_priv {4264 struct device *dev;4265 struct regmap *regmap;4266 unsigned int dl_rate[MT6359_AIF_NUM];4267 unsigned int ul_rate[MT6359_AIF_NUM];4268 int ana_gain[AUDIO_ANALOG_VOLUME_TYPE_MAX];4269 unsigned int mux_select[MUX_NUM];4270 unsigned int dmic_one_wire_mode;4271 int dev_counter[DEVICE_NUM];4272 int hp_gain_ctl;4273 int hp_hifi_mode;4274 int mtkaif_protocol;4275};4276 4277#define CODEC_MT6359_NAME "mtk-codec-mt6359"4278#define IS_DCC_BASE(type) ((type) == MIC_TYPE_MUX_DCC || \4279 (type) == MIC_TYPE_MUX_DCC_ECM_DIFF || \4280 (type) == MIC_TYPE_MUX_DCC_ECM_SINGLE)4281 4282void mt6359_set_mtkaif_protocol(struct snd_soc_component *cmpnt,4283 int mtkaif_protocol);4284void mt6359_mtkaif_calibration_enable(struct snd_soc_component *cmpnt);4285void mt6359_mtkaif_calibration_disable(struct snd_soc_component *cmpnt);4286void mt6359_set_mtkaif_calibration_phase(struct snd_soc_component *cmpnt,4287 int phase_1, int phase_2, int phase_3);4288 4289#endif/* end _MT6359_H_ */4290