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1/* SPDX-License-Identifier: GPL-2.0-only */2/*3 * NAU85L40 ALSA SoC audio driver4 *5 * Copyright 2016 Nuvoton Technology Corp.6 * Author: John Hsu <KCHSU0@nuvoton.com>7 */8 9#ifndef __NAU8540_H__10#define __NAU8540_H__11 12#define NAU8540_REG_SW_RESET 0x0013#define NAU8540_REG_POWER_MANAGEMENT 0x0114#define NAU8540_REG_CLOCK_CTRL 0x0215#define NAU8540_REG_CLOCK_SRC 0x0316#define NAU8540_REG_FLL1 0x0417#define NAU8540_REG_FLL2 0x0518#define NAU8540_REG_FLL3 0x0619#define NAU8540_REG_FLL4 0x0720#define NAU8540_REG_FLL5 0x0821#define NAU8540_REG_FLL6 0x0922#define NAU8540_REG_FLL_VCO_RSV 0x0A23#define NAU8540_REG_PCM_CTRL0 0x1024#define NAU8540_REG_PCM_CTRL1 0x1125#define NAU8540_REG_PCM_CTRL2 0x1226#define NAU8540_REG_PCM_CTRL3 0x1327#define NAU8540_REG_PCM_CTRL4 0x1428#define NAU8540_REG_ALC_CONTROL_1 0x2029#define NAU8540_REG_ALC_CONTROL_2 0x2130#define NAU8540_REG_ALC_CONTROL_3 0x2231#define NAU8540_REG_ALC_CONTROL_4 0x2332#define NAU8540_REG_ALC_CONTROL_5 0x2433#define NAU8540_REG_ALC_GAIN_CH12 0x2D34#define NAU8540_REG_ALC_GAIN_CH34 0x2E35#define NAU8540_REG_ALC_STATUS 0x2F36#define NAU8540_REG_NOTCH_FIL1_CH1 0x3037#define NAU8540_REG_NOTCH_FIL2_CH1 0x3138#define NAU8540_REG_NOTCH_FIL1_CH2 0x3239#define NAU8540_REG_NOTCH_FIL2_CH2 0x3340#define NAU8540_REG_NOTCH_FIL1_CH3 0x3441#define NAU8540_REG_NOTCH_FIL2_CH3 0x3542#define NAU8540_REG_NOTCH_FIL1_CH4 0x3643#define NAU8540_REG_NOTCH_FIL2_CH4 0x3744#define NAU8540_REG_HPF_FILTER_CH12 0x3845#define NAU8540_REG_HPF_FILTER_CH34 0x3946#define NAU8540_REG_ADC_SAMPLE_RATE 0x3A47#define NAU8540_REG_DIGITAL_GAIN_CH1 0x4048#define NAU8540_REG_DIGITAL_GAIN_CH2 0x4149#define NAU8540_REG_DIGITAL_GAIN_CH3 0x4250#define NAU8540_REG_DIGITAL_GAIN_CH4 0x4351#define NAU8540_REG_DIGITAL_MUX 0x4452#define NAU8540_REG_P2P_CH1 0x4853#define NAU8540_REG_P2P_CH2 0x4954#define NAU8540_REG_P2P_CH3 0x4A55#define NAU8540_REG_P2P_CH4 0x4B56#define NAU8540_REG_PEAK_CH1 0x4C57#define NAU8540_REG_PEAK_CH2 0x4D58#define NAU8540_REG_PEAK_CH3 0x4E59#define NAU8540_REG_PEAK_CH4 0x4F60#define NAU8540_REG_GPIO_CTRL 0x5061#define NAU8540_REG_MISC_CTRL 0x5162#define NAU8540_REG_I2C_CTRL 0x5263#define NAU8540_REG_I2C_DEVICE_ID 0x5864#define NAU8540_REG_RST 0x5A65#define NAU8540_REG_VMID_CTRL 0x6066#define NAU8540_REG_MUTE 0x6167#define NAU8540_REG_ANALOG_ADC1 0x6468#define NAU8540_REG_ANALOG_ADC2 0x6569#define NAU8540_REG_ANALOG_PWR 0x6670#define NAU8540_REG_MIC_BIAS 0x6771#define NAU8540_REG_REFERENCE 0x6872#define NAU8540_REG_FEPGA1 0x6973#define NAU8540_REG_FEPGA2 0x6A74#define NAU8540_REG_FEPGA3 0x6B75#define NAU8540_REG_FEPGA4 0x6C76#define NAU8540_REG_PWR 0x6D77#define NAU8540_REG_MAX NAU8540_REG_PWR78 79 80/* POWER_MANAGEMENT (0x01) */81#define NAU8540_ADC_ALL_EN 0xf82#define NAU8540_ADC4_EN (0x1 << 3)83#define NAU8540_ADC3_EN (0x1 << 2)84#define NAU8540_ADC2_EN (0x1 << 1)85#define NAU8540_ADC1_EN 0x186 87/* CLOCK_CTRL (0x02) */88#define NAU8540_CLK_ADC_EN (0x1 << 15)89#define NAU8540_CLK_AGC_EN (0x1 << 3)90#define NAU8540_CLK_I2S_EN (0x1 << 1)91 92/* CLOCK_SRC (0x03) */93#define NAU8540_CLK_SRC_SFT 1594#define NAU8540_CLK_SRC_MASK (1 << NAU8540_CLK_SRC_SFT)95#define NAU8540_CLK_SRC_VCO (1 << NAU8540_CLK_SRC_SFT)96#define NAU8540_CLK_SRC_MCLK (0 << NAU8540_CLK_SRC_SFT)97#define NAU8540_CLK_ADC_SRC_SFT 698#define NAU8540_CLK_ADC_SRC_MASK (0x3 << NAU8540_CLK_ADC_SRC_SFT)99#define NAU8540_CLK_MCLK_SRC_MASK 0xf100 101/* FLL1 (0x04) */102#define NAU8540_ICTRL_LATCH_SFT 10103#define NAU8540_ICTRL_LATCH_MASK (0x7 << NAU8540_ICTRL_LATCH_SFT)104#define NAU8540_FLL_RATIO_MASK 0x7f105 106/* FLL3 (0x06) */107#define NAU8540_GAIN_ERR_SFT 12108#define NAU8540_GAIN_ERR_MASK (0xf << NAU8540_GAIN_ERR_SFT)109#define NAU8540_FLL_CLK_SRC_SFT 10110#define NAU8540_FLL_CLK_SRC_MASK (0x3 << NAU8540_FLL_CLK_SRC_SFT)111#define NAU8540_FLL_CLK_SRC_MCLK (0 << NAU8540_FLL_CLK_SRC_SFT)112#define NAU8540_FLL_CLK_SRC_BLK (0x2 << NAU8540_FLL_CLK_SRC_SFT)113#define NAU8540_FLL_CLK_SRC_FS (0x3 << NAU8540_FLL_CLK_SRC_SFT)114#define NAU8540_FLL_INTEGER_MASK 0x3ff115 116/* FLL4 (0x07) */117#define NAU8540_FLL_REF_DIV_SFT 10118#define NAU8540_FLL_REF_DIV_MASK (0x3 << NAU8540_FLL_REF_DIV_SFT)119 120/* FLL5 (0x08) */121#define NAU8540_FLL_PDB_DAC_EN (0x1 << 15)122#define NAU8540_FLL_LOOP_FTR_EN (0x1 << 14)123#define NAU8540_FLL_CLK_SW_MASK (0x1 << 13)124#define NAU8540_FLL_CLK_SW_N2 (0x1 << 13)125#define NAU8540_FLL_CLK_SW_REF (0x0 << 13)126#define NAU8540_FLL_FTR_SW_MASK (0x1 << 12)127#define NAU8540_FLL_FTR_SW_ACCU (0x1 << 12)128#define NAU8540_FLL_FTR_SW_FILTER (0x0 << 12)129 130/* FLL6 (0x9) */131#define NAU8540_DCO_EN (0x1 << 15)132#define NAU8540_SDM_EN (0x1 << 14)133#define NAU8540_CUTOFF500 (0x1 << 13)134 135/* PCM_CTRL0 (0x10) */136#define NAU8540_I2S_BP_SFT 7137#define NAU8540_I2S_BP_INV (0x1 << NAU8540_I2S_BP_SFT)138#define NAU8540_I2S_PCMB_SFT 6139#define NAU8540_I2S_PCMB_EN (0x1 << NAU8540_I2S_PCMB_SFT)140#define NAU8540_I2S_DL_SFT 2141#define NAU8540_I2S_DL_MASK (0x3 << NAU8540_I2S_DL_SFT)142#define NAU8540_I2S_DL_16 (0 << NAU8540_I2S_DL_SFT)143#define NAU8540_I2S_DL_20 (0x1 << NAU8540_I2S_DL_SFT)144#define NAU8540_I2S_DL_24 (0x2 << NAU8540_I2S_DL_SFT)145#define NAU8540_I2S_DL_32 (0x3 << NAU8540_I2S_DL_SFT)146#define NAU8540_I2S_DF_MASK 0x3147#define NAU8540_I2S_DF_RIGTH 0148#define NAU8540_I2S_DF_LEFT 0x1149#define NAU8540_I2S_DF_I2S 0x2150#define NAU8540_I2S_DF_PCM_AB 0x3151 152/* PCM_CTRL1 (0x11) */153#define NAU8540_I2S_DO12_TRI (0x1 << 15)154#define NAU8540_I2S_LRC_DIV_SFT 12155#define NAU8540_I2S_LRC_DIV_MASK (0x3 << NAU8540_I2S_LRC_DIV_SFT)156#define NAU8540_I2S_DO12_OE (0x1 << 4)157#define NAU8540_I2S_MS_SFT 3158#define NAU8540_I2S_MS_MASK (0x1 << NAU8540_I2S_MS_SFT)159#define NAU8540_I2S_MS_MASTER (0x1 << NAU8540_I2S_MS_SFT)160#define NAU8540_I2S_MS_SLAVE (0x0 << NAU8540_I2S_MS_SFT)161#define NAU8540_I2S_BLK_DIV_MASK 0x7162 163/* PCM_CTRL1 (0x12) */164#define NAU8540_I2S_DO34_TRI (0x1 << 15)165#define NAU8540_I2S_DO34_OE (0x1 << 11)166#define NAU8540_I2S_TSLOT_L_MASK 0x3ff167 168/* PCM_CTRL4 (0x14) */169#define NAU8540_TDM_MODE (0x1 << 15)170#define NAU8540_TDM_OFFSET_EN (0x1 << 14)171#define NAU8540_TDM_TX_MASK 0xf172 173/* ALC_CONTROL_3 (0x22) */174#define NAU8540_ALC_CH1_EN (0x1 << 12)175#define NAU8540_ALC_CH2_EN (0x1 << 13)176#define NAU8540_ALC_CH3_EN (0x1 << 14)177#define NAU8540_ALC_CH4_EN (0x1 << 15)178#define NAU8540_ALC_CH_ALL_EN (0xf << 12)179 180/* ADC_SAMPLE_RATE (0x3A) */181#define NAU8540_CH_SYNC (0x1 << 14)182#define NAU8540_ADC_OSR_MASK 0x3183#define NAU8540_ADC_OSR_256 0x3184#define NAU8540_ADC_OSR_128 0x2185#define NAU8540_ADC_OSR_64 0x1186#define NAU8540_ADC_OSR_32 0x0187 188/* VMID_CTRL (0x60) */189#define NAU8540_VMID_EN (1 << 6)190#define NAU8540_VMID_SEL_SFT 4191#define NAU8540_VMID_SEL_MASK (0x3 << NAU8540_VMID_SEL_SFT)192 193/* MUTE (0x61) */194#define NAU8540_PGA_CH1_MUTE 0x1195#define NAU8540_PGA_CH2_MUTE 0x2196#define NAU8540_PGA_CH3_MUTE 0x4197#define NAU8540_PGA_CH4_MUTE 0x8198#define NAU8540_PGA_CH_ALL_MUTE 0xf199 200/* MIC_BIAS (0x67) */201#define NAU8540_PU_PRE (0x1 << 8)202 203/* REFERENCE (0x68) */204#define NAU8540_PRECHARGE_DIS (0x1 << 13)205#define NAU8540_GLOBAL_BIAS_EN (0x1 << 12)206#define NAU8540_DISCHRG_EN (0x1 << 11)207 208/* FEPGA1 (0x69) */209#define NAU8540_FEPGA1_MODCH2_SHT_SFT 7210#define NAU8540_FEPGA1_MODCH2_SHT (0x1 << NAU8540_FEPGA1_MODCH2_SHT_SFT)211#define NAU8540_FEPGA1_MODCH1_SHT_SFT 3212#define NAU8540_FEPGA1_MODCH1_SHT (0x1 << NAU8540_FEPGA1_MODCH1_SHT_SFT)213 214/* FEPGA2 (0x6A) */215#define NAU8540_FEPGA2_MODCH4_SHT_SFT 7216#define NAU8540_FEPGA2_MODCH4_SHT (0x1 << NAU8540_FEPGA2_MODCH4_SHT_SFT)217#define NAU8540_FEPGA2_MODCH3_SHT_SFT 3218#define NAU8540_FEPGA2_MODCH3_SHT (0x1 << NAU8540_FEPGA2_MODCH3_SHT_SFT)219#define NAU8540_ACDC_CTL_SFT 8220#define NAU8540_ACDC_CTL_MASK (0xff << NAU8540_ACDC_CTL_SFT)221#define NAU8540_ACDC_CTL_MIC4N_VREF (0x1 << 15)222#define NAU8540_ACDC_CTL_MIC4P_VREF (0x1 << 14)223#define NAU8540_ACDC_CTL_MIC3N_VREF (0x1 << 13)224#define NAU8540_ACDC_CTL_MIC3P_VREF (0x1 << 12)225#define NAU8540_ACDC_CTL_MIC2N_VREF (0x1 << 11)226#define NAU8540_ACDC_CTL_MIC2P_VREF (0x1 << 10)227#define NAU8540_ACDC_CTL_MIC1N_VREF (0x1 << 9)228#define NAU8540_ACDC_CTL_MIC1P_VREF (0x1 << 8)229 230/* System Clock Source */231enum {232 NAU8540_CLK_DIS,233 NAU8540_CLK_MCLK,234 NAU8540_CLK_INTERNAL,235 NAU8540_CLK_FLL_MCLK,236 NAU8540_CLK_FLL_BLK,237 NAU8540_CLK_FLL_FS,238};239 240struct nau8540 {241 struct device *dev;242 struct regmap *regmap;243};244 245struct nau8540_fll {246 int mclk_src;247 int ratio;248 int fll_frac;249 int fll_int;250 int clk_ref_div;251};252 253struct nau8540_fll_attr {254 unsigned int param;255 unsigned int val;256};257 258/* over sampling rate */259struct nau8540_osr_attr {260 unsigned int osr;261 unsigned int clk_src;262};263 264 265#endif /* __NAU8540_H__ */266