587 lines · c
1/* SPDX-License-Identifier: GPL-2.0-only */2/*3 * NAU88L21 ALSA SoC audio driver4 *5 * Copyright 2021 Nuvoton Technology Corp.6 * Author: John Hsu <kchsu0@nuvoton.com>7 * Co-author: Seven Lee <wtli@nuvoton.com>8 */9 10#ifndef __NAU8821_H__11#define __NAU8821_H__12 13#define NAU8821_R00_RESET 0x0014#define NAU8821_R01_ENA_CTRL 0x0115#define NAU8821_R03_CLK_DIVIDER 0x0316#define NAU8821_R04_FLL1 0x0417#define NAU8821_R05_FLL2 0x0518#define NAU8821_R06_FLL3 0x0619#define NAU8821_R07_FLL4 0x0720#define NAU8821_R08_FLL5 0x0821#define NAU8821_R09_FLL6 0x0922#define NAU8821_R0A_FLL7 0x0a23#define NAU8821_R0B_FLL8 0x0b24#define NAU8821_R0D_JACK_DET_CTRL 0x0d25#define NAU8821_R0F_INTERRUPT_MASK 0x0f26#define NAU8821_R10_IRQ_STATUS 0x1027#define NAU8821_R11_INT_CLR_KEY_STATUS 0x1128#define NAU8821_R12_INTERRUPT_DIS_CTRL 0x1229#define NAU8821_R13_DMIC_CTRL 0x1330#define NAU8821_R1A_GPIO12_CTRL 0x1a31#define NAU8821_R1B_TDM_CTRL 0x1b32#define NAU8821_R1C_I2S_PCM_CTRL1 0x1c33#define NAU8821_R1D_I2S_PCM_CTRL2 0x1d34#define NAU8821_R1E_LEFT_TIME_SLOT 0x1e35#define NAU8821_R1F_RIGHT_TIME_SLOT 0x1f36#define NAU8821_R21_BIQ0_COF1 0x2137#define NAU8821_R22_BIQ0_COF2 0x2238#define NAU8821_R23_BIQ0_COF3 0x2339#define NAU8821_R24_BIQ0_COF4 0x2440#define NAU8821_R25_BIQ0_COF5 0x2541#define NAU8821_R26_BIQ0_COF6 0x2642#define NAU8821_R27_BIQ0_COF7 0x2743#define NAU8821_R28_BIQ0_COF8 0x2844#define NAU8821_R29_BIQ0_COF9 0x2945#define NAU8821_R2A_BIQ0_COF10 0x2a46#define NAU8821_R2B_ADC_RATE 0x2b47#define NAU8821_R2C_DAC_CTRL1 0x2c48#define NAU8821_R2D_DAC_CTRL2 0x2d49#define NAU8821_R2F_DAC_DGAIN_CTRL 0x2f50#define NAU8821_R30_ADC_DGAIN_CTRL 0x3051#define NAU8821_R31_MUTE_CTRL 0x3152#define NAU8821_R32_HSVOL_CTRL 0x3253#define NAU8821_R34_DACR_CTRL 0x3454#define NAU8821_R35_ADC_DGAIN_CTRL1 0x3555#define NAU8821_R36_ADC_DRC_KNEE_IP12 0x3656#define NAU8821_R37_ADC_DRC_KNEE_IP34 0x3757#define NAU8821_R38_ADC_DRC_SLOPES 0x3858#define NAU8821_R39_ADC_DRC_ATKDCY 0x3959#define NAU8821_R3A_DAC_DRC_KNEE_IP12 0x3a60#define NAU8821_R3B_DAC_DRC_KNEE_IP34 0x3b61#define NAU8821_R3C_DAC_DRC_SLOPES 0x3c62#define NAU8821_R3D_DAC_DRC_ATKDCY 0x3d63#define NAU8821_R41_BIQ1_COF1 0x4164#define NAU8821_R42_BIQ1_COF2 0x4265#define NAU8821_R43_BIQ1_COF3 0x4366#define NAU8821_R44_BIQ1_COF4 0x4467#define NAU8821_R45_BIQ1_COF5 0x4568#define NAU8821_R46_BIQ1_COF6 0x4669#define NAU8821_R47_BIQ1_COF7 0x4770#define NAU8821_R48_BIQ1_COF8 0x4871#define NAU8821_R49_BIQ1_COF9 0x4972#define NAU8821_R4A_BIQ1_COF10 0x4a73#define NAU8821_R4B_CLASSG_CTRL 0x4b74#define NAU8821_R4C_IMM_MODE_CTRL 0x4c75#define NAU8821_R4D_IMM_RMS_L 0x4d76#define NAU8821_R4E_FUSE_CTRL2 0x4e77#define NAU8821_R4F_FUSE_CTRL3 0x4f78#define NAU8821_R51_FUSE_CTRL1 0x5179#define NAU8821_R53_OTPDOUT_1 0x5380#define NAU8821_R54_OTPDOUT_2 0x5481#define NAU8821_R55_MISC_CTRL 0x5582#define NAU8821_R58_I2C_DEVICE_ID 0x5883#define NAU8821_R59_SARDOUT_RAM_STATUS 0x5984#define NAU8821_R5A_SOFTWARE_RST 0x5a85#define NAU8821_R66_BIAS_ADJ 0x6686#define NAU8821_R68_TRIM_SETTINGS 0x6887#define NAU8821_R69_ANALOG_CONTROL_1 0x6988#define NAU8821_R6A_ANALOG_CONTROL_2 0x6a89#define NAU8821_R6B_PGA_MUTE 0x6b90#define NAU8821_R71_ANALOG_ADC_1 0x7191#define NAU8821_R72_ANALOG_ADC_2 0x7292#define NAU8821_R73_RDAC 0x7393#define NAU8821_R74_MIC_BIAS 0x7494#define NAU8821_R76_BOOST 0x7695#define NAU8821_R77_FEPGA 0x7796#define NAU8821_R7E_PGA_GAIN 0x7e97#define NAU8821_R7F_POWER_UP_CONTROL 0x7f98#define NAU8821_R80_CHARGE_PUMP 0x8099#define NAU8821_R81_CHARGE_PUMP_INPUT_READ 0x81100#define NAU8821_R82_GENERAL_STATUS 0x82101#define NAU8821_REG_MAX NAU8821_R82_GENERAL_STATUS102/* 16-bit control register address, and 16-bits control register data */103#define NAU8821_REG_ADDR_LEN 16104#define NAU8821_REG_DATA_LEN 16105 106/* ENA_CTRL (0x01) */107#define NAU8821_CLK_DAC_INV_SFT 14108#define NAU8821_CLK_DAC_INV (0x1 << NAU8821_CLK_DAC_INV)109#define NAU8821_EN_DACR_SFT 11110#define NAU8821_EN_DACR (0x1 << NAU8821_EN_DACR_SFT)111#define NAU8821_EN_DACL_SFT 10112#define NAU8821_EN_DACL (0x1 << NAU8821_EN_DACL_SFT)113#define NAU8821_EN_ADCR_SFT 9114#define NAU8821_EN_ADCR (0x1 << NAU8821_EN_ADCR_SFT)115#define NAU8821_EN_ADCL_SFT 8116#define NAU8821_EN_ADCL (0x1 << NAU8821_EN_ADCL_SFT)117#define NAU8821_EN_ADC_CLK_SFT 7118#define NAU8821_EN_ADC_CLK (0x1 << NAU8821_EN_ADC_CLK_SFT)119#define NAU8821_EN_DAC_CLK_SFT 6120#define NAU8821_EN_DAC_CLK (0x1 << NAU8821_EN_DAC_CLK_SFT)121#define NAU8821_EN_I2S_CLK_SFT 4122#define NAU8821_EN_I2S_CLK (0x1 << NAU8821_EN_I2S_CLK_SFT)123#define NAU8821_EN_DRC_CLK_SFT 0124#define NAU8821_EN_DRC_CLK (0x1 << NAU8821_EN_DRC_CLK_SFT)125 126/* CLK_DIVIDER (0x03) */127#define NAU8821_CLK_SRC_SFT 15128#define NAU8821_CLK_SRC_MASK (0x1 << NAU8821_CLK_SRC_SFT)129#define NAU8821_CLK_SRC_VCO (0x1 << NAU8821_CLK_SRC_SFT)130#define NAU8821_CLK_SRC_MCLK (0x0 << NAU8821_CLK_SRC_SFT)131#define NAU8821_CLK_CODEC_SRC_SFT 13132#define NAU8821_CLK_CODEC_SRC_MASK (0x1 << NAU8821_CLK_CODEC_SRC_SFT)133#define NAU8821_CLK_CODEC_SRC_VCO (0x1 << NAU8821_CLK_CODEC_SRC_SFT)134#define NAU8821_CLK_CODEC_SRC_MCLK (0x0 << NAU8821_CLK_CODEC_SRC_SFT)135#define NAU8821_CLK_ADC_SRC_SFT 6136#define NAU8821_CLK_ADC_SRC_MASK (0x3 << NAU8821_CLK_ADC_SRC_SFT)137#define NAU8821_CLK_DAC_SRC_SFT 4138#define NAU8821_CLK_DAC_SRC_MASK (0x3 << NAU8821_CLK_DAC_SRC_SFT)139#define NAU8821_CLK_MCLK_SRC_MASK 0xf140 141/* FLL1 (0x04) */142#define NAU8821_ICTRL_LATCH_SFT 10143#define NAU8821_ICTRL_LATCH_MASK (0x7 << NAU8821_ICTRL_LATCH_SFT)144#define NAU8821_FLL_RATIO_MASK 0x7f145 146/* FLL3 (0x06) */147#define NAU8821_GAIN_ERR_SFT 12148#define NAU8821_GAIN_ERR_MASK (0xf << NAU8821_GAIN_ERR_SFT)149#define NAU8821_FLL_CLK_SRC_SFT 10150#define NAU8821_FLL_CLK_SRC_MASK (0x3 << NAU8821_FLL_CLK_SRC_SFT)151#define NAU8821_FLL_CLK_SRC_FS (0x3 << NAU8821_FLL_CLK_SRC_SFT)152#define NAU8821_FLL_CLK_SRC_BLK (0x2 << NAU8821_FLL_CLK_SRC_SFT)153#define NAU8821_FLL_CLK_SRC_MCLK (0x0 << NAU8821_FLL_CLK_SRC_SFT)154#define NAU8821_FLL_INTEGER_MASK 0x3ff155 156/* FLL4 (0x07) */157#define NAU8821_HIGHBW_EN_SFT 15158#define NAU8821_HIGHBW_EN (0x1 << NAU8821_HIGHBW_EN_SFT)159#define NAU8821_FLL_REF_DIV_SFT 10160#define NAU8821_FLL_REF_DIV_MASK (0x3 << NAU8821_FLL_REF_DIV_SFT)161 162/* FLL5 (0x08) */163#define NAU8821_FLL_PDB_DAC_EN (0x1 << 15)164#define NAU8821_FLL_LOOP_FTR_EN (0x1 << 14)165#define NAU8821_FLL_CLK_SW_SFT 13166#define NAU8821_FLL_CLK_SW_MASK (0x1 << NAU8821_FLL_CLK_SW_SFT)167#define NAU8821_FLL_CLK_SW_N2 (0x1 << NAU8821_FLL_CLK_SW_SFT)168#define NAU8821_FLL_CLK_SW_REF (0x0 << NAU8821_FLL_CLK_SW_SFT)169#define NAU8821_FLL_FTR_SW_SFT 12170#define NAU8821_FLL_FTR_SW_MASK (0x1 << NAU8821_FLL_FTR_SW_SFT)171#define NAU8821_FLL_FTR_SW_ACCU (0x1 << NAU8821_FLL_FTR_SW_SFT)172#define NAU8821_FLL_FTR_SW_FILTER (0x0 << NAU8821_FLL_FTR_SW_SFT)173 174/* FLL6 (0x09) */175#define NAU8821_DCO_EN (0x1 << 15)176#define NAU8821_SDM_EN (0x1 << 14)177#define NAU8821_CUTOFF500 (0x1 << 13)178 179/* FLL7 (0x0a) */180#define NAU8821_FLL_FRACH_MASK 0xff181 182/* FLL8 (0x0b) */183#define NAU8821_FLL_FRACL_MASK 0xffff184 185/* JACK_DET_CTRL (0x0d) */186/* 0 - open, 1 - short to GND */187#define NAU8821_SPKR_DWN1R_SFT 15188#define NAU8821_SPKR_DWN1R (0x1 << NAU8821_SPKR_DWN1R_SFT)189#define NAU8821_SPKR_DWN1L_SFT 14190#define NAU8821_SPKR_DWN1L (0x1 << NAU8821_SPKR_DWN1L_SFT)191#define NAU8821_JACK_DET_RESTART (0x1 << 9)192#define NAU8821_JACK_DET_DB_BYPASS (0x1 << 8)193#define NAU8821_JACK_INSERT_DEBOUNCE_SFT 5194#define NAU8821_JACK_INSERT_DEBOUNCE_MASK (0x7 << NAU8821_JACK_INSERT_DEBOUNCE_SFT)195#define NAU8821_JACK_EJECT_DEBOUNCE_SFT 2196#define NAU8821_JACK_EJECT_DEBOUNCE_MASK (0x7 << NAU8821_JACK_EJECT_DEBOUNCE_SFT)197#define NAU8821_JACK_POLARITY (0x1 << 1) /* 0 - active low, 1 - active high */198 199/* INTERRUPT_MASK (0x0f) */200#define NAU8821_IRQ_PIN_PULL_UP (0x1 << 14)201#define NAU8821_IRQ_PIN_PULL_EN (0x1 << 13)202#define NAU8821_IRQ_OUTPUT_EN (0x1 << 11)203#define NAU8821_IRQ_RMS_EN (0x1 << 8)204#define NAU8821_IRQ_KEY_RELEASE_EN (0x1 << 7)205#define NAU8821_IRQ_KEY_PRESS_EN (0x1 << 6)206#define NAU8821_IRQ_MIC_DET_EN (0x1 << 4)207#define NAU8821_IRQ_EJECT_EN (0x1 << 2)208#define NAU8821_IRQ_INSERT_EN 0x1209 210/* IRQ_STATUS (0x10) */211#define NAU8821_SHORT_CIRCUIT_IRQ (0x1 << 9)212#define NAU8821_IMPEDANCE_MEAS_IRQ (0x1 << 8)213#define NAU8821_KEY_IRQ_SFT 6214#define NAU8821_KEY_IRQ_MASK (0x3 << NAU8821_KEY_IRQ_SFT)215#define NAU8821_KEY_RELEASE_IRQ (0x2 << NAU8821_KEY_IRQ_SFT)216#define NAU8821_KEY_SHORT_PRESS_IRQ (0x1 << NAU8821_KEY_IRQ_SFT)217#define NAU8821_MIC_DETECT_IRQ (0x1 << 4)218#define NAU8821_JACK_EJECT_IRQ_MASK (0x3 << 2)219#define NAU8821_JACK_EJECT_DETECTED (0x1 << 2)220#define NAU8821_JACK_INSERT_IRQ_MASK 0x3221#define NAU8821_JACK_INSERT_DETECTED 0x1222 223/* INTERRUPT_DIS_CTRL (0x12) */224#define NAU8821_IRQ_KEY_RELEASE_DIS (0x1 << 7)225#define NAU8821_IRQ_KEY_PRESS_DIS (0x1 << 6)226#define NAU8821_IRQ_MIC_DIS (0x1 << 4)227#define NAU8821_IRQ_EJECT_DIS (0x1 << 2)228#define NAU8821_IRQ_INSERT_DIS 0x1229 230/* DMIC_CTRL (0x13) */231#define NAU8821_DMIC_DS_SFT 7232#define NAU8821_DMIC_DS_MASK (0x1 << NAU8821_DMIC_DS_SFT)233#define NAU8821_DMIC_DS_HIGH (0x1 << NAU8821_DMIC_DS_SFT)234#define NAU8821_DMIC_DS_LOW (0x0 << NAU8821_DMIC_DS_SFT)235#define NAU8821_DMIC_SRC_SFT 1236#define NAU8821_DMIC_SRC_MASK (0x3 << NAU8821_DMIC_SRC_SFT)237#define NAU8821_CLK_DMIC_SRC (0x2 << NAU8821_DMIC_SRC_SFT)238#define NAU8821_DMIC_EN_SFT 0239#define NAU8821_DMIC_SLEW_SFT 8240#define NAU8821_DMIC_SLEW_MASK (0x7 << NAU8821_DMIC_SLEW_SFT)241 242/* GPIO12_CTRL (0x1a) */243#define NAU8821_JKDET_PULL_UP (0x1 << 11) /* 0 - pull down, 1 - pull up */244#define NAU8821_JKDET_PULL_EN (0x1 << 9) /* 0 - enable pull, 1 - disable */245#define NAU8821_JKDET_OUTPUT_EN (0x1 << 8) /* 0 - enable input, 1 - enable output */246 247/* TDM_CTRL (0x1b) */248#define NAU8821_TDM_EN_SFT 15249#define NAU8821_TDM_EN (0x1 << NAU8821_TDM_EN_SFT)250#define NAU8821_ADCPHS_SFT 13251#define NAU8821_DACL_CH_SFT 7252#define NAU8821_DACL_CH_MASK (0x7 << NAU8821_DACL_CH_SFT)253#define NAU8821_DACR_CH_SFT 4254#define NAU8821_DACR_CH_MASK (0x7 << NAU8821_DACR_CH_SFT)255#define NAU8821_ADCL_CH_SFT 2256#define NAU8821_ADCL_CH_MASK (0x3 << NAU8821_ADCL_CH_SFT)257#define NAU8821_ADCR_CH_SFT 0258#define NAU8821_ADCR_CH_MASK 0x3259 260/* I2S_PCM_CTRL1 (0x1c) */261#define NAU8821_I2S_BP_SFT 7262#define NAU8821_I2S_BP_MASK (0x1 << NAU8821_I2S_BP_SFT)263#define NAU8821_I2S_BP_INV (0x1 << NAU8821_I2S_BP_SFT)264#define NAU8821_I2S_PCMB_SFT 6265#define NAU8821_I2S_PCMB_MASK (0x1 << NAU8821_I2S_PCMB_SFT)266#define NAU8821_I2S_PCMB_EN (0x1 << NAU8821_I2S_PCMB_SFT)267#define NAU8821_I2S_DL_SFT 2268#define NAU8821_I2S_DL_MASK (0x3 << NAU8821_I2S_DL_SFT)269#define NAU8821_I2S_DL_32 (0x3 << NAU8821_I2S_DL_SFT)270#define NAU8821_I2S_DL_24 (0x2 << NAU8821_I2S_DL_SFT)271#define NAU8821_I2S_DL_20 (0x1 << NAU8821_I2S_DL_SFT)272#define NAU8821_I2S_DL_16 (0x0 << NAU8821_I2S_DL_SFT)273#define NAU8821_I2S_DF_MASK 0x3274#define NAU8821_I2S_DF_PCM_AB 0x3275#define NAU8821_I2S_DF_I2S 0x2276#define NAU8821_I2S_DF_LEFT 0x1277#define NAU8821_I2S_DF_RIGTH 0x0278 279/* I2S_PCM_CTRL2 (0x1d) */280#define NAU8821_I2S_TRISTATE_SFT 15281#define NAU8821_I2S_TRISTATE (0x1 << NAU8821_I2S_TRISTATE_SFT)282#define NAU8821_I2S_LRC_DIV_SFT 12283#define NAU8821_I2S_LRC_DIV_MASK (0x3 << NAU8821_I2S_LRC_DIV_SFT)284#define NAU8821_I2S_MS_SFT 3285#define NAU8821_I2S_MS_MASK (0x1 << NAU8821_I2S_MS_SFT)286#define NAU8821_I2S_MS_MASTER (0x1 << NAU8821_I2S_MS_SFT)287#define NAU8821_I2S_MS_SLAVE (0x0 << NAU8821_I2S_MS_SFT)288#define NAU8821_I2S_BLK_DIV_MASK 0x7289 290/* LEFT_TIME_SLOT (0x1e) */291#define NAU8821_TSLOT_L_OFFSET_MASK 0x3ff292#define NAU8821_DIS_FS_SHORT_DET (0x1 << 13)293 294/* RIGHT_TIME_SLOT (0x1f) */295#define NAU8821_TSLOT_R_OFFSET_MASK 0x3ff296 297/* BIQ0_COF10 (0x2a) */298#define NAU8821_BIQ0_ADC_EN_SFT 3299#define NAU8821_BIQ0_ADC_EN_EN (0x1 << NAU8821_BIQ0_ADC_EN_SFT)300 301/* ADC_RATE (0x2b) */302#define NAU8821_ADC_SYNC_DOWN_SFT 0303#define NAU8821_ADC_SYNC_DOWN_MASK 0x3304#define NAU8821_ADC_SYNC_DOWN_256 0x3305#define NAU8821_ADC_SYNC_DOWN_128 0x2306#define NAU8821_ADC_SYNC_DOWN_64 0x1307#define NAU8821_ADC_SYNC_DOWN_32 0x0308#define NAU8821_ADC_L_SRC_SFT 15309#define NAU8821_ADC_L_SRC_EN (0x1 << NAU8821_ADC_L_SRC_SFT)310#define NAU8821_ADC_R_SRC_SFT 14311#define NAU8821_ADC_R_SRC_EN (0x1 << NAU8821_ADC_R_SRC_SFT)312 313/* DAC_CTRL1 (0x2c) */314#define NAU8821_DAC_OVERSAMPLE_SFT 0315#define NAU8821_DAC_OVERSAMPLE_MASK 0x7316#define NAU8821_DAC_OVERSAMPLE_32 0x4317#define NAU8821_DAC_OVERSAMPLE_128 0x2318#define NAU8821_DAC_OVERSAMPLE_256 0x1319#define NAU8821_DAC_OVERSAMPLE_64 0x0320 321/* DAC_DGAIN_CTRL (0x2f) */322#define NAU8821_DAC1_TO_DAC0_ST_SFT 8323#define NAU8821_DAC1_TO_DAC0_ST_MASK (0xff << NAU8821_DAC1_TO_DAC0_ST_SFT)324#define NAU8821_DAC0_TO_DAC1_ST_SFT 0325#define NAU8821_DAC0_TO_DAC1_ST_MASK 0xff326 327/* MUTE_CTRL (0x31) */328#define NAU8821_DAC_ZC_EN (0x1 << 12)329#define NAU8821_DAC_SOFT_MUTE (0x1 << 9)330#define NAU8821_ADC_ZC_EN (0x1 << 2)331#define NAU8821_ADC_SOFT_MUTE (0x1 << 1)332 333/* HSVOL_CTRL (0x32) */334#define NAU8821_HP_MUTE (0x1 << 15)335#define NAU8821_HP_MUTE_AUTO (0x1 << 14)336#define NAU8821_HPL_MUTE (0x1 << 13)337#define NAU8821_HPR_MUTE (0x1 << 12)338#define NAU8821_HPL_VOL_SFT 4339#define NAU8821_HPL_VOL_MASK (0x3 << NAU8821_HPL_VOL_SFT)340#define NAU8821_HPR_VOL_SFT 0341#define NAU8821_HPR_VOL_MASK (0x3 << NAU8821_HPR_VOL_SFT)342 343/* DACR_CTRL (0x34) */344#define NAU8821_DACR_CH_VOL_SFT 8345#define NAU8821_DACR_CH_VOL_MASK (0xff << NAU8821_DACR_CH_VOL_SFT)346#define NAU8821_DACL_CH_VOL_SFT 0347#define NAU8821_DACL_CH_VOL_MASK 0xff348 349/* ADC_DGAIN_CTRL1 (0x35) */350#define NAU8821_ADCR_CH_VOL_SFT 8351#define NAU8821_ADCR_CH_VOL_MASK (0xff << NAU8821_ADCR_CH_VOL_SFT)352#define NAU8821_ADCL_CH_VOL_SFT 0353#define NAU8821_ADCL_CH_VOL_MASK 0xff354 355/* ADC_DRC_KNEE_IP12 (0x36) */356#define NAU8821_DRC_ENA_ADC_SFT 15357#define NAU8821_DRC_ENA_ADC_EN (0x1 << NAU8821_DRC_ENA_ADC_SFT)358 359/* ADC_DRC_KNEE_IP34 (0x37) */360#define NAU8821_DRC_KNEE4_IP_ADC_SFT 8361#define NAU8821_DRC_KNEE4_IP_ADC_MASK (0xff << NAU8821_DRC_KNEE4_IP_ADC_SFT)362#define NAU8821_DRC_KNEE3_IP_ADC_SFT 0363#define NAU8821_DRC_KNEE3_IP_ADC_MASK 0xff364 365/* ADC_DRC_SLOPES (0x38) */366#define NAU8821_DRC_NG_SLP_ADC_SFT 12367#define NAU8821_DRC_EXP_SLP_ADC_SFT 9368#define NAU8821_DRC_CMP2_SLP_ADC_SFT 6369#define NAU8821_DRC_CMP1_SLP_ADC_SFT 3370#define NAU8821_DRC_LMT_SLP_ADC_SFT 0371 372/* ADC_DRC_ATKDCY (0x39) */373#define NAU8821_DRC_PK_COEF1_ADC_SFT 12374#define NAU8821_DRC_PK_COEF2_ADC_SFT 8375#define NAU8821_DRC_ATK_ADC_SFT 4376#define NAU8821_DRC_DCY_ADC_SFT 0377 378/* BIQ1_COF10 (0x4a) */379#define NAU8821_BIQ1_DAC_EN_SFT 3380#define NAU8821_BIQ1_DAC_EN_EN (0x1 << NAU8821_BIQ1_DAC_EN_SFT)381 382/* CLASSG_CTRL (0x4b) */383#define NAU8821_CLASSG_TIMER_SFT 8384#define NAU8821_CLASSG_TIMER_MASK (0x3f << NAU8821_CLASSG_TIMER_SFT)385#define NAU8821_CLASSG_TIMER_64MS (0x20 << NAU8821_CLASSG_TIMER_SFT)386#define NAU8821_CLASSG_TIMER_32MS (0x10 << NAU8821_CLASSG_TIMER_SFT)387#define NAU8821_CLASSG_TIMER_16MS (0x8 << NAU8821_CLASSG_TIMER_SFT)388#define NAU8821_CLASSG_TIMER_8MS (0x4 << NAU8821_CLASSG_TIMER_SFT)389#define NAU8821_CLASSG_TIMER_2MS (0x2 << NAU8821_CLASSG_TIMER_SFT)390#define NAU8821_CLASSG_TIMER_1MS (0x1 << NAU8821_CLASSG_TIMER_SFT)391#define NAU8821_CLASSG_RDAC_EN_SFT 2392#define NAU8821_CLASSG_RDAC_EN (0x1 << NAU8821_CLASSG_RDAC_EN_SFT)393#define NAU8821_CLASSG_LDAC_EN_SFT 1394#define NAU8821_CLASSG_LDAC_EN (0x1 << NAU8821_CLASSG_LDAC_EN_SFT)395#define NAU8821_CLASSG_EN_SFT 0396#define NAU8821_CLASSG_EN 0x1397 398/* IMM_MODE_CTRL (0x4c) */399#define NAU8821_IMM_THD_SFT 8400#define NAU8821_IMM_THD_MASK (0x3f << NAU8821_IMM_THD_SFT)401#define NAU8821_IMM_GEN_VOL_SFT 6402#define NAU8821_IMM_GEN_VOL_MASK (0x3 << NAU8821_IMM_GEN_VOL_SFT)403#define NAU8821_IMM_CYC_SFT 4404#define NAU8821_IMM_CYC_MASK (0x3 << NAU8821_IMM_CYC_SFT)405#define NAU8821_IMM_EN (0x1 << 3)406#define NAU8821_IMM_DAC_SRC_MASK 0x3407 408/* I2C_DEVICE_ID (0x58) */409#define NAU8821_KEYDET (0x1 << 7)410#define NAU8821_MICDET (0x1 << 6)411#define NAU8821_SOFTWARE_ID_MASK 0x3412 413/* BIAS_ADJ (0x66) */414#define NAU8821_BIAS_HP_IMP (0x1 << 15)415#define NAU8821_BIAS_TESTDAC_SFT 8416#define NAU8821_BIAS_TESTDAC_EN (0x3 << NAU8821_BIAS_TESTDAC_SFT)417#define NAU8821_BIAS_TESTDACR_EN (0x2 << NAU8821_BIAS_TESTDAC_SFT)418#define NAU8821_BIAS_TESTDACL_EN (0x1 << NAU8821_BIAS_TESTDAC_SFT)419#define NAU8821_BIAS_VMID (0x1 << 6)420#define NAU8821_BIAS_VMID_SEL_SFT 4421#define NAU8821_BIAS_VMID_SEL_MASK (0x3 << NAU8821_BIAS_VMID_SEL_SFT)422 423/* ANALOG_CONTROL_1 (0x69) */424#define NAU8821_JD_POL_SFT 2425#define NAU8821_JD_POL_MASK (0x1 << NAU8821_JD_POL_SFT)426#define NAU8821_JD_POL_INV (0x1 << NAU8821_JD_POL_SFT)427#define NAU8821_JD_OUT_POL_SFT 1428#define NAU8821_JD_OUT_POL_MASK (0x1 << NAU8821_JD_OUT_POL_SFT)429#define NAU8821_JD_OUT_POL_INV (0x1 << NAU8821_JD_OUT_POL_SFT)430#define NAU8821_JD_EN_SFT 0431#define NAU8821_JD_EN 0x1432 433/* ANALOG_CONTROL_2 (0x6a) */434#define NAU8821_HP_NON_CLASSG_CURRENT_2xADJ (0x1 << 12)435#define NAU8821_DAC_CAPACITOR_MSB (0x1 << 1)436#define NAU8821_DAC_CAPACITOR_LSB 0x1437 438/* MUTE_MIC_L_N (0x6b) */439#define NAU8821_MUTE_MICNL_SFT 5440#define NAU8821_MUTE_MICNL_EN (0x1 << NAU8821_MUTE_MICNL_SFT)441#define NAU8821_MUTE_MICNR_SFT 4442#define NAU8821_MUTE_MICNR_EN (0x1 << NAU8821_MUTE_MICNR_SFT)443#define NAU8821_MUTE_MICRP_SFT 2444#define NAU8821_MUTE_MICRP_EN (0x1 << NAU8821_MUTE_MICRP_SFT)445 446/* ANALOG_ADC_1 (0x71) */447#define NAU8821_MICDET_EN_SFT 0448#define NAU8821_MICDET_MASK 0x1449#define NAU8821_MICDET_DIS 0x1450#define NAU8821_MICDET_EN 0x0451 452/* ANALOG_ADC_2 (0x72) */453#define NAU8821_ADC_VREFSEL_SFT 8454#define NAU8821_ADC_VREFSEL_MASK (0x3 << NAU8821_ADC_VREFSEL_SFT)455#define NAU8821_POWERUP_ADCL_SFT 6456#define NAU8821_POWERUP_ADCL (0x1 << NAU8821_POWERUP_ADCL_SFT)457#define NAU8821_POWERUP_ADCR_SFT 4458#define NAU8821_POWERUP_ADCR (0x1 << NAU8821_POWERUP_ADCR_SFT)459 460/* RDAC (0x73) */461#define NAU8821_DACR_EN_SFT 13462#define NAU8821_DACR_EN (0x3 << NAU8821_DACR_EN_SFT)463#define NAU8821_DACL_EN_SFT 12464#define NAU8821_DACL_EN (0x3 << NAU8821_DACL_EN_SFT)465#define NAU8821_DACR_CLK_EN_SFT 9466#define NAU8821_DACR_CLK_EN (0x3 << NAU8821_DACR_CLK_EN_SFT)467#define NAU8821_DACL_CLK_EN_SFT 8468#define NAU8821_DACL_CLK_EN (0x3 << NAU8821_DACL_CLK_EN_SFT)469#define NAU8821_DAC_CLK_DELAY_SFT 4470#define NAU8821_DAC_CLK_DELAY_MASK (0x7 << NAU8821_DAC_CLK_DELAY_SFT)471#define NAU8821_DAC_VREF_SFT 2472#define NAU8821_DAC_VREF_MASK (0x3 << NAU8821_DAC_VREF_SFT)473 474/* MIC_BIAS (0x74) */475#define NAU8821_MICBIAS_JKR2 (0x1 << 12)476#define NAU8821_MICBIAS_LOWNOISE_SFT 10477#define NAU8821_MICBIAS_LOWNOISE_EN (0x1 << NAU8821_MICBIAS_LOWNOISE_SFT)478#define NAU8821_MICBIAS_POWERUP_SFT 8479#define NAU8821_MICBIAS_POWERUP_EN (0x1 << NAU8821_MICBIAS_POWERUP_SFT)480#define NAU8821_MICBIAS_VOLTAGE_SFT 0481#define NAU8821_MICBIAS_VOLTAGE_MASK 0x7482 483/* BOOST (0x76) */484#define NAU8821_PRECHARGE_DIS (0x1 << 13)485#define NAU8821_GLOBAL_BIAS_EN (0x1 << 12)486#define NAU8821_HP_BOOST_DISCHRG_SFT 11487#define NAU8821_HP_BOOST_DISCHRG_EN (0x1 << NAU8821_HP_BOOST_DISCHRG_SFT)488#define NAU8821_HP_BOOST_DIS_SFT 9489#define NAU8821_HP_BOOST_DIS (0x1 << NAU8821_HP_BOOST_DIS_SFT)490#define NAU8821_HP_BOOST_G_DIS (0x1 << 8)491#define NAU8821_SHORT_SHUTDOWN_EN (0x1 << 6)492 493/* FEPGA (0x77) */494#define NAU8821_ACDC_CTRL_SFT 14495#define NAU8821_ACDC_CTRL_MASK (0x3 << NAU8821_ACDC_CTRL_SFT)496#define NAU8821_ACDC_VREF_MICP (0x1 << NAU8821_ACDC_CTRL_SFT)497#define NAU8821_ACDC_VREF_MICN (0x2 << NAU8821_ACDC_CTRL_SFT)498#define NAU8821_FEPGA_MODEL_SFT 4499#define NAU8821_FEPGA_MODEL_MASK (0xf << NAU8821_FEPGA_MODEL_SFT)500#define NAU8821_FEPGA_MODEL_AAF (0x1 << NAU8821_FEPGA_MODEL_SFT)501#define NAU8821_FEPGA_MODEL_DIS (0x2 << NAU8821_FEPGA_MODEL_SFT)502#define NAU8821_FEPGA_MODEL_IMP12K (0x8 << NAU8821_FEPGA_MODEL_SFT)503#define NAU8821_FEPGA_MODER_SFT 0504#define NAU8821_FEPGA_MODER_MASK 0xf505#define NAU8821_FEPGA_MODER_AAF 0x1506#define NAU8821_FEPGA_MODER_DIS 0x2507#define NAU8821_FEPGA_MODER_IMP12K 0x8508 509 510/* PGA_GAIN (0x7e) */511#define NAU8821_PGA_GAIN_L_SFT 8512#define NAU8821_PGA_GAIN_L_MASK (0x3f << NAU8821_PGA_GAIN_L_SFT)513#define NAU8821_PGA_GAIN_R_SFT 0514#define NAU8821_PGA_GAIN_R_MASK 0x3f515 516/* POWER_UP_CONTROL (0x7f) */517#define NAU8821_PUP_PGA_L_SFT 15518#define NAU8821_PUP_PGA_L (0x1 << NAU8821_PUP_PGA_L_SFT)519#define NAU8821_PUP_PGA_R_SFT 14520#define NAU8821_PUP_PGA_R (0x1 << NAU8821_PUP_PGA_R_SFT)521#define NAU8821_PUP_INTEG_R_SFT 5522#define NAU8821_PUP_INTEG_R (0x1 << NAU8821_PUP_INTEG_R_SFT)523#define NAU8821_PUP_INTEG_L_SFT 4524#define NAU8821_PUP_INTEG_L (0x1 << NAU8821_PUP_INTEG_L_SFT)525#define NAU8821_PUP_DRV_INSTG_R_SFT 3526#define NAU8821_PUP_DRV_INSTG_R (0x1 << NAU8821_PUP_DRV_INSTG_R_SFT)527#define NAU8821_PUP_DRV_INSTG_L_SFT 2528#define NAU8821_PUP_DRV_INSTG_L (0x1 << NAU8821_PUP_DRV_INSTG_L_SFT)529#define NAU8821_PUP_MAIN_DRV_R_SFT 1530#define NAU8821_PUP_MAIN_DRV_R (0x1 << NAU8821_PUP_MAIN_DRV_R_SFT)531#define NAU8821_PUP_MAIN_DRV_L_SFT 0532#define NAU8821_PUP_MAIN_DRV_L 0x1533 534/* CHARGE_PUMP (0x80) */535#define NAU8821_JAMNODCLOW (0x1 << 10)536#define NAU8821_POWER_DOWN_DACR_SFT 9537#define NAU8821_POWER_DOWN_DACR (0x1 << NAU8821_POWER_DOWN_DACR_SFT)538#define NAU8821_POWER_DOWN_DACL_SFT 8539#define NAU8821_POWER_DOWN_DACL (0x1 << NAU8821_POWER_DOWN_DACL_SFT)540#define NAU8821_CHANRGE_PUMP_EN_SFT 5541#define NAU8821_CHANRGE_PUMP_EN (0x1 << NAU8821_CHANRGE_PUMP_EN_SFT)542 543/* GENERAL_STATUS (0x82) */544#define NAU8821_GPIO2_IN_SFT 1545#define NAU8821_GPIO2_IN (0x1 << NAU8821_GPIO2_IN_SFT)546 547#define NUVOTON_CODEC_DAI "nau8821-hifi"548 549/* System Clock Source */550enum {551 NAU8821_CLK_DIS,552 NAU8821_CLK_MCLK,553 NAU8821_CLK_INTERNAL,554 NAU8821_CLK_FLL_MCLK,555 NAU8821_CLK_FLL_BLK,556 NAU8821_CLK_FLL_FS,557};558 559struct nau8821 {560 struct device *dev;561 struct regmap *regmap;562 struct snd_soc_dapm_context *dapm;563 struct snd_soc_jack *jack;564 struct work_struct jdet_work;565 int irq;566 int clk_id;567 int micbias_voltage;568 int vref_impedance;569 bool jkdet_enable;570 bool jkdet_pull_enable;571 bool jkdet_pull_up;572 bool left_input_single_end;573 int jkdet_polarity;574 int jack_insert_debounce;575 int jack_eject_debounce;576 int fs;577 int dmic_clk_threshold;578 int dmic_slew_rate;579 int key_enable;580 int adc_delay;581};582 583int nau8821_enable_jack_detect(struct snd_soc_component *component,584 struct snd_soc_jack *jack);585 586#endif /* __NAU8821_H__ */587