225 lines · c
1/* SPDX-License-Identifier: GPL-2.0 */2/*3 * nau8822.h -- NAU8822 ALSA SoC Audio driver4 *5 * Copyright 2017 Nuvoton Technology Crop.6 *7 * Author: David Lin <ctlin0@nuvoton.com>8 * Co-author: John Hsu <kchsu0@nuvoton.com>9 * Co-author: Seven Li <wtli@nuvoton.com>10 */11 12#ifndef __NAU8822_H__13#define __NAU8822_H__14 15#define NAU8822_REG_RESET 0x0016#define NAU8822_REG_POWER_MANAGEMENT_1 0x0117#define NAU8822_REG_POWER_MANAGEMENT_2 0x0218#define NAU8822_REG_POWER_MANAGEMENT_3 0x0319#define NAU8822_REG_AUDIO_INTERFACE 0x0420#define NAU8822_REG_COMPANDING_CONTROL 0x0521#define NAU8822_REG_CLOCKING 0x0622#define NAU8822_REG_ADDITIONAL_CONTROL 0x0723#define NAU8822_REG_GPIO_CONTROL 0x0824#define NAU8822_REG_JACK_DETECT_CONTROL_1 0x0925#define NAU8822_REG_DAC_CONTROL 0x0A26#define NAU8822_REG_LEFT_DAC_DIGITAL_VOLUME 0x0B27#define NAU8822_REG_RIGHT_DAC_DIGITAL_VOLUME 0x0C28#define NAU8822_REG_JACK_DETECT_CONTROL_2 0x0D29#define NAU8822_REG_ADC_CONTROL 0x0E30#define NAU8822_REG_LEFT_ADC_DIGITAL_VOLUME 0x0F31#define NAU8822_REG_RIGHT_ADC_DIGITAL_VOLUME 0x1032#define NAU8822_REG_EQ1 0x1233#define NAU8822_REG_EQ2 0x1334#define NAU8822_REG_EQ3 0x1435#define NAU8822_REG_EQ4 0x1536#define NAU8822_REG_EQ5 0x1637#define NAU8822_REG_DAC_LIMITER_1 0x1838#define NAU8822_REG_DAC_LIMITER_2 0x1939#define NAU8822_REG_NOTCH_FILTER_1 0x1B40#define NAU8822_REG_NOTCH_FILTER_2 0x1C41#define NAU8822_REG_NOTCH_FILTER_3 0x1D42#define NAU8822_REG_NOTCH_FILTER_4 0x1E43#define NAU8822_REG_ALC_CONTROL_1 0x2044#define NAU8822_REG_ALC_CONTROL_2 0x2145#define NAU8822_REG_ALC_CONTROL_3 0x2246#define NAU8822_REG_NOISE_GATE 0x2347#define NAU8822_REG_PLL_N 0x2448#define NAU8822_REG_PLL_K1 0x2549#define NAU8822_REG_PLL_K2 0x2650#define NAU8822_REG_PLL_K3 0x2751#define NAU8822_REG_3D_CONTROL 0x2952#define NAU8822_REG_RIGHT_SPEAKER_CONTROL 0x2B53#define NAU8822_REG_INPUT_CONTROL 0x2C54#define NAU8822_REG_LEFT_INP_PGA_CONTROL 0x2D55#define NAU8822_REG_RIGHT_INP_PGA_CONTROL 0x2E56#define NAU8822_REG_LEFT_ADC_BOOST_CONTROL 0x2F57#define NAU8822_REG_RIGHT_ADC_BOOST_CONTROL 0x3058#define NAU8822_REG_OUTPUT_CONTROL 0x3159#define NAU8822_REG_LEFT_MIXER_CONTROL 0x3260#define NAU8822_REG_RIGHT_MIXER_CONTROL 0x3361#define NAU8822_REG_LHP_VOLUME 0x3462#define NAU8822_REG_RHP_VOLUME 0x3563#define NAU8822_REG_LSPKOUT_VOLUME 0x3664#define NAU8822_REG_RSPKOUT_VOLUME 0x3765#define NAU8822_REG_AUX2_MIXER 0x3866#define NAU8822_REG_AUX1_MIXER 0x3967#define NAU8822_REG_POWER_MANAGEMENT_4 0x3A68#define NAU8822_REG_LEFT_TIME_SLOT 0x3B69#define NAU8822_REG_MISC 0x3C70#define NAU8822_REG_RIGHT_TIME_SLOT 0x3D71#define NAU8822_REG_DEVICE_REVISION 0x3E72#define NAU8822_REG_DEVICE_ID 0x3F73#define NAU8822_REG_DAC_DITHER 0x4174#define NAU8822_REG_ALC_ENHANCE_1 0x4675#define NAU8822_REG_ALC_ENHANCE_2 0x4776#define NAU8822_REG_192KHZ_SAMPLING 0x4877#define NAU8822_REG_MISC_CONTROL 0x4978#define NAU8822_REG_INPUT_TIEOFF 0x4A79#define NAU8822_REG_POWER_REDUCTION 0x4B80#define NAU8822_REG_AGC_PEAK2PEAK 0x4C81#define NAU8822_REG_AGC_PEAK_DETECT 0x4D82#define NAU8822_REG_AUTOMUTE_CONTROL 0x4E83#define NAU8822_REG_OUTPUT_TIEOFF 0x4F84#define NAU8822_REG_MAX_REGISTER NAU8822_REG_OUTPUT_TIEOFF85 86/* NAU8822_REG_POWER_MANAGEMENT_1 (0x1) */87#define NAU8822_REFIMP_MASK 0x388#define NAU8822_REFIMP_80K 0x189#define NAU8822_REFIMP_300K 0x290#define NAU8822_REFIMP_3K 0x391#define NAU8822_IOBUF_EN (0x1 << 2)92#define NAU8822_ABIAS_EN (0x1 << 3)93#define NAU8822_PLL_EN_MASK (0x1 << 5)94#define NAU8822_PLL_ON (0x1 << 5)95#define NAU8822_PLL_OFF (0x0 << 5)96 97/* NAU8822_REG_AUDIO_INTERFACE (0x4) */98#define NAU8822_AIFMT_MASK (0x3 << 3)99#define NAU8822_WLEN_MASK (0x3 << 5)100#define NAU8822_WLEN_20 (0x1 << 5)101#define NAU8822_WLEN_24 (0x2 << 5)102#define NAU8822_WLEN_32 (0x3 << 5)103#define NAU8822_LRP_MASK (0x1 << 7)104#define NAU8822_BCLKP_MASK (0x1 << 8)105 106/* NAU8822_REG_COMPANDING_CONTROL (0x5) */107#define NAU8822_ADDAP_SFT 0108#define NAU8822_ADCCM_SFT 1109#define NAU8822_DACCM_SFT 3110 111/* NAU8822_REG_CLOCKING (0x6) */112#define NAU8822_CLKIOEN_MASK 0x1113#define NAU8822_CLK_MASTER 0x1114#define NAU8822_CLK_SLAVE 0x0115#define NAU8822_MCLKSEL_SFT 5116#define NAU8822_MCLKSEL_MASK (0x7 << 5)117#define NAU8822_BCLKSEL_SFT 2118#define NAU8822_BCLKSEL_MASK (0x7 << 2)119#define NAU8822_BCLKDIV_1 (0x0 << 2)120#define NAU8822_BCLKDIV_2 (0x1 << 2)121#define NAU8822_BCLKDIV_4 (0x2 << 2)122#define NAU8822_BCLKDIV_8 (0x3 << 2)123#define NAU8822_BCLKDIV_16 (0x4 << 2)124#define NAU8822_CLKM_MASK (0x1 << 8)125#define NAU8822_CLKM_MCLK (0x0 << 8)126#define NAU8822_CLKM_PLL (0x1 << 8)127 128/* NAU8822_REG_ADDITIONAL_CONTROL (0x08) */129#define NAU8822_SMPLR_SFT 1130#define NAU8822_SMPLR_MASK (0x7 << 1)131#define NAU8822_SMPLR_48K (0x0 << 1)132#define NAU8822_SMPLR_32K (0x1 << 1)133#define NAU8822_SMPLR_24K (0x2 << 1)134#define NAU8822_SMPLR_16K (0x3 << 1)135#define NAU8822_SMPLR_12K (0x4 << 1)136#define NAU8822_SMPLR_8K (0x5 << 1)137 138/* NAU8822_REG_EQ1 (0x12) */139#define NAU8822_EQ1GC_SFT 0140#define NAU8822_EQ1CF_SFT 5141#define NAU8822_EQM_SFT 8142 143/* NAU8822_REG_EQ2 (0x13) */144#define NAU8822_EQ2GC_SFT 0145#define NAU8822_EQ2CF_SFT 5146#define NAU8822_EQ2BW_SFT 8147 148/* NAU8822_REG_EQ3 (0x14) */149#define NAU8822_EQ3GC_SFT 0150#define NAU8822_EQ3CF_SFT 5151#define NAU8822_EQ3BW_SFT 8152 153/* NAU8822_REG_EQ4 (0x15) */154#define NAU8822_EQ4GC_SFT 0155#define NAU8822_EQ4CF_SFT 5156#define NAU8822_EQ4BW_SFT 8157 158/* NAU8822_REG_EQ5 (0x16) */159#define NAU8822_EQ5GC_SFT 0160#define NAU8822_EQ5CF_SFT 5161 162/* NAU8822_REG_ALC_CONTROL_1 (0x20) */163#define NAU8822_ALCMINGAIN_SFT 0164#define NAU8822_ALCMXGAIN_SFT 3165#define NAU8822_ALCEN_SFT 7166 167/* NAU8822_REG_ALC_CONTROL_2 (0x21) */168#define NAU8822_ALCSL_SFT 0169#define NAU8822_ALCHT_SFT 4170 171/* NAU8822_REG_ALC_CONTROL_3 (0x22) */172#define NAU8822_ALCATK_SFT 0173#define NAU8822_ALCDCY_SFT 4174#define NAU8822_ALCM_SFT 8175 176/* NAU8822_REG_PLL_N (0x24) */177#define NAU8822_PLLMCLK_DIV2 (0x1 << 4)178#define NAU8822_PLLN_MASK 0xF179 180#define NAU8822_PLLK1_SFT 18181#define NAU8822_PLLK1_MASK 0x3F182 183/* NAU8822_REG_PLL_K2 (0x26) */184#define NAU8822_PLLK2_SFT 9185#define NAU8822_PLLK2_MASK 0x1FF186 187/* NAU8822_REG_PLL_K3 (0x27) */188#define NAU8822_PLLK3_MASK 0x1FF189 190/* NAU8822_REG_RIGHT_SPEAKER_CONTROL (0x2B) */191#define NAU8822_RMIXMUT 0x20192#define NAU8822_RSUBBYP 0x10193 194#define NAU8822_RAUXRSUBG_SFT 1195#define NAU8822_RAUXRSUBG_MASK 0x0E196 197#define NAU8822_RAUXSMUT 0x01198 199/* System Clock Source */200enum {201 NAU8822_CLK_MCLK,202 NAU8822_CLK_PLL,203};204 205struct nau8822_pll {206 int pre_factor;207 int mclk_scaler;208 int pll_frac;209 int pll_int;210 int freq_in;211 int freq_out;212};213 214/* Codec Private Data */215struct nau8822 {216 struct device *dev;217 struct regmap *regmap;218 struct clk *mclk;219 struct nau8822_pll pll;220 int sysclk;221 int div_id;222};223 224#endif /* __NAU8822_H__ */225