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1/* SPDX-License-Identifier: GPL-2.0-only */2/*3 * Rockchip RK3308 internal audio codec driver -- register definitions4 *5 * Copyright (c) 2018, Fuzhou Rockchip Electronics Co., Ltd All rights reserved.6 * Copyright (c) 2022, Vivax-Metrotech Ltd7 */8 9#ifndef __RK3308_CODEC_H__10#define __RK3308_CODEC_H__11 12#define RK3308_GLB_CON 0x0013 14/* ADC DIGITAL REGISTERS */15 16/*17 * The ADC group are 0 ~ 3, that control:18 *19 * CH0: left_0(ADC1) and right_0(ADC2)20 * CH1: left_1(ADC3) and right_1(ADC4)21 * CH2: left_2(ADC5) and right_2(ADC6)22 * CH3: left_3(ADC7) and right_3(ADC8)23 */24#define RK3308_ADC_DIG_OFFSET(ch) (((ch) & 0x3) * 0xc0 + 0x0)25 26#define RK3308_ADC_DIG_CON01(ch) (RK3308_ADC_DIG_OFFSET((ch)) + 0x04)27#define RK3308_ADC_DIG_CON02(ch) (RK3308_ADC_DIG_OFFSET((ch)) + 0x08)28#define RK3308_ADC_DIG_CON03(ch) (RK3308_ADC_DIG_OFFSET((ch)) + 0x0c)29#define RK3308_ADC_DIG_CON04(ch) (RK3308_ADC_DIG_OFFSET((ch)) + 0x10)30#define RK3308_ADC_DIG_CON05(ch) (RK3308_ADC_DIG_OFFSET((ch)) + 0x14) // ver.C only31#define RK3308_ADC_DIG_CON06(ch) (RK3308_ADC_DIG_OFFSET((ch)) + 0x18) // ver.C only32#define RK3308_ADC_DIG_CON07(ch) (RK3308_ADC_DIG_OFFSET((ch)) + 0x1c)33 34#define RK3308_ALC_L_DIG_CON00(ch) (RK3308_ADC_DIG_OFFSET((ch)) + 0x40)35#define RK3308_ALC_L_DIG_CON01(ch) (RK3308_ADC_DIG_OFFSET((ch)) + 0x44)36#define RK3308_ALC_L_DIG_CON02(ch) (RK3308_ADC_DIG_OFFSET((ch)) + 0x48)37#define RK3308_ALC_L_DIG_CON03(ch) (RK3308_ADC_DIG_OFFSET((ch)) + 0x4c)38#define RK3308_ALC_L_DIG_CON04(ch) (RK3308_ADC_DIG_OFFSET((ch)) + 0x50)39#define RK3308_ALC_L_DIG_CON05(ch) (RK3308_ADC_DIG_OFFSET((ch)) + 0x54)40#define RK3308_ALC_L_DIG_CON06(ch) (RK3308_ADC_DIG_OFFSET((ch)) + 0x58)41#define RK3308_ALC_L_DIG_CON07(ch) (RK3308_ADC_DIG_OFFSET((ch)) + 0x5c)42#define RK3308_ALC_L_DIG_CON08(ch) (RK3308_ADC_DIG_OFFSET((ch)) + 0x60)43#define RK3308_ALC_L_DIG_CON09(ch) (RK3308_ADC_DIG_OFFSET((ch)) + 0x64)44#define RK3308_ALC_L_DIG_CON12(ch) (RK3308_ADC_DIG_OFFSET((ch)) + 0x70)45 46#define RK3308_ALC_R_DIG_CON00(ch) (RK3308_ADC_DIG_OFFSET((ch)) + 0x80)47#define RK3308_ALC_R_DIG_CON01(ch) (RK3308_ADC_DIG_OFFSET((ch)) + 0x84)48#define RK3308_ALC_R_DIG_CON02(ch) (RK3308_ADC_DIG_OFFSET((ch)) + 0x88)49#define RK3308_ALC_R_DIG_CON03(ch) (RK3308_ADC_DIG_OFFSET((ch)) + 0x8c)50#define RK3308_ALC_R_DIG_CON04(ch) (RK3308_ADC_DIG_OFFSET((ch)) + 0x90)51#define RK3308_ALC_R_DIG_CON05(ch) (RK3308_ADC_DIG_OFFSET((ch)) + 0x94)52#define RK3308_ALC_R_DIG_CON06(ch) (RK3308_ADC_DIG_OFFSET((ch)) + 0x98)53#define RK3308_ALC_R_DIG_CON07(ch) (RK3308_ADC_DIG_OFFSET((ch)) + 0x9c)54#define RK3308_ALC_R_DIG_CON08(ch) (RK3308_ADC_DIG_OFFSET((ch)) + 0xa0)55#define RK3308_ALC_R_DIG_CON09(ch) (RK3308_ADC_DIG_OFFSET((ch)) + 0xa4)56#define RK3308_ALC_R_DIG_CON12(ch) (RK3308_ADC_DIG_OFFSET((ch)) + 0xb0)57 58/* DAC DIGITAL REGISTERS */59#define RK3308_DAC_DIG_OFFSET 0x30060#define RK3308_DAC_DIG_CON01 (RK3308_DAC_DIG_OFFSET + 0x04)61#define RK3308_DAC_DIG_CON02 (RK3308_DAC_DIG_OFFSET + 0x08)62#define RK3308_DAC_DIG_CON03 (RK3308_DAC_DIG_OFFSET + 0x0c)63#define RK3308_DAC_DIG_CON04 (RK3308_DAC_DIG_OFFSET + 0x10)64#define RK3308_DAC_DIG_CON05 (RK3308_DAC_DIG_OFFSET + 0x14)65#define RK3308_DAC_DIG_CON10 (RK3308_DAC_DIG_OFFSET + 0x28)66#define RK3308_DAC_DIG_CON11 (RK3308_DAC_DIG_OFFSET + 0x2c)67#define RK3308_DAC_DIG_CON13 (RK3308_DAC_DIG_OFFSET + 0x34)68#define RK3308_DAC_DIG_CON14 (RK3308_DAC_DIG_OFFSET + 0x38)69 70/* ADC ANALOG REGISTERS */71/*72 * The ADC group are 0 ~ 3, that control:73 *74 * CH0: left_0(ADC1) and right_0(ADC2)75 * CH1: left_1(ADC3) and right_1(ADC4)76 * CH2: left_2(ADC5) and right_2(ADC6)77 * CH3: left_3(ADC7) and right_3(ADC8)78 */79#define RK3308_ADC_ANA_OFFSET(ch) (((ch) & 0x3) * 0x40 + 0x340)80#define RK3308_ADC_ANA_CON00(ch) (RK3308_ADC_ANA_OFFSET((ch)) + 0x00)81#define RK3308_ADC_ANA_CON01(ch) (RK3308_ADC_ANA_OFFSET((ch)) + 0x04)82#define RK3308_ADC_ANA_CON02(ch) (RK3308_ADC_ANA_OFFSET((ch)) + 0x08)83#define RK3308_ADC_ANA_CON03(ch) (RK3308_ADC_ANA_OFFSET((ch)) + 0x0c)84#define RK3308_ADC_ANA_CON04(ch) (RK3308_ADC_ANA_OFFSET((ch)) + 0x10)85#define RK3308_ADC_ANA_CON05(ch) (RK3308_ADC_ANA_OFFSET((ch)) + 0x14)86#define RK3308_ADC_ANA_CON06(ch) (RK3308_ADC_ANA_OFFSET((ch)) + 0x18)87#define RK3308_ADC_ANA_CON07(ch) (RK3308_ADC_ANA_OFFSET((ch)) + 0x1c)88#define RK3308_ADC_ANA_CON08(ch) (RK3308_ADC_ANA_OFFSET((ch)) + 0x20)89#define RK3308_ADC_ANA_CON10(ch) (RK3308_ADC_ANA_OFFSET((ch)) + 0x28)90#define RK3308_ADC_ANA_CON11(ch) (RK3308_ADC_ANA_OFFSET((ch)) + 0x2c)91 92/* DAC ANALOG REGISTERS */93#define RK3308_DAC_ANA_OFFSET 0x44094#define RK3308_DAC_ANA_CON00 (RK3308_DAC_ANA_OFFSET + 0x00)95#define RK3308_DAC_ANA_CON01 (RK3308_DAC_ANA_OFFSET + 0x04)96#define RK3308_DAC_ANA_CON02 (RK3308_DAC_ANA_OFFSET + 0x08)97#define RK3308_DAC_ANA_CON03 (RK3308_DAC_ANA_OFFSET + 0x0c)98#define RK3308_DAC_ANA_CON04 (RK3308_DAC_ANA_OFFSET + 0x10)99#define RK3308_DAC_ANA_CON05 (RK3308_DAC_ANA_OFFSET + 0x14)100#define RK3308_DAC_ANA_CON06 (RK3308_DAC_ANA_OFFSET + 0x18)101#define RK3308_DAC_ANA_CON07 (RK3308_DAC_ANA_OFFSET + 0x1c)102#define RK3308_DAC_ANA_CON08 (RK3308_DAC_ANA_OFFSET + 0x20)103#define RK3308_DAC_ANA_CON12 (RK3308_DAC_ANA_OFFSET + 0x30)104#define RK3308_DAC_ANA_CON13 (RK3308_DAC_ANA_OFFSET + 0x34)105#define RK3308_DAC_ANA_CON14 (RK3308_DAC_ANA_OFFSET + 0x38)106#define RK3308_DAC_ANA_CON15 (RK3308_DAC_ANA_OFFSET + 0x3c)107 108/*109 * These are the bits for registers110 */111 112/* RK3308_GLB_CON - REG: 0x0000 */113#define RK3308_ADC_BIST_WORK BIT(7)114#define RK3308_DAC_BIST_WORK BIT(6)115#define RK3308_ADC_MCLK_GATING BIT(5)116#define RK3308_DAC_MCLK_GATING BIT(4)117#define RK3308_ADC_DIG_WORK BIT(2)118#define RK3308_DAC_DIG_WORK BIT(1)119#define RK3308_SYS_WORK BIT(0)120 121/* RK3308_ADC_DIG_CON01 - REG: 0x0004 */122#define RK3308_ADC_I2S_LRC_POL_REVERSAL BIT(7)123#define RK3308_ADC_I2S_VALID_LEN_SFT 5124#define RK3308_ADC_I2S_VALID_LEN_MSK (0x3 << RK3308_ADC_I2S_VALID_LEN_SFT)125#define RK3308_ADC_I2S_VALID_LEN_32BITS (0x3 << RK3308_ADC_I2S_VALID_LEN_SFT)126#define RK3308_ADC_I2S_VALID_LEN_24BITS (0x2 << RK3308_ADC_I2S_VALID_LEN_SFT)127#define RK3308_ADC_I2S_VALID_LEN_20BITS (0x1 << RK3308_ADC_I2S_VALID_LEN_SFT)128#define RK3308_ADC_I2S_VALID_LEN_16BITS (0x0 << RK3308_ADC_I2S_VALID_LEN_SFT)129#define RK3308_ADC_I2S_MODE_SFT 3130#define RK3308_ADC_I2S_MODE_MSK (0x3 << RK3308_ADC_I2S_MODE_SFT)131#define RK3308_ADC_I2S_MODE_PCM (0x3 << RK3308_ADC_I2S_MODE_SFT)132#define RK3308_ADC_I2S_MODE_I2S (0x2 << RK3308_ADC_I2S_MODE_SFT)133#define RK3308_ADC_I2S_MODE_LJ (0x1 << RK3308_ADC_I2S_MODE_SFT)134#define RK3308_ADC_I2S_MODE_RJ (0x0 << RK3308_ADC_I2S_MODE_SFT)135#define RK3308_ADC_I2S_LR_SWAP BIT(1)136#define RK3308_ADC_I2S_MONO BIT(0)137 138/* RK3308_ADC_DIG_CON02 - REG: 0x0008 */139#define RK3308_ADC_IO_MODE_MASTER BIT(5)140#define RK3308_ADC_MODE_MASTER BIT(4)141#define RK3308_ADC_I2S_FRAME_LEN_SFT 2142#define RK3308_ADC_I2S_FRAME_LEN_MSK (0x3 << RK3308_ADC_I2S_FRAME_LEN_SFT)143#define RK3308_ADC_I2S_FRAME_32BITS (0x3 << RK3308_ADC_I2S_FRAME_LEN_SFT)144#define RK3308_ADC_I2S_FRAME_24BITS (0x2 << RK3308_ADC_I2S_FRAME_LEN_SFT)145#define RK3308_ADC_I2S_FRAME_20BITS (0x1 << RK3308_ADC_I2S_FRAME_LEN_SFT)146#define RK3308_ADC_I2S_FRAME_16BITS (0x0 << RK3308_ADC_I2S_FRAME_LEN_SFT)147#define RK3308_ADC_I2S_WORK BIT(1)148#define RK3308_ADC_I2S_BIT_CLK_POL_REVERSAL BIT(0)149 150/* RK3308_ADC_DIG_CON03 - REG: 0x000c */151#define RK3308_ADC_L_CH_BIST_SFT 2152#define RK3308_ADC_L_CH_BIST_MSK (0x3 << RK3308_ADC_L_CH_BIST_SFT)153#define RK3308_ADC_L_CH_NORMAL_RIGHT (0x3 << RK3308_ADC_L_CH_BIST_SFT) /* normal mode */154#define RK3308_ADC_L_CH_BIST_CUBE (0x2 << RK3308_ADC_L_CH_BIST_SFT)155#define RK3308_ADC_L_CH_BIST_SINE (0x1 << RK3308_ADC_L_CH_BIST_SFT)156#define RK3308_ADC_L_CH_NORMAL_LEFT (0x0 << RK3308_ADC_L_CH_BIST_SFT) /* normal mode */157#define RK3308_ADC_R_CH_BIST_SFT 0158#define RK3308_ADC_R_CH_BIST_MSK (0x3 << RK3308_ADC_R_CH_BIST_SFT)159#define RK3308_ADC_R_CH_NORMAL_LEFT (0x3 << RK3308_ADC_R_CH_BIST_SFT) /* normal mode */160#define RK3308_ADC_R_CH_BIST_CUBE (0x2 << RK3308_ADC_R_CH_BIST_SFT)161#define RK3308_ADC_R_CH_BIST_SINE (0x1 << RK3308_ADC_R_CH_BIST_SFT)162#define RK3308_ADC_R_CH_NORMAL_RIGHT (0x0 << RK3308_ADC_R_CH_BIST_SFT) /* normal mode */163 164/* RK3308_ADC_DIG_CON04 - REG: 0x0010 */165#define RK3308_ADC_HPF_PATH_DIS BIT(2)166#define RK3308_ADC_HPF_CUTOFF_SFT 0167#define RK3308_ADC_HPF_CUTOFF_MSK (0x3 << RK3308_ADC_HPF_CUTOFF_SFT)168#define RK3308_ADC_HPF_CUTOFF_612HZ (0x2 << RK3308_ADC_HPF_CUTOFF_SFT)169#define RK3308_ADC_HPF_CUTOFF_245HZ (0x1 << RK3308_ADC_HPF_CUTOFF_SFT)170#define RK3308_ADC_HPF_CUTOFF_20HZ (0x0 << RK3308_ADC_HPF_CUTOFF_SFT)171 172/* RK3308_ADC_DIG_CON07 - REG: 0x001c */173#define RK3308_ADCL_DATA_SFT 4174#define RK3308_ADCR_DATA_SFT 2175#define RK3308_ADCL_DATA_SEL_ADCL BIT(1)176#define RK3308_ADCR_DATA_SEL_ADCR BIT(0)177 178/*179 * RK3308_ALC_L_DIG_CON00 - REG: 0x0040 + ch * 0xc0180 * RK3308_ALC_R_DIG_CON00 - REG: 0x0080 + ch * 0xc0181 */182#define RK3308_GAIN_ATTACK_JACK BIT(6)183#define RK3308_CTRL_GEN_SFT 4184#define RK3308_CTRL_GEN_MSK (0x3 << RK3308_ALC_CTRL_GEN_SFT)185#define RK3308_CTRL_GEN_JACK3 (0x3 << RK3308_ALC_CTRL_GEN_SFT)186#define RK3308_CTRL_GEN_JACK2 (0x2 << RK3308_ALC_CTRL_GEN_SFT)187#define RK3308_CTRL_GEN_JACK1 (0x1 << RK3308_ALC_CTRL_GEN_SFT)188#define RK3308_CTRL_GEN_NORMAL (0x0 << RK3308_ALC_CTRL_GEN_SFT)189#define RK3308_AGC_HOLD_TIME_SFT 0190#define RK3308_AGC_HOLD_TIME_MSK (0xf << RK3308_AGC_HOLD_TIME_SFT)191#define RK3308_AGC_HOLD_TIME_1S (0xa << RK3308_AGC_HOLD_TIME_SFT)192#define RK3308_AGC_HOLD_TIME_512MS (0x9 << RK3308_AGC_HOLD_TIME_SFT)193#define RK3308_AGC_HOLD_TIME_256MS (0x8 << RK3308_AGC_HOLD_TIME_SFT)194#define RK3308_AGC_HOLD_TIME_128MS (0x7 << RK3308_AGC_HOLD_TIME_SFT)195#define RK3308_AGC_HOLD_TIME_64MS (0x6 << RK3308_AGC_HOLD_TIME_SFT)196#define RK3308_AGC_HOLD_TIME_32MS (0x5 << RK3308_AGC_HOLD_TIME_SFT)197#define RK3308_AGC_HOLD_TIME_16MS (0x4 << RK3308_AGC_HOLD_TIME_SFT)198#define RK3308_AGC_HOLD_TIME_8MS (0x3 << RK3308_AGC_HOLD_TIME_SFT)199#define RK3308_AGC_HOLD_TIME_4MS (0x2 << RK3308_AGC_HOLD_TIME_SFT)200#define RK3308_AGC_HOLD_TIME_2MS (0x1 << RK3308_AGC_HOLD_TIME_SFT)201#define RK3308_AGC_HOLD_TIME_0MS (0x0 << RK3308_AGC_HOLD_TIME_SFT)202 203/*204 * RK3308_ALC_L_DIG_CON01 - REG: 0x0044 + ch * 0xc0205 * RK3308_ALC_R_DIG_CON01 - REG: 0x0084 + ch * 0xc0206 */207#define RK3308_AGC_DECAY_TIME_SFT 4208#define RK3308_AGC_ATTACK_TIME_SFT 0209 210/*211 * RK3308_ALC_L_DIG_CON02 - REG: 0x0048 + ch * 0xc0212 * RK3308_ALC_R_DIG_CON02 - REG: 0x0088 + ch * 0xc0213 */214#define RK3308_AGC_MODE_LIMITER BIT(7)215#define RK3308_AGC_ZERO_CRO_EN BIT(6)216#define RK3308_AGC_AMP_RECOVER_GAIN BIT(5)217#define RK3308_AGC_FAST_DEC_EN BIT(4)218#define RK3308_AGC_NOISE_GATE_EN BIT(3)219#define RK3308_AGC_NOISE_GATE_THRESH_SFT 0220#define RK3308_AGC_NOISE_GATE_THRESH_MSK (0x7 << RK3308_AGC_NOISE_GATE_THRESH_SFT)221 222/*223 * RK3308_ALC_L_DIG_CON03 - REG: 0x004c + ch * 0xc0224 * RK3308_ALC_R_DIG_CON03 - REG: 0x008c + ch * 0xc0225 */226#define RK3308_AGC_PGA_ZERO_CRO_EN BIT(5)227#define RK3308_AGC_PGA_GAIN_MAX 0x1f228#define RK3308_AGC_PGA_GAIN_MIN 0229#define RK3308_AGC_PGA_GAIN_SFT 0230 231/*232 * RK3308_ALC_L_DIG_CON04 - REG: 0x0050 + ch * 0xc0233 * RK3308_ALC_R_DIG_CON04 - REG: 0x0090 + ch * 0xc0234 */235#define RK3308_AGC_SLOW_CLK_EN BIT(3)236#define RK3308_AGC_APPROX_RATE_SFT 0237#define RK3308_AGC_APPROX_RATE_MSK (0x7 << RK3308_AGC_APPROX_RATE_SFT)238 239/*240 * RK3308_ALC_L_DIG_CON05 - REG: 0x0054 + ch * 0xc0241 * RK3308_ALC_R_DIG_CON05 - REG: 0x0094 + ch * 0xc0242 */243#define RK3308_AGC_LO_8BITS_AGC_MAX_MSK 0xff244 245/*246 * RK3308_ALC_L_DIG_CON06 - REG: 0x0058 + ch * 0xc0247 * RK3308_ALC_R_DIG_CON06 - REG: 0x0098 + ch * 0xc0248 */249#define RK3308_AGC_HI_8BITS_AGC_MAX_MSK 0xff250 251/*252 * RK3308_ALC_L_DIG_CON07 - REG: 0x005c + ch * 0xc0253 * RK3308_ALC_R_DIG_CON07 - REG: 0x009c + ch * 0xc0254 */255#define RK3308_AGC_LO_8BITS_AGC_MIN_MSK 0xff256 257/*258 * RK3308_ALC_L_DIG_CON08 - REG: 0x0060 + ch * 0xc0259 * RK3308_ALC_R_DIG_CON08 - REG: 0x00a0 + ch * 0xc0260 */261#define RK3308_AGC_HI_8BITS_AGC_MIN_MSK 0xff262 263/*264 * RK3308_ALC_L_DIG_CON09 - REG: 0x0064 + ch * 0xc0265 * RK3308_ALC_R_DIG_CON09 - REG: 0x00a4 + ch * 0xc0266 */267#define RK3308_AGC_FUNC_SEL BIT(6)268#define RK3308_AGC_MAX_GAIN_PGA_MAX 0x7269#define RK3308_AGC_MAX_GAIN_PGA_MIN 0270#define RK3308_AGC_MAX_GAIN_PGA_SFT 3271#define RK3308_AGC_MAX_GAIN_PGA_MSK (0x7 << RK3308_AGC_MAX_GAIN_PGA_SFT)272#define RK3308_AGC_MIN_GAIN_PGA_MAX 0x7273#define RK3308_AGC_MIN_GAIN_PGA_MIN 0274#define RK3308_AGC_MIN_GAIN_PGA_SFT 0275#define RK3308_AGC_MIN_GAIN_PGA_MSK (0x7 << RK3308_AGC_MIN_GAIN_PGA_SFT)276 277/*278 * RK3308_ALC_L_DIG_CON12 - REG: 0x0068 + ch * 0xc0279 * RK3308_ALC_R_DIG_CON12 - REG: 0x00a8 + ch * 0xc0280 */281#define RK3308_AGC_GAIN_MSK 0x1f282 283/* RK3308_DAC_DIG_CON01 - REG: 0x0304 */284#define RK3308_DAC_I2S_LRC_POL_REVERSAL BIT(7)285#define RK3308_DAC_I2S_VALID_LEN_SFT 5286#define RK3308_DAC_I2S_VALID_LEN_MSK (0x3 << RK3308_DAC_I2S_VALID_LEN_SFT)287#define RK3308_DAC_I2S_VALID_LEN_32BITS (0x3 << RK3308_DAC_I2S_VALID_LEN_SFT)288#define RK3308_DAC_I2S_VALID_LEN_24BITS (0x2 << RK3308_DAC_I2S_VALID_LEN_SFT)289#define RK3308_DAC_I2S_VALID_LEN_20BITS (0x1 << RK3308_DAC_I2S_VALID_LEN_SFT)290#define RK3308_DAC_I2S_VALID_LEN_16BITS (0x0 << RK3308_DAC_I2S_VALID_LEN_SFT)291#define RK3308_DAC_I2S_MODE_SFT 3292#define RK3308_DAC_I2S_MODE_MSK (0x3 << RK3308_DAC_I2S_MODE_SFT)293#define RK3308_DAC_I2S_MODE_PCM (0x3 << RK3308_DAC_I2S_MODE_SFT)294#define RK3308_DAC_I2S_MODE_I2S (0x2 << RK3308_DAC_I2S_MODE_SFT)295#define RK3308_DAC_I2S_MODE_LJ (0x1 << RK3308_DAC_I2S_MODE_SFT)296#define RK3308_DAC_I2S_MODE_RJ (0x0 << RK3308_DAC_I2S_MODE_SFT)297#define RK3308_DAC_I2S_LR_SWAP BIT(2)298 299/* RK3308_DAC_DIG_CON02 - REG: 0x0308 */300#define RK3308BS_DAC_IO_MODE_MASTER BIT(7)301#define RK3308BS_DAC_MODE_MASTER BIT(6)302#define RK3308_DAC_IO_MODE_MASTER BIT(5)303#define RK3308_DAC_MODE_MASTER BIT(4)304#define RK3308_DAC_I2S_FRAME_LEN_SFT 2305#define RK3308_DAC_I2S_FRAME_LEN_MSK (0x3 << RK3308_DAC_I2S_FRAME_LEN_SFT)306#define RK3308_DAC_I2S_FRAME_32BITS (0x3 << RK3308_DAC_I2S_FRAME_LEN_SFT)307#define RK3308_DAC_I2S_FRAME_24BITS (0x2 << RK3308_DAC_I2S_FRAME_LEN_SFT)308#define RK3308_DAC_I2S_FRAME_20BITS (0x1 << RK3308_DAC_I2S_FRAME_LEN_SFT)309#define RK3308_DAC_I2S_FRAME_16BITS (0x0 << RK3308_DAC_I2S_FRAME_LEN_SFT)310#define RK3308_DAC_I2S_WORK BIT(1)311#define RK3308_DAC_I2S_BIT_CLK_POL_REVERSAL BIT(0)312 313/* RK3308_DAC_DIG_CON03 - REG: 0x030C */314#define RK3308_DAC_L_CH_BIST_SFT 2315#define RK3308_DAC_L_CH_BIST_MSK (0x3 << RK3308_DAC_L_CH_BIST_SFT)316#define RK3308_DAC_L_CH_BIST_LEFT (0x3 << RK3308_DAC_L_CH_BIST_SFT) /* normal mode */317#define RK3308_DAC_L_CH_BIST_CUBE (0x2 << RK3308_DAC_L_CH_BIST_SFT)318#define RK3308_DAC_L_CH_BIST_SINE (0x1 << RK3308_DAC_L_CH_BIST_SFT)319#define RK3308_DAC_L_CH_BIST_RIGHT (0x0 << RK3308_DAC_L_CH_BIST_SFT) /* normal mode */320#define RK3308_DAC_R_CH_BIST_SFT 0321#define RK3308_DAC_R_CH_BIST_MSK (0x3 << RK3308_DAC_R_CH_BIST_SFT)322#define RK3308_DAC_R_CH_BIST_LEFT (0x3 << RK3308_DAC_R_CH_BIST_SFT) /* normal mode */323#define RK3308_DAC_R_CH_BIST_CUBE (0x2 << RK3308_DAC_R_CH_BIST_SFT)324#define RK3308_DAC_R_CH_BIST_SINE (0x1 << RK3308_DAC_R_CH_BIST_SFT)325#define RK3308_DAC_R_CH_BIST_RIGHT (0x0 << RK3308_DAC_R_CH_BIST_SFT) /* normal mode */326 327/* RK3308_DAC_DIG_CON04 - REG: 0x0310 */328/* Versions up to B: */329#define RK3308_DAC_MODULATOR_GAIN_SFT 4330#define RK3308_DAC_MODULATOR_GAIN_MSK (0x7 << RK3308_DAC_MODULATOR_GAIN_SFT)331#define RK3308_DAC_CIC_IF_GAIN_SFT 0332#define RK3308_DAC_CIC_IF_GAIN_MSK (0x7 << RK3308_DAC_CIC_IF_GAIN_SFT)333/* Version C: */334#define RK3308BS_DAC_DIG_GAIN_SFT 0335#define RK3308BS_DAC_DIG_GAIN_MSK (0xff << RK3308BS_DAC_DIG_GAIN_SFT)336#define RK3308BS_DAC_DIG_GAIN_0DB (0xed << RK3308BS_DAC_DIG_GAIN_SFT)337 338/* RK3308BS_ADC_DIG_CON05..06 (Version C only) */339#define RK3308_ADC_DIG_VOL_CON_x_SFT 0340#define RK3308_ADC_DIG_VOL_CON_x_MSK (0xff << RK3308_ADC_DIG_VOL_CON_x_SFT)341#define RK3308_ADC_DIG_VOL_CON_x_0DB (0xc2 << RK3308_ADC_DIG_VOL_CON_x_SFT)342 343/* RK3308_DAC_DIG_CON05 - REG: 0x0314 */344#define RK3308_DAC_L_REG_CTL_INDATA BIT(2)345#define RK3308_DAC_R_REG_CTL_INDATA BIT(1)346 347/* RK3308_DAC_DIG_CON10 - REG: 0x0328 */348#define RK3308_DAC_DATA_HI4(x) ((x) & 0xf)349 350/* RK3308_DAC_DIG_CON11 - REG: 0x032c */351#define RK3308_DAC_DATA_LO8(x) ((x) & 0xff)352 353/* RK3308_ADC_ANA_CON00 - REG: 0x0340 */354#define RK3308_ADC_CH1_CH2_MIC_ALL_MSK (0xff << 0)355#define RK3308_ADC_CH1_CH2_MIC_ALL 0xff356#define RK3308_ADC_CH2_MIC_UNMUTE BIT(7)357#define RK3308_ADC_CH2_MIC_WORK BIT(6)358#define RK3308_ADC_CH2_MIC_EN BIT(5)359#define RK3308_ADC_CH2_BUF_REF_EN BIT(4)360#define RK3308_ADC_CH1_MIC_UNMUTE BIT(3)361#define RK3308_ADC_CH1_MIC_WORK BIT(2)362#define RK3308_ADC_CH1_MIC_EN BIT(1)363#define RK3308_ADC_CH1_BUF_REF_EN BIT(0)364 365/* RK3308_ADC_ANA_CON01 - REG: 0x0344366 *367 * The PGA of MIC-INs:368 * - HW version A:369 * 0x0 - MIC1~MIC8 0 dB (recommended when ADC used as loopback)370 * 0x3 - MIC1~MIC8 20 dB (recommended when ADC used as MIC input)371 * - HW version B:372 * 0x0 - MIC1~MIC8 0 dB373 * 0x1 - MIC1~MIC8 6.6 dB374 * 0x2 - MIC1~MIC8 13 dB375 * 0x3 - MIC1~MIC8 20 dB376 */377#define RK3308_ADC_CH2_MIC_GAIN_MAX 0x3378#define RK3308_ADC_CH2_MIC_GAIN_MIN 0379#define RK3308_ADC_CH2_MIC_GAIN_SFT 4380#define RK3308_ADC_CH2_MIC_GAIN_MSK (0x3 << RK3308_ADC_CH2_MIC_GAIN_SFT)381#define RK3308_ADC_CH2_MIC_GAIN_20DB (0x3 << RK3308_ADC_CH2_MIC_GAIN_SFT)382#define RK3308_ADC_CH2_MIC_GAIN_13DB (0x2 << RK3308_ADC_CH2_MIC_GAIN_SFT)383#define RK3308_ADC_CH2_MIC_GAIN_6_6DB (0x1 << RK3308_ADC_CH2_MIC_GAIN_SFT)384#define RK3308_ADC_CH2_MIC_GAIN_0DB (0x0 << RK3308_ADC_CH2_MIC_GAIN_SFT)385 386#define RK3308_ADC_CH1_MIC_GAIN_MAX 0x3387#define RK3308_ADC_CH1_MIC_GAIN_MIN 0388#define RK3308_ADC_CH1_MIC_GAIN_SFT 0389#define RK3308_ADC_CH1_MIC_GAIN_MSK (0x3 << RK3308_ADC_CH1_MIC_GAIN_SFT)390#define RK3308_ADC_CH1_MIC_GAIN_20DB (0x3 << RK3308_ADC_CH1_MIC_GAIN_SFT)391#define RK3308_ADC_CH1_MIC_GAIN_13DB (0x2 << RK3308_ADC_CH1_MIC_GAIN_SFT)392#define RK3308_ADC_CH1_MIC_GAIN_6_6DB (0x1 << RK3308_ADC_CH1_MIC_GAIN_SFT)393#define RK3308_ADC_CH1_MIC_GAIN_0DB (0x0 << RK3308_ADC_CH1_MIC_GAIN_SFT)394 395/* RK3308_ADC_ANA_CON02 - REG: 0x0348 */396#define RK3308_ADC_CH2_ZEROCROSS_DET_EN BIT(6)397#define RK3308_ADC_CH2_ALC_WORK BIT(5)398#define RK3308_ADC_CH2_ALC_EN BIT(4)399#define RK3308_ADC_CH1_ZEROCROSS_DET_EN BIT(2)400#define RK3308_ADC_CH1_ALC_WORK BIT(1)401#define RK3308_ADC_CH1_ALC_EN BIT(0)402 403/* RK3308_ADC_ANA_CON03 - REG: 0x034c */404#define RK3308_ADC_CH1_ALC_GAIN_MAX 0x1f405#define RK3308_ADC_CH1_ALC_GAIN_MIN 0406#define RK3308_ADC_CH1_ALC_GAIN_SFT 0407#define RK3308_ADC_CH1_ALC_GAIN_MSK (0x1f << RK3308_ADC_CH1_ALC_GAIN_SFT)408#define RK3308_ADC_CH1_ALC_GAIN_0DB (0x0c << RK3308_ADC_CH1_ALC_GAIN_SFT)409 410/* RK3308_ADC_ANA_CON04 - REG: 0x0350 */411#define RK3308_ADC_CH2_ALC_GAIN_MAX 0x1f412#define RK3308_ADC_CH2_ALC_GAIN_MIN 0413#define RK3308_ADC_CH2_ALC_GAIN_SFT 0414#define RK3308_ADC_CH2_ALC_GAIN_MSK (0x1f << RK3308_ADC_CH2_ALC_GAIN_SFT)415#define RK3308_ADC_CH2_ALC_GAIN_0DB (0x0c << RK3308_ADC_CH2_ALC_GAIN_SFT)416 417/* RK3308_ADC_ANA_CON05 - REG: 0x0354 */418#define RK3308_ADC_CH2_ADC_WORK BIT(6)419#define RK3308_ADC_CH2_ADC_EN BIT(5)420#define RK3308_ADC_CH2_CLK_EN BIT(4)421#define RK3308_ADC_CH1_ADC_WORK BIT(2)422#define RK3308_ADC_CH1_ADC_EN BIT(1)423#define RK3308_ADC_CH1_CLK_EN BIT(0)424 425/* RK3308_ADC_ANA_CON06 - REG: 0x0358 */426#define RK3308_ADC_CURRENT_EN BIT(0)427 428/* RK3308_ADC_ANA_CON07 - REG: 0x035c */429/* Note: The register configuration is only valid for ADC2 */430#define RK3308_ADC_CH2_IN_SEL_SFT 6431#define RK3308_ADC_CH2_IN_SEL_MSK (0x3 << RK3308_ADC_CH2_IN_SEL_SFT)432#define RK3308_ADC_CH2_IN_LINEIN_MIC (0x3 << RK3308_ADC_CH2_IN_SEL_SFT)433#define RK3308_ADC_CH2_IN_LINEIN (0x2 << RK3308_ADC_CH2_IN_SEL_SFT)434#define RK3308_ADC_CH2_IN_MIC (0x1 << RK3308_ADC_CH2_IN_SEL_SFT)435#define RK3308_ADC_CH2_IN_NONE (0x0 << RK3308_ADC_CH2_IN_SEL_SFT)436/* Note: The register configuration is only valid for ADC1 */437#define RK3308_ADC_CH1_IN_SEL_SFT 4438#define RK3308_ADC_CH1_IN_SEL_MSK (0x3 << RK3308_ADC_CH1_IN_SEL_SFT)439#define RK3308_ADC_CH1_IN_LINEIN_MIC (0x3 << RK3308_ADC_CH1_IN_SEL_SFT)440#define RK3308_ADC_CH1_IN_LINEIN (0x2 << RK3308_ADC_CH1_IN_SEL_SFT)441#define RK3308_ADC_CH1_IN_MIC (0x1 << RK3308_ADC_CH1_IN_SEL_SFT)442#define RK3308_ADC_CH1_IN_NONE (0x0 << RK3308_ADC_CH1_IN_SEL_SFT)443#define RK3308_ADC_MIC_BIAS_BUF_EN BIT(3)444#define RK3308_ADC_LEVEL_RANGE_MICBIAS_MAX 7445#define RK3308_ADC_LEVEL_RANGE_MICBIAS_SFT 0446#define RK3308_ADC_LEVEL_RANGE_MICBIAS_MSK (0x7 << RK3308_ADC_LEVEL_RANGE_MICBIAS_SFT)447 448/* RK3308_ADC_ANA_CON08 - REG: 0x0360 */449#define RK3308_ADC_MICBIAS_CURRENT_EN BIT(4)450 451/* RK3308_ADC_ANA_CON10 - REG: 0x0368 */452#define RK3308_ADC_REF_EN BIT(7)453#define RK3308_ADC_CURRENT_CHARGE_SFT 0454#define RK3308_ADC_CURRENT_CHARGE_MSK (0x7f << RK3308_ADC_CURRENT_CHARGE_SFT)455 456/* RK3308_ADC_ANA_CON11 - REG: 0x036c */457#define RK3308_ADC_ALCR_CON_GAIN_PGAR_EN BIT(1)458#define RK3308_ADC_ALCL_CON_GAIN_PGAL_EN BIT(0)459 460/* RK3308_DAC_ANA_CON00 - REG: 0x0440 */461#define RK3308_DAC_HEADPHONE_DET_EN BIT(1)462#define RK3308_DAC_CURRENT_EN BIT(0)463 464/* RK3308_DAC_ANA_CON01 - REG: 0x0444 */465#define RK3308_DAC_BUF_REF_R_EN BIT(6)466#define RK3308_DAC_BUF_REF_L_EN BIT(2)467#define RK3308_DAC_HPOUT_POP_SOUND_R_SFT 4468#define RK3308_DAC_HPOUT_POP_SOUND_L_SFT 0469// unshifted values for both L and R:470#define RK3308_DAC_HPOUT_POP_SOUND_x_MSK 0x3471#define RK3308_DAC_HPOUT_POP_SOUND_x_WORK 0x2472#define RK3308_DAC_HPOUT_POP_SOUND_x_INIT 0x1473 474/* RK3308_DAC_ANA_CON02 - REG: 0x0448 */475#define RK3308_DAC_R_DAC_WORK BIT(7)476#define RK3308_DAC_R_DAC_EN BIT(6)477#define RK3308_DAC_R_CLK_EN BIT(5)478#define RK3308_DAC_R_REF_EN BIT(4)479#define RK3308_DAC_L_DAC_WORK BIT(3)480#define RK3308_DAC_L_DAC_EN BIT(2)481#define RK3308_DAC_L_CLK_EN BIT(1)482#define RK3308_DAC_L_REF_EN BIT(0)483 484/* RK3308_DAC_ANA_CON03 - REG: 0x044c */485#define RK3308_DAC_R_HPOUT_WORK BIT(6)486#define RK3308_DAC_R_HPOUT_EN BIT(5)487#define RK3308_DAC_R_HPOUT_MUTE_SFT 4488#define RK3308_DAC_L_HPOUT_WORK BIT(2)489#define RK3308_DAC_L_HPOUT_EN BIT(1)490#define RK3308_DAC_L_HPOUT_MUTE_SFT 0491 492/* RK3308_DAC_ANA_CON04 - REG: 0x0450 */493#define RK3308_DAC_x_LINEOUT_GAIN_MAX 0x3494#define RK3308_DAC_R_LINEOUT_GAIN_SFT 6495#define RK3308_DAC_R_LINEOUT_GAIN_MSK (0x3 << RK3308_DAC_R_LINEOUT_GAIN_SFT)496#define RK3308_DAC_R_LINEOUT_GAIN_0DB (0x3 << RK3308_DAC_R_LINEOUT_GAIN_SFT)497#define RK3308_DAC_R_LINEOUT_GAIN_NDB_1_5 (0x2 << RK3308_DAC_R_LINEOUT_GAIN_SFT)498#define RK3308_DAC_R_LINEOUT_GAIN_NDB_3 (0x1 << RK3308_DAC_R_LINEOUT_GAIN_SFT)499#define RK3308_DAC_R_LINEOUT_GAIN_NDB_6 (0x0 << RK3308_DAC_R_LINEOUT_GAIN_SFT)500#define RK3308_DAC_R_LINEOUT_MUTE_SFT 5501#define RK3308_DAC_R_LINEOUT_EN BIT(4)502#define RK3308_DAC_L_LINEOUT_GAIN_SFT 2503#define RK3308_DAC_L_LINEOUT_GAIN_MSK (0x3 << RK3308_DAC_L_LINEOUT_GAIN_SFT)504#define RK3308_DAC_L_LINEOUT_GAIN_0DB (0x3 << RK3308_DAC_L_LINEOUT_GAIN_SFT)505#define RK3308_DAC_L_LINEOUT_GAIN_NDB_1_5 (0x2 << RK3308_DAC_L_LINEOUT_GAIN_SFT)506#define RK3308_DAC_L_LINEOUT_GAIN_NDB_3 (0x1 << RK3308_DAC_L_LINEOUT_GAIN_SFT)507#define RK3308_DAC_L_LINEOUT_GAIN_NDB_6 (0x0 << RK3308_DAC_L_LINEOUT_GAIN_SFT)508#define RK3308_DAC_L_LINEOUT_MUTE_SFT 1509#define RK3308_DAC_L_LINEOUT_EN BIT(0)510 511/* RK3308_DAC_ANA_CON05 - REG: 0x0454, step is 1.5db */512/* RK3308_DAC_ANA_CON06 - REG: 0x0458, step is 1.5db */513#define RK3308_DAC_x_HPOUT_GAIN_MAX 0x1e514#define RK3308_DAC_x_HPOUT_GAIN_SFT 0515#define RK3308_DAC_x_HPOUT_GAIN_MSK (0x1f << RK3308_DAC_x_HPOUT_GAIN_SFT)516#define RK3308_DAC_x_HPOUT_GAIN_MIN (0x00 << RK3308_DAC_x_HPOUT_GAIN_SFT)517 518/* RK3308_DAC_ANA_CON07 - REG: 0x045c */519#define RK3308_DAC_R_HPOUT_DRV_SFT 4520#define RK3308_DAC_R_HPOUT_DRV_MSK (0xf << RK3308_DAC_R_HPOUT_DRV_SFT)521#define RK3308_DAC_L_HPOUT_DRV_SFT 0522#define RK3308_DAC_L_HPOUT_DRV_MSK (0xf << RK3308_DAC_L_HPOUT_DRV_SFT)523 524/* RK3308_DAC_ANA_CON08 - REG: 0x0460 */525#define RK3308_DAC_R_LINEOUT_DRV_SFT 4526#define RK3308_DAC_R_LINEOUT_DRV_MSK (0xf << RK3308_DAC_R_LINEOUT_DRV_SFT)527#define RK3308_DAC_L_LINEOUT_DRV_SFT 0528#define RK3308_DAC_L_LINEOUT_DRV_MSK (0xf << RK3308_DAC_L_LINEOUT_DRV_SFT)529 530/* RK3308_DAC_ANA_CON12 - REG: 0x0470 */531#define RK3308_DAC_R_HPMIX_SEL_SFT 6532#define RK3308_DAC_R_HPMIX_SEL_MSK (0x3 << RK3308_DAC_R_HPMIX_SEL_SFT)533#define RK3308_DAC_R_HPMIX_LINEIN_I2S (0x3 << RK3308_DAC_R_HPMIX_SEL_SFT)534#define RK3308_DAC_R_HPMIX_LINEIN (0x2 << RK3308_DAC_R_HPMIX_SEL_SFT)535#define RK3308_DAC_R_HPMIX_I2S (0x1 << RK3308_DAC_R_HPMIX_SEL_SFT)536#define RK3308_DAC_R_HPMIX_NONE (0x0 << RK3308_DAC_R_HPMIX_SEL_SFT)537#define RK3308_DAC_L_HPMIX_SEL_SFT 2538#define RK3308_DAC_L_HPMIX_SEL_MSK (0x3 << RK3308_DAC_L_HPMIX_SEL_SFT)539#define RK3308_DAC_L_HPMIX_LINEIN_I2S (0x3 << RK3308_DAC_L_HPMIX_SEL_SFT)540#define RK3308_DAC_L_HPMIX_LINEIN (0x2 << RK3308_DAC_L_HPMIX_SEL_SFT)541#define RK3308_DAC_L_HPMIX_I2S (0x1 << RK3308_DAC_L_HPMIX_SEL_SFT)542#define RK3308_DAC_L_HPMIX_NONE (0x0 << RK3308_DAC_L_HPMIX_SEL_SFT)543#define RK3308_DAC_x_HPMIX_GAIN_MIN 0x1 /* 0x0 and 0x3 are reserved */544#define RK3308_DAC_x_HPMIX_GAIN_MAX 0x2545#define RK3308_DAC_R_HPMIX_GAIN_SFT 4546#define RK3308_DAC_R_HPMIX_GAIN_MSK (0x3 << RK3308_DAC_R_HPMIX_GAIN_SFT)547#define RK3308_DAC_R_HPMIX_GAIN_0DB (0x2 << RK3308_DAC_R_HPMIX_GAIN_SFT)548#define RK3308_DAC_R_HPMIX_GAIN_NDB_6 (0x1 << RK3308_DAC_R_HPMIX_GAIN_SFT)549#define RK3308_DAC_L_HPMIX_GAIN_SFT 0550#define RK3308_DAC_L_HPMIX_GAIN_MSK (0x3 << RK3308_DAC_L_HPMIX_GAIN_SFT)551#define RK3308_DAC_L_HPMIX_GAIN_0DB (0x2 << RK3308_DAC_L_HPMIX_GAIN_SFT)552#define RK3308_DAC_L_HPMIX_GAIN_NDB_6 (0x1 << RK3308_DAC_L_HPMIX_GAIN_SFT)553 554/* RK3308_DAC_ANA_CON13 - REG: 0x0474 */555#define RK3308_DAC_R_HPMIX_UNMUTE BIT(6)556#define RK3308_DAC_R_HPMIX_WORK BIT(5)557#define RK3308_DAC_R_HPMIX_EN BIT(4)558#define RK3308_DAC_L_HPMIX_UNMUTE BIT(2)559#define RK3308_DAC_L_HPMIX_WORK BIT(1)560#define RK3308_DAC_L_HPMIX_EN BIT(0)561 562/* RK3308_DAC_ANA_CON14 - REG: 0x0478 */563#define RK3308_DAC_VCM_LINEOUT_EN (0x1 << 4)564#define RK3308_DAC_CURRENT_CHARGE_SFT 0565#define RK3308_DAC_CURRENT_CHARGE_MSK (0xf << RK3308_DAC_CURRENT_CHARGE_SFT)566 567/* RK3308_DAC_ANA_CON15 - REG: 0x047C */568#define RK3308_DAC_LINEOUT_POP_SOUND_R_SFT 4569#define RK3308_DAC_LINEOUT_POP_SOUND_R_MSK (0x3 << RK3308_DAC_LINEOUT_POP_SOUND_R_SFT)570#define RK3308_DAC_R_SEL_DC_FROM_INTERNAL (0x2 << RK3308_DAC_LINEOUT_POP_SOUND_R_SFT)571#define RK3308_DAC_R_SEL_DC_FROM_VCM (0x1 << RK3308_DAC_LINEOUT_POP_SOUND_R_SFT)572#define RK3308_DAC_R_SEL_LINEOUT_FROM_INTERNAL (0x0 << RK3308_DAC_LINEOUT_POP_SOUND_R_SFT)573#define RK3308_DAC_LINEOUT_POP_SOUND_L_SFT 0574#define RK3308_DAC_LINEOUT_POP_SOUND_L_MSK (0x3 << RK3308_DAC_LINEOUT_POP_SOUND_L_SFT)575#define RK3308_DAC_L_SEL_DC_FROM_INTERNAL (0x2 << RK3308_DAC_LINEOUT_POP_SOUND_L_SFT)576#define RK3308_DAC_L_SEL_DC_FROM_VCM (0x1 << RK3308_DAC_LINEOUT_POP_SOUND_L_SFT)577#define RK3308_DAC_L_SEL_LINEOUT_FROM_INTERNAL (0x0 << RK3308_DAC_LINEOUT_POP_SOUND_L_SFT)578 579#endif /* __RK3308_CODEC_H__ */580