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1/* SPDX-License-Identifier: GPL-2.0-only */2/*3 * rt1017-sdca-sdw.h -- RT1017 SDCA ALSA SoC audio driver header4 *5 * Copyright(c) 2023 Realtek Semiconductor Corp.6 */7 8#ifndef __RT1017_SDW_H__9#define __RT1017_SDW_H__10 11#include <linux/regmap.h>12#include <linux/soundwire/sdw.h>13#include <linux/soundwire/sdw_type.h>14#include <linux/soundwire/sdw_registers.h>15#include <sound/soc.h>16 17/* RT1017 SDCA Control - function number */18#define FUNC_NUM_SMART_AMP 0x0419 20/* RT1017 SDCA entity */21#define RT1017_SDCA_ENT_PDE23 0x3122#define RT1017_SDCA_ENT_PDE22 0x3323#define RT1017_SDCA_ENT_CS21 0x2124#define RT1017_SDCA_ENT_SAPU29 0x2925#define RT1017_SDCA_ENT_XU22 0x2226#define RT1017_SDCA_ENT_FU 0x0327#define RT1017_SDCA_ENT_UDMPU21 0x0228 29/* RT1017 SDCA control */30#define RT1017_SDCA_CTL_FS_INDEX 0x1031#define RT1017_SDCA_CTL_REQ_POWER_STATE 0x0132#define RT1017_SDCA_CTL_PROT_STAT 0x1133#define RT1017_SDCA_CTL_BYPASS 0x0134#define RT1017_SDCA_CTL_FU_MUTE 0x0135#define RT1017_SDCA_CTL_FU_VOLUME 0x0236#define RT1017_SDCA_CTL_UDMPU_CLUSTER 0x1037 38 39#define RT1017_CLASSD_INT_1 0xd30040#define RT1017_PWM_TRIM_1 0xd37041 42 43#define RT1017_PWM_FREQ_CTL_SRC_SEL_MASK (0x3 << 2)44#define RT1017_PWM_FREQ_CTL_SRC_SEL_EFUSE (0x2 << 2)45#define RT1017_PWM_FREQ_CTL_SRC_SEL_REG (0x0 << 2)46 47enum {48 RT1017_SDCA_RATE_44100HZ = 0x8,49 RT1017_SDCA_RATE_48000HZ = 0x9,50 RT1017_SDCA_RATE_96000HZ = 0xb,51 RT1017_SDCA_RATE_192000HZ = 0xd,52};53 54struct rt1017_sdca_priv {55 struct snd_soc_component *component;56 struct regmap *regmap;57 struct sdw_slave *sdw_slave;58 struct sdw_bus_params params;59 bool hw_init;60 bool first_hw_init;61};62 63static const struct reg_default rt1017_sdca_reg_defaults[] = {64 { 0x3206, 0x00 },65 { 0xc001, 0x43 },66 { 0xc030, 0x54 },67 { 0xc104, 0x8a },68 { 0xc10b, 0x2f },69 { 0xc10c, 0x2f },70 { 0xc110, 0x49 },71 { 0xc112, 0x10 },72 { 0xc300, 0xff },73 { 0xc301, 0xdd },74 { 0xc318, 0x40 },75 { 0xc325, 0x00 },76 { 0xc326, 0x00 },77 { 0xc327, 0x00 },78 { 0xc328, 0x02 },79 { 0xc331, 0xb2 },80 { 0xc340, 0x02 },81 { 0xc350, 0x21 },82 { 0xc500, 0x00 },83 { 0xc502, 0x00 },84 { 0xc504, 0x3f },85 { 0xc507, 0x1f },86 { 0xc509, 0x1f },87 { 0xc510, 0x40 },88 { 0xc512, 0x00 },89 { 0xc518, 0x02 },90 { 0xc51b, 0x7f },91 { 0xc51d, 0x0f },92 { 0xc520, 0x00 },93 { 0xc540, 0x80 },94 { 0xc541, 0x00 },95 { 0xc542, 0x0a },96 { 0xc550, 0x80 },97 { 0xc551, 0x0f },98 { 0xc552, 0xff },99 { 0xc600, 0x10 },100 { 0xc602, 0x83 },101 { 0xc612, 0x40 },102 { 0xc622, 0x40 },103 { 0xc632, 0x40 },104 { 0xc642, 0x40 },105 { 0xc651, 0x00 },106 { 0xca00, 0xc1 },107 { 0xca09, 0x00 },108 { 0xca0a, 0x51 },109 { 0xca0b, 0xeb },110 { 0xca0c, 0x85 },111 { 0xca0e, 0x00 },112 { 0xca0f, 0x10 },113 { 0xca10, 0x62 },114 { 0xca11, 0x4d },115 { 0xca16, 0x0f },116 { 0xca17, 0x00 },117 { 0xcb00, 0x10 },118 { 0xcc00, 0x10 },119 { 0xcc02, 0x0b },120 { 0xd017, 0x09 },121 { 0xd01a, 0x00 },122 { 0xd01b, 0x00 },123 { 0xd01c, 0x00 },124 { 0xd101, 0xa0 },125 { 0xd20c, 0x14 },126 { 0xd300, 0x0f },127 { 0xd370, 0x18 },128 { 0xd500, 0x00 },129 { 0xd545, 0x0b },130 { 0xd546, 0xf9 },131 { 0xd547, 0xb2 },132 { 0xd548, 0xa9 },133 { 0xd5a5, 0x00 },134 { 0xd5a6, 0x00 },135 { 0xd5a7, 0x00 },136 { 0xd5a8, 0x00 },137 { 0xd5aa, 0x00 },138 { 0xd5ab, 0x00 },139 { 0xd5ac, 0x00 },140 { 0xd5ad, 0x00 },141 { 0xda04, 0x03 },142 { 0xda05, 0x33 },143 { 0xda06, 0x33 },144 { 0xda07, 0x33 },145 { 0xda09, 0x5d },146 { 0xda0a, 0xc0 },147 { 0xda0c, 0x00 },148 { 0xda0d, 0x01 },149 { 0xda0e, 0x5d },150 { 0xda0f, 0x86 },151 { 0xda11, 0x20 },152 { 0xda12, 0x00 },153 { 0xda13, 0x00 },154 { 0xda14, 0x00 },155 { 0xda16, 0x7f },156 { 0xda17, 0xff },157 { 0xda18, 0xff },158 { 0xda19, 0xff },159 { 0xdab6, 0x00 },160 { 0xdab7, 0x01 },161 { 0xdab8, 0x00 },162 { 0xdab9, 0x01 },163 { 0xdaba, 0x00 },164 { 0xdabb, 0x01 },165 { 0xdb09, 0x0f },166 { 0xdb0a, 0xff },167 { 0xdb14, 0x00 },168 169 { SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1017_SDCA_ENT_UDMPU21,170 RT1017_SDCA_CTL_UDMPU_CLUSTER, 0), 0x00 },171 { SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1017_SDCA_ENT_FU,172 RT1017_SDCA_CTL_FU_MUTE, 0x01), 0x01 },173 { SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1017_SDCA_ENT_XU22,174 RT1017_SDCA_CTL_BYPASS, 0), 0x01 },175 { SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1017_SDCA_ENT_CS21,176 RT1017_SDCA_CTL_FS_INDEX, 0), 0x09 },177 { SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1017_SDCA_ENT_PDE23,178 RT1017_SDCA_CTL_REQ_POWER_STATE, 0), 0x03 },179 { SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1017_SDCA_ENT_PDE22,180 RT1017_SDCA_CTL_REQ_POWER_STATE, 0), 0x03 },181};182 183#endif /* __RT1017_SDW_H__ */184