165 lines · c
1/* SPDX-License-Identifier: GPL-2.0-only */2/*3 * rt1019.h -- RT1019 ALSA SoC audio amplifier driver4 *5 * Copyright(c) 2021 Realtek Semiconductor Corp.6 */7 8#ifndef __RT1019_H__9#define __RT1019_H__10 11#define RT1019_DEVICE_ID_VAL 0x101912#define RT1019_DEVICE_ID_VAL2 0x673113 14#define RT1019_RESET 0x000015#define RT1019_IDS_CTRL 0x001116#define RT1019_ASEL_CTRL 0x001317#define RT1019_PWR_STRP_2 0x001918#define RT1019_BEEP_TONE 0x001b19#define RT1019_VER_ID 0x005c20#define RT1019_VEND_ID_1 0x005e21#define RT1019_VEND_ID_2 0x005f22#define RT1019_DEV_ID_1 0x006123#define RT1019_DEV_ID_2 0x006224#define RT1019_SDB_CTRL 0x006625#define RT1019_CLK_TREE_1 0x010026#define RT1019_CLK_TREE_2 0x010127#define RT1019_CLK_TREE_3 0x010228#define RT1019_PLL_1 0x031129#define RT1019_PLL_2 0x031230#define RT1019_PLL_3 0x031331#define RT1019_TDM_1 0x040032#define RT1019_TDM_2 0x040133#define RT1019_TDM_3 0x040234#define RT1019_DMIX_MONO_1 0x050435#define RT1019_DMIX_MONO_2 0x050536#define RT1019_BEEP_1 0x0b0037#define RT1019_BEEP_2 0x0b0138 39/* 0x0019 Power On Strap Control-2 */40#define RT1019_AUTO_BITS_SEL_MASK (0x1 << 5)41#define RT1019_AUTO_BITS_SEL_AUTO (0x1 << 5)42#define RT1019_AUTO_BITS_SEL_MANU (0x0 << 5)43#define RT1019_AUTO_CLK_SEL_MASK (0x1 << 4)44#define RT1019_AUTO_CLK_SEL_AUTO (0x1 << 4)45#define RT1019_AUTO_CLK_SEL_MANU (0x0 << 4)46 47/* 0x0100 Clock Tree Control-1 */48#define RT1019_CLK_SYS_PRE_SEL_MASK (0x1 << 7)49#define RT1019_CLK_SYS_PRE_SEL_SFT 750#define RT1019_CLK_SYS_PRE_SEL_BCLK (0x0 << 7)51#define RT1019_CLK_SYS_PRE_SEL_PLL (0x1 << 7)52#define RT1019_PLL_SRC_MASK (0x1 << 4)53#define RT1019_PLL_SRC_SFT 454#define RT1019_PLL_SRC_SEL_BCLK (0x0 << 4)55#define RT1019_PLL_SRC_SEL_RC (0x1 << 4)56#define RT1019_SEL_FIFO_MASK (0x3 << 2)57#define RT1019_SEL_FIFO_DIV1 (0x0 << 2)58#define RT1019_SEL_FIFO_DIV2 (0x1 << 2)59#define RT1019_SEL_FIFO_DIV4 (0x2 << 2)60 61/* 0x0101 clock tree control-2 */62#define RT1019_SYS_DIV_DA_FIL_MASK (0x7 << 5)63#define RT1019_SYS_DIV_DA_FIL_DIV1 (0x2 << 5)64#define RT1019_SYS_DIV_DA_FIL_DIV2 (0x3 << 5)65#define RT1019_SYS_DIV_DA_FIL_DIV4 (0x4 << 5)66#define RT1019_SYS_DA_OSR_MASK (0x3 << 2)67#define RT1019_SYS_DA_OSR_DIV1 (0x0 << 2)68#define RT1019_SYS_DA_OSR_DIV2 (0x1 << 2)69#define RT1019_SYS_DA_OSR_DIV4 (0x2 << 2)70#define RT1019_ASRC_256FS_MASK 0x371#define RT1019_ASRC_256FS_DIV1 0x072#define RT1019_ASRC_256FS_DIV2 0x173#define RT1019_ASRC_256FS_DIV4 0x274 75/* 0x0102 clock tree control-3 */76#define RT1019_SEL_CLK_CAL_MASK (0x3 << 6)77#define RT1019_SEL_CLK_CAL_DIV1 (0x0 << 6)78#define RT1019_SEL_CLK_CAL_DIV2 (0x1 << 6)79#define RT1019_SEL_CLK_CAL_DIV4 (0x2 << 6)80 81/* 0x0311 PLL-1 */82#define RT1019_PLL_M_MASK (0xf << 4)83#define RT1019_PLL_M_SFT 484#define RT1019_PLL_M_BP_MASK (0x1 << 1)85#define RT1019_PLL_M_BP_SFT 186#define RT1019_PLL_Q_8_8_MASK (0x1)87 88/* 0x0312 PLL-2 */89#define RT1019_PLL_Q_7_0_MASK 0xff90 91/* 0x0313 PLL-3 */92#define RT1019_PLL_K_MASK 0x1f93 94/* 0x0400 TDM Control-1 */95#define RT1019_TDM_BCLK_MASK (0x1 << 6)96#define RT1019_TDM_BCLK_NORM (0x0 << 6)97#define RT1019_TDM_BCLK_INV (0x1 << 6)98#define RT1019_TDM_CL_MASK (0x7)99#define RT1019_TDM_CL_8 (0x4)100#define RT1019_TDM_CL_32 (0x3)101#define RT1019_TDM_CL_24 (0x2)102#define RT1019_TDM_CL_20 (0x1)103#define RT1019_TDM_CL_16 (0x0)104 105/* 0x0401 TDM Control-2 */106#define RT1019_I2S_CH_TX_MASK (0x3 << 6)107#define RT1019_I2S_CH_TX_SFT 6108#define RT1019_I2S_TX_2CH (0x0 << 6)109#define RT1019_I2S_TX_4CH (0x1 << 6)110#define RT1019_I2S_TX_6CH (0x2 << 6)111#define RT1019_I2S_TX_8CH (0x3 << 6)112#define RT1019_I2S_DF_MASK (0x7 << 3)113#define RT1019_I2S_DF_SFT 3114#define RT1019_I2S_DF_I2S (0x0 << 3)115#define RT1019_I2S_DF_LEFT (0x1 << 3)116#define RT1019_I2S_DF_PCM_A_R (0x2 << 3)117#define RT1019_I2S_DF_PCM_B_R (0x3 << 3)118#define RT1019_I2S_DF_PCM_A_F (0x6 << 3)119#define RT1019_I2S_DF_PCM_B_F (0x7 << 3)120#define RT1019_I2S_DL_MASK 0x7121#define RT1019_I2S_DL_SFT 0122#define RT1019_I2S_DL_16 0x0123#define RT1019_I2S_DL_20 0x1124#define RT1019_I2S_DL_24 0x2125#define RT1019_I2S_DL_32 0x3126#define RT1019_I2S_DL_8 0x4127 128/* TDM1 Control-3 (0x0402) */129#define RT1019_TDM_I2S_TX_L_DAC1_1_MASK (0x7 << 4)130#define RT1019_TDM_I2S_TX_R_DAC1_1_MASK 0x7131#define RT1019_TDM_I2S_TX_L_DAC1_1_SFT 4132#define RT1019_TDM_I2S_TX_R_DAC1_1_SFT 0133 134/* System Clock Source */135enum {136 RT1019_SCLK_S_BCLK,137 RT1019_SCLK_S_PLL,138};139 140/* PLL1 Source */141enum {142 RT1019_PLL_S_BCLK,143 RT1019_PLL_S_RC25M,144};145 146enum {147 RT1019_AIF1,148 RT1019_AIFS149};150 151struct rt1019_priv {152 struct snd_soc_component *component;153 struct regmap *regmap;154 int sysclk;155 int sysclk_src;156 int lrck;157 int bclk;158 int pll_src;159 int pll_in;160 int pll_out;161 unsigned int bclk_ratio;162};163 164#endif /* __RT1019_H__ */165