274 lines · c
1/* SPDX-License-Identifier: GPL-2.0-only */2/*3 * RT1305.h -- RT1305 ALSA SoC amplifier component driver4 *5 * Copyright 2018 Realtek Semiconductor Corp.6 * Author: Shuming Fan <shumingf@realtek.com>7 */8 9#ifndef _RT1305_H_10#define _RT1305_H_11 12#define RT1305_DEVICE_ID_NUM 0x625113 14#define RT1305_RESET 0x0015#define RT1305_CLK_1 0x0416#define RT1305_CLK_2 0x0517#define RT1305_CLK_3 0x0618#define RT1305_DFLL_REG 0x0719#define RT1305_CAL_EFUSE_CLOCK 0x0820#define RT1305_PLL0_1 0x0a21#define RT1305_PLL0_2 0x0b22#define RT1305_PLL1_1 0x0c23#define RT1305_PLL1_2 0x0d24#define RT1305_MIXER_CTRL_1 0x1025#define RT1305_MIXER_CTRL_2 0x1126#define RT1305_DAC_SET_1 0x1227#define RT1305_DAC_SET_2 0x1428#define RT1305_ADC_SET_1 0x1629#define RT1305_ADC_SET_2 0x1730#define RT1305_ADC_SET_3 0x1831#define RT1305_PATH_SET 0x2032#define RT1305_SPDIF_IN_SET_1 0x2233#define RT1305_SPDIF_IN_SET_2 0x2434#define RT1305_SPDIF_IN_SET_3 0x2635#define RT1305_SPDIF_OUT_SET_1 0x2836#define RT1305_SPDIF_OUT_SET_2 0x2a37#define RT1305_SPDIF_OUT_SET_3 0x2b38#define RT1305_I2S_SET_1 0x2d39#define RT1305_I2S_SET_2 0x2e40#define RT1305_PBTL_MONO_MODE_SRC 0x2f41#define RT1305_MANUALLY_I2C_DEVICE 0x3242#define RT1305_POWER_STATUS 0x3943#define RT1305_POWER_CTRL_1 0x3a44#define RT1305_POWER_CTRL_2 0x3b45#define RT1305_POWER_CTRL_3 0x3c46#define RT1305_POWER_CTRL_4 0x3d47#define RT1305_POWER_CTRL_5 0x3e48#define RT1305_CLOCK_DETECT 0x3f49#define RT1305_BIQUAD_SET_1 0x4050#define RT1305_BIQUAD_SET_2 0x4251#define RT1305_ADJUSTED_HPF_1 0x4652#define RT1305_ADJUSTED_HPF_2 0x4753#define RT1305_EQ_SET_1 0x4b54#define RT1305_EQ_SET_2 0x4c55#define RT1305_SPK_TEMP_PROTECTION_0 0x4f56#define RT1305_SPK_TEMP_PROTECTION_1 0x5057#define RT1305_SPK_TEMP_PROTECTION_2 0x5158#define RT1305_SPK_TEMP_PROTECTION_3 0x5259#define RT1305_SPK_DC_DETECT_1 0x5360#define RT1305_SPK_DC_DETECT_2 0x5461#define RT1305_LOUDNESS 0x5862#define RT1305_THERMAL_FOLD_BACK_1 0x5e63#define RT1305_THERMAL_FOLD_BACK_2 0x5f64#define RT1305_SILENCE_DETECT 0x6065#define RT1305_ALC_DRC_1 0x6266#define RT1305_ALC_DRC_2 0x6367#define RT1305_ALC_DRC_3 0x6468#define RT1305_ALC_DRC_4 0x6569#define RT1305_PRIV_INDEX 0x6a70#define RT1305_PRIV_DATA 0x6c71#define RT1305_SPK_EXCURSION_LIMITER_7 0x7672#define RT1305_VERSION_ID 0x7a73#define RT1305_VENDOR_ID 0x7c74#define RT1305_DEVICE_ID 0x7e75#define RT1305_EFUSE_1 0x8076#define RT1305_EFUSE_2 0x8177#define RT1305_EFUSE_3 0x8278#define RT1305_DC_CALIB_1 0x9079#define RT1305_DC_CALIB_2 0x9180#define RT1305_DC_CALIB_3 0x9281#define RT1305_DAC_OFFSET_1 0x9382#define RT1305_DAC_OFFSET_2 0x9483#define RT1305_DAC_OFFSET_3 0x9584#define RT1305_DAC_OFFSET_4 0x9685#define RT1305_DAC_OFFSET_5 0x9786#define RT1305_DAC_OFFSET_6 0x9887#define RT1305_DAC_OFFSET_7 0x9988#define RT1305_DAC_OFFSET_8 0x9a89#define RT1305_DAC_OFFSET_9 0x9b90#define RT1305_DAC_OFFSET_10 0x9c91#define RT1305_DAC_OFFSET_11 0x9d92#define RT1305_DAC_OFFSET_12 0x9e93#define RT1305_DAC_OFFSET_13 0x9f94#define RT1305_DAC_OFFSET_14 0xa095#define RT1305_TRIM_1 0xb096#define RT1305_TRIM_2 0xb197#define RT1305_TUNE_INTERNAL_OSC 0xb298#define RT1305_BIQUAD1_H0_L_28_16 0xc099#define RT1305_BIQUAD3_A2_R_15_0 0xfb100#define RT1305_MAX_REG 0xff101 102/* CLOCK-1 (0x04) */103#define RT1305_SEL_PLL_SRC_2_MASK (0x1 << 15)104#define RT1305_SEL_PLL_SRC_2_SFT 15105#define RT1305_SEL_PLL_SRC_2_MCLK (0x0 << 15)106#define RT1305_SEL_PLL_SRC_2_RCCLK (0x1 << 15)107#define RT1305_DIV_PLL_SRC_2_MASK (0x3 << 13)108#define RT1305_DIV_PLL_SRC_2_SFT 13109#define RT1305_SEL_PLL_SRC_1_MASK (0x3 << 10)110#define RT1305_SEL_PLL_SRC_1_SFT 10111#define RT1305_SEL_PLL_SRC_1_PLL2 (0x0 << 10)112#define RT1305_SEL_PLL_SRC_1_BCLK (0x1 << 10)113#define RT1305_SEL_PLL_SRC_1_DFLL (0x2 << 10)114#define RT1305_SEL_FS_SYS_PRE_MASK (0x3 << 8)115#define RT1305_SEL_FS_SYS_PRE_SFT 8116#define RT1305_SEL_FS_SYS_PRE_MCLK (0x0 << 8)117#define RT1305_SEL_FS_SYS_PRE_PLL (0x1 << 8)118#define RT1305_SEL_FS_SYS_PRE_RCCLK (0x2 << 8)119#define RT1305_DIV_FS_SYS_MASK (0x7 << 4)120#define RT1305_DIV_FS_SYS_SFT 4121 122/* PLL1M/N/K Code-1 (0x0c) */123#define RT1305_PLL_1_M_SFT 12124#define RT1305_PLL_1_M_BYPASS_MASK (0x1 << 11)125#define RT1305_PLL_1_M_BYPASS_SFT 11126#define RT1305_PLL_1_M_BYPASS (0x1 << 11)127#define RT1305_PLL_1_N_MASK (0x1ff << 0)128 129/* DAC Setting (0x14) */130#define RT1305_DVOL_MUTE_L_EN_SFT 15131#define RT1305_DVOL_MUTE_R_EN_SFT 14132 133/* I2S Setting-1 (0x2d) */134#define RT1305_SEL_I2S_OUT_MODE_MASK (0x1 << 15)135#define RT1305_SEL_I2S_OUT_MODE_SFT 15136#define RT1305_SEL_I2S_OUT_MODE_S (0x0 << 15)137#define RT1305_SEL_I2S_OUT_MODE_M (0x1 << 15)138 139/* I2S Setting-2 (0x2e) */140#define RT1305_I2S_DF_SEL_MASK (0x3 << 12)141#define RT1305_I2S_DF_SEL_SFT 12142#define RT1305_I2S_DF_SEL_I2S (0x0 << 12)143#define RT1305_I2S_DF_SEL_LEFT (0x1 << 12)144#define RT1305_I2S_DF_SEL_PCM_A (0x2 << 12)145#define RT1305_I2S_DF_SEL_PCM_B (0x3 << 12)146#define RT1305_I2S_DL_SEL_MASK (0x3 << 10)147#define RT1305_I2S_DL_SEL_SFT 10148#define RT1305_I2S_DL_SEL_16B (0x0 << 10)149#define RT1305_I2S_DL_SEL_20B (0x1 << 10)150#define RT1305_I2S_DL_SEL_24B (0x2 << 10)151#define RT1305_I2S_DL_SEL_8B (0x3 << 10)152#define RT1305_I2S_BCLK_MASK (0x1 << 9)153#define RT1305_I2S_BCLK_SFT 9154#define RT1305_I2S_BCLK_NORMAL (0x0 << 9)155#define RT1305_I2S_BCLK_INV (0x1 << 9)156 157/* Power Control-1 (0x3a) */158#define RT1305_POW_PDB_JD_MASK (0x1 << 12)159#define RT1305_POW_PDB_JD (0x1 << 12)160#define RT1305_POW_PDB_JD_BIT 12161#define RT1305_POW_PLL0_EN (0x1 << 11)162#define RT1305_POW_PLL0_EN_BIT 11163#define RT1305_POW_PLL1_EN (0x1 << 10)164#define RT1305_POW_PLL1_EN_BIT 10165#define RT1305_POW_PDB_JD_POLARITY (0x1 << 9)166#define RT1305_POW_PDB_JD_POLARITY_BIT 9167#define RT1305_POW_MBIAS_LV (0x1 << 8)168#define RT1305_POW_MBIAS_LV_BIT 8169#define RT1305_POW_BG_MBIAS_LV (0x1 << 7)170#define RT1305_POW_BG_MBIAS_LV_BIT 7171#define RT1305_POW_LDO2 (0x1 << 6)172#define RT1305_POW_LDO2_BIT 6173#define RT1305_POW_BG2 (0x1 << 5)174#define RT1305_POW_BG2_BIT 5175#define RT1305_POW_LDO2_IB2 (0x1 << 4)176#define RT1305_POW_LDO2_IB2_BIT 4177#define RT1305_POW_VREF (0x1 << 3)178#define RT1305_POW_VREF_BIT 3179#define RT1305_POW_VREF1 (0x1 << 2)180#define RT1305_POW_VREF1_BIT 2181#define RT1305_POW_VREF2 (0x1 << 1)182#define RT1305_POW_VREF2_BIT 1183 184/* Power Control-2 (0x3b) */185#define RT1305_POW_DISC_VREF (1 << 15)186#define RT1305_POW_DISC_VREF_BIT 15187#define RT1305_POW_FASTB_VREF (1 << 14)188#define RT1305_POW_FASTB_VREF_BIT 14189#define RT1305_POW_ULTRA_FAST_VREF (1 << 13)190#define RT1305_POW_ULTRA_FAST_VREF_BIT 13191#define RT1305_POW_CKXEN_DAC (1 << 12)192#define RT1305_POW_CKXEN_DAC_BIT 12193#define RT1305_POW_EN_CKGEN_DAC (1 << 11)194#define RT1305_POW_EN_CKGEN_DAC_BIT 11195#define RT1305_POW_DAC1_L (1 << 10)196#define RT1305_POW_DAC1_L_BIT 10197#define RT1305_POW_DAC1_R (1 << 9)198#define RT1305_POW_DAC1_R_BIT 9199#define RT1305_POW_CLAMP (1 << 8)200#define RT1305_POW_CLAMP_BIT 8201#define RT1305_POW_BUFL (1 << 7)202#define RT1305_POW_BUFL_BIT 7203#define RT1305_POW_BUFR (1 << 6)204#define RT1305_POW_BUFR_BIT 6205#define RT1305_POW_EN_CKGEN_ADC (1 << 5)206#define RT1305_POW_EN_CKGEN_ADC_BIT 5207#define RT1305_POW_ADC3_L (1 << 4)208#define RT1305_POW_ADC3_L_BIT 4209#define RT1305_POW_ADC3_R (1 << 3)210#define RT1305_POW_ADC3_R_BIT 3211#define RT1305_POW_TRIOSC (1 << 2)212#define RT1305_POW_TRIOSC_BIT 2213#define RT1305_POR_AVDD1 (1 << 1)214#define RT1305_POR_AVDD1_BIT 1215#define RT1305_POR_AVDD2 (1 << 0)216#define RT1305_POR_AVDD2_BIT 0217 218/* Power Control-3 (0x3c) */219#define RT1305_POW_VSENSE_RCH (1 << 15)220#define RT1305_POW_VSENSE_RCH_BIT 15221#define RT1305_POW_VSENSE_LCH (1 << 14)222#define RT1305_POW_VSENSE_LCH_BIT 14223#define RT1305_POW_ISENSE_RCH (1 << 13)224#define RT1305_POW_ISENSE_RCH_BIT 13225#define RT1305_POW_ISENSE_LCH (1 << 12)226#define RT1305_POW_ISENSE_LCH_BIT 12227#define RT1305_POW_POR_AVDD1 (1 << 11)228#define RT1305_POW_POR_AVDD1_BIT 11229#define RT1305_POW_POR_AVDD2 (1 << 10)230#define RT1305_POW_POR_AVDD2_BIT 10231#define RT1305_EN_K_HV (1 << 9)232#define RT1305_EN_K_HV_BIT 9233#define RT1305_EN_PRE_K_HV (1 << 8)234#define RT1305_EN_PRE_K_HV_BIT 8235#define RT1305_EN_EFUSE_1P8V (1 << 7)236#define RT1305_EN_EFUSE_1P8V_BIT 7237#define RT1305_EN_EFUSE_5V (1 << 6)238#define RT1305_EN_EFUSE_5V_BIT 6239#define RT1305_EN_VCM_6172 (1 << 5)240#define RT1305_EN_VCM_6172_BIT 5241#define RT1305_POR_EFUSE (1 << 4)242#define RT1305_POR_EFUSE_BIT 4243 244/* Clock Detect (0x3f) */245#define RT1305_SEL_CLK_DET_SRC_MASK (0x1 << 12)246#define RT1305_SEL_CLK_DET_SRC_SFT 12247#define RT1305_SEL_CLK_DET_SRC_MCLK (0x0 << 12)248#define RT1305_SEL_CLK_DET_SRC_BCLK (0x1 << 12)249 250 251/* System Clock Source */252enum {253 RT1305_FS_SYS_PRE_S_MCLK,254 RT1305_FS_SYS_PRE_S_PLL1,255 RT1305_FS_SYS_PRE_S_RCCLK, /* 98.304M Hz */256};257 258/* PLL Source 1/2 */259enum {260 RT1305_PLL1_S_BCLK,261 RT1305_PLL2_S_MCLK,262 RT1305_PLL2_S_RCCLK, /* 98.304M Hz */263};264 265enum {266 RT1305_AIF1,267 RT1305_AIFS268};269 270#define R0_UPPER 0x2E8BA2 //5.5 ohm271#define R0_LOWER 0x666666 //2.5 ohm272 273#endif /* end of _RT1305_H_ */274