295 lines · c
1/* SPDX-License-Identifier: GPL-2.0 */2/*3 * rt1308.h -- RT1308 ALSA SoC amplifier component driver4 *5 * Copyright 2019 Realtek Semiconductor Corp.6 * Author: Derek Fang <derek.fang@realtek.com>7 *8 */9 10#ifndef _RT1308_H_11#define _RT1308_H_12 13#define RT1308_DEVICE_ID_NUM 0x10ec130014 15#define RT1308_RESET 0x0016#define RT1308_RESET_N 0x0117#define RT1308_CLK_GATING 0x0218#define RT1308_PLL_1 0x0319#define RT1308_PLL_2 0x0420#define RT1308_PLL_INT 0x0521#define RT1308_CLK_1 0x0622#define RT1308_DATA_PATH 0x0723#define RT1308_CLK_2 0x0824#define RT1308_SIL_DET 0x0925#define RT1308_CLK_DET 0x0a26#define RT1308_DC_DET 0x0b27#define RT1308_DC_DET_THRES 0x0c28#define RT1308_DAC_SET 0x1029#define RT1308_SRC_SET 0x1130#define RT1308_DAC_BUF 0x1231#define RT1308_ADC_SET 0x1332#define RT1308_ADC_SET_INT 0x1433#define RT1308_I2S_SET_1 0x1534#define RT1308_I2S_SET_2 0x1635#define RT1308_I2C_I2S_SDW_SET 0x1736#define RT1308_SDW_REG_RW 0x1837#define RT1308_SDW_REG_RDATA 0x1938#define RT1308_IV_SENSE 0x1a39#define RT1308_I2S_TX_DAC_SET 0x1b40#define RT1308_AD_FILTER_SET 0x1c41#define RT1308_DC_CAL_1 0x2042#define RT1308_DC_CAL_2 0x2143#define RT1308_DC_CAL_L_OFFSET 0x2244#define RT1308_DC_CAL_R_OFFSET 0x2345#define RT1308_PVDD_OFFSET_CTL 0x2446#define RT1308_PVDD_OFFSET_L 0x2547#define RT1308_PVDD_OFFSET_R 0x2648#define RT1308_PVDD_OFFSET_PBTL 0x2749#define RT1308_PVDD_OFFSET_PVDD 0x2850#define RT1308_CAL_OFFSET_DAC_PBTL 0x2951#define RT1308_CAL_OFFSET_DAC_L 0x2a52#define RT1308_CAL_OFFSET_DAC_R 0x2b53#define RT1308_CAL_OFFSET_PWM_L 0x2c54#define RT1308_CAL_OFFSET_PWM_R 0x2d55#define RT1308_CAL_PWM_VOS_ADC_L 0x2e56#define RT1308_CAL_PWM_VOS_ADC_R 0x2f57#define RT1308_CLASS_D_SET_1 0x3058#define RT1308_CLASS_D_SET_2 0x3159#define RT1308_POWER 0x3260#define RT1308_LDO 0x3361#define RT1308_VREF 0x3462#define RT1308_MBIAS 0x3563#define RT1308_POWER_STATUS 0x3664#define RT1308_POWER_INT 0x3765#define RT1308_SINE_TONE_GEN_1 0x5066#define RT1308_SINE_TONE_GEN_2 0x5167#define RT1308_BQ_SET 0x5468#define RT1308_BQ_PARA_UPDATE 0x5569#define RT1308_BQ_PRE_VOL_L 0x5670#define RT1308_BQ_PRE_VOL_R 0x5771#define RT1308_BQ_POST_VOL_L 0x5872#define RT1308_BQ_POST_VOL_R 0x5973#define RT1308_BQ1_L_H0 0x5b74#define RT1308_BQ1_L_B1 0x5c75#define RT1308_BQ1_L_B2 0x5d76#define RT1308_BQ1_L_A1 0x5e77#define RT1308_BQ1_L_A2 0x5f78#define RT1308_BQ1_R_H0 0x6079#define RT1308_BQ1_R_B1 0x6180#define RT1308_BQ1_R_B2 0x6281#define RT1308_BQ1_R_A1 0x6382#define RT1308_BQ1_R_A2 0x6483#define RT1308_BQ2_L_H0 0x6584#define RT1308_BQ2_L_B1 0x6685#define RT1308_BQ2_L_B2 0x6786#define RT1308_BQ2_L_A1 0x6887#define RT1308_BQ2_L_A2 0x6988#define RT1308_BQ2_R_H0 0x6a89#define RT1308_BQ2_R_B1 0x6b90#define RT1308_BQ2_R_B2 0x6c91#define RT1308_BQ2_R_A1 0x6d92#define RT1308_BQ2_R_A2 0x6e93#define RT1308_VEN_DEV_ID 0x7094#define RT1308_VERSION_ID 0x7195#define RT1308_SPK_BOUND 0x7296#define RT1308_BQ1_EQ_L_1 0x7397#define RT1308_BQ1_EQ_L_2 0x7498#define RT1308_BQ1_EQ_L_3 0x7599#define RT1308_BQ1_EQ_R_1 0x76100#define RT1308_BQ1_EQ_R_2 0x77101#define RT1308_BQ1_EQ_R_3 0x78102#define RT1308_BQ2_EQ_L_1 0x79103#define RT1308_BQ2_EQ_L_2 0x7a104#define RT1308_BQ2_EQ_L_3 0x7b105#define RT1308_BQ2_EQ_R_1 0x7c106#define RT1308_BQ2_EQ_R_2 0x7d107#define RT1308_BQ2_EQ_R_3 0x7e108#define RT1308_EFUSE_1 0x7f109#define RT1308_EFUSE_2 0x80110#define RT1308_EFUSE_PROG_PVDD_L 0x81111#define RT1308_EFUSE_PROG_PVDD_R 0x82112#define RT1308_EFUSE_PROG_R0_L 0x83113#define RT1308_EFUSE_PROG_R0_R 0x84114#define RT1308_EFUSE_PROG_DEV 0x85115#define RT1308_EFUSE_READ_PVDD_L 0x86116#define RT1308_EFUSE_READ_PVDD_R 0x87117#define RT1308_EFUSE_READ_PVDD_PTBL 0x88118#define RT1308_EFUSE_READ_DEV 0x89119#define RT1308_EFUSE_READ_R0 0x8a120#define RT1308_EFUSE_READ_ADC_L 0x8b121#define RT1308_EFUSE_READ_ADC_R 0x8c122#define RT1308_EFUSE_READ_ADC_PBTL 0x8d123#define RT1308_EFUSE_RESERVE 0x8e124#define RT1308_PADS_1 0x90125#define RT1308_PADS_2 0x91126#define RT1308_TEST_MODE 0xa0127#define RT1308_TEST_1 0xa1128#define RT1308_TEST_2 0xa2129#define RT1308_TEST_3 0xa3130#define RT1308_TEST_4 0xa4131#define RT1308_EFUSE_DATA_0_MSB 0xb0132#define RT1308_EFUSE_DATA_0_LSB 0xb1133#define RT1308_EFUSE_DATA_1_MSB 0xb2134#define RT1308_EFUSE_DATA_1_LSB 0xb3135#define RT1308_EFUSE_DATA_2_MSB 0xb4136#define RT1308_EFUSE_DATA_2_LSB 0xb5137#define RT1308_EFUSE_DATA_3_MSB 0xb6138#define RT1308_EFUSE_DATA_3_LSB 0xb7139#define RT1308_EFUSE_DATA_TEST_MSB 0xb8140#define RT1308_EFUSE_DATA_TEST_LSB 0xb9141#define RT1308_EFUSE_STATUS_1 0xba142#define RT1308_EFUSE_STATUS_2 0xbb143#define RT1308_TCON_1 0xc0144#define RT1308_TCON_2 0xc1145#define RT1308_DUMMY_REG 0xf0146#define RT1308_MAX_REG 0xff147 148/* PLL1 M/N/K Code-1 (0x03) */149#define RT1308_PLL1_K_SFT 24150#define RT1308_PLL1_K_MASK (0x1f << 24)151#define RT1308_PLL1_M_BYPASS_MASK (0x1 << 23)152#define RT1308_PLL1_M_BYPASS_SFT 23153#define RT1308_PLL1_M_BYPASS (0x1 << 23)154#define RT1308_PLL1_M_MASK (0x3f << 16)155#define RT1308_PLL1_M_SFT 16156#define RT1308_PLL1_N_MASK (0x7f << 8)157#define RT1308_PLL1_N_SFT 8158 159/* CLOCK-1 (0x06) */160#define RT1308_DIV_FS_SYS_MASK (0xf << 28)161#define RT1308_DIV_FS_SYS_SFT 28162#define RT1308_SEL_FS_SYS_MASK (0x7 << 24)163#define RT1308_SEL_FS_SYS_SFT 24164#define RT1308_SEL_FS_SYS_SRC_MCLK (0x0 << 24)165#define RT1308_SEL_FS_SYS_SRC_BCLK (0x1 << 24)166#define RT1308_SEL_FS_SYS_SRC_PLL (0x2 << 24)167#define RT1308_SEL_FS_SYS_SRC_RCCLK (0x4 << 24)168 169/* CLOCK-2 (0x08) */170#define RT1308_DIV_PRE_PLL_MASK (0xf << 28)171#define RT1308_DIV_PRE_PLL_SFT 28172#define RT1308_SEL_PLL_SRC_MASK (0x7 << 24)173#define RT1308_SEL_PLL_SRC_SFT 24174#define RT1308_SEL_PLL_SRC_MCLK (0x0 << 24)175#define RT1308_SEL_PLL_SRC_BCLK (0x1 << 24)176#define RT1308_SEL_PLL_SRC_RCCLK (0x4 << 24)177 178/* Clock Detect (0x0a) */179#define RT1308_MCLK_DET_EN_MASK (0x1 << 25)180#define RT1308_MCLK_DET_EN_SFT 25181#define RT1308_MCLK_DET_EN (0x1 << 25)182#define RT1308_BCLK_DET_EN_MASK (0x1 << 24)183#define RT1308_BCLK_DET_EN_SFT 24184#define RT1308_BCLK_DET_EN (0x1 << 24)185 186/* DAC Setting (0x10) */187#define RT1308_DVOL_MUTE_R_EN_SFT 7188#define RT1308_DVOL_MUTE_L_EN_SFT 6189 190/* I2S Setting-1 (0x15) */191#define RT1308_I2S_DF_SEL_MASK (0x3 << 12)192#define RT1308_I2S_DF_SEL_SFT 12193#define RT1308_I2S_DF_SEL_I2S (0x0 << 12)194#define RT1308_I2S_DF_SEL_LEFT (0x1 << 12)195#define RT1308_I2S_DF_SEL_PCM_A (0x2 << 12)196#define RT1308_I2S_DF_SEL_PCM_B (0x3 << 12)197#define RT1308_I2S_DL_RX_SEL_MASK (0x7 << 4)198#define RT1308_I2S_DL_RX_SEL_SFT 4199#define RT1308_I2S_DL_RX_SEL_16B (0x0 << 4)200#define RT1308_I2S_DL_RX_SEL_20B (0x1 << 4)201#define RT1308_I2S_DL_RX_SEL_24B (0x2 << 4)202#define RT1308_I2S_DL_RX_SEL_32B (0x3 << 4)203#define RT1308_I2S_DL_RX_SEL_8B (0x4 << 4)204#define RT1308_I2S_DL_TX_SEL_MASK (0x7 << 0)205#define RT1308_I2S_DL_TX_SEL_SFT 0206#define RT1308_I2S_DL_TX_SEL_16B (0x0 << 0)207#define RT1308_I2S_DL_TX_SEL_20B (0x1 << 0)208#define RT1308_I2S_DL_TX_SEL_24B (0x2 << 0)209#define RT1308_I2S_DL_TX_SEL_32B (0x3 << 0)210#define RT1308_I2S_DL_TX_SEL_8B (0x4 << 0)211 212/* I2S Setting-2 (0x16) */213#define RT1308_I2S_DL_SEL_MASK (0x7 << 24)214#define RT1308_I2S_DL_SEL_SFT 24215#define RT1308_I2S_DL_SEL_16B (0x0 << 24)216#define RT1308_I2S_DL_SEL_20B (0x1 << 24)217#define RT1308_I2S_DL_SEL_24B (0x2 << 24)218#define RT1308_I2S_DL_SEL_32B (0x3 << 24)219#define RT1308_I2S_DL_SEL_8B (0x4 << 24)220#define RT1308_I2S_BCLK_MASK (0x1 << 14)221#define RT1308_I2S_BCLK_SFT 14222#define RT1308_I2S_BCLK_NORMAL (0x0 << 14)223#define RT1308_I2S_BCLK_INV (0x1 << 14)224 225/* Power Control-1 (0x32) */226#define RT1308_POW_MBIAS20U (0x1 << 31)227#define RT1308_POW_MBIAS20U_BIT 31228#define RT1308_POW_ALDO (0x1 << 30)229#define RT1308_POW_ALDO_BIT 30230#define RT1308_POW_DBG (0x1 << 29)231#define RT1308_POW_DBG_BIT 29232#define RT1308_POW_DACL (0x1 << 28)233#define RT1308_POW_DACL_BIT 28234#define RT1308_POW_DAC1 (0x1 << 27)235#define RT1308_POW_DAC1_BIT 27236#define RT1308_POW_CLK25M (0x1 << 26)237#define RT1308_POW_CLK25M_BIT 26238#define RT1308_POW_ADC_R (0x1 << 25)239#define RT1308_POW_ADC_R_BIT 25240#define RT1308_POW_ADC_L (0x1 << 24)241#define RT1308_POW_ADC_L_BIT 24242#define RT1308_POW_DLDO (0x1 << 21)243#define RT1308_POW_DLDO_BIT 21244#define RT1308_POW_VREF (0x1 << 20)245#define RT1308_POW_VREF_BIT 20246#define RT1308_POW_MIXER_R (0x1 << 18)247#define RT1308_POW_MIXER_R_BIT 18248#define RT1308_POW_MIXER_L (0x1 << 17)249#define RT1308_POW_MIXER_L_BIT 17250#define RT1308_POW_MBIAS4U (0x1 << 16)251#define RT1308_POW_MBIAS4U_BIT 16252#define RT1308_POW_PLL2_LDO_EN (0x1 << 12)253#define RT1308_POW_PLL2_LDO_EN_BIT 12254#define RT1308_POW_PLL2B_EN (0x1 << 11)255#define RT1308_POW_PLL2B_EN_BIT 11256#define RT1308_POW_PLL2F_EN (0x1 << 10)257#define RT1308_POW_PLL2F_EN_BIT 10258#define RT1308_POW_PLL2F2_EN (0x1 << 9)259#define RT1308_POW_PLL2F2_EN_BIT 9260#define RT1308_POW_PLL2B2_EN (0x1 << 8)261#define RT1308_POW_PLL2B2_EN_BIT 8262 263/* Power Control-2 (0x36) */264#define RT1308_POW_PDB_SRC_BIT (0x1 << 27)265#define RT1308_POW_PDB_MN_BIT (0x1 << 25)266#define RT1308_POW_PDB_REG_BIT (0x1 << 24)267 268 269/* System Clock Source */270enum {271 RT1308_FS_SYS_S_MCLK,272 RT1308_FS_SYS_S_BCLK,273 RT1308_FS_SYS_S_PLL,274 RT1308_FS_SYS_S_RCCLK, /* 25.0 MHz */275};276 277/* PLL Source */278enum {279 RT1308_PLL_S_MCLK,280 RT1308_PLL_S_BCLK,281 RT1308_PLL_S_RCCLK,282};283 284enum {285 RT1308_AIF1,286 RT1308_AIFS287};288 289enum rt1308_hw_ver {290 RT1308_VER_C = 2,291 RT1308_VER_D292};293 294#endif /* end of _RT1308_H_ */295