1234 lines · c
1// SPDX-License-Identifier: GPL-2.0-only2/*3 * rt274.c -- RT274 ALSA SoC audio codec driver4 *5 * Copyright 2017 Realtek Semiconductor Corp.6 * Author: Bard Liao <bardliao@realtek.com>7 */8 9#include <linux/module.h>10#include <linux/moduleparam.h>11#include <linux/init.h>12#include <linux/delay.h>13#include <linux/pm.h>14#include <linux/i2c.h>15#include <linux/platform_device.h>16#include <linux/spi/spi.h>17#include <linux/dmi.h>18#include <linux/acpi.h>19#include <sound/core.h>20#include <sound/pcm.h>21#include <sound/pcm_params.h>22#include <sound/soc.h>23#include <sound/soc-dapm.h>24#include <sound/initval.h>25#include <sound/tlv.h>26#include <sound/jack.h>27#include <linux/workqueue.h>28 29#include "rl6347a.h"30#include "rt274.h"31 32#define RT274_VENDOR_ID 0x10ec027433 34struct rt274_priv {35 struct reg_default *index_cache;36 int index_cache_size;37 struct regmap *regmap;38 struct snd_soc_component *component;39 struct i2c_client *i2c;40 struct snd_soc_jack *jack;41 struct delayed_work jack_detect_work;42 int sys_clk;43 int clk_id;44 int fs;45 bool master;46};47 48static const struct reg_default rt274_index_def[] = {49 { 0x00, 0x1004 },50 { 0x01, 0xaaaa },51 { 0x02, 0x88aa },52 { 0x03, 0x0002 },53 { 0x04, 0xaa09 },54 { 0x05, 0x0700 },55 { 0x06, 0x6110 },56 { 0x07, 0x0200 },57 { 0x08, 0xa807 },58 { 0x09, 0x0021 },59 { 0x0a, 0x7770 },60 { 0x0b, 0x7770 },61 { 0x0c, 0x002b },62 { 0x0d, 0x2420 },63 { 0x0e, 0x65c0 },64 { 0x0f, 0x7770 },65 { 0x10, 0x0420 },66 { 0x11, 0x7418 },67 { 0x12, 0x6bd0 },68 { 0x13, 0x645f },69 { 0x14, 0x0400 },70 { 0x15, 0x8ccc },71 { 0x16, 0x4c50 },72 { 0x17, 0xff00 },73 { 0x18, 0x0003 },74 { 0x19, 0x2c11 },75 { 0x1a, 0x830b },76 { 0x1b, 0x4e4b },77 { 0x1c, 0x0000 },78 { 0x1d, 0x0000 },79 { 0x1e, 0x0000 },80 { 0x1f, 0x0000 },81 { 0x20, 0x51ff },82 { 0x21, 0x8000 },83 { 0x22, 0x8f00 },84 { 0x23, 0x88f4 },85 { 0x24, 0x0000 },86 { 0x25, 0x0000 },87 { 0x26, 0x0000 },88 { 0x27, 0x0000 },89 { 0x28, 0x0000 },90 { 0x29, 0x3000 },91 { 0x2a, 0x0000 },92 { 0x2b, 0x0000 },93 { 0x2c, 0x0f00 },94 { 0x2d, 0x100f },95 { 0x2e, 0x2902 },96 { 0x2f, 0xe280 },97 { 0x30, 0x1000 },98 { 0x31, 0x8400 },99 { 0x32, 0x5aaa },100 { 0x33, 0x8420 },101 { 0x34, 0xa20c },102 { 0x35, 0x096a },103 { 0x36, 0x5757 },104 { 0x37, 0xfe05 },105 { 0x38, 0x4901 },106 { 0x39, 0x110a },107 { 0x3a, 0x0010 },108 { 0x3b, 0x60d9 },109 { 0x3c, 0xf214 },110 { 0x3d, 0xc2ba },111 { 0x3e, 0xa928 },112 { 0x3f, 0x0000 },113 { 0x40, 0x9800 },114 { 0x41, 0x0000 },115 { 0x42, 0x2000 },116 { 0x43, 0x3d90 },117 { 0x44, 0x4900 },118 { 0x45, 0x5289 },119 { 0x46, 0x0004 },120 { 0x47, 0xa47a },121 { 0x48, 0xd049 },122 { 0x49, 0x0049 },123 { 0x4a, 0xa83b },124 { 0x4b, 0x0777 },125 { 0x4c, 0x065c },126 { 0x4d, 0x7fff },127 { 0x4e, 0x7fff },128 { 0x4f, 0x0000 },129 { 0x50, 0x0000 },130 { 0x51, 0x0000 },131 { 0x52, 0xbf5f },132 { 0x53, 0x3320 },133 { 0x54, 0xcc00 },134 { 0x55, 0x0000 },135 { 0x56, 0x3f00 },136 { 0x57, 0x0000 },137 { 0x58, 0x0000 },138 { 0x59, 0x0000 },139 { 0x5a, 0x1300 },140 { 0x5b, 0x005f },141 { 0x5c, 0x0000 },142 { 0x5d, 0x1001 },143 { 0x5e, 0x1000 },144 { 0x5f, 0x0000 },145 { 0x60, 0x5554 },146 { 0x61, 0xffc0 },147 { 0x62, 0xa000 },148 { 0x63, 0xd010 },149 { 0x64, 0x0000 },150 { 0x65, 0x3fb1 },151 { 0x66, 0x1881 },152 { 0x67, 0xc810 },153 { 0x68, 0x2000 },154 { 0x69, 0xfff0 },155 { 0x6a, 0x0300 },156 { 0x6b, 0x5060 },157 { 0x6c, 0x0000 },158 { 0x6d, 0x0000 },159 { 0x6e, 0x0c25 },160 { 0x6f, 0x0c0b },161 { 0x70, 0x8000 },162 { 0x71, 0x4008 },163 { 0x72, 0x0000 },164 { 0x73, 0x0800 },165 { 0x74, 0xa28f },166 { 0x75, 0xa050 },167 { 0x76, 0x7fe8 },168 { 0x77, 0xdb8c },169 { 0x78, 0x0000 },170 { 0x79, 0x0000 },171 { 0x7a, 0x2a96 },172 { 0x7b, 0x800f },173 { 0x7c, 0x0200 },174 { 0x7d, 0x1600 },175 { 0x7e, 0x0000 },176 { 0x7f, 0x0000 },177};178#define INDEX_CACHE_SIZE ARRAY_SIZE(rt274_index_def)179 180static const struct reg_default rt274_reg[] = {181 { 0x00170500, 0x00000400 },182 { 0x00220000, 0x00000031 },183 { 0x00239000, 0x00000057 },184 { 0x0023a000, 0x00000057 },185 { 0x00270500, 0x00000400 },186 { 0x00370500, 0x00000400 },187 { 0x00870500, 0x00000400 },188 { 0x00920000, 0x00000031 },189 { 0x00935000, 0x00000097 },190 { 0x00936000, 0x00000097 },191 { 0x00970500, 0x00000400 },192 { 0x00b37000, 0x00000400 },193 { 0x00b37200, 0x00000400 },194 { 0x00b37300, 0x00000400 },195 { 0x00c37000, 0x00000400 },196 { 0x00c37100, 0x00000400 },197 { 0x01270500, 0x00000400 },198 { 0x01370500, 0x00000400 },199 { 0x01371f00, 0x411111f0 },200 { 0x01937000, 0x00000000 },201 { 0x01970500, 0x00000400 },202 { 0x02050000, 0x0000001b },203 { 0x02139000, 0x00000080 },204 { 0x0213a000, 0x00000080 },205 { 0x02170100, 0x00000001 },206 { 0x02170500, 0x00000400 },207 { 0x02170700, 0x00000000 },208 { 0x02270100, 0x00000000 },209 { 0x02370100, 0x00000000 },210 { 0x01970700, 0x00000020 },211 { 0x00830000, 0x00000097 },212 { 0x00930000, 0x00000097 },213 { 0x01270700, 0x00000000 },214};215 216static bool rt274_volatile_register(struct device *dev, unsigned int reg)217{218 switch (reg) {219 case 0 ... 0xff:220 case RT274_GET_PARAM(AC_NODE_ROOT, AC_PAR_VENDOR_ID):221 case RT274_GET_HP_SENSE:222 case RT274_GET_MIC_SENSE:223 case RT274_PROC_COEF:224 case VERB_CMD(AC_VERB_GET_EAPD_BTLENABLE, RT274_MIC, 0):225 case VERB_CMD(AC_VERB_GET_EAPD_BTLENABLE, RT274_HP_OUT, 0):226 case VERB_CMD(AC_VERB_GET_STREAM_FORMAT, RT274_DAC_OUT0, 0):227 case VERB_CMD(AC_VERB_GET_STREAM_FORMAT, RT274_DAC_OUT1, 0):228 case VERB_CMD(AC_VERB_GET_STREAM_FORMAT, RT274_ADC_IN1, 0):229 case VERB_CMD(AC_VERB_GET_STREAM_FORMAT, RT274_ADC_IN2, 0):230 case VERB_CMD(AC_VERB_GET_AMP_GAIN_MUTE, RT274_DAC_OUT0, 0):231 case VERB_CMD(AC_VERB_GET_AMP_GAIN_MUTE, RT274_DAC_OUT1, 0):232 case VERB_CMD(AC_VERB_GET_AMP_GAIN_MUTE, RT274_ADC_IN1, 0):233 case VERB_CMD(AC_VERB_GET_AMP_GAIN_MUTE, RT274_ADC_IN2, 0):234 case VERB_CMD(AC_VERB_GET_AMP_GAIN_MUTE, RT274_DMIC1, 0):235 case VERB_CMD(AC_VERB_GET_AMP_GAIN_MUTE, RT274_DMIC2, 0):236 case VERB_CMD(AC_VERB_GET_AMP_GAIN_MUTE, RT274_MIC, 0):237 case VERB_CMD(AC_VERB_GET_AMP_GAIN_MUTE, RT274_LINE1, 0):238 case VERB_CMD(AC_VERB_GET_AMP_GAIN_MUTE, RT274_LINE2, 0):239 case VERB_CMD(AC_VERB_GET_AMP_GAIN_MUTE, RT274_HP_OUT, 0):240 case VERB_CMD(AC_VERB_GET_CONNECT_SEL, RT274_HP_OUT, 0):241 case VERB_CMD(AC_VERB_GET_CONNECT_SEL, RT274_MIXER_IN1, 0):242 case VERB_CMD(AC_VERB_GET_CONNECT_SEL, RT274_MIXER_IN2, 0):243 case VERB_CMD(AC_VERB_GET_PIN_WIDGET_CONTROL, RT274_DMIC1, 0):244 case VERB_CMD(AC_VERB_GET_PIN_WIDGET_CONTROL, RT274_DMIC2, 0):245 case VERB_CMD(AC_VERB_GET_PIN_WIDGET_CONTROL, RT274_MIC, 0):246 case VERB_CMD(AC_VERB_GET_PIN_WIDGET_CONTROL, RT274_LINE1, 0):247 case VERB_CMD(AC_VERB_GET_PIN_WIDGET_CONTROL, RT274_LINE2, 0):248 case VERB_CMD(AC_VERB_GET_PIN_WIDGET_CONTROL, RT274_HP_OUT, 0):249 case VERB_CMD(AC_VERB_GET_UNSOLICITED_RESPONSE, RT274_HP_OUT, 0):250 case VERB_CMD(AC_VERB_GET_UNSOLICITED_RESPONSE, RT274_MIC, 0):251 case VERB_CMD(AC_VERB_GET_UNSOLICITED_RESPONSE, RT274_INLINE_CMD, 0):252 return true;253 default:254 return false;255 }256 257 258}259 260static bool rt274_readable_register(struct device *dev, unsigned int reg)261{262 switch (reg) {263 case 0 ... 0xff:264 case RT274_GET_PARAM(AC_NODE_ROOT, AC_PAR_VENDOR_ID):265 case RT274_GET_HP_SENSE:266 case RT274_GET_MIC_SENSE:267 case RT274_SET_AUDIO_POWER:268 case RT274_SET_HPO_POWER:269 case RT274_SET_DMIC1_POWER:270 case RT274_LOUT_MUX:271 case RT274_HPO_MUX:272 case RT274_ADC0_MUX:273 case RT274_ADC1_MUX:274 case RT274_SET_MIC:275 case RT274_SET_PIN_HPO:276 case RT274_SET_PIN_LOUT3:277 case RT274_SET_PIN_DMIC1:278 case RT274_SET_AMP_GAIN_HPO:279 case RT274_SET_DMIC2_DEFAULT:280 case RT274_DAC0L_GAIN:281 case RT274_DAC0R_GAIN:282 case RT274_DAC1L_GAIN:283 case RT274_DAC1R_GAIN:284 case RT274_ADCL_GAIN:285 case RT274_ADCR_GAIN:286 case RT274_MIC_GAIN:287 case RT274_HPOL_GAIN:288 case RT274_HPOR_GAIN:289 case RT274_LOUTL_GAIN:290 case RT274_LOUTR_GAIN:291 case RT274_DAC_FORMAT:292 case RT274_ADC_FORMAT:293 case RT274_COEF_INDEX:294 case RT274_PROC_COEF:295 case RT274_SET_AMP_GAIN_ADC_IN1:296 case RT274_SET_AMP_GAIN_ADC_IN2:297 case RT274_SET_POWER(RT274_DAC_OUT0):298 case RT274_SET_POWER(RT274_DAC_OUT1):299 case RT274_SET_POWER(RT274_ADC_IN1):300 case RT274_SET_POWER(RT274_ADC_IN2):301 case RT274_SET_POWER(RT274_DMIC2):302 case RT274_SET_POWER(RT274_MIC):303 case VERB_CMD(AC_VERB_GET_EAPD_BTLENABLE, RT274_MIC, 0):304 case VERB_CMD(AC_VERB_GET_EAPD_BTLENABLE, RT274_HP_OUT, 0):305 case VERB_CMD(AC_VERB_GET_STREAM_FORMAT, RT274_DAC_OUT0, 0):306 case VERB_CMD(AC_VERB_GET_STREAM_FORMAT, RT274_DAC_OUT1, 0):307 case VERB_CMD(AC_VERB_GET_STREAM_FORMAT, RT274_ADC_IN1, 0):308 case VERB_CMD(AC_VERB_GET_STREAM_FORMAT, RT274_ADC_IN2, 0):309 case VERB_CMD(AC_VERB_GET_AMP_GAIN_MUTE, RT274_DAC_OUT0, 0):310 case VERB_CMD(AC_VERB_GET_AMP_GAIN_MUTE, RT274_DAC_OUT1, 0):311 case VERB_CMD(AC_VERB_GET_AMP_GAIN_MUTE, RT274_ADC_IN1, 0):312 case VERB_CMD(AC_VERB_GET_AMP_GAIN_MUTE, RT274_ADC_IN2, 0):313 case VERB_CMD(AC_VERB_GET_AMP_GAIN_MUTE, RT274_DMIC1, 0):314 case VERB_CMD(AC_VERB_GET_AMP_GAIN_MUTE, RT274_DMIC2, 0):315 case VERB_CMD(AC_VERB_GET_AMP_GAIN_MUTE, RT274_MIC, 0):316 case VERB_CMD(AC_VERB_GET_AMP_GAIN_MUTE, RT274_LINE1, 0):317 case VERB_CMD(AC_VERB_GET_AMP_GAIN_MUTE, RT274_LINE2, 0):318 case VERB_CMD(AC_VERB_GET_AMP_GAIN_MUTE, RT274_HP_OUT, 0):319 case VERB_CMD(AC_VERB_GET_CONNECT_SEL, RT274_HP_OUT, 0):320 case VERB_CMD(AC_VERB_GET_CONNECT_SEL, RT274_MIXER_IN1, 0):321 case VERB_CMD(AC_VERB_GET_CONNECT_SEL, RT274_MIXER_IN2, 0):322 case VERB_CMD(AC_VERB_GET_PIN_WIDGET_CONTROL, RT274_DMIC1, 0):323 case VERB_CMD(AC_VERB_GET_PIN_WIDGET_CONTROL, RT274_DMIC2, 0):324 case VERB_CMD(AC_VERB_GET_PIN_WIDGET_CONTROL, RT274_MIC, 0):325 case VERB_CMD(AC_VERB_GET_PIN_WIDGET_CONTROL, RT274_LINE1, 0):326 case VERB_CMD(AC_VERB_GET_PIN_WIDGET_CONTROL, RT274_LINE2, 0):327 case VERB_CMD(AC_VERB_GET_PIN_WIDGET_CONTROL, RT274_HP_OUT, 0):328 case VERB_CMD(AC_VERB_GET_UNSOLICITED_RESPONSE, RT274_HP_OUT, 0):329 case VERB_CMD(AC_VERB_GET_UNSOLICITED_RESPONSE, RT274_MIC, 0):330 case VERB_CMD(AC_VERB_GET_UNSOLICITED_RESPONSE, RT274_INLINE_CMD, 0):331 return true;332 default:333 return false;334 }335}336 337#ifdef CONFIG_PM338static void rt274_index_sync(struct snd_soc_component *component)339{340 struct rt274_priv *rt274 = snd_soc_component_get_drvdata(component);341 int i;342 343 for (i = 0; i < INDEX_CACHE_SIZE; i++) {344 snd_soc_component_write(component, rt274->index_cache[i].reg,345 rt274->index_cache[i].def);346 }347}348#endif349 350static int rt274_jack_detect(struct rt274_priv *rt274, bool *hp, bool *mic)351{352 unsigned int buf;353 int ret;354 355 *hp = false;356 *mic = false;357 358 if (!rt274->component)359 return -EINVAL;360 361 ret = regmap_read(rt274->regmap, RT274_GET_HP_SENSE, &buf);362 if (ret)363 return ret;364 365 *hp = buf & 0x80000000;366 ret = regmap_read(rt274->regmap, RT274_GET_MIC_SENSE, &buf);367 if (ret)368 return ret;369 370 *mic = buf & 0x80000000;371 372 pr_debug("*hp = %d *mic = %d\n", *hp, *mic);373 374 return 0;375}376 377static void rt274_jack_detect_work(struct work_struct *work)378{379 struct rt274_priv *rt274 =380 container_of(work, struct rt274_priv, jack_detect_work.work);381 int status = 0;382 bool hp = false;383 bool mic = false;384 385 if (rt274_jack_detect(rt274, &hp, &mic) < 0)386 return;387 388 if (hp)389 status |= SND_JACK_HEADPHONE;390 391 if (mic)392 status |= SND_JACK_MICROPHONE;393 394 snd_soc_jack_report(rt274->jack, status,395 SND_JACK_MICROPHONE | SND_JACK_HEADPHONE);396}397 398static irqreturn_t rt274_irq(int irq, void *data);399 400static int rt274_mic_detect(struct snd_soc_component *component,401 struct snd_soc_jack *jack, void *data)402{403 struct rt274_priv *rt274 = snd_soc_component_get_drvdata(component);404 405 rt274->jack = jack;406 407 if (jack == NULL) {408 /* Disable jack detection */409 regmap_update_bits(rt274->regmap, RT274_EAPD_GPIO_IRQ_CTRL,410 RT274_IRQ_EN, RT274_IRQ_DIS);411 412 return 0;413 }414 415 regmap_update_bits(rt274->regmap, RT274_EAPD_GPIO_IRQ_CTRL,416 RT274_IRQ_EN, RT274_IRQ_EN);417 418 /* Send an initial report */419 rt274_irq(0, rt274);420 421 return 0;422}423 424static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -6350, 50, 0);425static const DECLARE_TLV_DB_SCALE(mic_vol_tlv, 0, 1000, 0);426 427static const struct snd_kcontrol_new rt274_snd_controls[] = {428 SOC_DOUBLE_R_TLV("DAC0 Playback Volume", RT274_DAC0L_GAIN,429 RT274_DAC0R_GAIN, 0, 0x7f, 0, out_vol_tlv),430 SOC_DOUBLE_R_TLV("DAC1 Playback Volume", RT274_DAC1L_GAIN,431 RT274_DAC1R_GAIN, 0, 0x7f, 0, out_vol_tlv),432 SOC_DOUBLE_R_TLV("ADC0 Capture Volume", RT274_ADCL_GAIN,433 RT274_ADCR_GAIN, 0, 0x7f, 0, out_vol_tlv),434 SOC_DOUBLE_R("ADC0 Capture Switch", RT274_ADCL_GAIN,435 RT274_ADCR_GAIN, RT274_MUTE_SFT, 1, 1),436 SOC_SINGLE_TLV("AMIC Volume", RT274_MIC_GAIN,437 0, 0x3, 0, mic_vol_tlv),438};439 440static const struct snd_kcontrol_new hpol_enable_control =441 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT274_HPOL_GAIN,442 RT274_MUTE_SFT, 1, 1);443 444static const struct snd_kcontrol_new hpor_enable_control =445 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT274_HPOR_GAIN,446 RT274_MUTE_SFT, 1, 1);447 448static const struct snd_kcontrol_new loutl_enable_control =449 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT274_LOUTL_GAIN,450 RT274_MUTE_SFT, 1, 1);451 452static const struct snd_kcontrol_new loutr_enable_control =453 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT274_LOUTR_GAIN,454 RT274_MUTE_SFT, 1, 1);455 456/* ADC0 source */457static const char * const rt274_adc_src[] = {458 "Mic", "Line1", "Line2", "Dmic"459};460 461static SOC_ENUM_SINGLE_DECL(462 rt274_adc0_enum, RT274_ADC0_MUX, RT274_ADC_SEL_SFT,463 rt274_adc_src);464 465static const struct snd_kcontrol_new rt274_adc0_mux =466 SOC_DAPM_ENUM("ADC 0 source", rt274_adc0_enum);467 468static SOC_ENUM_SINGLE_DECL(469 rt274_adc1_enum, RT274_ADC1_MUX, RT274_ADC_SEL_SFT,470 rt274_adc_src);471 472static const struct snd_kcontrol_new rt274_adc1_mux =473 SOC_DAPM_ENUM("ADC 1 source", rt274_adc1_enum);474 475static const char * const rt274_dac_src[] = {476 "DAC OUT0", "DAC OUT1"477};478/* HP-OUT source */479static SOC_ENUM_SINGLE_DECL(rt274_hpo_enum, RT274_HPO_MUX,480 0, rt274_dac_src);481 482static const struct snd_kcontrol_new rt274_hpo_mux =483SOC_DAPM_ENUM("HPO source", rt274_hpo_enum);484 485/* Line out source */486static SOC_ENUM_SINGLE_DECL(rt274_lout_enum, RT274_LOUT_MUX,487 0, rt274_dac_src);488 489static const struct snd_kcontrol_new rt274_lout_mux =490SOC_DAPM_ENUM("LOUT source", rt274_lout_enum);491 492static const struct snd_soc_dapm_widget rt274_dapm_widgets[] = {493 /* Input Lines */494 SND_SOC_DAPM_INPUT("DMIC1 Pin"),495 SND_SOC_DAPM_INPUT("DMIC2 Pin"),496 SND_SOC_DAPM_INPUT("MIC"),497 SND_SOC_DAPM_INPUT("LINE1"),498 SND_SOC_DAPM_INPUT("LINE2"),499 500 /* DMIC */501 SND_SOC_DAPM_PGA("DMIC1", SND_SOC_NOPM, 0, 0, NULL, 0),502 SND_SOC_DAPM_PGA("DMIC2", SND_SOC_NOPM, 0, 0, NULL, 0),503 504 /* ADCs */505 SND_SOC_DAPM_ADC("ADC 0", NULL, RT274_SET_STREAMID_ADC1, 4, 0),506 SND_SOC_DAPM_ADC("ADC 1", NULL, RT274_SET_STREAMID_ADC2, 4, 0),507 508 /* ADC Mux */509 SND_SOC_DAPM_MUX("ADC 0 Mux", SND_SOC_NOPM, 0, 0,510 &rt274_adc0_mux),511 SND_SOC_DAPM_MUX("ADC 1 Mux", SND_SOC_NOPM, 0, 0,512 &rt274_adc1_mux),513 514 /* Audio Interface */515 SND_SOC_DAPM_AIF_IN("AIF1RXL", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),516 SND_SOC_DAPM_AIF_IN("AIF1RXR", "AIF1 Playback", 1, SND_SOC_NOPM, 0, 0),517 SND_SOC_DAPM_AIF_OUT("AIF1TXL", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),518 SND_SOC_DAPM_AIF_OUT("AIF1TXR", "AIF1 Capture", 1, SND_SOC_NOPM, 0, 0),519 SND_SOC_DAPM_AIF_IN("AIF2RXL", "AIF1 Playback", 2, SND_SOC_NOPM, 0, 0),520 SND_SOC_DAPM_AIF_IN("AIF2RXR", "AIF1 Playback", 3, SND_SOC_NOPM, 0, 0),521 SND_SOC_DAPM_AIF_OUT("AIF2TXL", "AIF1 Capture", 2, SND_SOC_NOPM, 0, 0),522 SND_SOC_DAPM_AIF_OUT("AIF2TXR", "AIF1 Capture", 3, SND_SOC_NOPM, 0, 0),523 524 /* Output Side */525 /* DACs */526 SND_SOC_DAPM_DAC("DAC 0", NULL, RT274_SET_STREAMID_DAC0, 4, 0),527 SND_SOC_DAPM_DAC("DAC 1", NULL, RT274_SET_STREAMID_DAC1, 4, 0),528 529 /* Output Mux */530 SND_SOC_DAPM_MUX("HPO Mux", SND_SOC_NOPM, 0, 0, &rt274_hpo_mux),531 SND_SOC_DAPM_MUX("LOUT Mux", SND_SOC_NOPM, 0, 0, &rt274_lout_mux),532 533 SND_SOC_DAPM_SUPPLY("HP Power", RT274_SET_PIN_HPO,534 RT274_SET_PIN_SFT, 0, NULL, 0),535 SND_SOC_DAPM_SUPPLY("LOUT Power", RT274_SET_PIN_LOUT3,536 RT274_SET_PIN_SFT, 0, NULL, 0),537 538 /* Output Mixer */539 SND_SOC_DAPM_PGA("DAC OUT0", SND_SOC_NOPM, 0, 0,540 NULL, 0),541 SND_SOC_DAPM_PGA("DAC OUT1", SND_SOC_NOPM, 0, 0,542 NULL, 0),543 544 /* Output Pga */545 SND_SOC_DAPM_SWITCH("LOUT L", SND_SOC_NOPM, 0, 0,546 &loutl_enable_control),547 SND_SOC_DAPM_SWITCH("LOUT R", SND_SOC_NOPM, 0, 0,548 &loutr_enable_control),549 SND_SOC_DAPM_SWITCH("HPO L", SND_SOC_NOPM, 0, 0,550 &hpol_enable_control),551 SND_SOC_DAPM_SWITCH("HPO R", SND_SOC_NOPM, 0, 0,552 &hpor_enable_control),553 554 /* Output Lines */555 SND_SOC_DAPM_OUTPUT("HPO Pin"),556 SND_SOC_DAPM_OUTPUT("SPDIF"),557 SND_SOC_DAPM_OUTPUT("LINE3"),558};559 560static const struct snd_soc_dapm_route rt274_dapm_routes[] = {561 {"DMIC1", NULL, "DMIC1 Pin"},562 {"DMIC2", NULL, "DMIC2 Pin"},563 564 {"ADC 0 Mux", "Mic", "MIC"},565 {"ADC 0 Mux", "Dmic", "DMIC1"},566 {"ADC 0 Mux", "Line1", "LINE1"},567 {"ADC 0 Mux", "Line2", "LINE2"},568 {"ADC 1 Mux", "Mic", "MIC"},569 {"ADC 1 Mux", "Dmic", "DMIC2"},570 {"ADC 1 Mux", "Line1", "LINE1"},571 {"ADC 1 Mux", "Line2", "LINE2"},572 573 {"ADC 0", NULL, "ADC 0 Mux"},574 {"ADC 1", NULL, "ADC 1 Mux"},575 576 {"AIF1TXL", NULL, "ADC 0"},577 {"AIF1TXR", NULL, "ADC 0"},578 {"AIF2TXL", NULL, "ADC 1"},579 {"AIF2TXR", NULL, "ADC 1"},580 581 {"DAC 0", NULL, "AIF1RXL"},582 {"DAC 0", NULL, "AIF1RXR"},583 {"DAC 1", NULL, "AIF2RXL"},584 {"DAC 1", NULL, "AIF2RXR"},585 586 {"DAC OUT0", NULL, "DAC 0"},587 588 {"DAC OUT1", NULL, "DAC 1"},589 590 {"LOUT Mux", "DAC OUT0", "DAC OUT0"},591 {"LOUT Mux", "DAC OUT1", "DAC OUT1"},592 593 {"LOUT L", "Switch", "LOUT Mux"},594 {"LOUT R", "Switch", "LOUT Mux"},595 {"LOUT L", NULL, "LOUT Power"},596 {"LOUT R", NULL, "LOUT Power"},597 598 {"LINE3", NULL, "LOUT L"},599 {"LINE3", NULL, "LOUT R"},600 601 {"HPO Mux", "DAC OUT0", "DAC OUT0"},602 {"HPO Mux", "DAC OUT1", "DAC OUT1"},603 604 {"HPO L", "Switch", "HPO Mux"},605 {"HPO R", "Switch", "HPO Mux"},606 {"HPO L", NULL, "HP Power"},607 {"HPO R", NULL, "HP Power"},608 609 {"HPO Pin", NULL, "HPO L"},610 {"HPO Pin", NULL, "HPO R"},611};612 613static int rt274_hw_params(struct snd_pcm_substream *substream,614 struct snd_pcm_hw_params *params,615 struct snd_soc_dai *dai)616{617 struct snd_soc_component *component = dai->component;618 struct rt274_priv *rt274 = snd_soc_component_get_drvdata(component);619 unsigned int val = 0;620 int d_len_code = 0, c_len_code = 0;621 622 switch (params_rate(params)) {623 /* bit 14 0:48K 1:44.1K */624 case 44100:625 case 48000:626 break;627 default:628 dev_err(component->dev, "Unsupported sample rate %d\n",629 params_rate(params));630 return -EINVAL;631 }632 switch (rt274->sys_clk) {633 case 12288000:634 case 24576000:635 if (params_rate(params) != 48000) {636 dev_err(component->dev, "Sys_clk is not matched (%d %d)\n",637 params_rate(params), rt274->sys_clk);638 return -EINVAL;639 }640 break;641 case 11289600:642 case 22579200:643 if (params_rate(params) != 44100) {644 dev_err(component->dev, "Sys_clk is not matched (%d %d)\n",645 params_rate(params), rt274->sys_clk);646 return -EINVAL;647 }648 break;649 }650 651 if (params_channels(params) <= 16) {652 /* bit 3:0 Number of Channel */653 val |= (params_channels(params) - 1);654 } else {655 dev_err(component->dev, "Unsupported channels %d\n",656 params_channels(params));657 return -EINVAL;658 }659 660 switch (params_width(params)) {661 /* bit 6:4 Bits per Sample */662 case 16:663 d_len_code = 0;664 c_len_code = 0;665 val |= (0x1 << 4);666 break;667 case 32:668 d_len_code = 2;669 c_len_code = 3;670 val |= (0x4 << 4);671 break;672 case 20:673 d_len_code = 1;674 c_len_code = 1;675 val |= (0x2 << 4);676 break;677 case 24:678 d_len_code = 2;679 c_len_code = 2;680 val |= (0x3 << 4);681 break;682 case 8:683 d_len_code = 3;684 c_len_code = 0;685 break;686 default:687 return -EINVAL;688 }689 690 if (rt274->master)691 c_len_code = 0x3;692 693 snd_soc_component_update_bits(component,694 RT274_I2S_CTRL1, 0xc018, d_len_code << 3 | c_len_code << 14);695 dev_dbg(component->dev, "format val = 0x%x\n", val);696 697 snd_soc_component_update_bits(component, RT274_DAC_FORMAT, 0x407f, val);698 snd_soc_component_update_bits(component, RT274_ADC_FORMAT, 0x407f, val);699 700 return 0;701}702 703static int rt274_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)704{705 struct snd_soc_component *component = dai->component;706 struct rt274_priv *rt274 = snd_soc_component_get_drvdata(component);707 708 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {709 case SND_SOC_DAIFMT_CBM_CFM:710 snd_soc_component_update_bits(component,711 RT274_I2S_CTRL1, RT274_I2S_MODE_MASK, RT274_I2S_MODE_M);712 rt274->master = true;713 break;714 case SND_SOC_DAIFMT_CBS_CFS:715 snd_soc_component_update_bits(component,716 RT274_I2S_CTRL1, RT274_I2S_MODE_MASK, RT274_I2S_MODE_S);717 rt274->master = false;718 break;719 default:720 return -EINVAL;721 }722 723 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {724 case SND_SOC_DAIFMT_I2S:725 snd_soc_component_update_bits(component, RT274_I2S_CTRL1,726 RT274_I2S_FMT_MASK, RT274_I2S_FMT_I2S);727 break;728 case SND_SOC_DAIFMT_LEFT_J:729 snd_soc_component_update_bits(component, RT274_I2S_CTRL1,730 RT274_I2S_FMT_MASK, RT274_I2S_FMT_LJ);731 break;732 case SND_SOC_DAIFMT_DSP_A:733 snd_soc_component_update_bits(component, RT274_I2S_CTRL1,734 RT274_I2S_FMT_MASK, RT274_I2S_FMT_PCMA);735 break;736 case SND_SOC_DAIFMT_DSP_B:737 snd_soc_component_update_bits(component, RT274_I2S_CTRL1,738 RT274_I2S_FMT_MASK, RT274_I2S_FMT_PCMB);739 break;740 default:741 return -EINVAL;742 }743 /* bit 15 Stream Type 0:PCM 1:Non-PCM */744 snd_soc_component_update_bits(component, RT274_DAC_FORMAT, 0x8000, 0);745 snd_soc_component_update_bits(component, RT274_ADC_FORMAT, 0x8000, 0);746 747 return 0;748}749 750static int rt274_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source,751 unsigned int freq_in, unsigned int freq_out)752{753 struct snd_soc_component *component = dai->component;754 struct rt274_priv *rt274 = snd_soc_component_get_drvdata(component);755 756 switch (source) {757 case RT274_PLL2_S_MCLK:758 snd_soc_component_update_bits(component, RT274_PLL2_CTRL,759 RT274_PLL2_SRC_MASK, RT274_PLL2_SRC_MCLK);760 break;761 default:762 dev_warn(component->dev, "invalid pll source, use BCLK\n");763 fallthrough;764 case RT274_PLL2_S_BCLK:765 snd_soc_component_update_bits(component, RT274_PLL2_CTRL,766 RT274_PLL2_SRC_MASK, RT274_PLL2_SRC_BCLK);767 break;768 }769 770 if (source == RT274_PLL2_S_BCLK) {771 snd_soc_component_update_bits(component, RT274_MCLK_CTRL,772 (0x3 << 12), (0x3 << 12));773 switch (rt274->fs) {774 case 50:775 snd_soc_component_write(component, 0x7a, 0xaab6);776 snd_soc_component_write(component, 0x7b, 0x0301);777 snd_soc_component_write(component, 0x7c, 0x04fe);778 break;779 case 64:780 snd_soc_component_write(component, 0x7a, 0xaa96);781 snd_soc_component_write(component, 0x7b, 0x8003);782 snd_soc_component_write(component, 0x7c, 0x081e);783 break;784 case 128:785 snd_soc_component_write(component, 0x7a, 0xaa96);786 snd_soc_component_write(component, 0x7b, 0x8003);787 snd_soc_component_write(component, 0x7c, 0x080e);788 break;789 default:790 dev_warn(component->dev, "invalid freq_in, assume 4.8M\n");791 fallthrough;792 case 100:793 snd_soc_component_write(component, 0x7a, 0xaab6);794 snd_soc_component_write(component, 0x7b, 0x0301);795 snd_soc_component_write(component, 0x7c, 0x047e);796 break;797 }798 }799 800 return 0;801}802 803static int rt274_set_dai_sysclk(struct snd_soc_dai *dai,804 int clk_id, unsigned int freq, int dir)805{806 struct snd_soc_component *component = dai->component;807 struct rt274_priv *rt274 = snd_soc_component_get_drvdata(component);808 unsigned int clk_src, mclk_en;809 810 dev_dbg(component->dev, "%s freq=%d\n", __func__, freq);811 812 switch (clk_id) {813 case RT274_SCLK_S_MCLK:814 mclk_en = RT274_MCLK_MODE_EN;815 clk_src = RT274_CLK_SRC_MCLK;816 break;817 case RT274_SCLK_S_PLL1:818 mclk_en = RT274_MCLK_MODE_DIS;819 clk_src = RT274_CLK_SRC_MCLK;820 break;821 case RT274_SCLK_S_PLL2:822 mclk_en = RT274_MCLK_MODE_EN;823 clk_src = RT274_CLK_SRC_PLL2;824 break;825 default:826 mclk_en = RT274_MCLK_MODE_DIS;827 clk_src = RT274_CLK_SRC_MCLK;828 dev_warn(component->dev, "invalid sysclk source, use PLL1\n");829 break;830 }831 snd_soc_component_update_bits(component, RT274_MCLK_CTRL,832 RT274_MCLK_MODE_MASK, mclk_en);833 snd_soc_component_update_bits(component, RT274_CLK_CTRL,834 RT274_CLK_SRC_MASK, clk_src);835 836 switch (freq) {837 case 19200000:838 if (clk_id == RT274_SCLK_S_MCLK) {839 dev_err(component->dev, "Should not use MCLK\n");840 return -EINVAL;841 }842 snd_soc_component_update_bits(component,843 RT274_I2S_CTRL2, 0x40, 0x40);844 break;845 case 24000000:846 if (clk_id == RT274_SCLK_S_MCLK) {847 dev_err(component->dev, "Should not use MCLK\n");848 return -EINVAL;849 }850 snd_soc_component_update_bits(component,851 RT274_I2S_CTRL2, 0x40, 0x0);852 break;853 case 12288000:854 case 11289600:855 snd_soc_component_update_bits(component,856 RT274_MCLK_CTRL, 0x1fcf, 0x0008);857 break;858 case 24576000:859 case 22579200:860 snd_soc_component_update_bits(component,861 RT274_MCLK_CTRL, 0x1fcf, 0x1543);862 break;863 default:864 dev_err(component->dev, "Unsupported system clock\n");865 return -EINVAL;866 }867 868 rt274->sys_clk = freq;869 rt274->clk_id = clk_id;870 871 return 0;872}873 874static int rt274_set_bclk_ratio(struct snd_soc_dai *dai, unsigned int ratio)875{876 struct snd_soc_component *component = dai->component;877 struct rt274_priv *rt274 = snd_soc_component_get_drvdata(component);878 879 dev_dbg(component->dev, "%s ratio=%d\n", __func__, ratio);880 rt274->fs = ratio;881 if ((ratio / 50) == 0)882 snd_soc_component_update_bits(component,883 RT274_I2S_CTRL1, 0x1000, 0x1000);884 else885 snd_soc_component_update_bits(component,886 RT274_I2S_CTRL1, 0x1000, 0x0);887 888 889 return 0;890}891 892static int rt274_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,893 unsigned int rx_mask, int slots, int slot_width)894 895{896 struct snd_soc_component *component = dai->component;897 898 if (rx_mask || tx_mask) {899 snd_soc_component_update_bits(component,900 RT274_I2S_CTRL1, RT274_TDM_EN, RT274_TDM_EN);901 } else {902 snd_soc_component_update_bits(component,903 RT274_I2S_CTRL1, RT274_TDM_EN, RT274_TDM_DIS);904 return 0;905 }906 907 switch (slots) {908 case 4:909 snd_soc_component_update_bits(component,910 RT274_I2S_CTRL1, RT274_TDM_CH_NUM, RT274_TDM_4CH);911 break;912 case 2:913 snd_soc_component_update_bits(component,914 RT274_I2S_CTRL1, RT274_TDM_CH_NUM, RT274_TDM_2CH);915 break;916 default:917 dev_err(component->dev,918 "Support 2 or 4 slots TDM only\n");919 return -EINVAL;920 }921 922 return 0;923}924 925static int rt274_set_bias_level(struct snd_soc_component *component,926 enum snd_soc_bias_level level)927{928 switch (level) {929 case SND_SOC_BIAS_PREPARE:930 if (SND_SOC_BIAS_STANDBY ==931 snd_soc_component_get_bias_level(component)) {932 snd_soc_component_write(component,933 RT274_SET_AUDIO_POWER, AC_PWRST_D0);934 }935 break;936 937 case SND_SOC_BIAS_STANDBY:938 snd_soc_component_write(component,939 RT274_SET_AUDIO_POWER, AC_PWRST_D3);940 break;941 942 default:943 break;944 }945 946 return 0;947}948 949static irqreturn_t rt274_irq(int irq, void *data)950{951 struct rt274_priv *rt274 = data;952 bool hp = false;953 bool mic = false;954 int ret, status = 0;955 956 /* Clear IRQ */957 regmap_update_bits(rt274->regmap, RT274_EAPD_GPIO_IRQ_CTRL,958 RT274_IRQ_CLR, RT274_IRQ_CLR);959 960 ret = rt274_jack_detect(rt274, &hp, &mic);961 962 if (ret == 0) {963 if (hp)964 status |= SND_JACK_HEADPHONE;965 966 if (mic)967 status |= SND_JACK_MICROPHONE;968 969 snd_soc_jack_report(rt274->jack, status,970 SND_JACK_MICROPHONE | SND_JACK_HEADPHONE);971 972 pm_wakeup_event(&rt274->i2c->dev, 300);973 }974 975 return IRQ_HANDLED;976}977 978static int rt274_probe(struct snd_soc_component *component)979{980 struct rt274_priv *rt274 = snd_soc_component_get_drvdata(component);981 982 rt274->component = component;983 INIT_DELAYED_WORK(&rt274->jack_detect_work, rt274_jack_detect_work);984 985 if (rt274->i2c->irq)986 schedule_delayed_work(&rt274->jack_detect_work,987 msecs_to_jiffies(1250));988 return 0;989}990 991static void rt274_remove(struct snd_soc_component *component)992{993 struct rt274_priv *rt274 = snd_soc_component_get_drvdata(component);994 995 cancel_delayed_work_sync(&rt274->jack_detect_work);996 rt274->component = NULL;997}998 999#ifdef CONFIG_PM1000static int rt274_suspend(struct snd_soc_component *component)1001{1002 struct rt274_priv *rt274 = snd_soc_component_get_drvdata(component);1003 1004 regcache_cache_only(rt274->regmap, true);1005 regcache_mark_dirty(rt274->regmap);1006 1007 return 0;1008}1009 1010static int rt274_resume(struct snd_soc_component *component)1011{1012 struct rt274_priv *rt274 = snd_soc_component_get_drvdata(component);1013 1014 regcache_cache_only(rt274->regmap, false);1015 rt274_index_sync(component);1016 regcache_sync(rt274->regmap);1017 1018 return 0;1019}1020#else1021#define rt274_suspend NULL1022#define rt274_resume NULL1023#endif1024 1025#define RT274_STEREO_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000)1026#define RT274_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \1027 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)1028 1029static const struct snd_soc_dai_ops rt274_aif_dai_ops = {1030 .hw_params = rt274_hw_params,1031 .set_fmt = rt274_set_dai_fmt,1032 .set_sysclk = rt274_set_dai_sysclk,1033 .set_pll = rt274_set_dai_pll,1034 .set_bclk_ratio = rt274_set_bclk_ratio,1035 .set_tdm_slot = rt274_set_tdm_slot,1036};1037 1038static struct snd_soc_dai_driver rt274_dai[] = {1039 {1040 .name = "rt274-aif1",1041 .id = RT274_AIF1,1042 .playback = {1043 .stream_name = "AIF1 Playback",1044 .channels_min = 1,1045 .channels_max = 2,1046 .rates = RT274_STEREO_RATES,1047 .formats = RT274_FORMATS,1048 },1049 .capture = {1050 .stream_name = "AIF1 Capture",1051 .channels_min = 1,1052 .channels_max = 2,1053 .rates = RT274_STEREO_RATES,1054 .formats = RT274_FORMATS,1055 },1056 .ops = &rt274_aif_dai_ops,1057 .symmetric_rate = 1,1058 },1059};1060 1061static const struct snd_soc_component_driver soc_component_dev_rt274 = {1062 .probe = rt274_probe,1063 .remove = rt274_remove,1064 .suspend = rt274_suspend,1065 .resume = rt274_resume,1066 .set_bias_level = rt274_set_bias_level,1067 .set_jack = rt274_mic_detect,1068 .controls = rt274_snd_controls,1069 .num_controls = ARRAY_SIZE(rt274_snd_controls),1070 .dapm_widgets = rt274_dapm_widgets,1071 .num_dapm_widgets = ARRAY_SIZE(rt274_dapm_widgets),1072 .dapm_routes = rt274_dapm_routes,1073 .num_dapm_routes = ARRAY_SIZE(rt274_dapm_routes),1074 .use_pmdown_time = 1,1075 .endianness = 1,1076};1077 1078static const struct regmap_config rt274_regmap = {1079 .reg_bits = 32,1080 .val_bits = 32,1081 .max_register = 0x05bfffff,1082 .volatile_reg = rt274_volatile_register,1083 .readable_reg = rt274_readable_register,1084 .reg_write = rl6347a_hw_write,1085 .reg_read = rl6347a_hw_read,1086 .cache_type = REGCACHE_RBTREE,1087 .reg_defaults = rt274_reg,1088 .num_reg_defaults = ARRAY_SIZE(rt274_reg),1089};1090 1091#ifdef CONFIG_OF1092static const struct of_device_id rt274_of_match[] = {1093 {.compatible = "realtek,rt274"},1094 {},1095};1096MODULE_DEVICE_TABLE(of, rt274_of_match);1097#endif1098 1099static const struct i2c_device_id rt274_i2c_id[] = {1100 {"rt274"},1101 {}1102};1103MODULE_DEVICE_TABLE(i2c, rt274_i2c_id);1104 1105#ifdef CONFIG_ACPI1106static const struct acpi_device_id rt274_acpi_match[] = {1107 { "10EC0274", 0 },1108 { "INT34C2", 0 },1109 {},1110};1111MODULE_DEVICE_TABLE(acpi, rt274_acpi_match);1112#endif1113 1114static int rt274_i2c_probe(struct i2c_client *i2c)1115{1116 struct rt274_priv *rt274;1117 1118 int ret;1119 unsigned int val;1120 1121 rt274 = devm_kzalloc(&i2c->dev, sizeof(*rt274),1122 GFP_KERNEL);1123 if (rt274 == NULL)1124 return -ENOMEM;1125 1126 rt274->regmap = devm_regmap_init(&i2c->dev, NULL, i2c, &rt274_regmap);1127 if (IS_ERR(rt274->regmap)) {1128 ret = PTR_ERR(rt274->regmap);1129 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",1130 ret);1131 return ret;1132 }1133 1134 ret = regmap_read(rt274->regmap,1135 RT274_GET_PARAM(AC_NODE_ROOT, AC_PAR_VENDOR_ID), &val);1136 if (ret)1137 return ret;1138 1139 if (val != RT274_VENDOR_ID) {1140 dev_err(&i2c->dev,1141 "Device with ID register %#x is not rt274\n", val);1142 return -ENODEV;1143 }1144 1145 rt274->index_cache = devm_kmemdup(&i2c->dev, rt274_index_def,1146 sizeof(rt274_index_def), GFP_KERNEL);1147 if (!rt274->index_cache)1148 return -ENOMEM;1149 1150 rt274->index_cache_size = INDEX_CACHE_SIZE;1151 rt274->i2c = i2c;1152 i2c_set_clientdata(i2c, rt274);1153 1154 /* reset codec */1155 regmap_write(rt274->regmap, RT274_RESET, 0);1156 regmap_update_bits(rt274->regmap, 0x1a, 0x4000, 0x4000);1157 1158 /* Set Pad PDB is floating */1159 regmap_update_bits(rt274->regmap, RT274_PAD_CTRL12, 0x3, 0x0);1160 regmap_write(rt274->regmap, RT274_COEF5b_INDEX, 0x01);1161 regmap_write(rt274->regmap, RT274_COEF5b_COEF, 0x8540);1162 regmap_update_bits(rt274->regmap, 0x6f, 0x0100, 0x0100);1163 /* Combo jack auto detect */1164 regmap_write(rt274->regmap, 0x4a, 0x201b);1165 /* Aux mode off */1166 regmap_update_bits(rt274->regmap, 0x6f, 0x3000, 0x2000);1167 /* HP DC Calibration */1168 regmap_update_bits(rt274->regmap, 0x6f, 0xf, 0x0);1169 /* Set NID=58h.Index 00h [15]= 1b; */1170 regmap_write(rt274->regmap, RT274_COEF58_INDEX, 0x00);1171 regmap_write(rt274->regmap, RT274_COEF58_COEF, 0xb888);1172 msleep(500);1173 regmap_update_bits(rt274->regmap, 0x6f, 0xf, 0xb);1174 regmap_write(rt274->regmap, RT274_COEF58_INDEX, 0x00);1175 regmap_write(rt274->regmap, RT274_COEF58_COEF, 0x3888);1176 /* Set pin widget */1177 regmap_write(rt274->regmap, RT274_SET_PIN_HPO, 0x40);1178 regmap_write(rt274->regmap, RT274_SET_PIN_LOUT3, 0x40);1179 regmap_write(rt274->regmap, RT274_SET_MIC, 0x20);1180 regmap_write(rt274->regmap, RT274_SET_PIN_DMIC1, 0x20);1181 1182 regmap_update_bits(rt274->regmap, RT274_I2S_CTRL2, 0xc004, 0x4004);1183 regmap_update_bits(rt274->regmap, RT274_EAPD_GPIO_IRQ_CTRL,1184 RT274_GPI2_SEL_MASK, RT274_GPI2_SEL_DMIC_CLK);1185 1186 /* jack detection */1187 regmap_write(rt274->regmap, RT274_UNSOLICITED_HP_OUT, 0x81);1188 regmap_write(rt274->regmap, RT274_UNSOLICITED_MIC, 0x82);1189 1190 if (rt274->i2c->irq) {1191 ret = request_threaded_irq(rt274->i2c->irq, NULL, rt274_irq,1192 IRQF_TRIGGER_HIGH | IRQF_ONESHOT, "rt274", rt274);1193 if (ret != 0) {1194 dev_err(&i2c->dev,1195 "Failed to request IRQ: %d\n", ret);1196 return ret;1197 }1198 }1199 1200 ret = devm_snd_soc_register_component(&i2c->dev,1201 &soc_component_dev_rt274,1202 rt274_dai, ARRAY_SIZE(rt274_dai));1203 1204 return ret;1205}1206 1207static void rt274_i2c_remove(struct i2c_client *i2c)1208{1209 struct rt274_priv *rt274 = i2c_get_clientdata(i2c);1210 1211 if (i2c->irq)1212 free_irq(i2c->irq, rt274);1213}1214 1215 1216static struct i2c_driver rt274_i2c_driver = {1217 .driver = {1218 .name = "rt274",1219 .acpi_match_table = ACPI_PTR(rt274_acpi_match),1220#ifdef CONFIG_OF1221 .of_match_table = of_match_ptr(rt274_of_match),1222#endif1223 },1224 .probe = rt274_i2c_probe,1225 .remove = rt274_i2c_remove,1226 .id_table = rt274_i2c_id,1227};1228 1229module_i2c_driver(rt274_i2c_driver);1230 1231MODULE_DESCRIPTION("ASoC RT274 driver");1232MODULE_AUTHOR("Bard Liao <bardliao@realtek.com>");1233MODULE_LICENSE("GPL v2");1234