brintos / linux-shallow public Read only

1// SPDX-License-Identifier: GPL-2.0-only2/*3 * rt5645.c  --  RT5645 ALSA SoC audio codec driver4 *5 * Copyright 2013 Realtek Semiconductor Corp.6 * Author: Bard Liao <bardliao@realtek.com>7 */8 9#include <linux/module.h>10#include <linux/moduleparam.h>11#include <linux/init.h>12#include <linux/delay.h>13#include <linux/pm.h>14#include <linux/i2c.h>15#include <linux/platform_device.h>16#include <linux/spi/spi.h>17#include <linux/gpio/consumer.h>18#include <linux/acpi.h>19#include <linux/dmi.h>20#include <linux/regulator/consumer.h>21#include <sound/core.h>22#include <sound/pcm.h>23#include <sound/pcm_params.h>24#include <sound/jack.h>25#include <sound/soc.h>26#include <sound/soc-dapm.h>27#include <sound/initval.h>28#include <sound/tlv.h>29 30#include "rl6231.h"31#include "rt5645.h"32 33#define QUIRK_INV_JD1_1(q)	((q) & 1)34#define QUIRK_LEVEL_IRQ(q)	(((q) >> 1) & 1)35#define QUIRK_IN2_DIFF(q)	(((q) >> 2) & 1)36#define QUIRK_INV_HP_POL(q)	(((q) >> 3) & 1)37#define QUIRK_JD_MODE(q)	(((q) >> 4) & 7)38#define QUIRK_DMIC1_DATA_PIN(q)	(((q) >> 8) & 3)39#define QUIRK_DMIC2_DATA_PIN(q)	(((q) >> 12) & 3)40 41static unsigned int quirk = -1;42module_param(quirk, uint, 0444);43MODULE_PARM_DESC(quirk, "RT5645 pdata quirk override");44 45static const struct acpi_gpio_mapping *cht_rt5645_gpios;46 47#define RT5645_DEVICE_ID 0x630848#define RT5650_DEVICE_ID 0x641949 50#define RT5645_PR_RANGE_BASE (0xff + 1)51#define RT5645_PR_SPACING 0x10052 53#define RT5645_PR_BASE (RT5645_PR_RANGE_BASE + (0 * RT5645_PR_SPACING))54 55#define RT5645_HWEQ_NUM 5756 57#define TIME_TO_POWER_MS 40058 59static const struct regmap_range_cfg rt5645_ranges[] = {60	{61		.name = "PR",62		.range_min = RT5645_PR_BASE,63		.range_max = RT5645_PR_BASE + 0xf8,64		.selector_reg = RT5645_PRIV_INDEX,65		.selector_mask = 0xff,66		.selector_shift = 0x0,67		.window_start = RT5645_PRIV_DATA,68		.window_len = 0x1,69	},70};71 72static const struct reg_sequence init_list[] = {73	{RT5645_PR_BASE + 0x3d,	0x3600},74	{RT5645_PR_BASE + 0x1c,	0xfd70},75	{RT5645_PR_BASE + 0x20,	0x611f},76	{RT5645_PR_BASE + 0x21,	0x4040},77	{RT5645_PR_BASE + 0x23,	0x0004},78	{RT5645_ASRC_4, 0x0120},79};80 81static const struct reg_sequence rt5650_init_list[] = {82	{0xf6,	0x0100},83	{RT5645_PWR_ANLG1, 0x02},84	{RT5645_IL_CMD3, 0x6728},85};86 87static const struct reg_default rt5645_reg[] = {88	{ 0x00, 0x0000 },89	{ 0x01, 0xc8c8 },90	{ 0x02, 0xc8c8 },91	{ 0x03, 0xc8c8 },92	{ 0x0a, 0x0002 },93	{ 0x0b, 0x2827 },94	{ 0x0c, 0xe000 },95	{ 0x0d, 0x0000 },96	{ 0x0e, 0x0000 },97	{ 0x0f, 0x0808 },98	{ 0x14, 0x3333 },99	{ 0x16, 0x4b00 },100	{ 0x18, 0x018b },101	{ 0x19, 0xafaf },102	{ 0x1a, 0xafaf },103	{ 0x1b, 0x0001 },104	{ 0x1c, 0x2f2f },105	{ 0x1d, 0x2f2f },106	{ 0x1e, 0x0000 },107	{ 0x20, 0x0000 },108	{ 0x27, 0x7060 },109	{ 0x28, 0x7070 },110	{ 0x29, 0x8080 },111	{ 0x2a, 0x5656 },112	{ 0x2b, 0x5454 },113	{ 0x2c, 0xaaa0 },114	{ 0x2d, 0x0000 },115	{ 0x2f, 0x1002 },116	{ 0x31, 0x5000 },117	{ 0x32, 0x0000 },118	{ 0x33, 0x0000 },119	{ 0x34, 0x0000 },120	{ 0x35, 0x0000 },121	{ 0x3b, 0x0000 },122	{ 0x3c, 0x007f },123	{ 0x3d, 0x0000 },124	{ 0x3e, 0x007f },125	{ 0x3f, 0x0000 },126	{ 0x40, 0x001f },127	{ 0x41, 0x0000 },128	{ 0x42, 0x001f },129	{ 0x45, 0x6000 },130	{ 0x46, 0x003e },131	{ 0x47, 0x003e },132	{ 0x48, 0xf807 },133	{ 0x4a, 0x0004 },134	{ 0x4d, 0x0000 },135	{ 0x4e, 0x0000 },136	{ 0x4f, 0x01ff },137	{ 0x50, 0x0000 },138	{ 0x51, 0x0000 },139	{ 0x52, 0x01ff },140	{ 0x53, 0xf000 },141	{ 0x56, 0x0111 },142	{ 0x57, 0x0064 },143	{ 0x58, 0xef0e },144	{ 0x59, 0xf0f0 },145	{ 0x5a, 0xef0e },146	{ 0x5b, 0xf0f0 },147	{ 0x5c, 0xef0e },148	{ 0x5d, 0xf0f0 },149	{ 0x5e, 0xf000 },150	{ 0x5f, 0x0000 },151	{ 0x61, 0x0300 },152	{ 0x62, 0x0000 },153	{ 0x63, 0x00c2 },154	{ 0x64, 0x0000 },155	{ 0x65, 0x0000 },156	{ 0x66, 0x0000 },157	{ 0x6a, 0x0000 },158	{ 0x6c, 0x0aaa },159	{ 0x70, 0x8000 },160	{ 0x71, 0x8000 },161	{ 0x72, 0x8000 },162	{ 0x73, 0x7770 },163	{ 0x74, 0x3e00 },164	{ 0x75, 0x2409 },165	{ 0x76, 0x000a },166	{ 0x77, 0x0c00 },167	{ 0x78, 0x0000 },168	{ 0x79, 0x0123 },169	{ 0x80, 0x0000 },170	{ 0x81, 0x0000 },171	{ 0x82, 0x0000 },172	{ 0x83, 0x0000 },173	{ 0x84, 0x0000 },174	{ 0x85, 0x0000 },175	{ 0x8a, 0x0120 },176	{ 0x8e, 0x0004 },177	{ 0x8f, 0x1100 },178	{ 0x90, 0x0646 },179	{ 0x91, 0x0c06 },180	{ 0x93, 0x0000 },181	{ 0x94, 0x0200 },182	{ 0x95, 0x0000 },183	{ 0x9a, 0x2184 },184	{ 0x9b, 0x010a },185	{ 0x9c, 0x0aea },186	{ 0x9d, 0x000c },187	{ 0x9e, 0x0400 },188	{ 0xa0, 0xa0a8 },189	{ 0xa1, 0x0059 },190	{ 0xa2, 0x0001 },191	{ 0xae, 0x6000 },192	{ 0xaf, 0x0000 },193	{ 0xb0, 0x6000 },194	{ 0xb1, 0x0000 },195	{ 0xb2, 0x0000 },196	{ 0xb3, 0x001f },197	{ 0xb4, 0x020c },198	{ 0xb5, 0x1f00 },199	{ 0xb6, 0x0000 },200	{ 0xbb, 0x0000 },201	{ 0xbc, 0x0000 },202	{ 0xbd, 0x0000 },203	{ 0xbe, 0x0000 },204	{ 0xbf, 0x3100 },205	{ 0xc0, 0x0000 },206	{ 0xc1, 0x0000 },207	{ 0xc2, 0x0000 },208	{ 0xc3, 0x2000 },209	{ 0xcd, 0x0000 },210	{ 0xce, 0x0000 },211	{ 0xcf, 0x1813 },212	{ 0xd0, 0x0690 },213	{ 0xd1, 0x1c17 },214	{ 0xd3, 0xb320 },215	{ 0xd4, 0x0000 },216	{ 0xd6, 0x0400 },217	{ 0xd9, 0x0809 },218	{ 0xda, 0x0000 },219	{ 0xdb, 0x0003 },220	{ 0xdc, 0x0049 },221	{ 0xdd, 0x001b },222	{ 0xdf, 0x0008 },223	{ 0xe0, 0x4000 },224	{ 0xe6, 0x8000 },225	{ 0xe7, 0x0200 },226	{ 0xec, 0xb300 },227	{ 0xed, 0x0000 },228	{ 0xf0, 0x001f },229	{ 0xf1, 0x020c },230	{ 0xf2, 0x1f00 },231	{ 0xf3, 0x0000 },232	{ 0xf4, 0x4000 },233	{ 0xf8, 0x0000 },234	{ 0xf9, 0x0000 },235	{ 0xfa, 0x2060 },236	{ 0xfb, 0x4040 },237	{ 0xfc, 0x0000 },238	{ 0xfd, 0x0002 },239	{ 0xfe, 0x10ec },240	{ 0xff, 0x6308 },241};242 243static const struct reg_default rt5650_reg[] = {244	{ 0x00, 0x0000 },245	{ 0x01, 0xc8c8 },246	{ 0x02, 0xc8c8 },247	{ 0x03, 0xc8c8 },248	{ 0x0a, 0x0002 },249	{ 0x0b, 0x2827 },250	{ 0x0c, 0xe000 },251	{ 0x0d, 0x0000 },252	{ 0x0e, 0x0000 },253	{ 0x0f, 0x0808 },254	{ 0x14, 0x3333 },255	{ 0x16, 0x4b00 },256	{ 0x18, 0x018b },257	{ 0x19, 0xafaf },258	{ 0x1a, 0xafaf },259	{ 0x1b, 0x0001 },260	{ 0x1c, 0x2f2f },261	{ 0x1d, 0x2f2f },262	{ 0x1e, 0x0000 },263	{ 0x20, 0x0000 },264	{ 0x27, 0x7060 },265	{ 0x28, 0x7070 },266	{ 0x29, 0x8080 },267	{ 0x2a, 0x5656 },268	{ 0x2b, 0x5454 },269	{ 0x2c, 0xaaa0 },270	{ 0x2d, 0x0000 },271	{ 0x2f, 0x5002 },272	{ 0x31, 0x5000 },273	{ 0x32, 0x0000 },274	{ 0x33, 0x0000 },275	{ 0x34, 0x0000 },276	{ 0x35, 0x0000 },277	{ 0x3b, 0x0000 },278	{ 0x3c, 0x007f },279	{ 0x3d, 0x0000 },280	{ 0x3e, 0x007f },281	{ 0x3f, 0x0000 },282	{ 0x40, 0x001f },283	{ 0x41, 0x0000 },284	{ 0x42, 0x001f },285	{ 0x45, 0x6000 },286	{ 0x46, 0x003e },287	{ 0x47, 0x003e },288	{ 0x48, 0xf807 },289	{ 0x4a, 0x0004 },290	{ 0x4d, 0x0000 },291	{ 0x4e, 0x0000 },292	{ 0x4f, 0x01ff },293	{ 0x50, 0x0000 },294	{ 0x51, 0x0000 },295	{ 0x52, 0x01ff },296	{ 0x53, 0xf000 },297	{ 0x56, 0x0111 },298	{ 0x57, 0x0064 },299	{ 0x58, 0xef0e },300	{ 0x59, 0xf0f0 },301	{ 0x5a, 0xef0e },302	{ 0x5b, 0xf0f0 },303	{ 0x5c, 0xef0e },304	{ 0x5d, 0xf0f0 },305	{ 0x5e, 0xf000 },306	{ 0x5f, 0x0000 },307	{ 0x61, 0x0300 },308	{ 0x62, 0x0000 },309	{ 0x63, 0x00c2 },310	{ 0x64, 0x0000 },311	{ 0x65, 0x0000 },312	{ 0x66, 0x0000 },313	{ 0x6a, 0x0000 },314	{ 0x6c, 0x0aaa },315	{ 0x70, 0x8000 },316	{ 0x71, 0x8000 },317	{ 0x72, 0x8000 },318	{ 0x73, 0x7770 },319	{ 0x74, 0x3e00 },320	{ 0x75, 0x2409 },321	{ 0x76, 0x000a },322	{ 0x77, 0x0c00 },323	{ 0x78, 0x0000 },324	{ 0x79, 0x0123 },325	{ 0x7a, 0x0123 },326	{ 0x80, 0x0000 },327	{ 0x81, 0x0000 },328	{ 0x82, 0x0000 },329	{ 0x83, 0x0000 },330	{ 0x84, 0x0000 },331	{ 0x85, 0x0000 },332	{ 0x8a, 0x0120 },333	{ 0x8e, 0x0004 },334	{ 0x8f, 0x1100 },335	{ 0x90, 0x0646 },336	{ 0x91, 0x0c06 },337	{ 0x93, 0x0000 },338	{ 0x94, 0x0200 },339	{ 0x95, 0x0000 },340	{ 0x9a, 0x2184 },341	{ 0x9b, 0x010a },342	{ 0x9c, 0x0aea },343	{ 0x9d, 0x000c },344	{ 0x9e, 0x0400 },345	{ 0xa0, 0xa0a8 },346	{ 0xa1, 0x0059 },347	{ 0xa2, 0x0001 },348	{ 0xae, 0x6000 },349	{ 0xaf, 0x0000 },350	{ 0xb0, 0x6000 },351	{ 0xb1, 0x0000 },352	{ 0xb2, 0x0000 },353	{ 0xb3, 0x001f },354	{ 0xb4, 0x020c },355	{ 0xb5, 0x1f00 },356	{ 0xb6, 0x0000 },357	{ 0xbb, 0x0000 },358	{ 0xbc, 0x0000 },359	{ 0xbd, 0x0000 },360	{ 0xbe, 0x0000 },361	{ 0xbf, 0x3100 },362	{ 0xc0, 0x0000 },363	{ 0xc1, 0x0000 },364	{ 0xc2, 0x0000 },365	{ 0xc3, 0x2000 },366	{ 0xcd, 0x0000 },367	{ 0xce, 0x0000 },368	{ 0xcf, 0x1813 },369	{ 0xd0, 0x0690 },370	{ 0xd1, 0x1c17 },371	{ 0xd3, 0xb320 },372	{ 0xd4, 0x0000 },373	{ 0xd6, 0x0400 },374	{ 0xd9, 0x0809 },375	{ 0xda, 0x0000 },376	{ 0xdb, 0x0003 },377	{ 0xdc, 0x0049 },378	{ 0xdd, 0x001b },379	{ 0xdf, 0x0008 },380	{ 0xe0, 0x4000 },381	{ 0xe6, 0x8000 },382	{ 0xe7, 0x0200 },383	{ 0xec, 0xb300 },384	{ 0xed, 0x0000 },385	{ 0xf0, 0x001f },386	{ 0xf1, 0x020c },387	{ 0xf2, 0x1f00 },388	{ 0xf3, 0x0000 },389	{ 0xf4, 0x4000 },390	{ 0xf8, 0x0000 },391	{ 0xf9, 0x0000 },392	{ 0xfa, 0x2060 },393	{ 0xfb, 0x4040 },394	{ 0xfc, 0x0000 },395	{ 0xfd, 0x0002 },396	{ 0xfe, 0x10ec },397	{ 0xff, 0x6308 },398};399 400struct rt5645_eq_param_s {401	unsigned short reg;402	unsigned short val;403};404 405struct rt5645_eq_param_s_be16 {406	__be16 reg;407	__be16 val;408};409 410static const char *const rt5645_supply_names[] = {411	"avdd",412	"cpvdd",413};414 415struct rt5645_platform_data {416	/* IN2 can optionally be differential */417	bool in2_diff;418 419	unsigned int dmic1_data_pin;420	/* 0 = IN2N; 1 = GPIO5; 2 = GPIO11 */421	unsigned int dmic2_data_pin;422	/* 0 = IN2P; 1 = GPIO6; 2 = GPIO10; 3 = GPIO12 */423 424	unsigned int jd_mode;425	/* Use level triggered irq */426	bool level_trigger_irq;427	/* Invert JD1_1 status polarity */428	bool inv_jd1_1;429	/* Invert HP detect status polarity */430	bool inv_hp_pol;431 432	/* Only 1 speaker connected */433	bool mono_speaker;434 435	/* Value to assign to snd_soc_card.long_name */436	const char *long_name;437 438	/* Some (package) variants have the headset-mic pin not-connected */439	bool no_headset_mic;440};441 442struct rt5645_priv {443	struct snd_soc_component *component;444	struct rt5645_platform_data pdata;445	struct regmap *regmap;446	struct i2c_client *i2c;447	struct gpio_desc *gpiod_hp_det;448	struct gpio_desc *gpiod_cbj_sleeve;449	struct snd_soc_jack *hp_jack;450	struct snd_soc_jack *mic_jack;451	struct snd_soc_jack *btn_jack;452	struct delayed_work jack_detect_work, rcclock_work;453	struct regulator_bulk_data supplies[ARRAY_SIZE(rt5645_supply_names)];454	struct rt5645_eq_param_s *eq_param;455	struct timer_list btn_check_timer;456	struct mutex jd_mutex;457 458	int codec_type;459	int sysclk;460	int sysclk_src;461	int lrck[RT5645_AIFS];462	int bclk[RT5645_AIFS];463	int master[RT5645_AIFS];464 465	int pll_src;466	int pll_in;467	int pll_out;468 469	int jack_type;470	bool en_button_func;471	int v_id;472};473 474static int rt5645_reset(struct snd_soc_component *component)475{476	return snd_soc_component_write(component, RT5645_RESET, 0);477}478 479static bool rt5645_volatile_register(struct device *dev, unsigned int reg)480{481	int i;482 483	for (i = 0; i < ARRAY_SIZE(rt5645_ranges); i++) {484		if (reg >= rt5645_ranges[i].range_min &&485			reg <= rt5645_ranges[i].range_max) {486			return true;487		}488	}489 490	switch (reg) {491	case RT5645_RESET:492	case RT5645_PRIV_INDEX:493	case RT5645_PRIV_DATA:494	case RT5645_IN1_CTRL1:495	case RT5645_IN1_CTRL2:496	case RT5645_IN1_CTRL3:497	case RT5645_A_JD_CTRL1:498	case RT5645_ADC_EQ_CTRL1:499	case RT5645_EQ_CTRL1:500	case RT5645_ALC_CTRL_1:501	case RT5645_IRQ_CTRL2:502	case RT5645_IRQ_CTRL3:503	case RT5645_INT_IRQ_ST:504	case RT5645_IL_CMD:505	case RT5650_4BTN_IL_CMD1:506	case RT5645_VENDOR_ID:507	case RT5645_VENDOR_ID1:508	case RT5645_VENDOR_ID2:509		return true;510	default:511		return false;512	}513}514 515static bool rt5645_readable_register(struct device *dev, unsigned int reg)516{517	int i;518 519	for (i = 0; i < ARRAY_SIZE(rt5645_ranges); i++) {520		if (reg >= rt5645_ranges[i].range_min &&521			reg <= rt5645_ranges[i].range_max) {522			return true;523		}524	}525 526	switch (reg) {527	case RT5645_RESET:528	case RT5645_SPK_VOL:529	case RT5645_HP_VOL:530	case RT5645_LOUT1:531	case RT5645_IN1_CTRL1:532	case RT5645_IN1_CTRL2:533	case RT5645_IN1_CTRL3:534	case RT5645_IN2_CTRL:535	case RT5645_INL1_INR1_VOL:536	case RT5645_SPK_FUNC_LIM:537	case RT5645_ADJ_HPF_CTRL:538	case RT5645_DAC1_DIG_VOL:539	case RT5645_DAC2_DIG_VOL:540	case RT5645_DAC_CTRL:541	case RT5645_STO1_ADC_DIG_VOL:542	case RT5645_MONO_ADC_DIG_VOL:543	case RT5645_ADC_BST_VOL1:544	case RT5645_ADC_BST_VOL2:545	case RT5645_STO1_ADC_MIXER:546	case RT5645_MONO_ADC_MIXER:547	case RT5645_AD_DA_MIXER:548	case RT5645_STO_DAC_MIXER:549	case RT5645_MONO_DAC_MIXER:550	case RT5645_DIG_MIXER:551	case RT5650_A_DAC_SOUR:552	case RT5645_DIG_INF1_DATA:553	case RT5645_PDM_OUT_CTRL:554	case RT5645_REC_L1_MIXER:555	case RT5645_REC_L2_MIXER:556	case RT5645_REC_R1_MIXER:557	case RT5645_REC_R2_MIXER:558	case RT5645_HPMIXL_CTRL:559	case RT5645_HPOMIXL_CTRL:560	case RT5645_HPMIXR_CTRL:561	case RT5645_HPOMIXR_CTRL:562	case RT5645_HPO_MIXER:563	case RT5645_SPK_L_MIXER:564	case RT5645_SPK_R_MIXER:565	case RT5645_SPO_MIXER:566	case RT5645_SPO_CLSD_RATIO:567	case RT5645_OUT_L1_MIXER:568	case RT5645_OUT_R1_MIXER:569	case RT5645_OUT_L_GAIN1:570	case RT5645_OUT_L_GAIN2:571	case RT5645_OUT_R_GAIN1:572	case RT5645_OUT_R_GAIN2:573	case RT5645_LOUT_MIXER:574	case RT5645_HAPTIC_CTRL1:575	case RT5645_HAPTIC_CTRL2:576	case RT5645_HAPTIC_CTRL3:577	case RT5645_HAPTIC_CTRL4:578	case RT5645_HAPTIC_CTRL5:579	case RT5645_HAPTIC_CTRL6:580	case RT5645_HAPTIC_CTRL7:581	case RT5645_HAPTIC_CTRL8:582	case RT5645_HAPTIC_CTRL9:583	case RT5645_HAPTIC_CTRL10:584	case RT5645_PWR_DIG1:585	case RT5645_PWR_DIG2:586	case RT5645_PWR_ANLG1:587	case RT5645_PWR_ANLG2:588	case RT5645_PWR_MIXER:589	case RT5645_PWR_VOL:590	case RT5645_PRIV_INDEX:591	case RT5645_PRIV_DATA:592	case RT5645_I2S1_SDP:593	case RT5645_I2S2_SDP:594	case RT5645_ADDA_CLK1:595	case RT5645_ADDA_CLK2:596	case RT5645_DMIC_CTRL1:597	case RT5645_DMIC_CTRL2:598	case RT5645_TDM_CTRL_1:599	case RT5645_TDM_CTRL_2:600	case RT5645_TDM_CTRL_3:601	case RT5650_TDM_CTRL_4:602	case RT5645_GLB_CLK:603	case RT5645_PLL_CTRL1:604	case RT5645_PLL_CTRL2:605	case RT5645_ASRC_1:606	case RT5645_ASRC_2:607	case RT5645_ASRC_3:608	case RT5645_ASRC_4:609	case RT5645_DEPOP_M1:610	case RT5645_DEPOP_M2:611	case RT5645_DEPOP_M3:612	case RT5645_CHARGE_PUMP:613	case RT5645_MICBIAS:614	case RT5645_A_JD_CTRL1:615	case RT5645_VAD_CTRL4:616	case RT5645_CLSD_OUT_CTRL:617	case RT5645_ADC_EQ_CTRL1:618	case RT5645_ADC_EQ_CTRL2:619	case RT5645_EQ_CTRL1:620	case RT5645_EQ_CTRL2:621	case RT5645_ALC_CTRL_1:622	case RT5645_ALC_CTRL_2:623	case RT5645_ALC_CTRL_3:624	case RT5645_ALC_CTRL_4:625	case RT5645_ALC_CTRL_5:626	case RT5645_JD_CTRL:627	case RT5645_IRQ_CTRL1:628	case RT5645_IRQ_CTRL2:629	case RT5645_IRQ_CTRL3:630	case RT5645_INT_IRQ_ST:631	case RT5645_GPIO_CTRL1:632	case RT5645_GPIO_CTRL2:633	case RT5645_GPIO_CTRL3:634	case RT5645_BASS_BACK:635	case RT5645_MP3_PLUS1:636	case RT5645_MP3_PLUS2:637	case RT5645_ADJ_HPF1:638	case RT5645_ADJ_HPF2:639	case RT5645_HP_CALIB_AMP_DET:640	case RT5645_SV_ZCD1:641	case RT5645_SV_ZCD2:642	case RT5645_IL_CMD:643	case RT5645_IL_CMD2:644	case RT5645_IL_CMD3:645	case RT5650_4BTN_IL_CMD1:646	case RT5650_4BTN_IL_CMD2:647	case RT5645_DRC1_HL_CTRL1:648	case RT5645_DRC2_HL_CTRL1:649	case RT5645_ADC_MONO_HP_CTRL1:650	case RT5645_ADC_MONO_HP_CTRL2:651	case RT5645_DRC2_CTRL1:652	case RT5645_DRC2_CTRL2:653	case RT5645_DRC2_CTRL3:654	case RT5645_DRC2_CTRL4:655	case RT5645_DRC2_CTRL5:656	case RT5645_JD_CTRL3:657	case RT5645_JD_CTRL4:658	case RT5645_GEN_CTRL1:659	case RT5645_GEN_CTRL2:660	case RT5645_GEN_CTRL3:661	case RT5645_VENDOR_ID:662	case RT5645_VENDOR_ID1:663	case RT5645_VENDOR_ID2:664		return true;665	default:666		return false;667	}668}669 670static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -4650, 150, 0);671static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -6525, 75, 0);672static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -3450, 150, 0);673static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -1725, 75, 0);674static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0);675 676/* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */677static const DECLARE_TLV_DB_RANGE(bst_tlv,678	0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),679	1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0),680	2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),681	3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0),682	6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0),683	7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0),684	8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0)685);686 687/* {-6, -4.5, -3, -1.5, 0, 0.82, 1.58, 2.28} dB */688static const DECLARE_TLV_DB_RANGE(spk_clsd_tlv,689	0, 4, TLV_DB_SCALE_ITEM(-600, 150, 0),690	5, 5, TLV_DB_SCALE_ITEM(82, 0, 0),691	6, 6, TLV_DB_SCALE_ITEM(158, 0, 0),692	7, 7, TLV_DB_SCALE_ITEM(228, 0, 0)693);694 695static int rt5645_hweq_info(struct snd_kcontrol *kcontrol,696			 struct snd_ctl_elem_info *uinfo)697{698	uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;699	uinfo->count = RT5645_HWEQ_NUM * sizeof(struct rt5645_eq_param_s);700 701	return 0;702}703 704static int rt5645_hweq_get(struct snd_kcontrol *kcontrol,705			struct snd_ctl_elem_value *ucontrol)706{707	struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);708	struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);709	struct rt5645_eq_param_s_be16 *eq_param =710		(struct rt5645_eq_param_s_be16 *)ucontrol->value.bytes.data;711	int i;712 713	for (i = 0; i < RT5645_HWEQ_NUM; i++) {714		eq_param[i].reg = cpu_to_be16(rt5645->eq_param[i].reg);715		eq_param[i].val = cpu_to_be16(rt5645->eq_param[i].val);716	}717 718	return 0;719}720 721static bool rt5645_validate_hweq(unsigned short reg)722{723	if ((reg >= 0x1a4 && reg <= 0x1cd) || (reg >= 0x1e5 && reg <= 0x1f8) ||724		(reg == RT5645_EQ_CTRL2))725		return true;726 727	return false;728}729 730static int rt5645_hweq_put(struct snd_kcontrol *kcontrol,731			struct snd_ctl_elem_value *ucontrol)732{733	struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);734	struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);735	struct rt5645_eq_param_s_be16 *eq_param =736		(struct rt5645_eq_param_s_be16 *)ucontrol->value.bytes.data;737	int i;738 739	for (i = 0; i < RT5645_HWEQ_NUM; i++) {740		rt5645->eq_param[i].reg = be16_to_cpu(eq_param[i].reg);741		rt5645->eq_param[i].val = be16_to_cpu(eq_param[i].val);742	}743 744	/* The final setting of the table should be RT5645_EQ_CTRL2 */745	for (i = RT5645_HWEQ_NUM - 1; i >= 0; i--) {746		if (rt5645->eq_param[i].reg == 0)747			continue;748		else if (rt5645->eq_param[i].reg != RT5645_EQ_CTRL2)749			return 0;750		else751			break;752	}753 754	for (i = 0; i < RT5645_HWEQ_NUM; i++) {755		if (!rt5645_validate_hweq(rt5645->eq_param[i].reg) &&756		    rt5645->eq_param[i].reg != 0)757			return 0;758		else if (rt5645->eq_param[i].reg == 0)759			break;760	}761 762	return 0;763}764 765#define RT5645_HWEQ(xname) \766{	.iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \767	.info = rt5645_hweq_info, \768	.get = rt5645_hweq_get, \769	.put = rt5645_hweq_put \770}771 772static int rt5645_spk_put_volsw(struct snd_kcontrol *kcontrol,773		struct snd_ctl_elem_value *ucontrol)774{775	struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);776	struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);777	int ret;778 779	regmap_update_bits(rt5645->regmap, RT5645_MICBIAS,780		RT5645_PWR_CLK25M_MASK, RT5645_PWR_CLK25M_PU);781 782	ret = snd_soc_put_volsw(kcontrol, ucontrol);783 784	mod_delayed_work(system_power_efficient_wq, &rt5645->rcclock_work,785		msecs_to_jiffies(200));786 787	return ret;788}789 790static const char * const rt5645_dac1_vol_ctrl_mode_text[] = {791	"immediately", "zero crossing", "soft ramp"792};793 794static SOC_ENUM_SINGLE_DECL(795	rt5645_dac1_vol_ctrl_mode, RT5645_PR_BASE,796	RT5645_DA1_ZDET_SFT, rt5645_dac1_vol_ctrl_mode_text);797 798static const struct snd_kcontrol_new rt5645_snd_controls[] = {799	/* Speaker Output Volume */800	SOC_DOUBLE("Speaker Channel Switch", RT5645_SPK_VOL,801		RT5645_VOL_L_SFT, RT5645_VOL_R_SFT, 1, 1),802	SOC_DOUBLE_EXT_TLV("Speaker Playback Volume", RT5645_SPK_VOL,803		RT5645_L_VOL_SFT, RT5645_R_VOL_SFT, 39, 1, snd_soc_get_volsw,804		rt5645_spk_put_volsw, out_vol_tlv),805 806	/* ClassD modulator Speaker Gain Ratio */807	SOC_SINGLE_TLV("Speaker ClassD Playback Volume", RT5645_SPO_CLSD_RATIO,808		RT5645_SPK_G_CLSD_SFT, 7, 0, spk_clsd_tlv),809 810	/* Headphone Output Volume */811	SOC_DOUBLE("Headphone Channel Switch", RT5645_HP_VOL,812		RT5645_VOL_L_SFT, RT5645_VOL_R_SFT, 1, 1),813	SOC_DOUBLE_TLV("Headphone Playback Volume", RT5645_HP_VOL,814		RT5645_L_VOL_SFT, RT5645_R_VOL_SFT, 39, 1, out_vol_tlv),815 816	/* OUTPUT Control */817	SOC_DOUBLE("OUT Playback Switch", RT5645_LOUT1,818		RT5645_L_MUTE_SFT, RT5645_R_MUTE_SFT, 1, 1),819	SOC_DOUBLE("OUT Channel Switch", RT5645_LOUT1,820		RT5645_VOL_L_SFT, RT5645_VOL_R_SFT, 1, 1),821	SOC_DOUBLE_TLV("OUT Playback Volume", RT5645_LOUT1,822		RT5645_L_VOL_SFT, RT5645_R_VOL_SFT, 39, 1, out_vol_tlv),823 824	/* DAC Digital Volume */825	SOC_DOUBLE("DAC2 Playback Switch", RT5645_DAC_CTRL,826		RT5645_M_DAC_L2_VOL_SFT, RT5645_M_DAC_R2_VOL_SFT, 1, 1),827	SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5645_DAC1_DIG_VOL,828		RT5645_L_VOL_SFT + 1, RT5645_R_VOL_SFT + 1, 87, 0, dac_vol_tlv),829	SOC_DOUBLE_TLV("Mono DAC Playback Volume", RT5645_DAC2_DIG_VOL,830		RT5645_L_VOL_SFT + 1, RT5645_R_VOL_SFT + 1, 87, 0, dac_vol_tlv),831 832	/* IN1/IN2 Control */833	SOC_SINGLE_TLV("IN1 Boost", RT5645_IN1_CTRL1,834		RT5645_BST_SFT1, 12, 0, bst_tlv),835	SOC_SINGLE_TLV("IN2 Boost", RT5645_IN2_CTRL,836		RT5645_BST_SFT2, 8, 0, bst_tlv),837 838	/* INL/INR Volume Control */839	SOC_DOUBLE_TLV("IN Capture Volume", RT5645_INL1_INR1_VOL,840		RT5645_INL_VOL_SFT, RT5645_INR_VOL_SFT, 31, 1, in_vol_tlv),841 842	/* ADC Digital Volume Control */843	SOC_DOUBLE("ADC Capture Switch", RT5645_STO1_ADC_DIG_VOL,844		RT5645_L_MUTE_SFT, RT5645_R_MUTE_SFT, 1, 1),845	SOC_DOUBLE_TLV("ADC Capture Volume", RT5645_STO1_ADC_DIG_VOL,846		RT5645_L_VOL_SFT + 1, RT5645_R_VOL_SFT + 1, 63, 0, adc_vol_tlv),847	SOC_DOUBLE("Mono ADC Capture Switch", RT5645_MONO_ADC_DIG_VOL,848		RT5645_L_MUTE_SFT, RT5645_R_MUTE_SFT, 1, 1),849	SOC_DOUBLE_TLV("Mono ADC Capture Volume", RT5645_MONO_ADC_DIG_VOL,850		RT5645_L_VOL_SFT + 1, RT5645_R_VOL_SFT + 1, 63, 0, adc_vol_tlv),851 852	/* ADC Boost Volume Control */853	SOC_DOUBLE_TLV("ADC Boost Capture Volume", RT5645_ADC_BST_VOL1,854		RT5645_STO1_ADC_L_BST_SFT, RT5645_STO1_ADC_R_BST_SFT, 3, 0,855		adc_bst_tlv),856	SOC_DOUBLE_TLV("Mono ADC Boost Capture Volume", RT5645_ADC_BST_VOL2,857		RT5645_MONO_ADC_L_BST_SFT, RT5645_MONO_ADC_R_BST_SFT, 3, 0,858		adc_bst_tlv),859 860	/* I2S2 function select */861	SOC_SINGLE("I2S2 Func Switch", RT5645_GPIO_CTRL1, RT5645_I2S2_SEL_SFT,862		1, 1),863	RT5645_HWEQ("Speaker HWEQ"),864 865	/* Digital Soft Volume Control */866	SOC_ENUM("DAC1 Digital Volume Control Func", rt5645_dac1_vol_ctrl_mode),867};868 869/**870 * set_dmic_clk - Set parameter of dmic.871 *872 * @w: DAPM widget.873 * @kcontrol: The kcontrol of this widget.874 * @event: Event id.875 *876 */877static int set_dmic_clk(struct snd_soc_dapm_widget *w,878	struct snd_kcontrol *kcontrol, int event)879{880	struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);881	struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);882	int idx, rate;883 884	rate = rt5645->sysclk / rl6231_get_pre_div(rt5645->regmap,885		RT5645_ADDA_CLK1, RT5645_I2S_PD1_SFT);886	idx = rl6231_calc_dmic_clk(rate);887	if (idx < 0)888		dev_err(component->dev, "Failed to set DMIC clock\n");889	else890		snd_soc_component_update_bits(component, RT5645_DMIC_CTRL1,891			RT5645_DMIC_CLK_MASK, idx << RT5645_DMIC_CLK_SFT);892	return idx;893}894 895static int is_sys_clk_from_pll(struct snd_soc_dapm_widget *source,896			 struct snd_soc_dapm_widget *sink)897{898	struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm);899	unsigned int val;900 901	val = snd_soc_component_read(component, RT5645_GLB_CLK);902	val &= RT5645_SCLK_SRC_MASK;903	if (val == RT5645_SCLK_SRC_PLL1)904		return 1;905	else906		return 0;907}908 909static int is_using_asrc(struct snd_soc_dapm_widget *source,910			 struct snd_soc_dapm_widget *sink)911{912	struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm);913	unsigned int reg, shift, val;914 915	switch (source->shift) {916	case 0:917		reg = RT5645_ASRC_3;918		shift = 0;919		break;920	case 1:921		reg = RT5645_ASRC_3;922		shift = 4;923		break;924	case 3:925		reg = RT5645_ASRC_2;926		shift = 0;927		break;928	case 8:929		reg = RT5645_ASRC_2;930		shift = 4;931		break;932	case 9:933		reg = RT5645_ASRC_2;934		shift = 8;935		break;936	case 10:937		reg = RT5645_ASRC_2;938		shift = 12;939		break;940	default:941		return 0;942	}943 944	val = (snd_soc_component_read(component, reg) >> shift) & 0xf;945	switch (val) {946	case 1:947	case 2:948	case 3:949	case 4:950		return 1;951	default:952		return 0;953	}954 955}956 957static int rt5645_enable_hweq(struct snd_soc_component *component)958{959	struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);960	int i;961 962	for (i = 0; i < RT5645_HWEQ_NUM; i++) {963		if (rt5645_validate_hweq(rt5645->eq_param[i].reg))964			regmap_write(rt5645->regmap, rt5645->eq_param[i].reg,965					rt5645->eq_param[i].val);966		else967			break;968	}969 970	return 0;971}972 973/**974 * rt5645_sel_asrc_clk_src - select ASRC clock source for a set of filters975 * @component: SoC audio component device.976 * @filter_mask: mask of filters.977 * @clk_src: clock source978 *979 * The ASRC function is for asynchronous MCLK and LRCK. Also, since RT5645 can980 * only support standard 32fs or 64fs i2s format, ASRC should be enabled to981 * support special i2s clock format such as Intel's 100fs(100 * sampling rate).982 * ASRC function will track i2s clock and generate a corresponding system clock983 * for codec. This function provides an API to select the clock source for a984 * set of filters specified by the mask. And the codec driver will turn on ASRC985 * for these filters if ASRC is selected as their clock source.986 */987int rt5645_sel_asrc_clk_src(struct snd_soc_component *component,988		unsigned int filter_mask, unsigned int clk_src)989{990	unsigned int asrc2_mask = 0;991	unsigned int asrc2_value = 0;992	unsigned int asrc3_mask = 0;993	unsigned int asrc3_value = 0;994 995	switch (clk_src) {996	case RT5645_CLK_SEL_SYS:997	case RT5645_CLK_SEL_I2S1_ASRC:998	case RT5645_CLK_SEL_I2S2_ASRC:999	case RT5645_CLK_SEL_SYS2:1000		break;1001 1002	default:1003		return -EINVAL;1004	}1005 1006	if (filter_mask & RT5645_DA_STEREO_FILTER) {1007		asrc2_mask |= RT5645_DA_STO_CLK_SEL_MASK;1008		asrc2_value = (asrc2_value & ~RT5645_DA_STO_CLK_SEL_MASK)1009			| (clk_src << RT5645_DA_STO_CLK_SEL_SFT);1010	}1011 1012	if (filter_mask & RT5645_DA_MONO_L_FILTER) {1013		asrc2_mask |= RT5645_DA_MONOL_CLK_SEL_MASK;1014		asrc2_value = (asrc2_value & ~RT5645_DA_MONOL_CLK_SEL_MASK)1015			| (clk_src << RT5645_DA_MONOL_CLK_SEL_SFT);1016	}1017 1018	if (filter_mask & RT5645_DA_MONO_R_FILTER) {1019		asrc2_mask |= RT5645_DA_MONOR_CLK_SEL_MASK;1020		asrc2_value = (asrc2_value & ~RT5645_DA_MONOR_CLK_SEL_MASK)1021			| (clk_src << RT5645_DA_MONOR_CLK_SEL_SFT);1022	}1023 1024	if (filter_mask & RT5645_AD_STEREO_FILTER) {1025		asrc2_mask |= RT5645_AD_STO1_CLK_SEL_MASK;1026		asrc2_value = (asrc2_value & ~RT5645_AD_STO1_CLK_SEL_MASK)1027			| (clk_src << RT5645_AD_STO1_CLK_SEL_SFT);1028	}1029 1030	if (filter_mask & RT5645_AD_MONO_L_FILTER) {1031		asrc3_mask |= RT5645_AD_MONOL_CLK_SEL_MASK;1032		asrc3_value = (asrc3_value & ~RT5645_AD_MONOL_CLK_SEL_MASK)1033			| (clk_src << RT5645_AD_MONOL_CLK_SEL_SFT);1034	}1035 1036	if (filter_mask & RT5645_AD_MONO_R_FILTER)  {1037		asrc3_mask |= RT5645_AD_MONOR_CLK_SEL_MASK;1038		asrc3_value = (asrc3_value & ~RT5645_AD_MONOR_CLK_SEL_MASK)1039			| (clk_src << RT5645_AD_MONOR_CLK_SEL_SFT);1040	}1041 1042	if (asrc2_mask)1043		snd_soc_component_update_bits(component, RT5645_ASRC_2,1044			asrc2_mask, asrc2_value);1045 1046	if (asrc3_mask)1047		snd_soc_component_update_bits(component, RT5645_ASRC_3,1048			asrc3_mask, asrc3_value);1049 1050	return 0;1051}1052EXPORT_SYMBOL_GPL(rt5645_sel_asrc_clk_src);1053 1054/* Digital Mixer */1055static const struct snd_kcontrol_new rt5645_sto1_adc_l_mix[] = {1056	SOC_DAPM_SINGLE("ADC1 Switch", RT5645_STO1_ADC_MIXER,1057			RT5645_M_ADC_L1_SFT, 1, 1),1058	SOC_DAPM_SINGLE("ADC2 Switch", RT5645_STO1_ADC_MIXER,1059			RT5645_M_ADC_L2_SFT, 1, 1),1060};1061 1062static const struct snd_kcontrol_new rt5645_sto1_adc_r_mix[] = {1063	SOC_DAPM_SINGLE("ADC1 Switch", RT5645_STO1_ADC_MIXER,1064			RT5645_M_ADC_R1_SFT, 1, 1),1065	SOC_DAPM_SINGLE("ADC2 Switch", RT5645_STO1_ADC_MIXER,1066			RT5645_M_ADC_R2_SFT, 1, 1),1067};1068 1069static const struct snd_kcontrol_new rt5645_mono_adc_l_mix[] = {1070	SOC_DAPM_SINGLE("ADC1 Switch", RT5645_MONO_ADC_MIXER,1071			RT5645_M_MONO_ADC_L1_SFT, 1, 1),1072	SOC_DAPM_SINGLE("ADC2 Switch", RT5645_MONO_ADC_MIXER,1073			RT5645_M_MONO_ADC_L2_SFT, 1, 1),1074};1075 1076static const struct snd_kcontrol_new rt5645_mono_adc_r_mix[] = {1077	SOC_DAPM_SINGLE("ADC1 Switch", RT5645_MONO_ADC_MIXER,1078			RT5645_M_MONO_ADC_R1_SFT, 1, 1),1079	SOC_DAPM_SINGLE("ADC2 Switch", RT5645_MONO_ADC_MIXER,1080			RT5645_M_MONO_ADC_R2_SFT, 1, 1),1081};1082 1083static const struct snd_kcontrol_new rt5645_dac_l_mix[] = {1084	SOC_DAPM_SINGLE("Stereo ADC Switch", RT5645_AD_DA_MIXER,1085			RT5645_M_ADCMIX_L_SFT, 1, 1),1086	SOC_DAPM_SINGLE_AUTODISABLE("DAC1 Switch", RT5645_AD_DA_MIXER,1087			RT5645_M_DAC1_L_SFT, 1, 1),1088};1089 1090static const struct snd_kcontrol_new rt5645_dac_r_mix[] = {1091	SOC_DAPM_SINGLE("Stereo ADC Switch", RT5645_AD_DA_MIXER,1092			RT5645_M_ADCMIX_R_SFT, 1, 1),1093	SOC_DAPM_SINGLE_AUTODISABLE("DAC1 Switch", RT5645_AD_DA_MIXER,1094			RT5645_M_DAC1_R_SFT, 1, 1),1095};1096 1097static const struct snd_kcontrol_new rt5645_sto_dac_l_mix[] = {1098	SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_STO_DAC_MIXER,1099			RT5645_M_DAC_L1_SFT, 1, 1),1100	SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_STO_DAC_MIXER,1101			RT5645_M_DAC_L2_SFT, 1, 1),1102	SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_STO_DAC_MIXER,1103			RT5645_M_DAC_R1_STO_L_SFT, 1, 1),1104};1105 1106static const struct snd_kcontrol_new rt5645_sto_dac_r_mix[] = {1107	SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_STO_DAC_MIXER,1108			RT5645_M_DAC_R1_SFT, 1, 1),1109	SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_STO_DAC_MIXER,1110			RT5645_M_DAC_R2_SFT, 1, 1),1111	SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_STO_DAC_MIXER,1112			RT5645_M_DAC_L1_STO_R_SFT, 1, 1),1113};1114 1115static const struct snd_kcontrol_new rt5645_mono_dac_l_mix[] = {1116	SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_MONO_DAC_MIXER,1117			RT5645_M_DAC_L1_MONO_L_SFT, 1, 1),1118	SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_MONO_DAC_MIXER,1119			RT5645_M_DAC_L2_MONO_L_SFT, 1, 1),1120	SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_MONO_DAC_MIXER,1121			RT5645_M_DAC_R2_MONO_L_SFT, 1, 1),1122};1123 1124static const struct snd_kcontrol_new rt5645_mono_dac_r_mix[] = {1125	SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_MONO_DAC_MIXER,1126			RT5645_M_DAC_R1_MONO_R_SFT, 1, 1),1127	SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_MONO_DAC_MIXER,1128			RT5645_M_DAC_R2_MONO_R_SFT, 1, 1),1129	SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_MONO_DAC_MIXER,1130			RT5645_M_DAC_L2_MONO_R_SFT, 1, 1),1131};1132 1133static const struct snd_kcontrol_new rt5645_dig_l_mix[] = {1134	SOC_DAPM_SINGLE("Sto DAC Mix L Switch", RT5645_DIG_MIXER,1135			RT5645_M_STO_L_DAC_L_SFT, 1, 1),1136	SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_DIG_MIXER,1137			RT5645_M_DAC_L2_DAC_L_SFT, 1, 1),1138	SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_DIG_MIXER,1139			RT5645_M_DAC_R2_DAC_L_SFT, 1, 1),1140};1141 1142static const struct snd_kcontrol_new rt5645_dig_r_mix[] = {1143	SOC_DAPM_SINGLE("Sto DAC Mix R Switch", RT5645_DIG_MIXER,1144			RT5645_M_STO_R_DAC_R_SFT, 1, 1),1145	SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_DIG_MIXER,1146			RT5645_M_DAC_R2_DAC_R_SFT, 1, 1),1147	SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_DIG_MIXER,1148			RT5645_M_DAC_L2_DAC_R_SFT, 1, 1),1149};1150 1151/* Analog Input Mixer */1152static const struct snd_kcontrol_new rt5645_rec_l_mix[] = {1153	SOC_DAPM_SINGLE("HPOL Switch", RT5645_REC_L2_MIXER,1154			RT5645_M_HP_L_RM_L_SFT, 1, 1),1155	SOC_DAPM_SINGLE("INL Switch", RT5645_REC_L2_MIXER,1156			RT5645_M_IN_L_RM_L_SFT, 1, 1),1157	SOC_DAPM_SINGLE("BST2 Switch", RT5645_REC_L2_MIXER,1158			RT5645_M_BST2_RM_L_SFT, 1, 1),1159	SOC_DAPM_SINGLE("BST1 Switch", RT5645_REC_L2_MIXER,1160			RT5645_M_BST1_RM_L_SFT, 1, 1),1161	SOC_DAPM_SINGLE("OUT MIXL Switch", RT5645_REC_L2_MIXER,1162			RT5645_M_OM_L_RM_L_SFT, 1, 1),1163};1164 1165static const struct snd_kcontrol_new rt5645_rec_r_mix[] = {1166	SOC_DAPM_SINGLE("HPOR Switch", RT5645_REC_R2_MIXER,1167			RT5645_M_HP_R_RM_R_SFT, 1, 1),1168	SOC_DAPM_SINGLE("INR Switch", RT5645_REC_R2_MIXER,1169			RT5645_M_IN_R_RM_R_SFT, 1, 1),1170	SOC_DAPM_SINGLE("BST2 Switch", RT5645_REC_R2_MIXER,1171			RT5645_M_BST2_RM_R_SFT, 1, 1),1172	SOC_DAPM_SINGLE("BST1 Switch", RT5645_REC_R2_MIXER,1173			RT5645_M_BST1_RM_R_SFT, 1, 1),1174	SOC_DAPM_SINGLE("OUT MIXR Switch", RT5645_REC_R2_MIXER,1175			RT5645_M_OM_R_RM_R_SFT, 1, 1),1176};1177 1178static const struct snd_kcontrol_new rt5645_spk_l_mix[] = {1179	SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_SPK_L_MIXER,1180			RT5645_M_DAC_L1_SM_L_SFT, 1, 1),1181	SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_SPK_L_MIXER,1182			RT5645_M_DAC_L2_SM_L_SFT, 1, 1),1183	SOC_DAPM_SINGLE("INL Switch", RT5645_SPK_L_MIXER,1184			RT5645_M_IN_L_SM_L_SFT, 1, 1),1185	SOC_DAPM_SINGLE("BST1 Switch", RT5645_SPK_L_MIXER,1186			RT5645_M_BST1_L_SM_L_SFT, 1, 1),1187};1188 1189static const struct snd_kcontrol_new rt5645_spk_r_mix[] = {1190	SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_SPK_R_MIXER,1191			RT5645_M_DAC_R1_SM_R_SFT, 1, 1),1192	SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_SPK_R_MIXER,1193			RT5645_M_DAC_R2_SM_R_SFT, 1, 1),1194	SOC_DAPM_SINGLE("INR Switch", RT5645_SPK_R_MIXER,1195			RT5645_M_IN_R_SM_R_SFT, 1, 1),1196	SOC_DAPM_SINGLE("BST2 Switch", RT5645_SPK_R_MIXER,1197			RT5645_M_BST2_R_SM_R_SFT, 1, 1),1198};1199 1200static const struct snd_kcontrol_new rt5645_out_l_mix[] = {1201	SOC_DAPM_SINGLE("BST1 Switch", RT5645_OUT_L1_MIXER,1202			RT5645_M_BST1_OM_L_SFT, 1, 1),1203	SOC_DAPM_SINGLE("INL Switch", RT5645_OUT_L1_MIXER,1204			RT5645_M_IN_L_OM_L_SFT, 1, 1),1205	SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_OUT_L1_MIXER,1206			RT5645_M_DAC_L2_OM_L_SFT, 1, 1),1207	SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_OUT_L1_MIXER,1208			RT5645_M_DAC_L1_OM_L_SFT, 1, 1),1209};1210 1211static const struct snd_kcontrol_new rt5645_out_r_mix[] = {1212	SOC_DAPM_SINGLE("BST2 Switch", RT5645_OUT_R1_MIXER,1213			RT5645_M_BST2_OM_R_SFT, 1, 1),1214	SOC_DAPM_SINGLE("INR Switch", RT5645_OUT_R1_MIXER,1215			RT5645_M_IN_R_OM_R_SFT, 1, 1),1216	SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_OUT_R1_MIXER,1217			RT5645_M_DAC_R2_OM_R_SFT, 1, 1),1218	SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_OUT_R1_MIXER,1219			RT5645_M_DAC_R1_OM_R_SFT, 1, 1),1220};1221 1222static const struct snd_kcontrol_new rt5645_spo_l_mix[] = {1223	SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_SPO_MIXER,1224			RT5645_M_DAC_R1_SPM_L_SFT, 1, 1),1225	SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_SPO_MIXER,1226			RT5645_M_DAC_L1_SPM_L_SFT, 1, 1),1227	SOC_DAPM_SINGLE("SPKVOL R Switch", RT5645_SPO_MIXER,1228			RT5645_M_SV_R_SPM_L_SFT, 1, 1),1229	SOC_DAPM_SINGLE("SPKVOL L Switch", RT5645_SPO_MIXER,1230			RT5645_M_SV_L_SPM_L_SFT, 1, 1),1231};1232 1233static const struct snd_kcontrol_new rt5645_spo_r_mix[] = {1234	SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_SPO_MIXER,1235			RT5645_M_DAC_R1_SPM_R_SFT, 1, 1),1236	SOC_DAPM_SINGLE("SPKVOL R Switch", RT5645_SPO_MIXER,1237			RT5645_M_SV_R_SPM_R_SFT, 1, 1),1238};1239 1240static const struct snd_kcontrol_new rt5645_hpo_mix[] = {1241	SOC_DAPM_SINGLE("DAC1 Switch", RT5645_HPO_MIXER,1242			RT5645_M_DAC1_HM_SFT, 1, 1),1243	SOC_DAPM_SINGLE("HPVOL Switch", RT5645_HPO_MIXER,1244			RT5645_M_HPVOL_HM_SFT, 1, 1),1245};1246 1247static const struct snd_kcontrol_new rt5645_hpvoll_mix[] = {1248	SOC_DAPM_SINGLE("DAC1 Switch", RT5645_HPOMIXL_CTRL,1249			RT5645_M_DAC1_HV_SFT, 1, 1),1250	SOC_DAPM_SINGLE("DAC2 Switch", RT5645_HPOMIXL_CTRL,1251			RT5645_M_DAC2_HV_SFT, 1, 1),1252	SOC_DAPM_SINGLE("INL Switch", RT5645_HPOMIXL_CTRL,1253			RT5645_M_IN_HV_SFT, 1, 1),1254	SOC_DAPM_SINGLE("BST1 Switch", RT5645_HPOMIXL_CTRL,1255			RT5645_M_BST1_HV_SFT, 1, 1),1256};1257 1258static const struct snd_kcontrol_new rt5645_hpvolr_mix[] = {1259	SOC_DAPM_SINGLE("DAC1 Switch", RT5645_HPOMIXR_CTRL,1260			RT5645_M_DAC1_HV_SFT, 1, 1),1261	SOC_DAPM_SINGLE("DAC2 Switch", RT5645_HPOMIXR_CTRL,1262			RT5645_M_DAC2_HV_SFT, 1, 1),1263	SOC_DAPM_SINGLE("INR Switch", RT5645_HPOMIXR_CTRL,1264			RT5645_M_IN_HV_SFT, 1, 1),1265	SOC_DAPM_SINGLE("BST2 Switch", RT5645_HPOMIXR_CTRL,1266			RT5645_M_BST2_HV_SFT, 1, 1),1267};1268 1269static const struct snd_kcontrol_new rt5645_lout_mix[] = {1270	SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_LOUT_MIXER,1271			RT5645_M_DAC_L1_LM_SFT, 1, 1),1272	SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_LOUT_MIXER,1273			RT5645_M_DAC_R1_LM_SFT, 1, 1),1274	SOC_DAPM_SINGLE("OUTMIX L Switch", RT5645_LOUT_MIXER,1275			RT5645_M_OV_L_LM_SFT, 1, 1),1276	SOC_DAPM_SINGLE("OUTMIX R Switch", RT5645_LOUT_MIXER,1277			RT5645_M_OV_R_LM_SFT, 1, 1),1278};1279 1280/*DAC1 L/R source*/ /* MX-29 [9:8] [11:10] */1281static const char * const rt5645_dac1_src[] = {1282	"IF1 DAC", "IF2 DAC", "IF3 DAC"1283};1284 1285static SOC_ENUM_SINGLE_DECL(1286	rt5645_dac1l_enum, RT5645_AD_DA_MIXER,1287	RT5645_DAC1_L_SEL_SFT, rt5645_dac1_src);1288 1289static const struct snd_kcontrol_new rt5645_dac1l_mux =1290	SOC_DAPM_ENUM("DAC1 L source", rt5645_dac1l_enum);1291 1292static SOC_ENUM_SINGLE_DECL(1293	rt5645_dac1r_enum, RT5645_AD_DA_MIXER,1294	RT5645_DAC1_R_SEL_SFT, rt5645_dac1_src);1295 1296static const struct snd_kcontrol_new rt5645_dac1r_mux =1297	SOC_DAPM_ENUM("DAC1 R source", rt5645_dac1r_enum);1298 1299/*DAC2 L/R source*/ /* MX-1B [6:4] [2:0] */1300static const char * const rt5645_dac12_src[] = {1301	"IF1 DAC", "IF2 DAC", "IF3 DAC", "Mono ADC", "VAD_ADC"1302};1303 1304static SOC_ENUM_SINGLE_DECL(1305	rt5645_dac2l_enum, RT5645_DAC_CTRL,1306	RT5645_DAC2_L_SEL_SFT, rt5645_dac12_src);1307 1308static const struct snd_kcontrol_new rt5645_dac_l2_mux =1309	SOC_DAPM_ENUM("DAC2 L source", rt5645_dac2l_enum);1310 1311static const char * const rt5645_dacr2_src[] = {1312	"IF1 DAC", "IF2 DAC", "IF3 DAC", "Mono ADC", "Haptic"1313};1314 1315static SOC_ENUM_SINGLE_DECL(1316	rt5645_dac2r_enum, RT5645_DAC_CTRL,1317	RT5645_DAC2_R_SEL_SFT, rt5645_dacr2_src);1318 1319static const struct snd_kcontrol_new rt5645_dac_r2_mux =1320	SOC_DAPM_ENUM("DAC2 R source", rt5645_dac2r_enum);1321 1322/* Stereo1 ADC source */1323/* MX-27 [12] */1324static const char * const rt5645_stereo_adc1_src[] = {1325	"DAC MIX", "ADC"1326};1327 1328static SOC_ENUM_SINGLE_DECL(1329	rt5645_stereo1_adc1_enum, RT5645_STO1_ADC_MIXER,1330	RT5645_ADC_1_SRC_SFT, rt5645_stereo_adc1_src);1331 1332static const struct snd_kcontrol_new rt5645_sto_adc1_mux =1333	SOC_DAPM_ENUM("Stereo1 ADC1 Mux", rt5645_stereo1_adc1_enum);1334 1335/* MX-27 [11] */1336static const char * const rt5645_stereo_adc2_src[] = {1337	"DAC MIX", "DMIC"1338};1339 1340static SOC_ENUM_SINGLE_DECL(1341	rt5645_stereo1_adc2_enum, RT5645_STO1_ADC_MIXER,1342	RT5645_ADC_2_SRC_SFT, rt5645_stereo_adc2_src);1343 1344static const struct snd_kcontrol_new rt5645_sto_adc2_mux =1345	SOC_DAPM_ENUM("Stereo1 ADC2 Mux", rt5645_stereo1_adc2_enum);1346 1347/* MX-27 [8] */1348static const char * const rt5645_stereo_dmic_src[] = {1349	"DMIC1", "DMIC2"1350};1351 1352static SOC_ENUM_SINGLE_DECL(1353	rt5645_stereo1_dmic_enum, RT5645_STO1_ADC_MIXER,1354	RT5645_DMIC_SRC_SFT, rt5645_stereo_dmic_src);1355 1356static const struct snd_kcontrol_new rt5645_sto1_dmic_mux =1357	SOC_DAPM_ENUM("Stereo1 DMIC source", rt5645_stereo1_dmic_enum);1358 1359/* Mono ADC source */1360/* MX-28 [12] */1361static const char * const rt5645_mono_adc_l1_src[] = {1362	"Mono DAC MIXL", "ADC"1363};1364 1365static SOC_ENUM_SINGLE_DECL(1366	rt5645_mono_adc_l1_enum, RT5645_MONO_ADC_MIXER,1367	RT5645_MONO_ADC_L1_SRC_SFT, rt5645_mono_adc_l1_src);1368 1369static const struct snd_kcontrol_new rt5645_mono_adc_l1_mux =1370	SOC_DAPM_ENUM("Mono ADC1 left source", rt5645_mono_adc_l1_enum);1371/* MX-28 [11] */1372static const char * const rt5645_mono_adc_l2_src[] = {1373	"Mono DAC MIXL", "DMIC"1374};1375 1376static SOC_ENUM_SINGLE_DECL(1377	rt5645_mono_adc_l2_enum, RT5645_MONO_ADC_MIXER,1378	RT5645_MONO_ADC_L2_SRC_SFT, rt5645_mono_adc_l2_src);1379 1380static const struct snd_kcontrol_new rt5645_mono_adc_l2_mux =1381	SOC_DAPM_ENUM("Mono ADC2 left source", rt5645_mono_adc_l2_enum);1382 1383/* MX-28 [8] */1384static const char * const rt5645_mono_dmic_src[] = {1385	"DMIC1", "DMIC2"1386};1387 1388static SOC_ENUM_SINGLE_DECL(1389	rt5645_mono_dmic_l_enum, RT5645_MONO_ADC_MIXER,1390	RT5645_MONO_DMIC_L_SRC_SFT, rt5645_mono_dmic_src);1391 1392static const struct snd_kcontrol_new rt5645_mono_dmic_l_mux =1393	SOC_DAPM_ENUM("Mono DMIC left source", rt5645_mono_dmic_l_enum);1394/* MX-28 [1:0] */1395static SOC_ENUM_SINGLE_DECL(1396	rt5645_mono_dmic_r_enum, RT5645_MONO_ADC_MIXER,1397	RT5645_MONO_DMIC_R_SRC_SFT, rt5645_mono_dmic_src);1398 1399static const struct snd_kcontrol_new rt5645_mono_dmic_r_mux =1400	SOC_DAPM_ENUM("Mono DMIC Right source", rt5645_mono_dmic_r_enum);1401/* MX-28 [4] */1402static const char * const rt5645_mono_adc_r1_src[] = {1403	"Mono DAC MIXR", "ADC"1404};1405 1406static SOC_ENUM_SINGLE_DECL(1407	rt5645_mono_adc_r1_enum, RT5645_MONO_ADC_MIXER,1408	RT5645_MONO_ADC_R1_SRC_SFT, rt5645_mono_adc_r1_src);1409 1410static const struct snd_kcontrol_new rt5645_mono_adc_r1_mux =1411	SOC_DAPM_ENUM("Mono ADC1 right source", rt5645_mono_adc_r1_enum);1412/* MX-28 [3] */1413static const char * const rt5645_mono_adc_r2_src[] = {1414	"Mono DAC MIXR", "DMIC"1415};1416 1417static SOC_ENUM_SINGLE_DECL(1418	rt5645_mono_adc_r2_enum, RT5645_MONO_ADC_MIXER,1419	RT5645_MONO_ADC_R2_SRC_SFT, rt5645_mono_adc_r2_src);1420 1421static const struct snd_kcontrol_new rt5645_mono_adc_r2_mux =1422	SOC_DAPM_ENUM("Mono ADC2 right source", rt5645_mono_adc_r2_enum);1423 1424/* MX-77 [9:8] */1425static const char * const rt5645_if1_adc_in_src[] = {1426	"IF_ADC1/IF_ADC2/VAD_ADC", "IF_ADC2/IF_ADC1/VAD_ADC",1427	"VAD_ADC/IF_ADC1/IF_ADC2", "VAD_ADC/IF_ADC2/IF_ADC1"1428};1429 1430static SOC_ENUM_SINGLE_DECL(1431	rt5645_if1_adc_in_enum, RT5645_TDM_CTRL_1,1432	RT5645_IF1_ADC_IN_SFT, rt5645_if1_adc_in_src);1433 1434static const struct snd_kcontrol_new rt5645_if1_adc_in_mux =1435	SOC_DAPM_ENUM("IF1 ADC IN source", rt5645_if1_adc_in_enum);1436 1437/* MX-78 [4:0] */1438static const char * const rt5650_if1_adc_in_src[] = {1439	"IF_ADC1/IF_ADC2/DAC_REF/Null",1440	"IF_ADC1/IF_ADC2/Null/DAC_REF",1441	"IF_ADC1/DAC_REF/IF_ADC2/Null",1442	"IF_ADC1/DAC_REF/Null/IF_ADC2",1443	"IF_ADC1/Null/DAC_REF/IF_ADC2",1444	"IF_ADC1/Null/IF_ADC2/DAC_REF",1445 1446	"IF_ADC2/IF_ADC1/DAC_REF/Null",1447	"IF_ADC2/IF_ADC1/Null/DAC_REF",1448	"IF_ADC2/DAC_REF/IF_ADC1/Null",1449	"IF_ADC2/DAC_REF/Null/IF_ADC1",1450	"IF_ADC2/Null/DAC_REF/IF_ADC1",1451	"IF_ADC2/Null/IF_ADC1/DAC_REF",1452 1453	"DAC_REF/IF_ADC1/IF_ADC2/Null",1454	"DAC_REF/IF_ADC1/Null/IF_ADC2",1455	"DAC_REF/IF_ADC2/IF_ADC1/Null",1456	"DAC_REF/IF_ADC2/Null/IF_ADC1",1457	"DAC_REF/Null/IF_ADC1/IF_ADC2",1458	"DAC_REF/Null/IF_ADC2/IF_ADC1",1459 1460	"Null/IF_ADC1/IF_ADC2/DAC_REF",1461	"Null/IF_ADC1/DAC_REF/IF_ADC2",1462	"Null/IF_ADC2/IF_ADC1/DAC_REF",1463	"Null/IF_ADC2/DAC_REF/IF_ADC1",1464	"Null/DAC_REF/IF_ADC1/IF_ADC2",1465	"Null/DAC_REF/IF_ADC2/IF_ADC1",1466};1467 1468static SOC_ENUM_SINGLE_DECL(1469	rt5650_if1_adc_in_enum, RT5645_TDM_CTRL_2,1470	0, rt5650_if1_adc_in_src);1471 1472static const struct snd_kcontrol_new rt5650_if1_adc_in_mux =1473	SOC_DAPM_ENUM("IF1 ADC IN source", rt5650_if1_adc_in_enum);1474 1475/* MX-78 [15:14][13:12][11:10] */1476static const char * const rt5645_tdm_adc_swap_select[] = {1477	"L/R", "R/L", "L/L", "R/R"1478};1479 1480static SOC_ENUM_SINGLE_DECL(rt5650_tdm_adc_slot0_1_enum,1481	RT5645_TDM_CTRL_2, 14, rt5645_tdm_adc_swap_select);1482 1483static const struct snd_kcontrol_new rt5650_if1_adc1_in_mux =1484	SOC_DAPM_ENUM("IF1 ADC1 IN source", rt5650_tdm_adc_slot0_1_enum);1485 1486static SOC_ENUM_SINGLE_DECL(rt5650_tdm_adc_slot2_3_enum,1487	RT5645_TDM_CTRL_2, 12, rt5645_tdm_adc_swap_select);1488 1489static const struct snd_kcontrol_new rt5650_if1_adc2_in_mux =1490	SOC_DAPM_ENUM("IF1 ADC2 IN source", rt5650_tdm_adc_slot2_3_enum);1491 1492static SOC_ENUM_SINGLE_DECL(rt5650_tdm_adc_slot4_5_enum,1493	RT5645_TDM_CTRL_2, 10, rt5645_tdm_adc_swap_select);1494 1495static const struct snd_kcontrol_new rt5650_if1_adc3_in_mux =1496	SOC_DAPM_ENUM("IF1 ADC3 IN source", rt5650_tdm_adc_slot4_5_enum);1497 1498/* MX-77 [7:6][5:4][3:2] */1499static SOC_ENUM_SINGLE_DECL(rt5645_tdm_adc_slot0_1_enum,1500	RT5645_TDM_CTRL_1, 6, rt5645_tdm_adc_swap_select);1501 1502static const struct snd_kcontrol_new rt5645_if1_adc1_in_mux =1503	SOC_DAPM_ENUM("IF1 ADC1 IN source", rt5645_tdm_adc_slot0_1_enum);1504 1505static SOC_ENUM_SINGLE_DECL(rt5645_tdm_adc_slot2_3_enum,1506	RT5645_TDM_CTRL_1, 4, rt5645_tdm_adc_swap_select);1507 1508static const struct snd_kcontrol_new rt5645_if1_adc2_in_mux =1509	SOC_DAPM_ENUM("IF1 ADC2 IN source", rt5645_tdm_adc_slot2_3_enum);1510 1511static SOC_ENUM_SINGLE_DECL(rt5645_tdm_adc_slot4_5_enum,1512	RT5645_TDM_CTRL_1, 2, rt5645_tdm_adc_swap_select);1513 1514static const struct snd_kcontrol_new rt5645_if1_adc3_in_mux =1515	SOC_DAPM_ENUM("IF1 ADC3 IN source", rt5645_tdm_adc_slot4_5_enum);1516 1517/* MX-79 [14:12][10:8][6:4][2:0] */1518static const char * const rt5645_tdm_dac_swap_select[] = {1519	"Slot0", "Slot1", "Slot2", "Slot3"1520};1521 1522static SOC_ENUM_SINGLE_DECL(rt5645_tdm_dac0_enum,1523	RT5645_TDM_CTRL_3, 12, rt5645_tdm_dac_swap_select);1524 1525static const struct snd_kcontrol_new rt5645_if1_dac0_tdm_sel_mux =1526	SOC_DAPM_ENUM("IF1 DAC0 source", rt5645_tdm_dac0_enum);1527 1528static SOC_ENUM_SINGLE_DECL(rt5645_tdm_dac1_enum,1529	RT5645_TDM_CTRL_3, 8, rt5645_tdm_dac_swap_select);1530 1531static const struct snd_kcontrol_new rt5645_if1_dac1_tdm_sel_mux =1532	SOC_DAPM_ENUM("IF1 DAC1 source", rt5645_tdm_dac1_enum);1533 1534static SOC_ENUM_SINGLE_DECL(rt5645_tdm_dac2_enum,1535	RT5645_TDM_CTRL_3, 4, rt5645_tdm_dac_swap_select);1536 1537static const struct snd_kcontrol_new rt5645_if1_dac2_tdm_sel_mux =1538	SOC_DAPM_ENUM("IF1 DAC2 source", rt5645_tdm_dac2_enum);1539 1540static SOC_ENUM_SINGLE_DECL(rt5645_tdm_dac3_enum,1541	RT5645_TDM_CTRL_3, 0, rt5645_tdm_dac_swap_select);1542 1543static const struct snd_kcontrol_new rt5645_if1_dac3_tdm_sel_mux =1544	SOC_DAPM_ENUM("IF1 DAC3 source", rt5645_tdm_dac3_enum);1545 1546/* MX-7a [14:12][10:8][6:4][2:0] */1547static SOC_ENUM_SINGLE_DECL(rt5650_tdm_dac0_enum,1548	RT5650_TDM_CTRL_4, 12, rt5645_tdm_dac_swap_select);1549 1550static const struct snd_kcontrol_new rt5650_if1_dac0_tdm_sel_mux =1551	SOC_DAPM_ENUM("IF1 DAC0 source", rt5650_tdm_dac0_enum);1552 1553static SOC_ENUM_SINGLE_DECL(rt5650_tdm_dac1_enum,1554	RT5650_TDM_CTRL_4, 8, rt5645_tdm_dac_swap_select);1555 1556static const struct snd_kcontrol_new rt5650_if1_dac1_tdm_sel_mux =1557	SOC_DAPM_ENUM("IF1 DAC1 source", rt5650_tdm_dac1_enum);1558 1559static SOC_ENUM_SINGLE_DECL(rt5650_tdm_dac2_enum,1560	RT5650_TDM_CTRL_4, 4, rt5645_tdm_dac_swap_select);1561 1562static const struct snd_kcontrol_new rt5650_if1_dac2_tdm_sel_mux =1563	SOC_DAPM_ENUM("IF1 DAC2 source", rt5650_tdm_dac2_enum);1564 1565static SOC_ENUM_SINGLE_DECL(rt5650_tdm_dac3_enum,1566	RT5650_TDM_CTRL_4, 0, rt5645_tdm_dac_swap_select);1567 1568static const struct snd_kcontrol_new rt5650_if1_dac3_tdm_sel_mux =1569	SOC_DAPM_ENUM("IF1 DAC3 source", rt5650_tdm_dac3_enum);1570 1571/* MX-2d [3] [2] */1572static const char * const rt5650_a_dac1_src[] = {1573	"DAC1", "Stereo DAC Mixer"1574};1575 1576static SOC_ENUM_SINGLE_DECL(1577	rt5650_a_dac1_l_enum, RT5650_A_DAC_SOUR,1578	RT5650_A_DAC1_L_IN_SFT, rt5650_a_dac1_src);1579 1580static const struct snd_kcontrol_new rt5650_a_dac1_l_mux =1581	SOC_DAPM_ENUM("A DAC1 L source", rt5650_a_dac1_l_enum);1582 1583static SOC_ENUM_SINGLE_DECL(1584	rt5650_a_dac1_r_enum, RT5650_A_DAC_SOUR,1585	RT5650_A_DAC1_R_IN_SFT, rt5650_a_dac1_src);1586 1587static const struct snd_kcontrol_new rt5650_a_dac1_r_mux =1588	SOC_DAPM_ENUM("A DAC1 R source", rt5650_a_dac1_r_enum);1589 1590/* MX-2d [1] [0] */1591static const char * const rt5650_a_dac2_src[] = {1592	"Stereo DAC Mixer", "Mono DAC Mixer"1593};1594 1595static SOC_ENUM_SINGLE_DECL(1596	rt5650_a_dac2_l_enum, RT5650_A_DAC_SOUR,1597	RT5650_A_DAC2_L_IN_SFT, rt5650_a_dac2_src);1598 1599static const struct snd_kcontrol_new rt5650_a_dac2_l_mux =1600	SOC_DAPM_ENUM("A DAC2 L source", rt5650_a_dac2_l_enum);1601 1602static SOC_ENUM_SINGLE_DECL(1603	rt5650_a_dac2_r_enum, RT5650_A_DAC_SOUR,1604	RT5650_A_DAC2_R_IN_SFT, rt5650_a_dac2_src);1605 1606static const struct snd_kcontrol_new rt5650_a_dac2_r_mux =1607	SOC_DAPM_ENUM("A DAC2 R source", rt5650_a_dac2_r_enum);1608 1609/* MX-2F [13:12] */1610static const char * const rt5645_if2_adc_in_src[] = {1611	"IF_ADC1", "IF_ADC2", "VAD_ADC"1612};1613 1614static SOC_ENUM_SINGLE_DECL(1615	rt5645_if2_adc_in_enum, RT5645_DIG_INF1_DATA,1616	RT5645_IF2_ADC_IN_SFT, rt5645_if2_adc_in_src);1617 1618static const struct snd_kcontrol_new rt5645_if2_adc_in_mux =1619	SOC_DAPM_ENUM("IF2 ADC IN source", rt5645_if2_adc_in_enum);1620 1621/* MX-31 [15] [13] [11] [9] */1622static const char * const rt5645_pdm_src[] = {1623	"Mono DAC", "Stereo DAC"1624};1625 1626static SOC_ENUM_SINGLE_DECL(1627	rt5645_pdm1_l_enum, RT5645_PDM_OUT_CTRL,1628	RT5645_PDM1_L_SFT, rt5645_pdm_src);1629 1630static const struct snd_kcontrol_new rt5645_pdm1_l_mux =1631	SOC_DAPM_ENUM("PDM1 L source", rt5645_pdm1_l_enum);1632 1633static SOC_ENUM_SINGLE_DECL(1634	rt5645_pdm1_r_enum, RT5645_PDM_OUT_CTRL,1635	RT5645_PDM1_R_SFT, rt5645_pdm_src);1636 1637static const struct snd_kcontrol_new rt5645_pdm1_r_mux =1638	SOC_DAPM_ENUM("PDM1 R source", rt5645_pdm1_r_enum);1639 1640/* MX-9D [9:8] */1641static const char * const rt5645_vad_adc_src[] = {1642	"Sto1 ADC L", "Mono ADC L", "Mono ADC R"1643};1644 1645static SOC_ENUM_SINGLE_DECL(1646	rt5645_vad_adc_enum, RT5645_VAD_CTRL4,1647	RT5645_VAD_SEL_SFT, rt5645_vad_adc_src);1648 1649static const struct snd_kcontrol_new rt5645_vad_adc_mux =1650	SOC_DAPM_ENUM("VAD ADC source", rt5645_vad_adc_enum);1651 1652static const struct snd_kcontrol_new spk_l_vol_control =1653	SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_SPK_VOL,1654		RT5645_L_MUTE_SFT, 1, 1);1655 1656static const struct snd_kcontrol_new spk_r_vol_control =1657	SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_SPK_VOL,1658		RT5645_R_MUTE_SFT, 1, 1);1659 1660static const struct snd_kcontrol_new hp_l_vol_control =1661	SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_HP_VOL,1662		RT5645_L_MUTE_SFT, 1, 1);1663 1664static const struct snd_kcontrol_new hp_r_vol_control =1665	SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_HP_VOL,1666		RT5645_R_MUTE_SFT, 1, 1);1667 1668static const struct snd_kcontrol_new pdm1_l_vol_control =1669	SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_PDM_OUT_CTRL,1670		RT5645_M_PDM1_L, 1, 1);1671 1672static const struct snd_kcontrol_new pdm1_r_vol_control =1673	SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_PDM_OUT_CTRL,1674		RT5645_M_PDM1_R, 1, 1);1675 1676static void hp_amp_power(struct snd_soc_component *component, int on)1677{1678	static int hp_amp_power_count;1679	struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);1680	int i, val;1681 1682	if (on) {1683		if (hp_amp_power_count <= 0) {1684			if (rt5645->codec_type == CODEC_TYPE_RT5650) {1685				snd_soc_component_write(component, RT5645_DEPOP_M2, 0x3100);1686				snd_soc_component_write(component, RT5645_CHARGE_PUMP,1687					0x0e06);1688				snd_soc_component_write(component, RT5645_DEPOP_M1, 0x000d);1689				regmap_write(rt5645->regmap, RT5645_PR_BASE +1690					RT5645_HP_DCC_INT1, 0x9f01);1691				for (i = 0; i < 20; i++) {1692					usleep_range(1000, 1500);1693					regmap_read(rt5645->regmap, RT5645_PR_BASE +1694						RT5645_HP_DCC_INT1, &val);1695					if (!(val & 0x8000))1696						break;1697				}1698				snd_soc_component_update_bits(component, RT5645_DEPOP_M1,1699					RT5645_HP_CO_MASK, RT5645_HP_CO_EN);1700				regmap_write(rt5645->regmap, RT5645_PR_BASE +1701					0x3e, 0x7400);1702				snd_soc_component_write(component, RT5645_DEPOP_M3, 0x0737);1703				regmap_write(rt5645->regmap, RT5645_PR_BASE +1704					RT5645_MAMP_INT_REG2, 0xfc00);1705				snd_soc_component_write(component, RT5645_DEPOP_M2, 0x1140);1706				snd_soc_component_update_bits(component, RT5645_PWR_ANLG1,1707					RT5645_PWR_HP_L | RT5645_PWR_HP_R,1708					RT5645_PWR_HP_L | RT5645_PWR_HP_R);1709				msleep(90);1710			} else {1711				/* depop parameters */1712				snd_soc_component_update_bits(component, RT5645_DEPOP_M2,1713					RT5645_DEPOP_MASK, RT5645_DEPOP_MAN);1714				snd_soc_component_write(component, RT5645_DEPOP_M1, 0x000d);1715				regmap_write(rt5645->regmap, RT5645_PR_BASE +1716					RT5645_HP_DCC_INT1, 0x9f01);1717				mdelay(150);1718				/* headphone amp power on */1719				snd_soc_component_update_bits(component, RT5645_PWR_ANLG1,1720					RT5645_PWR_FV1 | RT5645_PWR_FV2, 0);1721				snd_soc_component_update_bits(component, RT5645_PWR_VOL,1722					RT5645_PWR_HV_L | RT5645_PWR_HV_R,1723					RT5645_PWR_HV_L | RT5645_PWR_HV_R);1724				snd_soc_component_update_bits(component, RT5645_PWR_ANLG1,1725					RT5645_PWR_HP_L | RT5645_PWR_HP_R |1726					RT5645_PWR_HA,1727					RT5645_PWR_HP_L | RT5645_PWR_HP_R |1728					RT5645_PWR_HA);1729				mdelay(5);1730				snd_soc_component_update_bits(component, RT5645_PWR_ANLG1,1731					RT5645_PWR_FV1 | RT5645_PWR_FV2,1732					RT5645_PWR_FV1 | RT5645_PWR_FV2);1733 1734				snd_soc_component_update_bits(component, RT5645_DEPOP_M1,1735					RT5645_HP_CO_MASK | RT5645_HP_SG_MASK,1736					RT5645_HP_CO_EN | RT5645_HP_SG_EN);1737				regmap_write(rt5645->regmap, RT5645_PR_BASE +1738					0x14, 0x1aaa);1739				regmap_write(rt5645->regmap, RT5645_PR_BASE +1740					0x24, 0x0430);1741			}1742		}1743		hp_amp_power_count++;1744	} else {1745		hp_amp_power_count--;1746		if (hp_amp_power_count <= 0) {1747			if (rt5645->codec_type == CODEC_TYPE_RT5650) {1748				regmap_write(rt5645->regmap, RT5645_PR_BASE +1749					0x3e, 0x7400);1750				snd_soc_component_write(component, RT5645_DEPOP_M3, 0x0737);1751				regmap_write(rt5645->regmap, RT5645_PR_BASE +1752					RT5645_MAMP_INT_REG2, 0xfc00);1753				snd_soc_component_write(component, RT5645_DEPOP_M2, 0x1140);1754				msleep(100);1755				snd_soc_component_write(component, RT5645_DEPOP_M1, 0x0001);1756				snd_soc_component_update_bits(component, RT5645_PWR_ANLG1,1757					RT5645_PWR_HP_L | RT5645_PWR_HP_R, 0);1758			} else {1759				snd_soc_component_update_bits(component, RT5645_DEPOP_M1,1760					RT5645_HP_SG_MASK |1761					RT5645_HP_L_SMT_MASK |1762					RT5645_HP_R_SMT_MASK,1763					RT5645_HP_SG_DIS |1764					RT5645_HP_L_SMT_DIS |1765					RT5645_HP_R_SMT_DIS);1766				/* headphone amp power down */1767				snd_soc_component_write(component, RT5645_DEPOP_M1, 0x0000);1768				snd_soc_component_update_bits(component, RT5645_PWR_ANLG1,1769					RT5645_PWR_HP_L | RT5645_PWR_HP_R |1770					RT5645_PWR_HA, 0);1771				snd_soc_component_update_bits(component, RT5645_DEPOP_M2,1772					RT5645_DEPOP_MASK, 0);1773			}1774		}1775	}1776}1777 1778static int rt5645_hp_event(struct snd_soc_dapm_widget *w,1779	struct snd_kcontrol *kcontrol, int event)1780{1781	struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);1782	struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);1783 1784	switch (event) {1785	case SND_SOC_DAPM_POST_PMU:1786		hp_amp_power(component, 1);1787		/* headphone unmute sequence */1788		if (rt5645->codec_type == CODEC_TYPE_RT5645) {1789			snd_soc_component_update_bits(component, RT5645_DEPOP_M3,1790				RT5645_CP_FQ1_MASK | RT5645_CP_FQ2_MASK |1791				RT5645_CP_FQ3_MASK,1792				(RT5645_CP_FQ_192_KHZ << RT5645_CP_FQ1_SFT) |1793				(RT5645_CP_FQ_12_KHZ << RT5645_CP_FQ2_SFT) |1794				(RT5645_CP_FQ_192_KHZ << RT5645_CP_FQ3_SFT));1795			regmap_write(rt5645->regmap, RT5645_PR_BASE +1796				RT5645_MAMP_INT_REG2, 0xfc00);1797			snd_soc_component_update_bits(component, RT5645_DEPOP_M1,1798				RT5645_SMT_TRIG_MASK, RT5645_SMT_TRIG_EN);1799			snd_soc_component_update_bits(component, RT5645_DEPOP_M1,1800				RT5645_RSTN_MASK, RT5645_RSTN_EN);1801			snd_soc_component_update_bits(component, RT5645_DEPOP_M1,1802				RT5645_RSTN_MASK | RT5645_HP_L_SMT_MASK |1803				RT5645_HP_R_SMT_MASK, RT5645_RSTN_DIS |1804				RT5645_HP_L_SMT_EN | RT5645_HP_R_SMT_EN);1805			msleep(40);1806			snd_soc_component_update_bits(component, RT5645_DEPOP_M1,1807				RT5645_HP_SG_MASK | RT5645_HP_L_SMT_MASK |1808				RT5645_HP_R_SMT_MASK, RT5645_HP_SG_DIS |1809				RT5645_HP_L_SMT_DIS | RT5645_HP_R_SMT_DIS);1810		}1811		break;1812 1813	case SND_SOC_DAPM_PRE_PMD:1814		/* headphone mute sequence */1815		if (rt5645->codec_type == CODEC_TYPE_RT5645) {1816			snd_soc_component_update_bits(component, RT5645_DEPOP_M3,1817				RT5645_CP_FQ1_MASK | RT5645_CP_FQ2_MASK |1818				RT5645_CP_FQ3_MASK,1819				(RT5645_CP_FQ_96_KHZ << RT5645_CP_FQ1_SFT) |1820				(RT5645_CP_FQ_12_KHZ << RT5645_CP_FQ2_SFT) |1821				(RT5645_CP_FQ_96_KHZ << RT5645_CP_FQ3_SFT));1822			regmap_write(rt5645->regmap, RT5645_PR_BASE +1823				RT5645_MAMP_INT_REG2, 0xfc00);1824			snd_soc_component_update_bits(component, RT5645_DEPOP_M1,1825				RT5645_HP_SG_MASK, RT5645_HP_SG_EN);1826			snd_soc_component_update_bits(component, RT5645_DEPOP_M1,1827				RT5645_RSTP_MASK, RT5645_RSTP_EN);1828			snd_soc_component_update_bits(component, RT5645_DEPOP_M1,1829				RT5645_RSTP_MASK | RT5645_HP_L_SMT_MASK |1830				RT5645_HP_R_SMT_MASK, RT5645_RSTP_DIS |1831				RT5645_HP_L_SMT_EN | RT5645_HP_R_SMT_EN);1832			msleep(30);1833		}1834		hp_amp_power(component, 0);1835		break;1836 1837	default:1838		return 0;1839	}1840 1841	return 0;1842}1843 1844static int rt5645_spk_event(struct snd_soc_dapm_widget *w,1845	struct snd_kcontrol *kcontrol, int event)1846{1847	struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);1848 1849	switch (event) {1850	case SND_SOC_DAPM_POST_PMU:1851		rt5645_enable_hweq(component);1852		snd_soc_component_update_bits(component, RT5645_PWR_DIG1,1853			RT5645_PWR_CLS_D | RT5645_PWR_CLS_D_R |1854			RT5645_PWR_CLS_D_L,1855			RT5645_PWR_CLS_D | RT5645_PWR_CLS_D_R |1856			RT5645_PWR_CLS_D_L);1857		snd_soc_component_update_bits(component, RT5645_GEN_CTRL3,1858			RT5645_DET_CLK_MASK, RT5645_DET_CLK_MODE1);1859		break;1860 1861	case SND_SOC_DAPM_PRE_PMD:1862		snd_soc_component_update_bits(component, RT5645_GEN_CTRL3,1863			RT5645_DET_CLK_MASK, RT5645_DET_CLK_DIS);1864		snd_soc_component_write(component, RT5645_EQ_CTRL2, 0);1865		snd_soc_component_update_bits(component, RT5645_PWR_DIG1,1866			RT5645_PWR_CLS_D | RT5645_PWR_CLS_D_R |1867			RT5645_PWR_CLS_D_L, 0);1868		break;1869 1870	default:1871		return 0;1872	}1873 1874	return 0;1875}1876 1877static int rt5645_lout_event(struct snd_soc_dapm_widget *w,1878	struct snd_kcontrol *kcontrol, int event)1879{1880	struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);1881 1882	switch (event) {1883	case SND_SOC_DAPM_POST_PMU:1884		hp_amp_power(component, 1);1885		snd_soc_component_update_bits(component, RT5645_PWR_ANLG1,1886			RT5645_PWR_LM, RT5645_PWR_LM);1887		snd_soc_component_update_bits(component, RT5645_LOUT1,1888			RT5645_L_MUTE | RT5645_R_MUTE, 0);1889		break;1890 1891	case SND_SOC_DAPM_PRE_PMD:1892		snd_soc_component_update_bits(component, RT5645_LOUT1,1893			RT5645_L_MUTE | RT5645_R_MUTE,1894			RT5645_L_MUTE | RT5645_R_MUTE);1895		snd_soc_component_update_bits(component, RT5645_PWR_ANLG1,1896			RT5645_PWR_LM, 0);1897		hp_amp_power(component, 0);1898		break;1899 1900	default:1901		return 0;1902	}1903 1904	return 0;1905}1906 1907static int rt5645_bst2_event(struct snd_soc_dapm_widget *w,1908	struct snd_kcontrol *kcontrol, int event)1909{1910	struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);1911 1912	switch (event) {1913	case SND_SOC_DAPM_POST_PMU:1914		snd_soc_component_update_bits(component, RT5645_PWR_ANLG2,1915			RT5645_PWR_BST2_P, RT5645_PWR_BST2_P);1916		break;1917 1918	case SND_SOC_DAPM_PRE_PMD:1919		snd_soc_component_update_bits(component, RT5645_PWR_ANLG2,1920			RT5645_PWR_BST2_P, 0);1921		break;1922 1923	default:1924		return 0;1925	}1926 1927	return 0;1928}1929 1930static int rt5645_set_micbias1_event(struct snd_soc_dapm_widget *w,1931		struct snd_kcontrol *k, int  event)1932{1933	struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);1934 1935	switch (event) {1936	case SND_SOC_DAPM_PRE_PMU:1937		snd_soc_component_update_bits(component, RT5645_GEN_CTRL2,1938			RT5645_MICBIAS1_POW_CTRL_SEL_MASK,1939			RT5645_MICBIAS1_POW_CTRL_SEL_M);1940		break;1941 1942	case SND_SOC_DAPM_POST_PMD:1943		snd_soc_component_update_bits(component, RT5645_GEN_CTRL2,1944			RT5645_MICBIAS1_POW_CTRL_SEL_MASK,1945			RT5645_MICBIAS1_POW_CTRL_SEL_A);1946		break;1947 1948	default:1949		return 0;1950	}1951 1952	return 0;1953}1954 1955static int rt5645_set_micbias2_event(struct snd_soc_dapm_widget *w,1956		struct snd_kcontrol *k, int  event)1957{1958	struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);1959 1960	switch (event) {1961	case SND_SOC_DAPM_PRE_PMU:1962		snd_soc_component_update_bits(component, RT5645_GEN_CTRL2,1963			RT5645_MICBIAS2_POW_CTRL_SEL_MASK,1964			RT5645_MICBIAS2_POW_CTRL_SEL_M);1965		break;1966 1967	case SND_SOC_DAPM_POST_PMD:1968		snd_soc_component_update_bits(component, RT5645_GEN_CTRL2,1969			RT5645_MICBIAS2_POW_CTRL_SEL_MASK,1970			RT5645_MICBIAS2_POW_CTRL_SEL_A);1971		break;1972 1973	default:1974		return 0;1975	}1976 1977	return 0;1978}1979 1980static const struct snd_soc_dapm_widget rt5645_dapm_widgets[] = {1981	SND_SOC_DAPM_SUPPLY("LDO2", RT5645_PWR_MIXER,1982		RT5645_PWR_LDO2_BIT, 0, NULL, 0),1983	SND_SOC_DAPM_SUPPLY("PLL1", RT5645_PWR_ANLG2,1984		RT5645_PWR_PLL_BIT, 0, NULL, 0),1985 1986	SND_SOC_DAPM_SUPPLY("JD Power", RT5645_PWR_ANLG2,1987		RT5645_PWR_JD1_BIT, 0, NULL, 0),1988	SND_SOC_DAPM_SUPPLY("Mic Det Power", RT5645_PWR_VOL,1989		RT5645_PWR_MIC_DET_BIT, 0, NULL, 0),1990 1991	/* ASRC */1992	SND_SOC_DAPM_SUPPLY_S("I2S1 ASRC", 1, RT5645_ASRC_1,1993			      11, 0, NULL, 0),1994	SND_SOC_DAPM_SUPPLY_S("I2S2 ASRC", 1, RT5645_ASRC_1,1995			      12, 0, NULL, 0),1996	SND_SOC_DAPM_SUPPLY_S("DAC STO ASRC", 1, RT5645_ASRC_1,1997			      10, 0, NULL, 0),1998	SND_SOC_DAPM_SUPPLY_S("DAC MONO L ASRC", 1, RT5645_ASRC_1,1999			      9, 0, NULL, 0),2000	SND_SOC_DAPM_SUPPLY_S("DAC MONO R ASRC", 1, RT5645_ASRC_1,2001			      8, 0, NULL, 0),2002	SND_SOC_DAPM_SUPPLY_S("DMIC STO1 ASRC", 1, RT5645_ASRC_1,2003			      7, 0, NULL, 0),2004	SND_SOC_DAPM_SUPPLY_S("DMIC MONO L ASRC", 1, RT5645_ASRC_1,2005			      5, 0, NULL, 0),2006	SND_SOC_DAPM_SUPPLY_S("DMIC MONO R ASRC", 1, RT5645_ASRC_1,2007			      4, 0, NULL, 0),2008	SND_SOC_DAPM_SUPPLY_S("ADC STO1 ASRC", 1, RT5645_ASRC_1,2009			      3, 0, NULL, 0),2010	SND_SOC_DAPM_SUPPLY_S("ADC MONO L ASRC", 1, RT5645_ASRC_1,2011			      1, 0, NULL, 0),2012	SND_SOC_DAPM_SUPPLY_S("ADC MONO R ASRC", 1, RT5645_ASRC_1,2013			      0, 0, NULL, 0),2014 2015	/* Input Side */2016	/* micbias */2017	SND_SOC_DAPM_SUPPLY("micbias1", RT5645_PWR_ANLG2,2018			RT5645_PWR_MB1_BIT, 0, rt5645_set_micbias1_event,2019			SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),2020	SND_SOC_DAPM_SUPPLY("micbias2", RT5645_PWR_ANLG2,2021			RT5645_PWR_MB2_BIT, 0, rt5645_set_micbias2_event,2022			SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),2023	/* Input Lines */2024	SND_SOC_DAPM_INPUT("DMIC L1"),2025	SND_SOC_DAPM_INPUT("DMIC R1"),2026	SND_SOC_DAPM_INPUT("DMIC L2"),2027	SND_SOC_DAPM_INPUT("DMIC R2"),2028 2029	SND_SOC_DAPM_INPUT("IN1P"),2030	SND_SOC_DAPM_INPUT("IN1N"),2031	SND_SOC_DAPM_INPUT("IN2P"),2032	SND_SOC_DAPM_INPUT("IN2N"),2033 2034	SND_SOC_DAPM_INPUT("Haptic Generator"),2035 2036	SND_SOC_DAPM_PGA("DMIC1", SND_SOC_NOPM, 0, 0, NULL, 0),2037	SND_SOC_DAPM_PGA("DMIC2", SND_SOC_NOPM, 0, 0, NULL, 0),2038	SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0,2039		set_dmic_clk, SND_SOC_DAPM_PRE_PMU),2040	SND_SOC_DAPM_SUPPLY("DMIC1 Power", RT5645_DMIC_CTRL1,2041		RT5645_DMIC_1_EN_SFT, 0, NULL, 0),2042	SND_SOC_DAPM_SUPPLY("DMIC2 Power", RT5645_DMIC_CTRL1,2043		RT5645_DMIC_2_EN_SFT, 0, NULL, 0),2044	/* Boost */2045	SND_SOC_DAPM_PGA("BST1", RT5645_PWR_ANLG2,2046		RT5645_PWR_BST1_BIT, 0, NULL, 0),2047	SND_SOC_DAPM_PGA_E("BST2", RT5645_PWR_ANLG2,2048		RT5645_PWR_BST2_BIT, 0, NULL, 0, rt5645_bst2_event,2049		SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),2050	/* Input Volume */2051	SND_SOC_DAPM_PGA("INL VOL", RT5645_PWR_VOL,2052		RT5645_PWR_IN_L_BIT, 0, NULL, 0),2053	SND_SOC_DAPM_PGA("INR VOL", RT5645_PWR_VOL,2054		RT5645_PWR_IN_R_BIT, 0, NULL, 0),2055	/* REC Mixer */2056	SND_SOC_DAPM_MIXER("RECMIXL", RT5645_PWR_MIXER, RT5645_PWR_RM_L_BIT,2057			0, rt5645_rec_l_mix, ARRAY_SIZE(rt5645_rec_l_mix)),2058	SND_SOC_DAPM_MIXER("RECMIXR", RT5645_PWR_MIXER, RT5645_PWR_RM_R_BIT,2059			0, rt5645_rec_r_mix, ARRAY_SIZE(rt5645_rec_r_mix)),2060	/* ADCs */2061	SND_SOC_DAPM_ADC("ADC L", NULL, SND_SOC_NOPM, 0, 0),2062	SND_SOC_DAPM_ADC("ADC R", NULL, SND_SOC_NOPM, 0, 0),2063 2064	SND_SOC_DAPM_SUPPLY("ADC L power", RT5645_PWR_DIG1,2065		RT5645_PWR_ADC_L_BIT, 0, NULL, 0),2066	SND_SOC_DAPM_SUPPLY("ADC R power", RT5645_PWR_DIG1,2067		RT5645_PWR_ADC_R_BIT, 0, NULL, 0),2068 2069	/* ADC Mux */2070	SND_SOC_DAPM_MUX("Stereo1 DMIC Mux", SND_SOC_NOPM, 0, 0,2071		&rt5645_sto1_dmic_mux),2072	SND_SOC_DAPM_MUX("Stereo1 ADC L2 Mux", SND_SOC_NOPM, 0, 0,2073		&rt5645_sto_adc2_mux),2074	SND_SOC_DAPM_MUX("Stereo1 ADC R2 Mux", SND_SOC_NOPM, 0, 0,2075		&rt5645_sto_adc2_mux),2076	SND_SOC_DAPM_MUX("Stereo1 ADC L1 Mux", SND_SOC_NOPM, 0, 0,2077		&rt5645_sto_adc1_mux),2078	SND_SOC_DAPM_MUX("Stereo1 ADC R1 Mux", SND_SOC_NOPM, 0, 0,2079		&rt5645_sto_adc1_mux),2080	SND_SOC_DAPM_MUX("Mono DMIC L Mux", SND_SOC_NOPM, 0, 0,2081		&rt5645_mono_dmic_l_mux),2082	SND_SOC_DAPM_MUX("Mono DMIC R Mux", SND_SOC_NOPM, 0, 0,2083		&rt5645_mono_dmic_r_mux),2084	SND_SOC_DAPM_MUX("Mono ADC L2 Mux", SND_SOC_NOPM, 0, 0,2085		&rt5645_mono_adc_l2_mux),2086	SND_SOC_DAPM_MUX("Mono ADC L1 Mux", SND_SOC_NOPM, 0, 0,2087		&rt5645_mono_adc_l1_mux),2088	SND_SOC_DAPM_MUX("Mono ADC R1 Mux", SND_SOC_NOPM, 0, 0,2089		&rt5645_mono_adc_r1_mux),2090	SND_SOC_DAPM_MUX("Mono ADC R2 Mux", SND_SOC_NOPM, 0, 0,2091		&rt5645_mono_adc_r2_mux),2092	/* ADC Mixer */2093 2094	SND_SOC_DAPM_SUPPLY_S("adc stereo1 filter", 1, RT5645_PWR_DIG2,2095		RT5645_PWR_ADC_S1F_BIT, 0, NULL, 0),2096	SND_SOC_DAPM_MIXER_E("Sto1 ADC MIXL", SND_SOC_NOPM, 0, 0,2097		rt5645_sto1_adc_l_mix, ARRAY_SIZE(rt5645_sto1_adc_l_mix),2098		NULL, 0),2099	SND_SOC_DAPM_MIXER_E("Sto1 ADC MIXR", SND_SOC_NOPM, 0, 0,2100		rt5645_sto1_adc_r_mix, ARRAY_SIZE(rt5645_sto1_adc_r_mix),2101		NULL, 0),2102	SND_SOC_DAPM_SUPPLY_S("adc mono left filter", 1, RT5645_PWR_DIG2,2103		RT5645_PWR_ADC_MF_L_BIT, 0, NULL, 0),2104	SND_SOC_DAPM_MIXER_E("Mono ADC MIXL", SND_SOC_NOPM, 0, 0,2105		rt5645_mono_adc_l_mix, ARRAY_SIZE(rt5645_mono_adc_l_mix),2106		NULL, 0),2107	SND_SOC_DAPM_SUPPLY_S("adc mono right filter", 1, RT5645_PWR_DIG2,2108		RT5645_PWR_ADC_MF_R_BIT, 0, NULL, 0),2109	SND_SOC_DAPM_MIXER_E("Mono ADC MIXR", SND_SOC_NOPM, 0, 0,2110		rt5645_mono_adc_r_mix, ARRAY_SIZE(rt5645_mono_adc_r_mix),2111		NULL, 0),2112 2113	/* ADC PGA */2114	SND_SOC_DAPM_PGA("Stereo1 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),2115	SND_SOC_DAPM_PGA("Stereo1 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),2116	SND_SOC_DAPM_PGA("Sto2 ADC LR MIX", SND_SOC_NOPM, 0, 0, NULL, 0),2117	SND_SOC_DAPM_PGA("VAD_ADC", SND_SOC_NOPM, 0, 0, NULL, 0),2118	SND_SOC_DAPM_PGA("IF_ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),2119	SND_SOC_DAPM_PGA("IF_ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),2120	SND_SOC_DAPM_PGA("IF1_ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),2121	SND_SOC_DAPM_PGA("IF1_ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),2122	SND_SOC_DAPM_PGA("IF1_ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),2123	SND_SOC_DAPM_PGA("IF1_ADC4", SND_SOC_NOPM, 0, 0, NULL, 0),2124 2125	/* IF1 2 Mux */2126	SND_SOC_DAPM_MUX("IF2 ADC Mux", SND_SOC_NOPM,2127		0, 0, &rt5645_if2_adc_in_mux),2128 2129	/* Digital Interface */2130	SND_SOC_DAPM_SUPPLY("I2S1", RT5645_PWR_DIG1,2131		RT5645_PWR_I2S1_BIT, 0, NULL, 0),2132	SND_SOC_DAPM_PGA("IF1 DAC0", SND_SOC_NOPM, 0, 0, NULL, 0),2133	SND_SOC_DAPM_PGA("IF1 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),2134	SND_SOC_DAPM_PGA("IF1 DAC2", SND_SOC_NOPM, 0, 0, NULL, 0),2135	SND_SOC_DAPM_PGA("IF1 DAC3", SND_SOC_NOPM, 0, 0, NULL, 0),2136	SND_SOC_DAPM_PGA("IF1 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),2137	SND_SOC_DAPM_PGA("IF1 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0),2138	SND_SOC_DAPM_PGA("IF1 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0),2139	SND_SOC_DAPM_SUPPLY("I2S2", RT5645_PWR_DIG1,2140		RT5645_PWR_I2S2_BIT, 0, NULL, 0),2141	SND_SOC_DAPM_PGA("IF2 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),2142	SND_SOC_DAPM_PGA("IF2 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),2143	SND_SOC_DAPM_PGA("IF2 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),2144	SND_SOC_DAPM_PGA("IF2 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),2145 2146	/* Digital Interface Select */2147	SND_SOC_DAPM_MUX("VAD ADC Mux", SND_SOC_NOPM,2148		0, 0, &rt5645_vad_adc_mux),2149 2150	/* Audio Interface */2151	SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),2152	SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),2153	SND_SOC_DAPM_AIF_IN("AIF2RX", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),2154	SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),2155 2156	/* Output Side */2157	/* DAC mixer before sound effect  */2158	SND_SOC_DAPM_MIXER("DAC1 MIXL", SND_SOC_NOPM, 0, 0,2159		rt5645_dac_l_mix, ARRAY_SIZE(rt5645_dac_l_mix)),2160	SND_SOC_DAPM_MIXER("DAC1 MIXR", SND_SOC_NOPM, 0, 0,2161		rt5645_dac_r_mix, ARRAY_SIZE(rt5645_dac_r_mix)),2162 2163	/* DAC2 channel Mux */2164	SND_SOC_DAPM_MUX("DAC L2 Mux", SND_SOC_NOPM, 0, 0, &rt5645_dac_l2_mux),2165	SND_SOC_DAPM_MUX("DAC R2 Mux", SND_SOC_NOPM, 0, 0, &rt5645_dac_r2_mux),2166	SND_SOC_DAPM_PGA("DAC L2 Volume", RT5645_PWR_DIG1,2167		RT5645_PWR_DAC_L2_BIT, 0, NULL, 0),2168	SND_SOC_DAPM_PGA("DAC R2 Volume", RT5645_PWR_DIG1,2169		RT5645_PWR_DAC_R2_BIT, 0, NULL, 0),2170 2171	SND_SOC_DAPM_MUX("DAC1 L Mux", SND_SOC_NOPM, 0, 0, &rt5645_dac1l_mux),2172	SND_SOC_DAPM_MUX("DAC1 R Mux", SND_SOC_NOPM, 0, 0, &rt5645_dac1r_mux),2173 2174	/* DAC Mixer */2175	SND_SOC_DAPM_SUPPLY_S("dac stereo1 filter", 1, RT5645_PWR_DIG2,2176		RT5645_PWR_DAC_S1F_BIT, 0, NULL, 0),2177	SND_SOC_DAPM_SUPPLY_S("dac mono left filter", 1, RT5645_PWR_DIG2,2178		RT5645_PWR_DAC_MF_L_BIT, 0, NULL, 0),2179	SND_SOC_DAPM_SUPPLY_S("dac mono right filter", 1, RT5645_PWR_DIG2,2180		RT5645_PWR_DAC_MF_R_BIT, 0, NULL, 0),2181	SND_SOC_DAPM_MIXER("Stereo DAC MIXL", SND_SOC_NOPM, 0, 0,2182		rt5645_sto_dac_l_mix, ARRAY_SIZE(rt5645_sto_dac_l_mix)),2183	SND_SOC_DAPM_MIXER("Stereo DAC MIXR", SND_SOC_NOPM, 0, 0,2184		rt5645_sto_dac_r_mix, ARRAY_SIZE(rt5645_sto_dac_r_mix)),2185	SND_SOC_DAPM_MIXER("Mono DAC MIXL", SND_SOC_NOPM, 0, 0,2186		rt5645_mono_dac_l_mix, ARRAY_SIZE(rt5645_mono_dac_l_mix)),2187	SND_SOC_DAPM_MIXER("Mono DAC MIXR", SND_SOC_NOPM, 0, 0,2188		rt5645_mono_dac_r_mix, ARRAY_SIZE(rt5645_mono_dac_r_mix)),2189	SND_SOC_DAPM_MIXER("DAC MIXL", SND_SOC_NOPM, 0, 0,2190		rt5645_dig_l_mix, ARRAY_SIZE(rt5645_dig_l_mix)),2191	SND_SOC_DAPM_MIXER("DAC MIXR", SND_SOC_NOPM, 0, 0,2192		rt5645_dig_r_mix, ARRAY_SIZE(rt5645_dig_r_mix)),2193 2194	/* DACs */2195	SND_SOC_DAPM_DAC("DAC L1", NULL, RT5645_PWR_DIG1, RT5645_PWR_DAC_L1_BIT,2196		0),2197	SND_SOC_DAPM_DAC("DAC L2", NULL, RT5645_PWR_DIG1, RT5645_PWR_DAC_L2_BIT,2198		0),2199	SND_SOC_DAPM_DAC("DAC R1", NULL, RT5645_PWR_DIG1, RT5645_PWR_DAC_R1_BIT,2200		0),2201	SND_SOC_DAPM_DAC("DAC R2", NULL, RT5645_PWR_DIG1, RT5645_PWR_DAC_R2_BIT,2202		0),2203	/* OUT Mixer */2204	SND_SOC_DAPM_MIXER("SPK MIXL", RT5645_PWR_MIXER, RT5645_PWR_SM_L_BIT,2205		0, rt5645_spk_l_mix, ARRAY_SIZE(rt5645_spk_l_mix)),2206	SND_SOC_DAPM_MIXER("SPK MIXR", RT5645_PWR_MIXER, RT5645_PWR_SM_R_BIT,2207		0, rt5645_spk_r_mix, ARRAY_SIZE(rt5645_spk_r_mix)),2208	SND_SOC_DAPM_MIXER("OUT MIXL", RT5645_PWR_MIXER, RT5645_PWR_OM_L_BIT,2209		0, rt5645_out_l_mix, ARRAY_SIZE(rt5645_out_l_mix)),2210	SND_SOC_DAPM_MIXER("OUT MIXR", RT5645_PWR_MIXER, RT5645_PWR_OM_R_BIT,2211		0, rt5645_out_r_mix, ARRAY_SIZE(rt5645_out_r_mix)),2212	/* Ouput Volume */2213	SND_SOC_DAPM_SWITCH("SPKVOL L", RT5645_PWR_VOL, RT5645_PWR_SV_L_BIT, 0,2214		&spk_l_vol_control),2215	SND_SOC_DAPM_SWITCH("SPKVOL R", RT5645_PWR_VOL, RT5645_PWR_SV_R_BIT, 0,2216		&spk_r_vol_control),2217	SND_SOC_DAPM_MIXER("HPOVOL MIXL", RT5645_PWR_VOL, RT5645_PWR_HV_L_BIT,2218		0, rt5645_hpvoll_mix, ARRAY_SIZE(rt5645_hpvoll_mix)),2219	SND_SOC_DAPM_MIXER("HPOVOL MIXR", RT5645_PWR_VOL, RT5645_PWR_HV_R_BIT,2220		0, rt5645_hpvolr_mix, ARRAY_SIZE(rt5645_hpvolr_mix)),2221	SND_SOC_DAPM_SUPPLY("HPOVOL MIXL Power", RT5645_PWR_MIXER,2222		RT5645_PWR_HM_L_BIT, 0, NULL, 0),2223	SND_SOC_DAPM_SUPPLY("HPOVOL MIXR Power", RT5645_PWR_MIXER,2224		RT5645_PWR_HM_R_BIT, 0, NULL, 0),2225	SND_SOC_DAPM_PGA("DAC 1", SND_SOC_NOPM, 0, 0, NULL, 0),2226	SND_SOC_DAPM_PGA("DAC 2", SND_SOC_NOPM, 0, 0, NULL, 0),2227	SND_SOC_DAPM_PGA("HPOVOL", SND_SOC_NOPM, 0, 0, NULL, 0),2228	SND_SOC_DAPM_SWITCH("HPOVOL L", SND_SOC_NOPM, 0, 0, &hp_l_vol_control),2229	SND_SOC_DAPM_SWITCH("HPOVOL R", SND_SOC_NOPM, 0, 0, &hp_r_vol_control),2230 2231	/* HPO/LOUT/Mono Mixer */2232	SND_SOC_DAPM_MIXER("SPOL MIX", SND_SOC_NOPM, 0, 0, rt5645_spo_l_mix,2233		ARRAY_SIZE(rt5645_spo_l_mix)),2234	SND_SOC_DAPM_MIXER("SPOR MIX", SND_SOC_NOPM, 0, 0, rt5645_spo_r_mix,2235		ARRAY_SIZE(rt5645_spo_r_mix)),2236	SND_SOC_DAPM_MIXER("HPO MIX", SND_SOC_NOPM, 0, 0, rt5645_hpo_mix,2237		ARRAY_SIZE(rt5645_hpo_mix)),2238	SND_SOC_DAPM_MIXER("LOUT MIX", SND_SOC_NOPM, 0, 0, rt5645_lout_mix,2239		ARRAY_SIZE(rt5645_lout_mix)),2240 2241	SND_SOC_DAPM_PGA_S("HP amp", 1, SND_SOC_NOPM, 0, 0, rt5645_hp_event,2242		SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),2243	SND_SOC_DAPM_PGA_S("LOUT amp", 1, SND_SOC_NOPM, 0, 0, rt5645_lout_event,2244		SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),2245	SND_SOC_DAPM_PGA_S("SPK amp", 2, SND_SOC_NOPM, 0, 0, rt5645_spk_event,2246		SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),2247 2248	/* PDM */2249	SND_SOC_DAPM_SUPPLY("PDM1 Power", RT5645_PWR_DIG2, RT5645_PWR_PDM1_BIT,2250		0, NULL, 0),2251	SND_SOC_DAPM_MUX("PDM1 L Mux", SND_SOC_NOPM, 0, 0, &rt5645_pdm1_l_mux),2252	SND_SOC_DAPM_MUX("PDM1 R Mux", SND_SOC_NOPM, 0, 0, &rt5645_pdm1_r_mux),2253 2254	SND_SOC_DAPM_SWITCH("PDM1 L", SND_SOC_NOPM, 0, 0, &pdm1_l_vol_control),2255	SND_SOC_DAPM_SWITCH("PDM1 R", SND_SOC_NOPM, 0, 0, &pdm1_r_vol_control),2256 2257	/* Output Lines */2258	SND_SOC_DAPM_OUTPUT("HPOL"),2259	SND_SOC_DAPM_OUTPUT("HPOR"),2260	SND_SOC_DAPM_OUTPUT("LOUTL"),2261	SND_SOC_DAPM_OUTPUT("LOUTR"),2262	SND_SOC_DAPM_OUTPUT("PDM1L"),2263	SND_SOC_DAPM_OUTPUT("PDM1R"),2264	SND_SOC_DAPM_OUTPUT("SPOL"),2265	SND_SOC_DAPM_OUTPUT("SPOR"),2266};2267 2268static const struct snd_soc_dapm_widget rt5645_specific_dapm_widgets[] = {2269	SND_SOC_DAPM_MUX("RT5645 IF1 DAC1 L Mux", SND_SOC_NOPM, 0, 0,2270		&rt5645_if1_dac0_tdm_sel_mux),2271	SND_SOC_DAPM_MUX("RT5645 IF1 DAC1 R Mux", SND_SOC_NOPM, 0, 0,2272		&rt5645_if1_dac1_tdm_sel_mux),2273	SND_SOC_DAPM_MUX("RT5645 IF1 DAC2 L Mux", SND_SOC_NOPM, 0, 0,2274		&rt5645_if1_dac2_tdm_sel_mux),2275	SND_SOC_DAPM_MUX("RT5645 IF1 DAC2 R Mux", SND_SOC_NOPM, 0, 0,2276		&rt5645_if1_dac3_tdm_sel_mux),2277	SND_SOC_DAPM_MUX("RT5645 IF1 ADC Mux", SND_SOC_NOPM,2278		0, 0, &rt5645_if1_adc_in_mux),2279	SND_SOC_DAPM_MUX("RT5645 IF1 ADC1 Swap Mux", SND_SOC_NOPM,2280		0, 0, &rt5645_if1_adc1_in_mux),2281	SND_SOC_DAPM_MUX("RT5645 IF1 ADC2 Swap Mux", SND_SOC_NOPM,2282		0, 0, &rt5645_if1_adc2_in_mux),2283	SND_SOC_DAPM_MUX("RT5645 IF1 ADC3 Swap Mux", SND_SOC_NOPM,2284		0, 0, &rt5645_if1_adc3_in_mux),2285};2286 2287static const struct snd_soc_dapm_widget rt5650_specific_dapm_widgets[] = {2288	SND_SOC_DAPM_MUX("A DAC1 L Mux", SND_SOC_NOPM,2289		0, 0, &rt5650_a_dac1_l_mux),2290	SND_SOC_DAPM_MUX("A DAC1 R Mux", SND_SOC_NOPM,2291		0, 0, &rt5650_a_dac1_r_mux),2292	SND_SOC_DAPM_MUX("A DAC2 L Mux", SND_SOC_NOPM,2293		0, 0, &rt5650_a_dac2_l_mux),2294	SND_SOC_DAPM_MUX("A DAC2 R Mux", SND_SOC_NOPM,2295		0, 0, &rt5650_a_dac2_r_mux),2296 2297	SND_SOC_DAPM_MUX("RT5650 IF1 ADC1 Swap Mux", SND_SOC_NOPM,2298		0, 0, &rt5650_if1_adc1_in_mux),2299	SND_SOC_DAPM_MUX("RT5650 IF1 ADC2 Swap Mux", SND_SOC_NOPM,2300		0, 0, &rt5650_if1_adc2_in_mux),2301	SND_SOC_DAPM_MUX("RT5650 IF1 ADC3 Swap Mux", SND_SOC_NOPM,2302		0, 0, &rt5650_if1_adc3_in_mux),2303	SND_SOC_DAPM_MUX("RT5650 IF1 ADC Mux", SND_SOC_NOPM,2304		0, 0, &rt5650_if1_adc_in_mux),2305 2306	SND_SOC_DAPM_MUX("RT5650 IF1 DAC1 L Mux", SND_SOC_NOPM, 0, 0,2307		&rt5650_if1_dac0_tdm_sel_mux),2308	SND_SOC_DAPM_MUX("RT5650 IF1 DAC1 R Mux", SND_SOC_NOPM, 0, 0,2309		&rt5650_if1_dac1_tdm_sel_mux),2310	SND_SOC_DAPM_MUX("RT5650 IF1 DAC2 L Mux", SND_SOC_NOPM, 0, 0,2311		&rt5650_if1_dac2_tdm_sel_mux),2312	SND_SOC_DAPM_MUX("RT5650 IF1 DAC2 R Mux", SND_SOC_NOPM, 0, 0,2313		&rt5650_if1_dac3_tdm_sel_mux),2314};2315 2316static const struct snd_soc_dapm_route rt5645_dapm_routes[] = {2317	{ "adc stereo1 filter", NULL, "ADC STO1 ASRC", is_using_asrc },2318	{ "adc mono left filter", NULL, "ADC MONO L ASRC", is_using_asrc },2319	{ "adc mono right filter", NULL, "ADC MONO R ASRC", is_using_asrc },2320	{ "dac mono left filter", NULL, "DAC MONO L ASRC", is_using_asrc },2321	{ "dac mono right filter", NULL, "DAC MONO R ASRC", is_using_asrc },2322	{ "dac stereo1 filter", NULL, "DAC STO ASRC", is_using_asrc },2323 2324	{ "I2S1", NULL, "I2S1 ASRC" },2325	{ "I2S2", NULL, "I2S2 ASRC" },2326 2327	{ "IN1P", NULL, "LDO2" },2328	{ "IN2P", NULL, "LDO2" },2329 2330	{ "DMIC1", NULL, "DMIC L1" },2331	{ "DMIC1", NULL, "DMIC R1" },2332	{ "DMIC2", NULL, "DMIC L2" },2333	{ "DMIC2", NULL, "DMIC R2" },2334 2335	{ "BST1", NULL, "IN1P" },2336	{ "BST1", NULL, "IN1N" },2337	{ "BST1", NULL, "JD Power" },2338	{ "BST1", NULL, "Mic Det Power" },2339	{ "BST2", NULL, "IN2P" },2340	{ "BST2", NULL, "IN2N" },2341 2342	{ "INL VOL", NULL, "IN2P" },2343	{ "INR VOL", NULL, "IN2N" },2344 2345	{ "RECMIXL", "HPOL Switch", "HPOL" },2346	{ "RECMIXL", "INL Switch", "INL VOL" },2347	{ "RECMIXL", "BST2 Switch", "BST2" },2348	{ "RECMIXL", "BST1 Switch", "BST1" },2349	{ "RECMIXL", "OUT MIXL Switch", "OUT MIXL" },2350 2351	{ "RECMIXR", "HPOR Switch", "HPOR" },2352	{ "RECMIXR", "INR Switch", "INR VOL" },2353	{ "RECMIXR", "BST2 Switch", "BST2" },2354	{ "RECMIXR", "BST1 Switch", "BST1" },2355	{ "RECMIXR", "OUT MIXR Switch", "OUT MIXR" },2356 2357	{ "ADC L", NULL, "RECMIXL" },2358	{ "ADC L", NULL, "ADC L power" },2359	{ "ADC R", NULL, "RECMIXR" },2360	{ "ADC R", NULL, "ADC R power" },2361 2362	{"DMIC L1", NULL, "DMIC CLK"},2363	{"DMIC L1", NULL, "DMIC1 Power"},2364	{"DMIC R1", NULL, "DMIC CLK"},2365	{"DMIC R1", NULL, "DMIC1 Power"},2366	{"DMIC L2", NULL, "DMIC CLK"},2367	{"DMIC L2", NULL, "DMIC2 Power"},2368	{"DMIC R2", NULL, "DMIC CLK"},2369	{"DMIC R2", NULL, "DMIC2 Power"},2370 2371	{ "Stereo1 DMIC Mux", "DMIC1", "DMIC1" },2372	{ "Stereo1 DMIC Mux", "DMIC2", "DMIC2" },2373	{ "Stereo1 DMIC Mux", NULL, "DMIC STO1 ASRC" },2374 2375	{ "Mono DMIC L Mux", "DMIC1", "DMIC L1" },2376	{ "Mono DMIC L Mux", "DMIC2", "DMIC L2" },2377	{ "Mono DMIC L Mux", NULL, "DMIC MONO L ASRC" },2378 2379	{ "Mono DMIC R Mux", "DMIC1", "DMIC R1" },2380	{ "Mono DMIC R Mux", "DMIC2", "DMIC R2" },2381	{ "Mono DMIC R Mux", NULL, "DMIC MONO R ASRC" },2382 2383	{ "Stereo1 ADC L2 Mux", "DMIC", "Stereo1 DMIC Mux" },2384	{ "Stereo1 ADC L2 Mux", "DAC MIX", "DAC MIXL" },2385	{ "Stereo1 ADC L1 Mux", "ADC", "ADC L" },2386	{ "Stereo1 ADC L1 Mux", "DAC MIX", "DAC MIXL" },2387 2388	{ "Stereo1 ADC R1 Mux", "ADC", "ADC R" },2389	{ "Stereo1 ADC R1 Mux", "DAC MIX", "DAC MIXR" },2390	{ "Stereo1 ADC R2 Mux", "DMIC", "Stereo1 DMIC Mux" },2391	{ "Stereo1 ADC R2 Mux", "DAC MIX", "DAC MIXR" },2392 2393	{ "Mono ADC L2 Mux", "DMIC", "Mono DMIC L Mux" },2394	{ "Mono ADC L2 Mux", "Mono DAC MIXL", "Mono DAC MIXL" },2395	{ "Mono ADC L1 Mux", "Mono DAC MIXL", "Mono DAC MIXL" },2396	{ "Mono ADC L1 Mux", "ADC", "ADC L" },2397 2398	{ "Mono ADC R1 Mux", "Mono DAC MIXR", "Mono DAC MIXR" },2399	{ "Mono ADC R1 Mux", "ADC", "ADC R" },2400	{ "Mono ADC R2 Mux", "DMIC", "Mono DMIC R Mux" },2401	{ "Mono ADC R2 Mux", "Mono DAC MIXR", "Mono DAC MIXR" },2402 2403	{ "Sto1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC L1 Mux" },2404	{ "Sto1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC L2 Mux" },2405	{ "Sto1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC R1 Mux" },2406	{ "Sto1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC R2 Mux" },2407 2408	{ "Stereo1 ADC MIXL", NULL, "Sto1 ADC MIXL" },2409	{ "Stereo1 ADC MIXL", NULL, "adc stereo1 filter" },2410	{ "adc stereo1 filter", NULL, "PLL1", is_sys_clk_from_pll },2411 2412	{ "Stereo1 ADC MIXR", NULL, "Sto1 ADC MIXR" },2413	{ "Stereo1 ADC MIXR", NULL, "adc stereo1 filter" },2414	{ "adc stereo1 filter", NULL, "PLL1", is_sys_clk_from_pll },2415 2416	{ "Mono ADC MIXL", "ADC1 Switch", "Mono ADC L1 Mux" },2417	{ "Mono ADC MIXL", "ADC2 Switch", "Mono ADC L2 Mux" },2418	{ "Mono ADC MIXL", NULL, "adc mono left filter" },2419	{ "adc mono left filter", NULL, "PLL1", is_sys_clk_from_pll },2420 2421	{ "Mono ADC MIXR", "ADC1 Switch", "Mono ADC R1 Mux" },2422	{ "Mono ADC MIXR", "ADC2 Switch", "Mono ADC R2 Mux" },2423	{ "Mono ADC MIXR", NULL, "adc mono right filter" },2424	{ "adc mono right filter", NULL, "PLL1", is_sys_clk_from_pll },2425 2426	{ "VAD ADC Mux", "Sto1 ADC L", "Stereo1 ADC MIXL" },2427	{ "VAD ADC Mux", "Mono ADC L", "Mono ADC MIXL" },2428	{ "VAD ADC Mux", "Mono ADC R", "Mono ADC MIXR" },2429 2430	{ "IF_ADC1", NULL, "Stereo1 ADC MIXL" },2431	{ "IF_ADC1", NULL, "Stereo1 ADC MIXR" },2432	{ "IF_ADC2", NULL, "Mono ADC MIXL" },2433	{ "IF_ADC2", NULL, "Mono ADC MIXR" },2434	{ "VAD_ADC", NULL, "VAD ADC Mux" },2435 2436	{ "IF2 ADC Mux", "IF_ADC1", "IF_ADC1" },2437	{ "IF2 ADC Mux", "IF_ADC2", "IF_ADC2" },2438	{ "IF2 ADC Mux", "VAD_ADC", "VAD_ADC" },2439 2440	{ "IF1 ADC", NULL, "I2S1" },2441	{ "IF2 ADC", NULL, "I2S2" },2442	{ "IF2 ADC", NULL, "IF2 ADC Mux" },2443 2444	{ "AIF2TX", NULL, "IF2 ADC" },2445 2446	{ "IF1 DAC0", NULL, "AIF1RX" },2447	{ "IF1 DAC1", NULL, "AIF1RX" },2448	{ "IF1 DAC2", NULL, "AIF1RX" },2449	{ "IF1 DAC3", NULL, "AIF1RX" },2450	{ "IF2 DAC", NULL, "AIF2RX" },2451 2452	{ "IF1 DAC0", NULL, "I2S1" },2453	{ "IF1 DAC1", NULL, "I2S1" },2454	{ "IF1 DAC2", NULL, "I2S1" },2455	{ "IF1 DAC3", NULL, "I2S1" },2456	{ "IF2 DAC", NULL, "I2S2" },2457 2458	{ "IF2 DAC L", NULL, "IF2 DAC" },2459	{ "IF2 DAC R", NULL, "IF2 DAC" },2460 2461	{ "DAC1 L Mux", "IF2 DAC", "IF2 DAC L" },2462	{ "DAC1 R Mux", "IF2 DAC", "IF2 DAC R" },2463 2464	{ "DAC1 MIXL", "Stereo ADC Switch", "Stereo1 ADC MIXL" },2465	{ "DAC1 MIXL", "DAC1 Switch", "DAC1 L Mux" },2466	{ "DAC1 MIXL", NULL, "dac stereo1 filter" },2467	{ "DAC1 MIXR", "Stereo ADC Switch", "Stereo1 ADC MIXR" },2468	{ "DAC1 MIXR", "DAC1 Switch", "DAC1 R Mux" },2469	{ "DAC1 MIXR", NULL, "dac stereo1 filter" },2470 2471	{ "DAC L2 Mux", "IF2 DAC", "IF2 DAC L" },2472	{ "DAC L2 Mux", "Mono ADC", "Mono ADC MIXL" },2473	{ "DAC L2 Mux", "VAD_ADC", "VAD_ADC" },2474	{ "DAC L2 Volume", NULL, "DAC L2 Mux" },2475	{ "DAC L2 Volume", NULL, "dac mono left filter" },2476 2477	{ "DAC R2 Mux", "IF2 DAC", "IF2 DAC R" },2478	{ "DAC R2 Mux", "Mono ADC", "Mono ADC MIXR" },2479	{ "DAC R2 Mux", "Haptic", "Haptic Generator" },2480	{ "DAC R2 Volume", NULL, "DAC R2 Mux" },2481	{ "DAC R2 Volume", NULL, "dac mono right filter" },2482 2483	{ "Stereo DAC MIXL", "DAC L1 Switch", "DAC1 MIXL" },2484	{ "Stereo DAC MIXL", "DAC R1 Switch", "DAC1 MIXR" },2485	{ "Stereo DAC MIXL", "DAC L2 Switch", "DAC L2 Volume" },2486	{ "Stereo DAC MIXL", NULL, "dac stereo1 filter" },2487	{ "Stereo DAC MIXR", "DAC R1 Switch", "DAC1 MIXR" },2488	{ "Stereo DAC MIXR", "DAC L1 Switch", "DAC1 MIXL" },2489	{ "Stereo DAC MIXR", "DAC R2 Switch", "DAC R2 Volume" },2490	{ "Stereo DAC MIXR", NULL, "dac stereo1 filter" },2491 2492	{ "Mono DAC MIXL", "DAC L1 Switch", "DAC1 MIXL" },2493	{ "Mono DAC MIXL", "DAC L2 Switch", "DAC L2 Volume" },2494	{ "Mono DAC MIXL", "DAC R2 Switch", "DAC R2 Volume" },2495	{ "Mono DAC MIXL", NULL, "dac mono left filter" },2496	{ "Mono DAC MIXR", "DAC R1 Switch", "DAC1 MIXR" },2497	{ "Mono DAC MIXR", "DAC R2 Switch", "DAC R2 Volume" },2498	{ "Mono DAC MIXR", "DAC L2 Switch", "DAC L2 Volume" },2499	{ "Mono DAC MIXR", NULL, "dac mono right filter" },2500 2501	{ "DAC MIXL", "Sto DAC Mix L Switch", "Stereo DAC MIXL" },2502	{ "DAC MIXL", "DAC L2 Switch", "DAC L2 Volume" },2503	{ "DAC MIXL", "DAC R2 Switch", "DAC R2 Volume" },2504	{ "DAC MIXR", "Sto DAC Mix R Switch", "Stereo DAC MIXR" },2505	{ "DAC MIXR", "DAC R2 Switch", "DAC R2 Volume" },2506	{ "DAC MIXR", "DAC L2 Switch", "DAC L2 Volume" },2507 2508	{ "DAC L1", NULL, "PLL1", is_sys_clk_from_pll },2509	{ "DAC R1", NULL, "PLL1", is_sys_clk_from_pll },2510	{ "DAC L2", NULL, "PLL1", is_sys_clk_from_pll },2511	{ "DAC R2", NULL, "PLL1", is_sys_clk_from_pll },2512 2513	{ "SPK MIXL", "BST1 Switch", "BST1" },2514	{ "SPK MIXL", "INL Switch", "INL VOL" },2515	{ "SPK MIXL", "DAC L1 Switch", "DAC L1" },2516	{ "SPK MIXL", "DAC L2 Switch", "DAC L2" },2517	{ "SPK MIXR", "BST2 Switch", "BST2" },2518	{ "SPK MIXR", "INR Switch", "INR VOL" },2519	{ "SPK MIXR", "DAC R1 Switch", "DAC R1" },2520	{ "SPK MIXR", "DAC R2 Switch", "DAC R2" },2521 2522	{ "OUT MIXL", "BST1 Switch", "BST1" },2523	{ "OUT MIXL", "INL Switch", "INL VOL" },2524	{ "OUT MIXL", "DAC L2 Switch", "DAC L2" },2525	{ "OUT MIXL", "DAC L1 Switch", "DAC L1" },2526 2527	{ "OUT MIXR", "BST2 Switch", "BST2" },2528	{ "OUT MIXR", "INR Switch", "INR VOL" },2529	{ "OUT MIXR", "DAC R2 Switch", "DAC R2" },2530	{ "OUT MIXR", "DAC R1 Switch", "DAC R1" },2531 2532	{ "HPOVOL MIXL", "DAC1 Switch", "DAC L1" },2533	{ "HPOVOL MIXL", "DAC2 Switch", "DAC L2" },2534	{ "HPOVOL MIXL", "INL Switch", "INL VOL" },2535	{ "HPOVOL MIXL", "BST1 Switch", "BST1" },2536	{ "HPOVOL MIXL", NULL, "HPOVOL MIXL Power" },2537	{ "HPOVOL MIXR", "DAC1 Switch", "DAC R1" },2538	{ "HPOVOL MIXR", "DAC2 Switch", "DAC R2" },2539	{ "HPOVOL MIXR", "INR Switch", "INR VOL" },2540	{ "HPOVOL MIXR", "BST2 Switch", "BST2" },2541	{ "HPOVOL MIXR", NULL, "HPOVOL MIXR Power" },2542 2543	{ "DAC 2", NULL, "DAC L2" },2544	{ "DAC 2", NULL, "DAC R2" },2545	{ "DAC 1", NULL, "DAC L1" },2546	{ "DAC 1", NULL, "DAC R1" },2547	{ "HPOVOL L", "Switch", "HPOVOL MIXL" },2548	{ "HPOVOL R", "Switch", "HPOVOL MIXR" },2549	{ "HPOVOL", NULL, "HPOVOL L" },2550	{ "HPOVOL", NULL, "HPOVOL R" },2551	{ "HPO MIX", "DAC1 Switch", "DAC 1" },2552	{ "HPO MIX", "HPVOL Switch", "HPOVOL" },2553 2554	{ "SPKVOL L", "Switch", "SPK MIXL" },2555	{ "SPKVOL R", "Switch", "SPK MIXR" },2556 2557	{ "SPOL MIX", "DAC L1 Switch", "DAC L1" },2558	{ "SPOL MIX", "SPKVOL L Switch", "SPKVOL L" },2559	{ "SPOR MIX", "DAC R1 Switch", "DAC R1" },2560	{ "SPOR MIX", "SPKVOL R Switch", "SPKVOL R" },2561 2562	{ "LOUT MIX", "DAC L1 Switch", "DAC L1" },2563	{ "LOUT MIX", "DAC R1 Switch", "DAC R1" },2564	{ "LOUT MIX", "OUTMIX L Switch", "OUT MIXL" },2565	{ "LOUT MIX", "OUTMIX R Switch", "OUT MIXR" },2566 2567	{ "PDM1 L Mux", "Stereo DAC", "Stereo DAC MIXL" },2568	{ "PDM1 L Mux", "Mono DAC", "Mono DAC MIXL" },2569	{ "PDM1 L Mux", NULL, "PDM1 Power" },2570	{ "PDM1 R Mux", "Stereo DAC", "Stereo DAC MIXR" },2571	{ "PDM1 R Mux", "Mono DAC", "Mono DAC MIXR" },2572	{ "PDM1 R Mux", NULL, "PDM1 Power" },2573 2574	{ "HP amp", NULL, "HPO MIX" },2575	{ "HP amp", NULL, "JD Power" },2576	{ "HP amp", NULL, "Mic Det Power" },2577	{ "HP amp", NULL, "LDO2" },2578	{ "HPOL", NULL, "HP amp" },2579	{ "HPOR", NULL, "HP amp" },2580 2581	{ "LOUT amp", NULL, "LOUT MIX" },2582	{ "LOUTL", NULL, "LOUT amp" },2583	{ "LOUTR", NULL, "LOUT amp" },2584 2585	{ "PDM1 L", "Switch", "PDM1 L Mux" },2586	{ "PDM1 R", "Switch", "PDM1 R Mux" },2587 2588	{ "PDM1L", NULL, "PDM1 L" },2589	{ "PDM1R", NULL, "PDM1 R" },2590 2591	{ "SPK amp", NULL, "SPOL MIX" },2592	{ "SPK amp", NULL, "SPOR MIX" },2593	{ "SPOL", NULL, "SPK amp" },2594	{ "SPOR", NULL, "SPK amp" },2595};2596 2597static const struct snd_soc_dapm_route rt5650_specific_dapm_routes[] = {2598	{ "A DAC1 L Mux", "DAC1",  "DAC1 MIXL"},2599	{ "A DAC1 L Mux", "Stereo DAC Mixer", "Stereo DAC MIXL"},2600	{ "A DAC1 R Mux", "DAC1",  "DAC1 MIXR"},2601	{ "A DAC1 R Mux", "Stereo DAC Mixer", "Stereo DAC MIXR"},2602 2603	{ "A DAC2 L Mux", "Stereo DAC Mixer", "Stereo DAC MIXL"},2604	{ "A DAC2 L Mux", "Mono DAC Mixer", "Mono DAC MIXL"},2605	{ "A DAC2 R Mux", "Stereo DAC Mixer", "Stereo DAC MIXR"},2606	{ "A DAC2 R Mux", "Mono DAC Mixer", "Mono DAC MIXR"},2607 2608	{ "DAC L1", NULL, "A DAC1 L Mux" },2609	{ "DAC R1", NULL, "A DAC1 R Mux" },2610	{ "DAC L2", NULL, "A DAC2 L Mux" },2611	{ "DAC R2", NULL, "A DAC2 R Mux" },2612 2613	{ "RT5650 IF1 ADC1 Swap Mux", "L/R", "IF_ADC1" },2614	{ "RT5650 IF1 ADC1 Swap Mux", "R/L", "IF_ADC1" },2615	{ "RT5650 IF1 ADC1 Swap Mux", "L/L", "IF_ADC1" },2616	{ "RT5650 IF1 ADC1 Swap Mux", "R/R", "IF_ADC1" },2617 2618	{ "RT5650 IF1 ADC2 Swap Mux", "L/R", "IF_ADC2" },2619	{ "RT5650 IF1 ADC2 Swap Mux", "R/L", "IF_ADC2" },2620	{ "RT5650 IF1 ADC2 Swap Mux", "L/L", "IF_ADC2" },2621	{ "RT5650 IF1 ADC2 Swap Mux", "R/R", "IF_ADC2" },2622 2623	{ "RT5650 IF1 ADC3 Swap Mux", "L/R", "VAD_ADC" },2624	{ "RT5650 IF1 ADC3 Swap Mux", "R/L", "VAD_ADC" },2625	{ "RT5650 IF1 ADC3 Swap Mux", "L/L", "VAD_ADC" },2626	{ "RT5650 IF1 ADC3 Swap Mux", "R/R", "VAD_ADC" },2627 2628	{ "IF1 ADC", NULL, "RT5650 IF1 ADC1 Swap Mux" },2629	{ "IF1 ADC", NULL, "RT5650 IF1 ADC2 Swap Mux" },2630	{ "IF1 ADC", NULL, "RT5650 IF1 ADC3 Swap Mux" },2631 2632	{ "RT5650 IF1 ADC Mux", "IF_ADC1/IF_ADC2/DAC_REF/Null", "IF1 ADC" },2633	{ "RT5650 IF1 ADC Mux", "IF_ADC1/IF_ADC2/Null/DAC_REF", "IF1 ADC" },2634	{ "RT5650 IF1 ADC Mux", "IF_ADC1/DAC_REF/IF_ADC2/Null", "IF1 ADC" },2635	{ "RT5650 IF1 ADC Mux", "IF_ADC1/DAC_REF/Null/IF_ADC2", "IF1 ADC" },2636	{ "RT5650 IF1 ADC Mux", "IF_ADC1/Null/DAC_REF/IF_ADC2", "IF1 ADC" },2637	{ "RT5650 IF1 ADC Mux", "IF_ADC1/Null/IF_ADC2/DAC_REF", "IF1 ADC" },2638 2639	{ "RT5650 IF1 ADC Mux", "IF_ADC2/IF_ADC1/DAC_REF/Null", "IF1 ADC" },2640	{ "RT5650 IF1 ADC Mux", "IF_ADC2/IF_ADC1/Null/DAC_REF", "IF1 ADC" },2641	{ "RT5650 IF1 ADC Mux", "IF_ADC2/DAC_REF/IF_ADC1/Null", "IF1 ADC" },2642	{ "RT5650 IF1 ADC Mux", "IF_ADC2/DAC_REF/Null/IF_ADC1", "IF1 ADC" },2643	{ "RT5650 IF1 ADC Mux", "IF_ADC2/Null/DAC_REF/IF_ADC1", "IF1 ADC" },2644	{ "RT5650 IF1 ADC Mux", "IF_ADC2/Null/IF_ADC1/DAC_REF", "IF1 ADC" },2645 2646	{ "RT5650 IF1 ADC Mux", "DAC_REF/IF_ADC1/IF_ADC2/Null", "IF1 ADC" },2647	{ "RT5650 IF1 ADC Mux", "DAC_REF/IF_ADC1/Null/IF_ADC2", "IF1 ADC" },2648	{ "RT5650 IF1 ADC Mux", "DAC_REF/IF_ADC2/IF_ADC1/Null", "IF1 ADC" },2649	{ "RT5650 IF1 ADC Mux", "DAC_REF/IF_ADC2/Null/IF_ADC1", "IF1 ADC" },2650	{ "RT5650 IF1 ADC Mux", "DAC_REF/Null/IF_ADC1/IF_ADC2", "IF1 ADC" },2651	{ "RT5650 IF1 ADC Mux", "DAC_REF/Null/IF_ADC2/IF_ADC1", "IF1 ADC" },2652 2653	{ "RT5650 IF1 ADC Mux", "Null/IF_ADC1/IF_ADC2/DAC_REF", "IF1 ADC" },2654	{ "RT5650 IF1 ADC Mux", "Null/IF_ADC1/DAC_REF/IF_ADC2", "IF1 ADC" },2655	{ "RT5650 IF1 ADC Mux", "Null/IF_ADC2/IF_ADC1/DAC_REF", "IF1 ADC" },2656	{ "RT5650 IF1 ADC Mux", "Null/IF_ADC2/DAC_REF/IF_ADC1", "IF1 ADC" },2657	{ "RT5650 IF1 ADC Mux", "Null/DAC_REF/IF_ADC1/IF_ADC2", "IF1 ADC" },2658	{ "RT5650 IF1 ADC Mux", "Null/DAC_REF/IF_ADC2/IF_ADC1", "IF1 ADC" },2659	{ "AIF1TX", NULL, "RT5650 IF1 ADC Mux" },2660 2661	{ "RT5650 IF1 DAC1 L Mux", "Slot0", "IF1 DAC0" },2662	{ "RT5650 IF1 DAC1 L Mux", "Slot1", "IF1 DAC1" },2663	{ "RT5650 IF1 DAC1 L Mux", "Slot2", "IF1 DAC2" },2664	{ "RT5650 IF1 DAC1 L Mux", "Slot3", "IF1 DAC3" },2665 2666	{ "RT5650 IF1 DAC1 R Mux", "Slot0", "IF1 DAC0" },2667	{ "RT5650 IF1 DAC1 R Mux", "Slot1", "IF1 DAC1" },2668	{ "RT5650 IF1 DAC1 R Mux", "Slot2", "IF1 DAC2" },2669	{ "RT5650 IF1 DAC1 R Mux", "Slot3", "IF1 DAC3" },2670 2671	{ "RT5650 IF1 DAC2 L Mux", "Slot0", "IF1 DAC0" },2672	{ "RT5650 IF1 DAC2 L Mux", "Slot1", "IF1 DAC1" },2673	{ "RT5650 IF1 DAC2 L Mux", "Slot2", "IF1 DAC2" },2674	{ "RT5650 IF1 DAC2 L Mux", "Slot3", "IF1 DAC3" },2675 2676	{ "RT5650 IF1 DAC2 R Mux", "Slot0", "IF1 DAC0" },2677	{ "RT5650 IF1 DAC2 R Mux", "Slot1", "IF1 DAC1" },2678	{ "RT5650 IF1 DAC2 R Mux", "Slot2", "IF1 DAC2" },2679	{ "RT5650 IF1 DAC2 R Mux", "Slot3", "IF1 DAC3" },2680 2681	{ "DAC1 L Mux", "IF1 DAC", "RT5650 IF1 DAC1 L Mux" },2682	{ "DAC1 R Mux", "IF1 DAC", "RT5650 IF1 DAC1 R Mux" },2683 2684	{ "DAC L2 Mux", "IF1 DAC", "RT5650 IF1 DAC2 L Mux" },2685	{ "DAC R2 Mux", "IF1 DAC", "RT5650 IF1 DAC2 R Mux" },2686};2687 2688static const struct snd_soc_dapm_route rt5645_specific_dapm_routes[] = {2689	{ "DAC L1", NULL, "Stereo DAC MIXL" },2690	{ "DAC R1", NULL, "Stereo DAC MIXR" },2691	{ "DAC L2", NULL, "Mono DAC MIXL" },2692	{ "DAC R2", NULL, "Mono DAC MIXR" },2693 2694	{ "RT5645 IF1 ADC1 Swap Mux", "L/R", "IF_ADC1" },2695	{ "RT5645 IF1 ADC1 Swap Mux", "R/L", "IF_ADC1" },2696	{ "RT5645 IF1 ADC1 Swap Mux", "L/L", "IF_ADC1" },2697	{ "RT5645 IF1 ADC1 Swap Mux", "R/R", "IF_ADC1" },2698 2699	{ "RT5645 IF1 ADC2 Swap Mux", "L/R", "IF_ADC2" },2700	{ "RT5645 IF1 ADC2 Swap Mux", "R/L", "IF_ADC2" },2701	{ "RT5645 IF1 ADC2 Swap Mux", "L/L", "IF_ADC2" },2702	{ "RT5645 IF1 ADC2 Swap Mux", "R/R", "IF_ADC2" },2703 2704	{ "RT5645 IF1 ADC3 Swap Mux", "L/R", "VAD_ADC" },2705	{ "RT5645 IF1 ADC3 Swap Mux", "R/L", "VAD_ADC" },2706	{ "RT5645 IF1 ADC3 Swap Mux", "L/L", "VAD_ADC" },2707	{ "RT5645 IF1 ADC3 Swap Mux", "R/R", "VAD_ADC" },2708 2709	{ "IF1 ADC", NULL, "RT5645 IF1 ADC1 Swap Mux" },2710	{ "IF1 ADC", NULL, "RT5645 IF1 ADC2 Swap Mux" },2711	{ "IF1 ADC", NULL, "RT5645 IF1 ADC3 Swap Mux" },2712 2713	{ "RT5645 IF1 ADC Mux", "IF_ADC1/IF_ADC2/VAD_ADC", "IF1 ADC" },2714	{ "RT5645 IF1 ADC Mux", "IF_ADC2/IF_ADC1/VAD_ADC", "IF1 ADC" },2715	{ "RT5645 IF1 ADC Mux", "VAD_ADC/IF_ADC1/IF_ADC2", "IF1 ADC" },2716	{ "RT5645 IF1 ADC Mux", "VAD_ADC/IF_ADC2/IF_ADC1", "IF1 ADC" },2717	{ "AIF1TX", NULL, "RT5645 IF1 ADC Mux" },2718 2719	{ "RT5645 IF1 DAC1 L Mux", "Slot0", "IF1 DAC0" },2720	{ "RT5645 IF1 DAC1 L Mux", "Slot1", "IF1 DAC1" },2721	{ "RT5645 IF1 DAC1 L Mux", "Slot2", "IF1 DAC2" },2722	{ "RT5645 IF1 DAC1 L Mux", "Slot3", "IF1 DAC3" },2723 2724	{ "RT5645 IF1 DAC1 R Mux", "Slot0", "IF1 DAC0" },2725	{ "RT5645 IF1 DAC1 R Mux", "Slot1", "IF1 DAC1" },2726	{ "RT5645 IF1 DAC1 R Mux", "Slot2", "IF1 DAC2" },2727	{ "RT5645 IF1 DAC1 R Mux", "Slot3", "IF1 DAC3" },2728 2729	{ "RT5645 IF1 DAC2 L Mux", "Slot0", "IF1 DAC0" },2730	{ "RT5645 IF1 DAC2 L Mux", "Slot1", "IF1 DAC1" },2731	{ "RT5645 IF1 DAC2 L Mux", "Slot2", "IF1 DAC2" },2732	{ "RT5645 IF1 DAC2 L Mux", "Slot3", "IF1 DAC3" },2733 2734	{ "RT5645 IF1 DAC2 R Mux", "Slot0", "IF1 DAC0" },2735	{ "RT5645 IF1 DAC2 R Mux", "Slot1", "IF1 DAC1" },2736	{ "RT5645 IF1 DAC2 R Mux", "Slot2", "IF1 DAC2" },2737	{ "RT5645 IF1 DAC2 R Mux", "Slot3", "IF1 DAC3" },2738 2739	{ "DAC1 L Mux", "IF1 DAC", "RT5645 IF1 DAC1 L Mux" },2740	{ "DAC1 R Mux", "IF1 DAC", "RT5645 IF1 DAC1 R Mux" },2741 2742	{ "DAC L2 Mux", "IF1 DAC", "RT5645 IF1 DAC2 L Mux" },2743	{ "DAC R2 Mux", "IF1 DAC", "RT5645 IF1 DAC2 R Mux" },2744};2745 2746static const struct snd_soc_dapm_route rt5645_old_dapm_routes[] = {2747	{ "SPOL MIX", "DAC R1 Switch", "DAC R1" },2748	{ "SPOL MIX", "SPKVOL R Switch", "SPKVOL R" },2749};2750 2751static int rt5645_hw_params(struct snd_pcm_substream *substream,2752	struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)2753{2754	struct snd_soc_component *component = dai->component;2755	struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);2756	unsigned int val_len = 0, val_clk, mask_clk, dl_sft;2757	int pre_div, bclk_ms, frame_size;2758 2759	rt5645->lrck[dai->id] = params_rate(params);2760	pre_div = rl6231_get_clk_info(rt5645->sysclk, rt5645->lrck[dai->id]);2761	if (pre_div < 0) {2762		dev_err(component->dev, "Unsupported clock setting\n");2763		return -EINVAL;2764	}2765	frame_size = snd_soc_params_to_frame_size(params);2766	if (frame_size < 0) {2767		dev_err(component->dev, "Unsupported frame size: %d\n", frame_size);2768		return -EINVAL;2769	}2770 2771	switch (rt5645->codec_type) {2772	case CODEC_TYPE_RT5650:2773		dl_sft = 4;2774		break;2775	default:2776		dl_sft = 2;2777		break;2778	}2779 2780	bclk_ms = frame_size > 32;2781	rt5645->bclk[dai->id] = rt5645->lrck[dai->id] * (32 << bclk_ms);2782 2783	dev_dbg(dai->dev, "bclk is %dHz and lrck is %dHz\n",2784		rt5645->bclk[dai->id], rt5645->lrck[dai->id]);2785	dev_dbg(dai->dev, "bclk_ms is %d and pre_div is %d for iis %d\n",2786				bclk_ms, pre_div, dai->id);2787 2788	switch (params_width(params)) {2789	case 16:2790		break;2791	case 20:2792		val_len = 0x1;2793		break;2794	case 24:2795		val_len = 0x2;2796		break;2797	case 8:2798		val_len = 0x3;2799		break;2800	default:2801		return -EINVAL;2802	}2803 2804	switch (dai->id) {2805	case RT5645_AIF1:2806		mask_clk = RT5645_I2S_PD1_MASK;2807		val_clk = pre_div << RT5645_I2S_PD1_SFT;2808		snd_soc_component_update_bits(component, RT5645_I2S1_SDP,2809			(0x3 << dl_sft), (val_len << dl_sft));2810		snd_soc_component_update_bits(component, RT5645_ADDA_CLK1, mask_clk, val_clk);2811		break;2812	case  RT5645_AIF2:2813		mask_clk = RT5645_I2S_BCLK_MS2_MASK | RT5645_I2S_PD2_MASK;2814		val_clk = bclk_ms << RT5645_I2S_BCLK_MS2_SFT |2815			pre_div << RT5645_I2S_PD2_SFT;2816		snd_soc_component_update_bits(component, RT5645_I2S2_SDP,2817			(0x3 << dl_sft), (val_len << dl_sft));2818		snd_soc_component_update_bits(component, RT5645_ADDA_CLK1, mask_clk, val_clk);2819		break;2820	default:2821		dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);2822		return -EINVAL;2823	}2824 2825	return 0;2826}2827 2828static int rt5645_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)2829{2830	struct snd_soc_component *component = dai->component;2831	struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);2832	unsigned int reg_val = 0, pol_sft;2833 2834	switch (rt5645->codec_type) {2835	case CODEC_TYPE_RT5650:2836		pol_sft = 8;2837		break;2838	default:2839		pol_sft = 7;2840		break;2841	}2842 2843	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {2844	case SND_SOC_DAIFMT_CBM_CFM:2845		rt5645->master[dai->id] = 1;2846		break;2847	case SND_SOC_DAIFMT_CBS_CFS:2848		reg_val |= RT5645_I2S_MS_S;2849		rt5645->master[dai->id] = 0;2850		break;2851	default:2852		return -EINVAL;2853	}2854 2855	switch (fmt & SND_SOC_DAIFMT_INV_MASK) {2856	case SND_SOC_DAIFMT_NB_NF:2857		break;2858	case SND_SOC_DAIFMT_IB_NF:2859		reg_val |= (1 << pol_sft);2860		break;2861	default:2862		return -EINVAL;2863	}2864 2865	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {2866	case SND_SOC_DAIFMT_I2S:2867		break;2868	case SND_SOC_DAIFMT_LEFT_J:2869		reg_val |= RT5645_I2S_DF_LEFT;2870		break;2871	case SND_SOC_DAIFMT_DSP_A:2872		reg_val |= RT5645_I2S_DF_PCM_A;2873		break;2874	case SND_SOC_DAIFMT_DSP_B:2875		reg_val |= RT5645_I2S_DF_PCM_B;2876		break;2877	default:2878		return -EINVAL;2879	}2880	switch (dai->id) {2881	case RT5645_AIF1:2882		snd_soc_component_update_bits(component, RT5645_I2S1_SDP,2883			RT5645_I2S_MS_MASK | (1 << pol_sft) |2884			RT5645_I2S_DF_MASK, reg_val);2885		break;2886	case RT5645_AIF2:2887		snd_soc_component_update_bits(component, RT5645_I2S2_SDP,2888			RT5645_I2S_MS_MASK | (1 << pol_sft) |2889			RT5645_I2S_DF_MASK, reg_val);2890		break;2891	default:2892		dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);2893		return -EINVAL;2894	}2895	return 0;2896}2897 2898static int rt5645_set_dai_sysclk(struct snd_soc_dai *dai,2899		int clk_id, unsigned int freq, int dir)2900{2901	struct snd_soc_component *component = dai->component;2902	struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);2903	unsigned int reg_val = 0;2904 2905	if (freq == rt5645->sysclk && clk_id == rt5645->sysclk_src)2906		return 0;2907 2908	switch (clk_id) {2909	case RT5645_SCLK_S_MCLK:2910		reg_val |= RT5645_SCLK_SRC_MCLK;2911		break;2912	case RT5645_SCLK_S_PLL1:2913		reg_val |= RT5645_SCLK_SRC_PLL1;2914		break;2915	case RT5645_SCLK_S_RCCLK:2916		reg_val |= RT5645_SCLK_SRC_RCCLK;2917		break;2918	default:2919		dev_err(component->dev, "Invalid clock id (%d)\n", clk_id);2920		return -EINVAL;2921	}2922	snd_soc_component_update_bits(component, RT5645_GLB_CLK,2923		RT5645_SCLK_SRC_MASK, reg_val);2924	rt5645->sysclk = freq;2925	rt5645->sysclk_src = clk_id;2926 2927	dev_dbg(dai->dev, "Sysclk is %dHz and clock id is %d\n", freq, clk_id);2928 2929	return 0;2930}2931 2932static int rt5645_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source,2933			unsigned int freq_in, unsigned int freq_out)2934{2935	struct snd_soc_component *component = dai->component;2936	struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);2937	struct rl6231_pll_code pll_code;2938	int ret;2939 2940	if (source == rt5645->pll_src && freq_in == rt5645->pll_in &&2941	    freq_out == rt5645->pll_out)2942		return 0;2943 2944	if (!freq_in || !freq_out) {2945		dev_dbg(component->dev, "PLL disabled\n");2946 2947		rt5645->pll_in = 0;2948		rt5645->pll_out = 0;2949		snd_soc_component_update_bits(component, RT5645_GLB_CLK,2950			RT5645_SCLK_SRC_MASK, RT5645_SCLK_SRC_MCLK);2951		return 0;2952	}2953 2954	switch (source) {2955	case RT5645_PLL1_S_MCLK:2956		snd_soc_component_update_bits(component, RT5645_GLB_CLK,2957			RT5645_PLL1_SRC_MASK, RT5645_PLL1_SRC_MCLK);2958		break;2959	case RT5645_PLL1_S_BCLK1:2960	case RT5645_PLL1_S_BCLK2:2961		switch (dai->id) {2962		case RT5645_AIF1:2963			snd_soc_component_update_bits(component, RT5645_GLB_CLK,2964				RT5645_PLL1_SRC_MASK, RT5645_PLL1_SRC_BCLK1);2965			break;2966		case  RT5645_AIF2:2967			snd_soc_component_update_bits(component, RT5645_GLB_CLK,2968				RT5645_PLL1_SRC_MASK, RT5645_PLL1_SRC_BCLK2);2969			break;2970		default:2971			dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);2972			return -EINVAL;2973		}2974		break;2975	default:2976		dev_err(component->dev, "Unknown PLL source %d\n", source);2977		return -EINVAL;2978	}2979 2980	ret = rl6231_pll_calc(freq_in, freq_out, &pll_code);2981	if (ret < 0) {2982		dev_err(component->dev, "Unsupported input clock %d\n", freq_in);2983		return ret;2984	}2985 2986	dev_dbg(component->dev, "bypass=%d m=%d n=%d k=%d\n",2987		pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),2988		pll_code.n_code, pll_code.k_code);2989 2990	snd_soc_component_write(component, RT5645_PLL_CTRL1,2991		pll_code.n_code << RT5645_PLL_N_SFT | pll_code.k_code);2992	snd_soc_component_write(component, RT5645_PLL_CTRL2,2993		((pll_code.m_bp ? 0 : pll_code.m_code) << RT5645_PLL_M_SFT) |2994		(pll_code.m_bp << RT5645_PLL_M_BP_SFT));2995 2996	rt5645->pll_in = freq_in;2997	rt5645->pll_out = freq_out;2998	rt5645->pll_src = source;2999 3000	return 0;3001}3002 3003static int rt5645_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,3004			unsigned int rx_mask, int slots, int slot_width)3005{3006	struct snd_soc_component *component = dai->component;3007	struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);3008	unsigned int i_slot_sft, o_slot_sft, i_width_sht, o_width_sht, en_sft;3009	unsigned int mask, val = 0;3010 3011	switch (rt5645->codec_type) {3012	case CODEC_TYPE_RT5650:3013		en_sft = 15;3014		i_slot_sft = 10;3015		o_slot_sft = 8;3016		i_width_sht = 6;3017		o_width_sht = 4;3018		mask = 0x8ff0;3019		break;3020	default:3021		en_sft = 14;3022		i_slot_sft = o_slot_sft = 12;3023		i_width_sht = o_width_sht = 10;3024		mask = 0x7c00;3025		break;3026	}3027	if (rx_mask || tx_mask) {3028		val |= (1 << en_sft);3029		if (rt5645->codec_type == CODEC_TYPE_RT5645)3030			snd_soc_component_update_bits(component, RT5645_BASS_BACK,3031				RT5645_G_BB_BST_MASK, RT5645_G_BB_BST_25DB);3032	}3033 3034	switch (slots) {3035	case 4:3036		val |= (1 << i_slot_sft) | (1 << o_slot_sft);3037		break;3038	case 6:3039		val |= (2 << i_slot_sft) | (2 << o_slot_sft);3040		break;3041	case 8:3042		val |= (3 << i_slot_sft) | (3 << o_slot_sft);3043		break;3044	case 2:3045	default:3046		break;3047	}3048 3049	switch (slot_width) {3050	case 20:3051		val |= (1 << i_width_sht) | (1 << o_width_sht);3052		break;3053	case 24:3054		val |= (2 << i_width_sht) | (2 << o_width_sht);3055		break;3056	case 32:3057		val |= (3 << i_width_sht) | (3 << o_width_sht);3058		break;3059	case 16:3060	default:3061		break;3062	}3063 3064	snd_soc_component_update_bits(component, RT5645_TDM_CTRL_1, mask, val);3065 3066	return 0;3067}3068 3069static int rt5645_set_bias_level(struct snd_soc_component *component,3070			enum snd_soc_bias_level level)3071{3072	struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);3073 3074	switch (level) {3075	case SND_SOC_BIAS_PREPARE:3076		if (SND_SOC_BIAS_STANDBY == snd_soc_component_get_bias_level(component)) {3077			snd_soc_component_update_bits(component, RT5645_PWR_ANLG1,3078				RT5645_PWR_VREF1 | RT5645_PWR_MB |3079				RT5645_PWR_BG | RT5645_PWR_VREF2,3080				RT5645_PWR_VREF1 | RT5645_PWR_MB |3081				RT5645_PWR_BG | RT5645_PWR_VREF2);3082			mdelay(10);3083			snd_soc_component_update_bits(component, RT5645_PWR_ANLG1,3084				RT5645_PWR_FV1 | RT5645_PWR_FV2,3085				RT5645_PWR_FV1 | RT5645_PWR_FV2);3086			snd_soc_component_update_bits(component, RT5645_GEN_CTRL1,3087				RT5645_DIG_GATE_CTRL, RT5645_DIG_GATE_CTRL);3088		}3089		break;3090 3091	case SND_SOC_BIAS_STANDBY:3092		snd_soc_component_update_bits(component, RT5645_PWR_ANLG1,3093			RT5645_PWR_VREF1 | RT5645_PWR_MB |3094			RT5645_PWR_BG | RT5645_PWR_VREF2,3095			RT5645_PWR_VREF1 | RT5645_PWR_MB |3096			RT5645_PWR_BG | RT5645_PWR_VREF2);3097		mdelay(10);3098		snd_soc_component_update_bits(component, RT5645_PWR_ANLG1,3099			RT5645_PWR_FV1 | RT5645_PWR_FV2,3100			RT5645_PWR_FV1 | RT5645_PWR_FV2);3101		if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {3102			snd_soc_component_write(component, RT5645_DEPOP_M2, 0x1140);3103			msleep(40);3104			if (rt5645->en_button_func)3105				queue_delayed_work(system_power_efficient_wq,3106					&rt5645->jack_detect_work,3107					msecs_to_jiffies(0));3108		}3109		break;3110 3111	case SND_SOC_BIAS_OFF:3112		snd_soc_component_write(component, RT5645_DEPOP_M2, 0x1100);3113		if (!rt5645->en_button_func)3114			snd_soc_component_update_bits(component, RT5645_GEN_CTRL1,3115					RT5645_DIG_GATE_CTRL, 0);3116		snd_soc_component_update_bits(component, RT5645_PWR_ANLG1,3117				RT5645_PWR_VREF1 | RT5645_PWR_MB |3118				RT5645_PWR_BG | RT5645_PWR_VREF2 |3119				RT5645_PWR_FV1 | RT5645_PWR_FV2, 0x0);3120		break;3121 3122	default:3123		break;3124	}3125 3126	return 0;3127}3128 3129static void rt5645_enable_push_button_irq(struct snd_soc_component *component,3130	bool enable)3131{3132	struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);3133	int ret;3134 3135	if (enable) {3136		snd_soc_dapm_force_enable_pin(dapm, "ADC L power");3137		snd_soc_dapm_force_enable_pin(dapm, "ADC R power");3138		snd_soc_dapm_sync(dapm);3139 3140		snd_soc_component_update_bits(component, RT5650_4BTN_IL_CMD2,3141			RT5645_EN_4BTN_IL_MASK | RT5645_RST_4BTN_IL_MASK,3142			RT5645_EN_4BTN_IL_EN | RT5645_RST_4BTN_IL_RST);3143		usleep_range(10000, 15000);3144		snd_soc_component_update_bits(component, RT5650_4BTN_IL_CMD2,3145			RT5645_EN_4BTN_IL_MASK | RT5645_RST_4BTN_IL_MASK,3146			RT5645_EN_4BTN_IL_EN | RT5645_RST_4BTN_IL_NORM);3147		msleep(50);3148		ret = snd_soc_component_read(component, RT5645_INT_IRQ_ST);3149		pr_debug("%s read %x = %x\n", __func__, RT5645_INT_IRQ_ST,3150			snd_soc_component_read(component, RT5645_INT_IRQ_ST));3151		snd_soc_component_write(component, RT5645_INT_IRQ_ST, ret);3152		ret = snd_soc_component_read(component, RT5650_4BTN_IL_CMD1);3153		pr_debug("%s read %x = %x\n", __func__, RT5650_4BTN_IL_CMD1,3154			snd_soc_component_read(component, RT5650_4BTN_IL_CMD1));3155		snd_soc_component_write(component, RT5650_4BTN_IL_CMD1, ret);3156		snd_soc_component_update_bits(component, RT5650_4BTN_IL_CMD1, 0x3, 0x3);3157		snd_soc_component_update_bits(component,3158					RT5645_INT_IRQ_ST, 0x8, 0x8);3159	} else {3160		snd_soc_component_update_bits(component, RT5650_4BTN_IL_CMD2, 0x8000, 0x0);3161		snd_soc_component_update_bits(component, RT5645_INT_IRQ_ST, 0x8, 0x0);3162 3163		snd_soc_dapm_disable_pin(dapm, "ADC L power");3164		snd_soc_dapm_disable_pin(dapm, "ADC R power");3165		snd_soc_dapm_sync(dapm);3166	}3167}3168 3169static int rt5645_jack_detect(struct snd_soc_component *component, int jack_insert)3170{3171	struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);3172	struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);3173	unsigned int val;3174 3175	if (jack_insert) {3176		regmap_write(rt5645->regmap, RT5645_CHARGE_PUMP, 0x0206);3177 3178		/* for jack type detect */3179		snd_soc_dapm_force_enable_pin(dapm, "LDO2");3180		snd_soc_dapm_force_enable_pin(dapm, "Mic Det Power");3181		snd_soc_dapm_sync(dapm);3182		if (!snd_soc_card_is_instantiated(dapm->card)) {3183			/* Power up necessary bits for JD if dapm is3184			   not ready yet */3185			regmap_update_bits(rt5645->regmap, RT5645_PWR_ANLG1,3186				RT5645_PWR_MB | RT5645_PWR_VREF2,3187				RT5645_PWR_MB | RT5645_PWR_VREF2);3188			regmap_update_bits(rt5645->regmap, RT5645_PWR_MIXER,3189				RT5645_PWR_LDO2, RT5645_PWR_LDO2);3190			regmap_update_bits(rt5645->regmap, RT5645_PWR_VOL,3191				RT5645_PWR_MIC_DET, RT5645_PWR_MIC_DET);3192		}3193 3194		regmap_write(rt5645->regmap, RT5645_JD_CTRL3, 0x00f0);3195		regmap_update_bits(rt5645->regmap, RT5645_IN1_CTRL2,3196			RT5645_CBJ_MN_JD, RT5645_CBJ_MN_JD);3197		regmap_update_bits(rt5645->regmap, RT5645_IN1_CTRL1,3198			RT5645_CBJ_BST1_EN, RT5645_CBJ_BST1_EN);3199		msleep(100);3200		regmap_update_bits(rt5645->regmap, RT5645_IN1_CTRL2,3201			RT5645_CBJ_MN_JD, 0);3202 3203		if (rt5645->gpiod_cbj_sleeve)3204			gpiod_set_value(rt5645->gpiod_cbj_sleeve, 1);3205 3206		msleep(600);3207		regmap_read(rt5645->regmap, RT5645_IN1_CTRL3, &val);3208		val &= 0x7;3209		dev_dbg(component->dev, "val = %d\n", val);3210 3211		if ((val == 1 || val == 2) && !rt5645->pdata.no_headset_mic) {3212			rt5645->jack_type = SND_JACK_HEADSET;3213			if (rt5645->en_button_func) {3214				rt5645_enable_push_button_irq(component, true);3215			}3216		} else {3217			if (rt5645->en_button_func)3218				rt5645_enable_push_button_irq(component, false);3219			snd_soc_dapm_disable_pin(dapm, "Mic Det Power");3220			snd_soc_dapm_sync(dapm);3221			rt5645->jack_type = SND_JACK_HEADPHONE;3222			if (rt5645->gpiod_cbj_sleeve)3223				gpiod_set_value(rt5645->gpiod_cbj_sleeve, 0);3224		}3225		if (rt5645->pdata.level_trigger_irq)3226			regmap_update_bits(rt5645->regmap, RT5645_IRQ_CTRL2,3227				RT5645_JD_1_1_MASK, RT5645_JD_1_1_NOR);3228 3229		regmap_write(rt5645->regmap, RT5645_CHARGE_PUMP, 0x0e06);3230	} else { /* jack out */3231		rt5645->jack_type = 0;3232 3233		regmap_update_bits(rt5645->regmap, RT5645_HP_VOL,3234			RT5645_L_MUTE | RT5645_R_MUTE,3235			RT5645_L_MUTE | RT5645_R_MUTE);3236		regmap_update_bits(rt5645->regmap, RT5645_IN1_CTRL2,3237			RT5645_CBJ_MN_JD, RT5645_CBJ_MN_JD);3238		regmap_update_bits(rt5645->regmap, RT5645_IN1_CTRL1,3239			RT5645_CBJ_BST1_EN, 0);3240 3241		if (rt5645->en_button_func)3242			rt5645_enable_push_button_irq(component, false);3243 3244		if (rt5645->pdata.jd_mode == 0)3245			snd_soc_dapm_disable_pin(dapm, "LDO2");3246		snd_soc_dapm_disable_pin(dapm, "Mic Det Power");3247		snd_soc_dapm_sync(dapm);3248		if (rt5645->pdata.level_trigger_irq)3249			regmap_update_bits(rt5645->regmap, RT5645_IRQ_CTRL2,3250				RT5645_JD_1_1_MASK, RT5645_JD_1_1_INV);3251 3252		if (rt5645->gpiod_cbj_sleeve)3253			gpiod_set_value(rt5645->gpiod_cbj_sleeve, 0);3254	}3255 3256	return rt5645->jack_type;3257}3258 3259static int rt5645_button_detect(struct snd_soc_component *component)3260{3261	int btn_type, val;3262 3263	val = snd_soc_component_read(component, RT5650_4BTN_IL_CMD1);3264	pr_debug("val=0x%x\n", val);3265	btn_type = val & 0xfff0;3266	snd_soc_component_write(component, RT5650_4BTN_IL_CMD1, val);3267 3268	return btn_type;3269}3270 3271static irqreturn_t rt5645_irq(int irq, void *data);3272 3273int rt5645_set_jack_detect(struct snd_soc_component *component,3274	struct snd_soc_jack *hp_jack, struct snd_soc_jack *mic_jack,3275	struct snd_soc_jack *btn_jack)3276{3277	struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);3278 3279	rt5645->hp_jack = hp_jack;3280	rt5645->mic_jack = mic_jack;3281	rt5645->btn_jack = btn_jack;3282	if (rt5645->btn_jack && rt5645->codec_type == CODEC_TYPE_RT5650) {3283		rt5645->en_button_func = true;3284		regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,3285				RT5645_GP1_PIN_IRQ, RT5645_GP1_PIN_IRQ);3286		regmap_update_bits(rt5645->regmap, RT5645_GEN_CTRL1,3287				RT5645_DIG_GATE_CTRL, RT5645_DIG_GATE_CTRL);3288		regmap_update_bits(rt5645->regmap, RT5645_DEPOP_M1,3289				RT5645_HP_CB_MASK, RT5645_HP_CB_PU);3290	}3291	rt5645_irq(0, rt5645);3292 3293	return 0;3294}3295EXPORT_SYMBOL_GPL(rt5645_set_jack_detect);3296 3297static int rt5645_component_set_jack(struct snd_soc_component *component,3298	struct snd_soc_jack *hs_jack, void *data)3299{3300	struct snd_soc_jack *mic_jack = NULL;3301	struct snd_soc_jack *btn_jack = NULL;3302	int type;3303 3304	if (hs_jack) {3305		type = *(int *)data;3306 3307		if (type & SND_JACK_MICROPHONE)3308			mic_jack = hs_jack;3309		if (type & (SND_JACK_BTN_0 | SND_JACK_BTN_1 |3310			SND_JACK_BTN_2 | SND_JACK_BTN_3))3311			btn_jack = hs_jack;3312	}3313 3314	return rt5645_set_jack_detect(component, hs_jack, mic_jack, btn_jack);3315}3316 3317static void rt5645_jack_detect_work(struct work_struct *work)3318{3319	struct rt5645_priv *rt5645 =3320		container_of(work, struct rt5645_priv, jack_detect_work.work);3321	int val, btn_type, gpio_state = 0, report = 0;3322 3323	if (!rt5645->component)3324		return;3325 3326	mutex_lock(&rt5645->jd_mutex);3327 3328	switch (rt5645->pdata.jd_mode) {3329	case 0: /* Not using rt5645 JD */3330		if (rt5645->gpiod_hp_det) {3331			gpio_state = gpiod_get_value(rt5645->gpiod_hp_det);3332			if (rt5645->pdata.inv_hp_pol)3333				gpio_state ^= 1;3334			dev_dbg(rt5645->component->dev, "gpio_state = %d\n",3335				gpio_state);3336			report = rt5645_jack_detect(rt5645->component, gpio_state);3337		}3338		snd_soc_jack_report(rt5645->hp_jack,3339				    report, SND_JACK_HEADPHONE);3340		snd_soc_jack_report(rt5645->mic_jack,3341				    report, SND_JACK_MICROPHONE);3342		mutex_unlock(&rt5645->jd_mutex);3343		return;3344	case 4:3345		val = snd_soc_component_read(rt5645->component, RT5645_A_JD_CTRL1) & 0x0020;3346		break;3347	default: /* read rt5645 jd1_1 status */3348		val = snd_soc_component_read(rt5645->component, RT5645_INT_IRQ_ST) & 0x1000;3349		break;3350 3351	}3352 3353	if (!val && (rt5645->jack_type == 0)) { /* jack in */3354		report = rt5645_jack_detect(rt5645->component, 1);3355	} else if (!val && rt5645->jack_type == SND_JACK_HEADSET) {3356		/* for push button and jack out */3357		btn_type = 0;3358		if (snd_soc_component_read(rt5645->component, RT5645_INT_IRQ_ST) & 0x4) {3359			/* button pressed */3360			report = SND_JACK_HEADSET;3361			btn_type = rt5645_button_detect(rt5645->component);3362			/* rt5650 can report three kinds of button behavior,3363			   one click, double click and hold. However,3364			   currently we will report button pressed/released3365			   event. So all the three button behaviors are3366			   treated as button pressed. */3367			switch (btn_type) {3368			case 0x8000:3369			case 0x4000:3370			case 0x2000:3371				report |= SND_JACK_BTN_0;3372				break;3373			case 0x1000:3374			case 0x0800:3375			case 0x0400:3376				report |= SND_JACK_BTN_1;3377				break;3378			case 0x0200:3379			case 0x0100:3380			case 0x0080:3381				report |= SND_JACK_BTN_2;3382				break;3383			case 0x0040:3384			case 0x0020:3385			case 0x0010:3386				report |= SND_JACK_BTN_3;3387				break;3388			case 0x0000: /* unpressed */3389				break;3390			default:3391				dev_err(rt5645->component->dev,3392					"Unexpected button code 0x%04x\n",3393					btn_type);3394				break;3395			}3396		}3397		if (btn_type == 0)/* button release */3398			report =  rt5645->jack_type;3399		else {3400			mod_timer(&rt5645->btn_check_timer,3401				msecs_to_jiffies(100));3402		}3403	} else {3404		/* jack out */3405		report = 0;3406		snd_soc_component_update_bits(rt5645->component,3407				    RT5645_INT_IRQ_ST, 0x1, 0x0);3408		rt5645_jack_detect(rt5645->component, 0);3409	}3410 3411	mutex_unlock(&rt5645->jd_mutex);3412 3413	snd_soc_jack_report(rt5645->hp_jack, report, SND_JACK_HEADPHONE);3414	snd_soc_jack_report(rt5645->mic_jack, report, SND_JACK_MICROPHONE);3415	if (rt5645->en_button_func)3416		snd_soc_jack_report(rt5645->btn_jack,3417			report, SND_JACK_BTN_0 | SND_JACK_BTN_1 |3418				SND_JACK_BTN_2 | SND_JACK_BTN_3);3419}3420 3421static void rt5645_rcclock_work(struct work_struct *work)3422{3423	struct rt5645_priv *rt5645 =3424		container_of(work, struct rt5645_priv, rcclock_work.work);3425 3426	regmap_update_bits(rt5645->regmap, RT5645_MICBIAS,3427		RT5645_PWR_CLK25M_MASK, RT5645_PWR_CLK25M_PD);3428}3429 3430static irqreturn_t rt5645_irq(int irq, void *data)3431{3432	struct rt5645_priv *rt5645 = data;3433 3434	queue_delayed_work(system_power_efficient_wq,3435			   &rt5645->jack_detect_work, msecs_to_jiffies(250));3436 3437	return IRQ_HANDLED;3438}3439 3440static void rt5645_btn_check_callback(struct timer_list *t)3441{3442	struct rt5645_priv *rt5645 = from_timer(rt5645, t, btn_check_timer);3443 3444	queue_delayed_work(system_power_efficient_wq,3445		   &rt5645->jack_detect_work, msecs_to_jiffies(5));3446}3447 3448static int rt5645_probe(struct snd_soc_component *component)3449{3450	struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);3451	struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);3452 3453	rt5645->component = component;3454 3455	switch (rt5645->codec_type) {3456	case CODEC_TYPE_RT5645:3457		snd_soc_dapm_new_controls(dapm,3458			rt5645_specific_dapm_widgets,3459			ARRAY_SIZE(rt5645_specific_dapm_widgets));3460		snd_soc_dapm_add_routes(dapm,3461			rt5645_specific_dapm_routes,3462			ARRAY_SIZE(rt5645_specific_dapm_routes));3463		if (rt5645->v_id < 3) {3464			snd_soc_dapm_add_routes(dapm,3465				rt5645_old_dapm_routes,3466				ARRAY_SIZE(rt5645_old_dapm_routes));3467		}3468		break;3469	case CODEC_TYPE_RT5650:3470		snd_soc_dapm_new_controls(dapm,3471			rt5650_specific_dapm_widgets,3472			ARRAY_SIZE(rt5650_specific_dapm_widgets));3473		snd_soc_dapm_add_routes(dapm,3474			rt5650_specific_dapm_routes,3475			ARRAY_SIZE(rt5650_specific_dapm_routes));3476		break;3477	}3478 3479	snd_soc_component_force_bias_level(component, SND_SOC_BIAS_OFF);3480 3481	/* for JD function */3482	if (rt5645->pdata.jd_mode) {3483		snd_soc_dapm_force_enable_pin(dapm, "JD Power");3484		snd_soc_dapm_force_enable_pin(dapm, "LDO2");3485		snd_soc_dapm_sync(dapm);3486	}3487 3488	if (rt5645->pdata.long_name)3489		component->card->long_name = rt5645->pdata.long_name;3490 3491	rt5645->eq_param = devm_kcalloc(component->dev,3492		RT5645_HWEQ_NUM, sizeof(struct rt5645_eq_param_s),3493		GFP_KERNEL);3494 3495	if (!rt5645->eq_param)3496		return -ENOMEM;3497 3498	return 0;3499}3500 3501static void rt5645_remove(struct snd_soc_component *component)3502{3503	rt5645_reset(component);3504}3505 3506#ifdef CONFIG_PM3507static int rt5645_suspend(struct snd_soc_component *component)3508{3509	struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);3510 3511	regcache_cache_only(rt5645->regmap, true);3512	regcache_mark_dirty(rt5645->regmap);3513 3514	return 0;3515}3516 3517static int rt5645_resume(struct snd_soc_component *component)3518{3519	struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);3520 3521	regcache_cache_only(rt5645->regmap, false);3522	regcache_sync(rt5645->regmap);3523 3524	return 0;3525}3526#else3527#define rt5645_suspend NULL3528#define rt5645_resume NULL3529#endif3530 3531#define RT5645_STEREO_RATES SNDRV_PCM_RATE_8000_960003532#define RT5645_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \3533			SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)3534 3535static const struct snd_soc_dai_ops rt5645_aif_dai_ops = {3536	.hw_params = rt5645_hw_params,3537	.set_fmt = rt5645_set_dai_fmt,3538	.set_sysclk = rt5645_set_dai_sysclk,3539	.set_tdm_slot = rt5645_set_tdm_slot,3540	.set_pll = rt5645_set_dai_pll,3541};3542 3543static struct snd_soc_dai_driver rt5645_dai[] = {3544	{3545		.name = "rt5645-aif1",3546		.id = RT5645_AIF1,3547		.playback = {3548			.stream_name = "AIF1 Playback",3549			.channels_min = 1,3550			.channels_max = 2,3551			.rates = RT5645_STEREO_RATES,3552			.formats = RT5645_FORMATS,3553		},3554		.capture = {3555			.stream_name = "AIF1 Capture",3556			.channels_min = 1,3557			.channels_max = 4,3558			.rates = RT5645_STEREO_RATES,3559			.formats = RT5645_FORMATS,3560		},3561		.ops = &rt5645_aif_dai_ops,3562	},3563	{3564		.name = "rt5645-aif2",3565		.id = RT5645_AIF2,3566		.playback = {3567			.stream_name = "AIF2 Playback",3568			.channels_min = 1,3569			.channels_max = 2,3570			.rates = RT5645_STEREO_RATES,3571			.formats = RT5645_FORMATS,3572		},3573		.capture = {3574			.stream_name = "AIF2 Capture",3575			.channels_min = 1,3576			.channels_max = 2,3577			.rates = RT5645_STEREO_RATES,3578			.formats = RT5645_FORMATS,3579		},3580		.ops = &rt5645_aif_dai_ops,3581	},3582};3583 3584static const struct snd_soc_component_driver soc_component_dev_rt5645 = {3585	.probe			= rt5645_probe,3586	.remove			= rt5645_remove,3587	.suspend		= rt5645_suspend,3588	.resume			= rt5645_resume,3589	.set_bias_level		= rt5645_set_bias_level,3590	.controls		= rt5645_snd_controls,3591	.num_controls		= ARRAY_SIZE(rt5645_snd_controls),3592	.dapm_widgets		= rt5645_dapm_widgets,3593	.num_dapm_widgets	= ARRAY_SIZE(rt5645_dapm_widgets),3594	.dapm_routes		= rt5645_dapm_routes,3595	.num_dapm_routes	= ARRAY_SIZE(rt5645_dapm_routes),3596	.set_jack		= rt5645_component_set_jack,3597	.use_pmdown_time	= 1,3598	.endianness		= 1,3599};3600 3601static const struct regmap_config rt5645_regmap = {3602	.reg_bits = 8,3603	.val_bits = 16,3604	.use_single_read = true,3605	.use_single_write = true,3606	.max_register = RT5645_VENDOR_ID2 + 1 + (ARRAY_SIZE(rt5645_ranges) *3607					       RT5645_PR_SPACING),3608	.volatile_reg = rt5645_volatile_register,3609	.readable_reg = rt5645_readable_register,3610 3611	.cache_type = REGCACHE_MAPLE,3612	.reg_defaults = rt5645_reg,3613	.num_reg_defaults = ARRAY_SIZE(rt5645_reg),3614	.ranges = rt5645_ranges,3615	.num_ranges = ARRAY_SIZE(rt5645_ranges),3616};3617 3618static const struct regmap_config rt5650_regmap = {3619	.reg_bits = 8,3620	.val_bits = 16,3621	.use_single_read = true,3622	.use_single_write = true,3623	.max_register = RT5645_VENDOR_ID2 + 1 + (ARRAY_SIZE(rt5645_ranges) *3624					       RT5645_PR_SPACING),3625	.volatile_reg = rt5645_volatile_register,3626	.readable_reg = rt5645_readable_register,3627 3628	.cache_type = REGCACHE_MAPLE,3629	.reg_defaults = rt5650_reg,3630	.num_reg_defaults = ARRAY_SIZE(rt5650_reg),3631	.ranges = rt5645_ranges,3632	.num_ranges = ARRAY_SIZE(rt5645_ranges),3633};3634 3635static const struct regmap_config temp_regmap = {3636	.name="nocache",3637	.reg_bits = 8,3638	.val_bits = 16,3639	.use_single_read = true,3640	.use_single_write = true,3641	.max_register = RT5645_VENDOR_ID2 + 1,3642	.cache_type = REGCACHE_NONE,3643};3644 3645static const struct i2c_device_id rt5645_i2c_id[] = {3646	{ "rt5645" },3647	{ "rt5650" },3648	{ }3649};3650MODULE_DEVICE_TABLE(i2c, rt5645_i2c_id);3651 3652#ifdef CONFIG_OF3653static const struct of_device_id rt5645_of_match[] = {3654	{ .compatible = "realtek,rt5645", },3655	{ .compatible = "realtek,rt5650", },3656	{ }3657};3658MODULE_DEVICE_TABLE(of, rt5645_of_match);3659#endif3660 3661#ifdef CONFIG_ACPI3662static const struct acpi_device_id rt5645_acpi_match[] = {3663	{ "10EC5645", 0 },3664	{ "10EC5648", 0 },3665	{ "10EC5650", 0 },3666	{ "10EC5640", 0 },3667	{ "10EC3270", 0 },3668	{},3669};3670MODULE_DEVICE_TABLE(acpi, rt5645_acpi_match);3671#endif3672 3673static const struct rt5645_platform_data intel_braswell_platform_data = {3674	.dmic1_data_pin = RT5645_DMIC1_DISABLE,3675	.dmic2_data_pin = RT5645_DMIC_DATA_IN2P,3676	.jd_mode = 3,3677};3678 3679static const struct rt5645_platform_data buddy_platform_data = {3680	.dmic1_data_pin = RT5645_DMIC_DATA_GPIO5,3681	.dmic2_data_pin = RT5645_DMIC_DATA_IN2P,3682	.jd_mode = 4,3683	.level_trigger_irq = true,3684};3685 3686static const struct rt5645_platform_data gpd_win_platform_data = {3687	.jd_mode = 3,3688	.inv_jd1_1 = true,3689	.mono_speaker = true,3690	.long_name = "gpd-win-pocket-rt5645",3691	/* The GPD pocket has a diff. mic, for the win this does not matter. */3692	.in2_diff = true,3693};3694 3695static const struct rt5645_platform_data asus_t100ha_platform_data = {3696	.dmic1_data_pin = RT5645_DMIC_DATA_IN2N,3697	.dmic2_data_pin = RT5645_DMIC2_DISABLE,3698	.jd_mode = 3,3699	.inv_jd1_1 = true,3700};3701 3702static const struct rt5645_platform_data asus_t101ha_platform_data = {3703	.dmic1_data_pin = RT5645_DMIC_DATA_IN2N,3704	.dmic2_data_pin = RT5645_DMIC2_DISABLE,3705	.jd_mode = 3,3706};3707 3708static const struct rt5645_platform_data lenovo_ideapad_miix_310_pdata = {3709	.jd_mode = 3,3710	.in2_diff = true,3711};3712 3713static const struct rt5645_platform_data jd_mode3_monospk_platform_data = {3714	.jd_mode = 3,3715	.mono_speaker = true,3716};3717 3718static const struct rt5645_platform_data jd_mode3_inv_data = {3719	.jd_mode = 3,3720	.inv_jd1_1 = true,3721};3722 3723static const struct rt5645_platform_data jd_mode3_platform_data = {3724	.jd_mode = 3,3725};3726 3727static const struct rt5645_platform_data lattepanda_board_platform_data = {3728	.jd_mode = 2,3729	.inv_jd1_1 = true3730};3731 3732static const struct rt5645_platform_data kahlee_platform_data = {3733	.dmic1_data_pin = RT5645_DMIC_DATA_GPIO5,3734	.dmic2_data_pin = RT5645_DMIC_DATA_IN2P,3735	.jd_mode = 3,3736};3737 3738static const struct rt5645_platform_data ecs_ef20_platform_data = {3739	.dmic1_data_pin = RT5645_DMIC1_DISABLE,3740	.dmic2_data_pin = RT5645_DMIC_DATA_IN2P,3741	.inv_hp_pol = 1,3742};3743 3744static const struct acpi_gpio_params ef20_hp_detect = { 1, 0, false };3745 3746static const struct acpi_gpio_mapping cht_rt5645_ef20_gpios[] = {3747	{ "hp-detect-gpios", &ef20_hp_detect, 1 },3748	{ },3749};3750 3751static int cht_rt5645_ef20_quirk_cb(const struct dmi_system_id *id)3752{3753	cht_rt5645_gpios = cht_rt5645_ef20_gpios;3754	return 1;3755}3756 3757static const struct dmi_system_id dmi_platform_data[] = {3758	{3759		.ident = "Chrome Buddy",3760		.matches = {3761			DMI_MATCH(DMI_PRODUCT_NAME, "Buddy"),3762		},3763		.driver_data = (void *)&buddy_platform_data,3764	},3765	{3766		.ident = "Intel Strago",3767		.matches = {3768			DMI_MATCH(DMI_PRODUCT_NAME, "Strago"),3769		},3770		.driver_data = (void *)&intel_braswell_platform_data,3771	},3772	{3773		.ident = "Google Chrome",3774		.matches = {3775			DMI_MATCH(DMI_SYS_VENDOR, "GOOGLE"),3776		},3777		.driver_data = (void *)&intel_braswell_platform_data,3778	},3779	{3780		.ident = "Google Setzer",3781		.matches = {3782			DMI_MATCH(DMI_PRODUCT_NAME, "Setzer"),3783		},3784		.driver_data = (void *)&intel_braswell_platform_data,3785	},3786	{3787		.ident = "Microsoft Surface 3",3788		.matches = {3789			DMI_MATCH(DMI_PRODUCT_NAME, "Surface 3"),3790		},3791		.driver_data = (void *)&intel_braswell_platform_data,3792	},3793	{3794		/*3795		 * Match for the GPDwin which unfortunately uses somewhat3796		 * generic dmi strings, which is why we test for 4 strings.3797		 * Comparing against 23 other byt/cht boards, board_vendor3798		 * and board_name are unique to the GPDwin, where as only one3799		 * other board has the same board_serial and 3 others have3800		 * the same default product_name. Also the GPDwin is the3801		 * only device to have both board_ and product_name not set.3802		 */3803		.ident = "GPD Win / Pocket",3804		.matches = {3805			DMI_MATCH(DMI_BOARD_VENDOR, "AMI Corporation"),3806			DMI_MATCH(DMI_BOARD_NAME, "Default string"),3807			DMI_MATCH(DMI_BOARD_SERIAL, "Default string"),3808			DMI_MATCH(DMI_PRODUCT_NAME, "Default string"),3809		},3810		.driver_data = (void *)&gpd_win_platform_data,3811	},3812	{3813		.ident = "ASUS T100HAN",3814		.matches = {3815			DMI_EXACT_MATCH(DMI_SYS_VENDOR, "ASUSTeK COMPUTER INC."),3816			DMI_MATCH(DMI_PRODUCT_NAME, "T100HAN"),3817		},3818		.driver_data = (void *)&asus_t100ha_platform_data,3819	},3820	{3821		.ident = "ASUS T101HA",3822		.matches = {3823			DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK COMPUTER INC."),3824			DMI_MATCH(DMI_PRODUCT_NAME, "T101HA"),3825		},3826		.driver_data = (void *)&asus_t101ha_platform_data,3827	},3828	{3829		.ident = "MINIX Z83-4",3830		.matches = {3831			DMI_EXACT_MATCH(DMI_SYS_VENDOR, "MINIX"),3832			DMI_MATCH(DMI_PRODUCT_NAME, "Z83-4"),3833		},3834		.driver_data = (void *)&jd_mode3_platform_data,3835	},3836	{3837		.ident = "Teclast X80 Pro",3838		.matches = {3839			DMI_MATCH(DMI_SYS_VENDOR, "TECLAST"),3840			DMI_MATCH(DMI_PRODUCT_NAME, "X80 Pro"),3841		},3842		.driver_data = (void *)&jd_mode3_monospk_platform_data,3843	},3844	{3845		.ident = "Lenovo Ideapad Miix 310",3846		.matches = {3847		  DMI_EXACT_MATCH(DMI_SYS_VENDOR, "LENOVO"),3848		  DMI_EXACT_MATCH(DMI_PRODUCT_NAME, "80SG"),3849		  DMI_EXACT_MATCH(DMI_PRODUCT_VERSION, "MIIX 310-10ICR"),3850		},3851		.driver_data = (void *)&lenovo_ideapad_miix_310_pdata,3852	},3853	{3854		.ident = "Lenovo Ideapad Miix 320",3855		.matches = {3856		  DMI_EXACT_MATCH(DMI_SYS_VENDOR, "LENOVO"),3857		  DMI_EXACT_MATCH(DMI_PRODUCT_NAME, "80XF"),3858		  DMI_EXACT_MATCH(DMI_PRODUCT_VERSION, "Lenovo MIIX 320-10ICR"),3859		},3860		.driver_data = (void *)&intel_braswell_platform_data,3861	},3862	{3863		.ident = "LattePanda board",3864		.matches = {3865		  DMI_EXACT_MATCH(DMI_BOARD_VENDOR, "AMI Corporation"),3866		  DMI_EXACT_MATCH(DMI_BOARD_NAME, "Cherry Trail CR"),3867		  DMI_EXACT_MATCH(DMI_BOARD_VERSION, "Default string"),3868		  /*3869		   * Above strings are too generic, LattePanda BIOS versions for3870		   * all 4 hw revisions are:3871		   * DF-BI-7-S70CR100-*3872		   * DF-BI-7-S70CR110-*3873		   * DF-BI-7-S70CR200-*3874		   * LP-BS-7-S70CR700-*3875		   * Do a partial match for S70CR to avoid false positive matches.3876		   */3877		  DMI_MATCH(DMI_BIOS_VERSION, "S70CR"),3878		},3879		.driver_data = (void *)&lattepanda_board_platform_data,3880	},3881	{3882		.ident = "Chrome Kahlee",3883		.matches = {3884			DMI_MATCH(DMI_PRODUCT_NAME, "Kahlee"),3885		},3886		.driver_data = (void *)&kahlee_platform_data,3887	},3888	{3889		.ident = "Medion E1239T",3890		.matches = {3891			DMI_EXACT_MATCH(DMI_SYS_VENDOR, "MEDION"),3892			DMI_MATCH(DMI_PRODUCT_NAME, "E1239T MD60568"),3893		},3894		.driver_data = (void *)&intel_braswell_platform_data,3895	},3896	{3897		.ident = "EF20",3898		.callback = cht_rt5645_ef20_quirk_cb,3899		.matches = {3900			DMI_MATCH(DMI_PRODUCT_NAME, "EF20"),3901		},3902		.driver_data = (void *)&ecs_ef20_platform_data,3903	},3904	{3905		.ident = "Acer Switch V 10 (SW5-017)",3906		.matches = {3907			DMI_EXACT_MATCH(DMI_SYS_VENDOR, "Acer"),3908			DMI_EXACT_MATCH(DMI_PRODUCT_NAME, "SW5-017"),3909		},3910		.driver_data = (void *)&intel_braswell_platform_data,3911	},3912	{3913		.ident = "Meegopad T08",3914		.matches = {3915			DMI_MATCH(DMI_SYS_VENDOR, "Default string"),3916			DMI_MATCH(DMI_PRODUCT_NAME, "Default string"),3917			DMI_MATCH(DMI_BOARD_NAME, "T3 MRD"),3918			DMI_MATCH(DMI_BOARD_VERSION, "V1.1"),3919		},3920		.driver_data = (void *)&jd_mode3_inv_data,3921	},3922	{ }3923};3924 3925static bool rt5645_check_dp(struct device *dev)3926{3927	if (device_property_present(dev, "realtek,in2-differential") ||3928	    device_property_present(dev, "realtek,dmic1-data-pin") ||3929	    device_property_present(dev, "realtek,dmic2-data-pin") ||3930	    device_property_present(dev, "realtek,jd-mode"))3931		return true;3932 3933	return false;3934}3935 3936static void rt5645_parse_dt(struct device *dev, struct rt5645_platform_data *pdata)3937{3938	pdata->in2_diff = device_property_read_bool(dev, "realtek,in2-differential");3939	device_property_read_u32(dev, "realtek,dmic1-data-pin", &pdata->dmic1_data_pin);3940	device_property_read_u32(dev, "realtek,dmic2-data-pin", &pdata->dmic2_data_pin);3941	device_property_read_u32(dev, "realtek,jd-mode", &pdata->jd_mode);3942}3943 3944static void rt5645_get_pdata(struct device *codec_dev, struct rt5645_platform_data *pdata)3945{3946	const struct dmi_system_id *dmi_data;3947 3948	dmi_data = dmi_first_match(dmi_platform_data);3949	if (dmi_data) {3950		dev_info(codec_dev, "Detected %s platform\n", dmi_data->ident);3951		*pdata = *((struct rt5645_platform_data *)dmi_data->driver_data);3952	} else if (rt5645_check_dp(codec_dev)) {3953		rt5645_parse_dt(codec_dev, pdata);3954	} else {3955		*pdata = jd_mode3_platform_data;3956	}3957 3958	if (quirk != -1) {3959		pdata->in2_diff = QUIRK_IN2_DIFF(quirk);3960		pdata->level_trigger_irq = QUIRK_LEVEL_IRQ(quirk);3961		pdata->inv_jd1_1 = QUIRK_INV_JD1_1(quirk);3962		pdata->inv_hp_pol = QUIRK_INV_HP_POL(quirk);3963		pdata->jd_mode = QUIRK_JD_MODE(quirk);3964		pdata->dmic1_data_pin = QUIRK_DMIC1_DATA_PIN(quirk);3965		pdata->dmic2_data_pin = QUIRK_DMIC2_DATA_PIN(quirk);3966	}3967}3968 3969const char *rt5645_components(struct device *codec_dev)3970{3971	struct rt5645_platform_data pdata = { };3972	static char buf[32];3973	const char *mic;3974	int spk = 2;3975 3976	rt5645_get_pdata(codec_dev, &pdata);3977 3978	if (pdata.mono_speaker)3979		spk = 1;3980 3981	if (pdata.dmic1_data_pin && pdata.dmic2_data_pin)3982		mic = "dmics12";3983	else if (pdata.dmic1_data_pin)3984		mic = "dmic1";3985	else if (pdata.dmic2_data_pin)3986		mic = "dmic2";3987	else3988		mic = "in2";3989 3990	snprintf(buf, sizeof(buf), "cfg-spk:%d cfg-mic:%s", spk, mic);3991 3992	return buf;3993}3994EXPORT_SYMBOL_GPL(rt5645_components);3995 3996static int rt5645_i2c_probe(struct i2c_client *i2c)3997{3998	struct rt5645_priv *rt5645;3999	int ret, i;4000	unsigned int val;4001	struct regmap *regmap;4002 4003	rt5645 = devm_kzalloc(&i2c->dev, sizeof(struct rt5645_priv),4004				GFP_KERNEL);4005	if (rt5645 == NULL)4006		return -ENOMEM;4007 4008	rt5645->i2c = i2c;4009	i2c_set_clientdata(i2c, rt5645);4010	rt5645_get_pdata(&i2c->dev, &rt5645->pdata);4011 4012	if (has_acpi_companion(&i2c->dev)) {4013		if (cht_rt5645_gpios) {4014			if (devm_acpi_dev_add_driver_gpios(&i2c->dev, cht_rt5645_gpios))4015				dev_dbg(&i2c->dev, "Failed to add driver gpios\n");4016		}4017 4018		/* The ALC3270 package has the headset-mic pin not-connected */4019		if (acpi_dev_hid_uid_match(ACPI_COMPANION(&i2c->dev), "10EC3270", NULL))4020			rt5645->pdata.no_headset_mic = true;4021	}4022 4023	rt5645->gpiod_hp_det = devm_gpiod_get_optional(&i2c->dev, "hp-detect",4024						       GPIOD_IN);4025 4026	if (IS_ERR(rt5645->gpiod_hp_det)) {4027		dev_info(&i2c->dev, "failed to initialize gpiod\n");4028		ret = PTR_ERR(rt5645->gpiod_hp_det);4029		/*4030		 * Continue if optional gpiod is missing, bail for all other4031		 * errors, including -EPROBE_DEFER4032		 */4033		if (ret != -ENOENT)4034			return ret;4035	}4036 4037	rt5645->gpiod_cbj_sleeve = devm_gpiod_get_optional(&i2c->dev, "cbj-sleeve",4038							   GPIOD_OUT_LOW);4039 4040	if (IS_ERR(rt5645->gpiod_cbj_sleeve)) {4041		ret = PTR_ERR(rt5645->gpiod_cbj_sleeve);4042		dev_info(&i2c->dev, "failed to initialize gpiod, ret=%d\n", ret);4043		if (ret != -ENOENT)4044			return ret;4045	}4046 4047	for (i = 0; i < ARRAY_SIZE(rt5645->supplies); i++)4048		rt5645->supplies[i].supply = rt5645_supply_names[i];4049 4050	ret = devm_regulator_bulk_get(&i2c->dev,4051				      ARRAY_SIZE(rt5645->supplies),4052				      rt5645->supplies);4053	if (ret) {4054		dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret);4055		return ret;4056	}4057 4058	ret = regulator_bulk_enable(ARRAY_SIZE(rt5645->supplies),4059				    rt5645->supplies);4060	if (ret) {4061		dev_err(&i2c->dev, "Failed to enable supplies: %d\n", ret);4062		return ret;4063	}4064 4065	regmap = devm_regmap_init_i2c(i2c, &temp_regmap);4066	if (IS_ERR(regmap)) {4067		ret = PTR_ERR(regmap);4068		dev_err(&i2c->dev, "Failed to allocate temp register map: %d\n",4069			ret);4070		goto err_enable;4071	}4072 4073	/*4074	 * Read after 400msec, as it is the interval required between4075	 * read and power On.4076	 */4077	msleep(TIME_TO_POWER_MS);4078	ret = regmap_read(regmap, RT5645_VENDOR_ID2, &val);4079	if (ret < 0) {4080		dev_err(&i2c->dev, "Failed to read: 0x%02X\n, ret = %d", RT5645_VENDOR_ID2, ret);4081		goto err_enable;4082	}4083 4084	switch (val) {4085	case RT5645_DEVICE_ID:4086		rt5645->regmap = devm_regmap_init_i2c(i2c, &rt5645_regmap);4087		rt5645->codec_type = CODEC_TYPE_RT5645;4088		break;4089	case RT5650_DEVICE_ID:4090		rt5645->regmap = devm_regmap_init_i2c(i2c, &rt5650_regmap);4091		rt5645->codec_type = CODEC_TYPE_RT5650;4092		break;4093	default:4094		dev_err(&i2c->dev,4095			"Device with ID register %#x is not rt5645 or rt5650\n",4096			val);4097		ret = -ENODEV;4098		goto err_enable;4099	}4100 4101	if (IS_ERR(rt5645->regmap)) {4102		ret = PTR_ERR(rt5645->regmap);4103		dev_err(&i2c->dev, "Failed to allocate register map: %d\n",4104			ret);4105		goto err_enable;4106	}4107 4108	regmap_write(rt5645->regmap, RT5645_RESET, 0);4109 4110	regmap_read(regmap, RT5645_VENDOR_ID, &val);4111	rt5645->v_id = val & 0xff;4112 4113	regmap_write(rt5645->regmap, RT5645_AD_DA_MIXER, 0x8080);4114 4115	ret = regmap_multi_reg_write(rt5645->regmap, init_list,4116				    ARRAY_SIZE(init_list));4117	if (ret != 0)4118		dev_warn(&i2c->dev, "Failed to apply regmap patch: %d\n", ret);4119 4120	if (rt5645->codec_type == CODEC_TYPE_RT5650) {4121		ret = regmap_multi_reg_write(rt5645->regmap, rt5650_init_list,4122				    ARRAY_SIZE(rt5650_init_list));4123		if (ret != 0)4124			dev_warn(&i2c->dev, "Apply rt5650 patch failed: %d\n",4125					   ret);4126	}4127 4128	regmap_update_bits(rt5645->regmap, RT5645_CLSD_OUT_CTRL, 0xc0, 0xc0);4129 4130	if (rt5645->pdata.in2_diff)4131		regmap_update_bits(rt5645->regmap, RT5645_IN2_CTRL,4132					RT5645_IN_DF2, RT5645_IN_DF2);4133 4134	if (rt5645->pdata.dmic1_data_pin || rt5645->pdata.dmic2_data_pin) {4135		regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,4136			RT5645_GP2_PIN_MASK, RT5645_GP2_PIN_DMIC1_SCL);4137	}4138	switch (rt5645->pdata.dmic1_data_pin) {4139	case RT5645_DMIC_DATA_IN2N:4140		regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,4141			RT5645_DMIC_1_DP_MASK, RT5645_DMIC_1_DP_IN2N);4142		break;4143 4144	case RT5645_DMIC_DATA_GPIO5:4145		regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,4146			RT5645_I2S2_DAC_PIN_MASK, RT5645_I2S2_DAC_PIN_GPIO);4147		regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,4148			RT5645_DMIC_1_DP_MASK, RT5645_DMIC_1_DP_GPIO5);4149		regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,4150			RT5645_GP5_PIN_MASK, RT5645_GP5_PIN_DMIC1_SDA);4151		break;4152 4153	case RT5645_DMIC_DATA_GPIO11:4154		regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,4155			RT5645_DMIC_1_DP_MASK, RT5645_DMIC_1_DP_GPIO11);4156		regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,4157			RT5645_GP11_PIN_MASK,4158			RT5645_GP11_PIN_DMIC1_SDA);4159		break;4160 4161	default:4162		break;4163	}4164 4165	switch (rt5645->pdata.dmic2_data_pin) {4166	case RT5645_DMIC_DATA_IN2P:4167		regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,4168			RT5645_DMIC_2_DP_MASK, RT5645_DMIC_2_DP_IN2P);4169		break;4170 4171	case RT5645_DMIC_DATA_GPIO6:4172		regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,4173			RT5645_DMIC_2_DP_MASK, RT5645_DMIC_2_DP_GPIO6);4174		regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,4175			RT5645_GP6_PIN_MASK, RT5645_GP6_PIN_DMIC2_SDA);4176		break;4177 4178	case RT5645_DMIC_DATA_GPIO10:4179		regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,4180			RT5645_DMIC_2_DP_MASK, RT5645_DMIC_2_DP_GPIO10);4181		regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,4182			RT5645_GP10_PIN_MASK,4183			RT5645_GP10_PIN_DMIC2_SDA);4184		break;4185 4186	case RT5645_DMIC_DATA_GPIO12:4187		regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,4188			RT5645_DMIC_2_DP_MASK, RT5645_DMIC_2_DP_GPIO12);4189		regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,4190			RT5645_GP12_PIN_MASK,4191			RT5645_GP12_PIN_DMIC2_SDA);4192		break;4193 4194	default:4195		break;4196	}4197 4198	if (rt5645->pdata.jd_mode) {4199		regmap_update_bits(rt5645->regmap, RT5645_GEN_CTRL3,4200				   RT5645_IRQ_CLK_GATE_CTRL,4201				   RT5645_IRQ_CLK_GATE_CTRL);4202		regmap_update_bits(rt5645->regmap, RT5645_MICBIAS,4203				   RT5645_IRQ_CLK_INT, RT5645_IRQ_CLK_INT);4204		regmap_update_bits(rt5645->regmap, RT5645_IRQ_CTRL2,4205				   RT5645_IRQ_JD_1_1_EN, RT5645_IRQ_JD_1_1_EN);4206		regmap_update_bits(rt5645->regmap, RT5645_GEN_CTRL3,4207				   RT5645_JD_PSV_MODE, RT5645_JD_PSV_MODE);4208		regmap_update_bits(rt5645->regmap, RT5645_HPO_MIXER,4209				   RT5645_IRQ_PSV_MODE, RT5645_IRQ_PSV_MODE);4210		regmap_update_bits(rt5645->regmap, RT5645_MICBIAS,4211				   RT5645_MIC2_OVCD_EN, RT5645_MIC2_OVCD_EN);4212		regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,4213				   RT5645_GP1_PIN_IRQ, RT5645_GP1_PIN_IRQ);4214		switch (rt5645->pdata.jd_mode) {4215		case 1:4216			regmap_update_bits(rt5645->regmap, RT5645_A_JD_CTRL1,4217					   RT5645_JD1_MODE_MASK,4218					   RT5645_JD1_MODE_0);4219			break;4220		case 2:4221			regmap_update_bits(rt5645->regmap, RT5645_A_JD_CTRL1,4222					   RT5645_JD1_MODE_MASK,4223					   RT5645_JD1_MODE_1);4224			break;4225		case 3:4226		case 4:4227			regmap_update_bits(rt5645->regmap, RT5645_A_JD_CTRL1,4228					   RT5645_JD1_MODE_MASK,4229					   RT5645_JD1_MODE_2);4230			break;4231		default:4232			break;4233		}4234		if (rt5645->pdata.inv_jd1_1) {4235			regmap_update_bits(rt5645->regmap, RT5645_IRQ_CTRL2,4236				RT5645_JD_1_1_MASK, RT5645_JD_1_1_INV);4237		}4238	}4239 4240	regmap_update_bits(rt5645->regmap, RT5645_ADDA_CLK1,4241		RT5645_I2S_PD1_MASK, RT5645_I2S_PD1_2);4242 4243	if (rt5645->pdata.level_trigger_irq) {4244		regmap_update_bits(rt5645->regmap, RT5645_IRQ_CTRL2,4245			RT5645_JD_1_1_MASK, RT5645_JD_1_1_INV);4246	}4247	timer_setup(&rt5645->btn_check_timer, rt5645_btn_check_callback, 0);4248 4249	mutex_init(&rt5645->jd_mutex);4250	INIT_DELAYED_WORK(&rt5645->jack_detect_work, rt5645_jack_detect_work);4251	INIT_DELAYED_WORK(&rt5645->rcclock_work, rt5645_rcclock_work);4252 4253	if (rt5645->i2c->irq) {4254		ret = request_threaded_irq(rt5645->i2c->irq, NULL, rt5645_irq,4255			IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING4256			| IRQF_ONESHOT, "rt5645", rt5645);4257		if (ret) {4258			dev_err(&i2c->dev, "Failed to request IRQ: %d\n", ret);4259			goto err_enable;4260		}4261	}4262 4263	ret = devm_snd_soc_register_component(&i2c->dev, &soc_component_dev_rt5645,4264				     rt5645_dai, ARRAY_SIZE(rt5645_dai));4265	if (ret)4266		goto err_irq;4267 4268	return 0;4269 4270err_irq:4271	if (rt5645->i2c->irq)4272		free_irq(rt5645->i2c->irq, rt5645);4273err_enable:4274	regulator_bulk_disable(ARRAY_SIZE(rt5645->supplies), rt5645->supplies);4275	return ret;4276}4277 4278static void rt5645_i2c_remove(struct i2c_client *i2c)4279{4280	struct rt5645_priv *rt5645 = i2c_get_clientdata(i2c);4281 4282	if (i2c->irq)4283		free_irq(i2c->irq, rt5645);4284 4285	/*4286	 * Since the rt5645_btn_check_callback() can queue jack_detect_work,4287	 * the timer need to be delted first4288	 */4289	del_timer_sync(&rt5645->btn_check_timer);4290 4291	cancel_delayed_work_sync(&rt5645->jack_detect_work);4292	cancel_delayed_work_sync(&rt5645->rcclock_work);4293 4294	if (rt5645->gpiod_cbj_sleeve)4295		gpiod_set_value(rt5645->gpiod_cbj_sleeve, 0);4296 4297	regulator_bulk_disable(ARRAY_SIZE(rt5645->supplies), rt5645->supplies);4298}4299 4300static void rt5645_i2c_shutdown(struct i2c_client *i2c)4301{4302	struct rt5645_priv *rt5645 = i2c_get_clientdata(i2c);4303 4304	regmap_update_bits(rt5645->regmap, RT5645_GEN_CTRL3,4305		RT5645_RING2_SLEEVE_GND, RT5645_RING2_SLEEVE_GND);4306	regmap_update_bits(rt5645->regmap, RT5645_IN1_CTRL2, RT5645_CBJ_MN_JD,4307		RT5645_CBJ_MN_JD);4308	regmap_update_bits(rt5645->regmap, RT5645_IN1_CTRL1, RT5645_CBJ_BST1_EN,4309		0);4310	msleep(20);4311	regmap_write(rt5645->regmap, RT5645_RESET, 0);4312 4313	if (rt5645->gpiod_cbj_sleeve)4314		gpiod_set_value(rt5645->gpiod_cbj_sleeve, 0);4315}4316 4317static int __maybe_unused rt5645_sys_suspend(struct device *dev)4318{4319	struct rt5645_priv *rt5645 = dev_get_drvdata(dev);4320 4321	del_timer_sync(&rt5645->btn_check_timer);4322	cancel_delayed_work_sync(&rt5645->jack_detect_work);4323	cancel_delayed_work_sync(&rt5645->rcclock_work);4324 4325	regcache_cache_only(rt5645->regmap, true);4326	regcache_mark_dirty(rt5645->regmap);4327	return 0;4328}4329 4330static int __maybe_unused rt5645_sys_resume(struct device *dev)4331{4332	struct rt5645_priv *rt5645 = dev_get_drvdata(dev);4333 4334	regcache_cache_only(rt5645->regmap, false);4335	regcache_sync(rt5645->regmap);4336 4337	if (rt5645->hp_jack) {4338		rt5645->jack_type = 0;4339		rt5645_jack_detect_work(&rt5645->jack_detect_work.work);4340	}4341	return 0;4342}4343 4344static const struct dev_pm_ops rt5645_pm = {4345	SET_SYSTEM_SLEEP_PM_OPS(rt5645_sys_suspend, rt5645_sys_resume)4346};4347 4348static struct i2c_driver rt5645_i2c_driver = {4349	.driver = {4350		.name = "rt5645",4351		.of_match_table = of_match_ptr(rt5645_of_match),4352		.acpi_match_table = ACPI_PTR(rt5645_acpi_match),4353		.pm = &rt5645_pm,4354	},4355	.probe = rt5645_i2c_probe,4356	.remove = rt5645_i2c_remove,4357	.shutdown = rt5645_i2c_shutdown,4358	.id_table = rt5645_i2c_id,4359};4360module_i2c_driver(rt5645_i2c_driver);4361 4362MODULE_DESCRIPTION("ASoC RT5645 driver");4363MODULE_AUTHOR("Bard Liao <bardliao@realtek.com>");4364MODULE_LICENSE("GPL v2");4365