2214 lines · c
1/* SPDX-License-Identifier: GPL-2.0-only */2/*3 * rt5645.h -- RT5645 ALSA SoC audio driver4 *5 * Copyright 2013 Realtek Microelectronics6 * Author: Bard Liao <bardliao@realtek.com>7 */8 9#ifndef __RT5645_H__10#define __RT5645_H__11 12/* Info */13#define RT5645_RESET 0x0014#define RT5645_VENDOR_ID 0xfd15#define RT5645_VENDOR_ID1 0xfe16#define RT5645_VENDOR_ID2 0xff17/* I/O - Output */18#define RT5645_SPK_VOL 0x0119#define RT5645_HP_VOL 0x0220#define RT5645_LOUT1 0x0321#define RT5645_LOUT_CTRL 0x0522/* I/O - Input */23#define RT5645_IN1_CTRL1 0x0a24#define RT5645_IN1_CTRL2 0x0b25#define RT5645_IN1_CTRL3 0x0c26#define RT5645_IN2_CTRL 0x0d27#define RT5645_INL1_INR1_VOL 0x0f28#define RT5645_SPK_FUNC_LIM 0x1429#define RT5645_ADJ_HPF_CTRL 0x1630/* I/O - ADC/DAC/DMIC */31#define RT5645_DAC1_DIG_VOL 0x1932#define RT5645_DAC2_DIG_VOL 0x1a33#define RT5645_DAC_CTRL 0x1b34#define RT5645_STO1_ADC_DIG_VOL 0x1c35#define RT5645_MONO_ADC_DIG_VOL 0x1d36#define RT5645_ADC_BST_VOL1 0x1e37#define RT5645_ADC_BST_VOL2 0x2038/* Mixer - D-D */39#define RT5645_STO1_ADC_MIXER 0x2740#define RT5645_MONO_ADC_MIXER 0x2841#define RT5645_AD_DA_MIXER 0x2942#define RT5645_STO_DAC_MIXER 0x2a43#define RT5645_MONO_DAC_MIXER 0x2b44#define RT5645_DIG_MIXER 0x2c45#define RT5650_A_DAC_SOUR 0x2d46#define RT5645_DIG_INF1_DATA 0x2f47/* Mixer - PDM */48#define RT5645_PDM_OUT_CTRL 0x3149/* Mixer - ADC */50#define RT5645_REC_L1_MIXER 0x3b51#define RT5645_REC_L2_MIXER 0x3c52#define RT5645_REC_R1_MIXER 0x3d53#define RT5645_REC_R2_MIXER 0x3e54/* Mixer - DAC */55#define RT5645_HPMIXL_CTRL 0x3f56#define RT5645_HPOMIXL_CTRL 0x4057#define RT5645_HPMIXR_CTRL 0x4158#define RT5645_HPOMIXR_CTRL 0x4259#define RT5645_HPO_MIXER 0x4560#define RT5645_SPK_L_MIXER 0x4661#define RT5645_SPK_R_MIXER 0x4762#define RT5645_SPO_MIXER 0x4863#define RT5645_SPO_CLSD_RATIO 0x4a64#define RT5645_OUT_L_GAIN1 0x4d65#define RT5645_OUT_L_GAIN2 0x4e66#define RT5645_OUT_L1_MIXER 0x4f67#define RT5645_OUT_R_GAIN1 0x5068#define RT5645_OUT_R_GAIN2 0x5169#define RT5645_OUT_R1_MIXER 0x5270#define RT5645_LOUT_MIXER 0x5371/* Haptic */72#define RT5645_HAPTIC_CTRL1 0x5673#define RT5645_HAPTIC_CTRL2 0x5774#define RT5645_HAPTIC_CTRL3 0x5875#define RT5645_HAPTIC_CTRL4 0x5976#define RT5645_HAPTIC_CTRL5 0x5a77#define RT5645_HAPTIC_CTRL6 0x5b78#define RT5645_HAPTIC_CTRL7 0x5c79#define RT5645_HAPTIC_CTRL8 0x5d80#define RT5645_HAPTIC_CTRL9 0x5e81#define RT5645_HAPTIC_CTRL10 0x5f82/* Power */83#define RT5645_PWR_DIG1 0x6184#define RT5645_PWR_DIG2 0x6285#define RT5645_PWR_ANLG1 0x6386#define RT5645_PWR_ANLG2 0x6487#define RT5645_PWR_MIXER 0x6588#define RT5645_PWR_VOL 0x6689/* Private Register Control */90#define RT5645_PRIV_INDEX 0x6a91#define RT5645_PRIV_DATA 0x6c92/* Format - ADC/DAC */93#define RT5645_I2S1_SDP 0x7094#define RT5645_I2S2_SDP 0x7195#define RT5645_ADDA_CLK1 0x7396#define RT5645_ADDA_CLK2 0x7497#define RT5645_DMIC_CTRL1 0x7598#define RT5645_DMIC_CTRL2 0x7699/* Format - TDM Control */100#define RT5645_TDM_CTRL_1 0x77101#define RT5645_TDM_CTRL_2 0x78102#define RT5645_TDM_CTRL_3 0x79103#define RT5650_TDM_CTRL_4 0x7a104 105/* Function - Analog */106#define RT5645_GLB_CLK 0x80107#define RT5645_PLL_CTRL1 0x81108#define RT5645_PLL_CTRL2 0x82109#define RT5645_ASRC_1 0x83110#define RT5645_ASRC_2 0x84111#define RT5645_ASRC_3 0x85112#define RT5645_ASRC_4 0x8a113#define RT5645_DEPOP_M1 0x8e114#define RT5645_DEPOP_M2 0x8f115#define RT5645_DEPOP_M3 0x90116#define RT5645_CHARGE_PUMP 0x91117#define RT5645_MICBIAS 0x93118#define RT5645_A_JD_CTRL1 0x94119#define RT5645_VAD_CTRL4 0x9d120#define RT5645_CLSD_OUT_CTRL 0xa0121/* Function - Digital */122#define RT5645_ADC_EQ_CTRL1 0xae123#define RT5645_ADC_EQ_CTRL2 0xaf124#define RT5645_EQ_CTRL1 0xb0125#define RT5645_EQ_CTRL2 0xb1126#define RT5645_ALC_CTRL_1 0xb3127#define RT5645_ALC_CTRL_2 0xb4128#define RT5645_ALC_CTRL_3 0xb5129#define RT5645_ALC_CTRL_4 0xb6130#define RT5645_ALC_CTRL_5 0xb7131#define RT5645_JD_CTRL 0xbb132#define RT5645_IRQ_CTRL1 0xbc133#define RT5645_IRQ_CTRL2 0xbd134#define RT5645_IRQ_CTRL3 0xbe135#define RT5645_INT_IRQ_ST 0xbf136#define RT5645_GPIO_CTRL1 0xc0137#define RT5645_GPIO_CTRL2 0xc1138#define RT5645_GPIO_CTRL3 0xc2139#define RT5645_BASS_BACK 0xcf140#define RT5645_MP3_PLUS1 0xd0141#define RT5645_MP3_PLUS2 0xd1142#define RT5645_ADJ_HPF1 0xd3143#define RT5645_ADJ_HPF2 0xd4144#define RT5645_HP_CALIB_AMP_DET 0xd6145#define RT5645_SV_ZCD1 0xd9146#define RT5645_SV_ZCD2 0xda147#define RT5645_IL_CMD 0xdb148#define RT5645_IL_CMD2 0xdc149#define RT5645_IL_CMD3 0xdd150#define RT5650_4BTN_IL_CMD1 0xdf151#define RT5650_4BTN_IL_CMD2 0xe0152#define RT5645_DRC1_HL_CTRL1 0xe7153#define RT5645_DRC2_HL_CTRL1 0xe9154#define RT5645_MUTI_DRC_CTRL1 0xea155#define RT5645_ADC_MONO_HP_CTRL1 0xec156#define RT5645_ADC_MONO_HP_CTRL2 0xed157#define RT5645_DRC2_CTRL1 0xf0158#define RT5645_DRC2_CTRL2 0xf1159#define RT5645_DRC2_CTRL3 0xf2160#define RT5645_DRC2_CTRL4 0xf3161#define RT5645_DRC2_CTRL5 0xf4162#define RT5645_JD_CTRL3 0xf8163#define RT5645_JD_CTRL4 0xf9164/* General Control */165#define RT5645_GEN_CTRL1 0xfa166#define RT5645_GEN_CTRL2 0xfb167#define RT5645_GEN_CTRL3 0xfc168 169 170/* Index of Codec Private Register definition */171#define RT5645_DIG_VOL 0x00172#define RT5645_PR_ALC_CTRL_1 0x01173#define RT5645_PR_ALC_CTRL_2 0x02174#define RT5645_PR_ALC_CTRL_3 0x03175#define RT5645_PR_ALC_CTRL_4 0x04176#define RT5645_PR_ALC_CTRL_5 0x05177#define RT5645_PR_ALC_CTRL_6 0x06178#define RT5645_BIAS_CUR1 0x12179#define RT5645_BIAS_CUR3 0x14180#define RT5645_CLSD_INT_REG1 0x1c181#define RT5645_MAMP_INT_REG2 0x37182#define RT5645_CHOP_DAC_ADC 0x3d183#define RT5645_MIXER_INT_REG 0x3f184#define RT5645_3D_SPK 0x63185#define RT5645_WND_1 0x6c186#define RT5645_WND_2 0x6d187#define RT5645_WND_3 0x6e188#define RT5645_WND_4 0x6f189#define RT5645_WND_5 0x70190#define RT5645_WND_8 0x73191#define RT5645_DIP_SPK_INF 0x75192#define RT5645_HP_DCC_INT1 0x77193#define RT5645_EQ_BW_LOP 0xa0194#define RT5645_EQ_GN_LOP 0xa1195#define RT5645_EQ_FC_BP1 0xa2196#define RT5645_EQ_BW_BP1 0xa3197#define RT5645_EQ_GN_BP1 0xa4198#define RT5645_EQ_FC_BP2 0xa5199#define RT5645_EQ_BW_BP2 0xa6200#define RT5645_EQ_GN_BP2 0xa7201#define RT5645_EQ_FC_BP3 0xa8202#define RT5645_EQ_BW_BP3 0xa9203#define RT5645_EQ_GN_BP3 0xaa204#define RT5645_EQ_FC_BP4 0xab205#define RT5645_EQ_BW_BP4 0xac206#define RT5645_EQ_GN_BP4 0xad207#define RT5645_EQ_FC_HIP1 0xae208#define RT5645_EQ_GN_HIP1 0xaf209#define RT5645_EQ_FC_HIP2 0xb0210#define RT5645_EQ_BW_HIP2 0xb1211#define RT5645_EQ_GN_HIP2 0xb2212#define RT5645_EQ_PRE_VOL 0xb3213#define RT5645_EQ_PST_VOL 0xb4214 215 216/* global definition */217#define RT5645_L_MUTE (0x1 << 15)218#define RT5645_L_MUTE_SFT 15219#define RT5645_VOL_L_MUTE (0x1 << 14)220#define RT5645_VOL_L_SFT 14221#define RT5645_R_MUTE (0x1 << 7)222#define RT5645_R_MUTE_SFT 7223#define RT5645_VOL_R_MUTE (0x1 << 6)224#define RT5645_VOL_R_SFT 6225#define RT5645_L_VOL_MASK (0x3f << 8)226#define RT5645_L_VOL_SFT 8227#define RT5645_R_VOL_MASK (0x3f)228#define RT5645_R_VOL_SFT 0229 230/* IN1 Control 1 (0x0a) */231#define RT5645_CBJ_BST1_MASK (0xf << 12)232#define RT5645_CBJ_BST1_SFT (12)233#define RT5645_CBJ_JD_HP_EN (0x1 << 9)234#define RT5645_CBJ_JD_MIC_EN (0x1 << 8)235#define RT5645_CBJ_JD_MIC_SW_EN (0x1 << 7)236#define RT5645_CBJ_MIC_SEL_R (0x1 << 6)237#define RT5645_CBJ_MIC_SEL_L (0x1 << 5)238#define RT5645_CBJ_MIC_SW (0x1 << 4)239#define RT5645_CBJ_BST1_EN (0x1 << 2)240 241/* IN1 Control 2 (0x0b) */242#define RT5645_CBJ_MN_JD (0x1 << 12)243#define RT5645_CAPLESS_EN (0x1 << 11)244#define RT5645_CBJ_DET_MODE (0x1 << 7)245 246/* IN1 Control 3 (0x0c) */247#define RT5645_CBJ_TIE_G_L (0x1 << 15)248#define RT5645_CBJ_TIE_G_R (0x1 << 14)249 250/* IN2 Control (0x0d) */251#define RT5645_BST_MASK1 (0xf<<12)252#define RT5645_BST_SFT1 12253#define RT5645_BST_MASK2 (0xf<<8)254#define RT5645_BST_SFT2 8255#define RT5645_IN_DF2 (0x1 << 6)256#define RT5645_IN_SFT2 6257 258/* INL and INR Volume Control (0x0f) */259#define RT5645_INL_SEL_MASK (0x1 << 15)260#define RT5645_INL_SEL_SFT 15261#define RT5645_INL_SEL_IN4P (0x0 << 15)262#define RT5645_INL_SEL_MONOP (0x1 << 15)263#define RT5645_INL_VOL_MASK (0x1f << 8)264#define RT5645_INL_VOL_SFT 8265#define RT5645_INR_SEL_MASK (0x1 << 7)266#define RT5645_INR_SEL_SFT 7267#define RT5645_INR_SEL_IN4N (0x0 << 7)268#define RT5645_INR_SEL_MONON (0x1 << 7)269#define RT5645_INR_VOL_MASK (0x1f)270#define RT5645_INR_VOL_SFT 0271 272/* DAC1 Digital Volume (0x19) */273#define RT5645_DAC_L1_VOL_MASK (0xff << 8)274#define RT5645_DAC_L1_VOL_SFT 8275#define RT5645_DAC_R1_VOL_MASK (0xff)276#define RT5645_DAC_R1_VOL_SFT 0277 278/* DAC2 Digital Volume (0x1a) */279#define RT5645_DAC_L2_VOL_MASK (0xff << 8)280#define RT5645_DAC_L2_VOL_SFT 8281#define RT5645_DAC_R2_VOL_MASK (0xff)282#define RT5645_DAC_R2_VOL_SFT 0283 284/* DAC2 Control (0x1b) */285#define RT5645_M_DAC_L2_VOL (0x1 << 13)286#define RT5645_M_DAC_L2_VOL_SFT 13287#define RT5645_M_DAC_R2_VOL (0x1 << 12)288#define RT5645_M_DAC_R2_VOL_SFT 12289#define RT5645_DAC2_L_SEL_MASK (0x7 << 4)290#define RT5645_DAC2_L_SEL_SFT 4291#define RT5645_DAC2_R_SEL_MASK (0x7 << 0)292#define RT5645_DAC2_R_SEL_SFT 0293 294/* ADC Digital Volume Control (0x1c) */295#define RT5645_ADC_L_VOL_MASK (0x7f << 8)296#define RT5645_ADC_L_VOL_SFT 8297#define RT5645_ADC_R_VOL_MASK (0x7f)298#define RT5645_ADC_R_VOL_SFT 0299 300/* Mono ADC Digital Volume Control (0x1d) */301#define RT5645_MONO_ADC_L_VOL_MASK (0x7f << 8)302#define RT5645_MONO_ADC_L_VOL_SFT 8303#define RT5645_MONO_ADC_R_VOL_MASK (0x7f)304#define RT5645_MONO_ADC_R_VOL_SFT 0305 306/* ADC Boost Volume Control (0x1e) */307#define RT5645_STO1_ADC_L_BST_MASK (0x3 << 14)308#define RT5645_STO1_ADC_L_BST_SFT 14309#define RT5645_STO1_ADC_R_BST_MASK (0x3 << 12)310#define RT5645_STO1_ADC_R_BST_SFT 12311#define RT5645_STO1_ADC_COMP_MASK (0x3 << 10)312#define RT5645_STO1_ADC_COMP_SFT 10313 314/* ADC Boost Volume Control (0x20) */315#define RT5645_MONO_ADC_L_BST_MASK (0x3 << 14)316#define RT5645_MONO_ADC_L_BST_SFT 14317#define RT5645_MONO_ADC_R_BST_MASK (0x3 << 12)318#define RT5645_MONO_ADC_R_BST_SFT 12319#define RT5645_MONO_ADC_COMP_MASK (0x3 << 10)320#define RT5645_MONO_ADC_COMP_SFT 10321 322/* Stereo2 ADC Mixer Control (0x26) */323#define RT5645_STO2_ADC_SRC_MASK (0x1 << 15)324#define RT5645_STO2_ADC_SRC_SFT 15325 326/* Stereo ADC Mixer Control (0x27) */327#define RT5645_M_ADC_L1 (0x1 << 14)328#define RT5645_M_ADC_L1_SFT 14329#define RT5645_M_ADC_L2 (0x1 << 13)330#define RT5645_M_ADC_L2_SFT 13331#define RT5645_ADC_1_SRC_MASK (0x1 << 12)332#define RT5645_ADC_1_SRC_SFT 12333#define RT5645_ADC_1_SRC_ADC (0x1 << 12)334#define RT5645_ADC_1_SRC_DACMIX (0x0 << 12)335#define RT5645_ADC_2_SRC_MASK (0x1 << 11)336#define RT5645_ADC_2_SRC_SFT 11337#define RT5645_DMIC_SRC_MASK (0x1 << 8)338#define RT5645_DMIC_SRC_SFT 8339#define RT5645_M_ADC_R1 (0x1 << 6)340#define RT5645_M_ADC_R1_SFT 6341#define RT5645_M_ADC_R2 (0x1 << 5)342#define RT5645_M_ADC_R2_SFT 5343#define RT5645_DMIC3_SRC_MASK (0x1 << 1)344#define RT5645_DMIC3_SRC_SFT 0345 346/* Mono ADC Mixer Control (0x28) */347#define RT5645_M_MONO_ADC_L1 (0x1 << 14)348#define RT5645_M_MONO_ADC_L1_SFT 14349#define RT5645_M_MONO_ADC_L2 (0x1 << 13)350#define RT5645_M_MONO_ADC_L2_SFT 13351#define RT5645_MONO_ADC_L1_SRC_MASK (0x1 << 12)352#define RT5645_MONO_ADC_L1_SRC_SFT 12353#define RT5645_MONO_ADC_L1_SRC_DACMIXL (0x0 << 12)354#define RT5645_MONO_ADC_L1_SRC_ADCL (0x1 << 12)355#define RT5645_MONO_ADC_L2_SRC_MASK (0x1 << 11)356#define RT5645_MONO_ADC_L2_SRC_SFT 11357#define RT5645_MONO_DMIC_L_SRC_MASK (0x1 << 8)358#define RT5645_MONO_DMIC_L_SRC_SFT 8359#define RT5645_M_MONO_ADC_R1 (0x1 << 6)360#define RT5645_M_MONO_ADC_R1_SFT 6361#define RT5645_M_MONO_ADC_R2 (0x1 << 5)362#define RT5645_M_MONO_ADC_R2_SFT 5363#define RT5645_MONO_ADC_R1_SRC_MASK (0x1 << 4)364#define RT5645_MONO_ADC_R1_SRC_SFT 4365#define RT5645_MONO_ADC_R1_SRC_ADCR (0x1 << 4)366#define RT5645_MONO_ADC_R1_SRC_DACMIXR (0x0 << 4)367#define RT5645_MONO_ADC_R2_SRC_MASK (0x1 << 3)368#define RT5645_MONO_ADC_R2_SRC_SFT 3369#define RT5645_MONO_DMIC_R_SRC_MASK (0x3)370#define RT5645_MONO_DMIC_R_SRC_SFT 0371 372/* ADC Mixer to DAC Mixer Control (0x29) */373#define RT5645_M_ADCMIX_L (0x1 << 15)374#define RT5645_M_ADCMIX_L_SFT 15375#define RT5645_M_DAC1_L (0x1 << 14)376#define RT5645_M_DAC1_L_SFT 14377#define RT5645_DAC1_R_SEL_MASK (0x3 << 10)378#define RT5645_DAC1_R_SEL_SFT 10379#define RT5645_DAC1_R_SEL_IF1 (0x0 << 10)380#define RT5645_DAC1_R_SEL_IF2 (0x1 << 10)381#define RT5645_DAC1_R_SEL_IF3 (0x2 << 10)382#define RT5645_DAC1_R_SEL_IF4 (0x3 << 10)383#define RT5645_DAC1_L_SEL_MASK (0x3 << 8)384#define RT5645_DAC1_L_SEL_SFT 8385#define RT5645_DAC1_L_SEL_IF1 (0x0 << 8)386#define RT5645_DAC1_L_SEL_IF2 (0x1 << 8)387#define RT5645_DAC1_L_SEL_IF3 (0x2 << 8)388#define RT5645_DAC1_L_SEL_IF4 (0x3 << 8)389#define RT5645_M_ADCMIX_R (0x1 << 7)390#define RT5645_M_ADCMIX_R_SFT 7391#define RT5645_M_DAC1_R (0x1 << 6)392#define RT5645_M_DAC1_R_SFT 6393 394/* Stereo DAC Mixer Control (0x2a) */395#define RT5645_M_DAC_L1 (0x1 << 14)396#define RT5645_M_DAC_L1_SFT 14397#define RT5645_DAC_L1_STO_L_VOL_MASK (0x1 << 13)398#define RT5645_DAC_L1_STO_L_VOL_SFT 13399#define RT5645_M_DAC_L2 (0x1 << 12)400#define RT5645_M_DAC_L2_SFT 12401#define RT5645_DAC_L2_STO_L_VOL_MASK (0x1 << 11)402#define RT5645_DAC_L2_STO_L_VOL_SFT 11403#define RT5645_M_ANC_DAC_L (0x1 << 10)404#define RT5645_M_ANC_DAC_L_SFT 10405#define RT5645_M_DAC_R1_STO_L (0x1 << 9)406#define RT5645_M_DAC_R1_STO_L_SFT 9407#define RT5645_DAC_R1_STO_L_VOL_MASK (0x1 << 8)408#define RT5645_DAC_R1_STO_L_VOL_SFT 8409#define RT5645_M_DAC_R1 (0x1 << 6)410#define RT5645_M_DAC_R1_SFT 6411#define RT5645_DAC_R1_STO_R_VOL_MASK (0x1 << 5)412#define RT5645_DAC_R1_STO_R_VOL_SFT 5413#define RT5645_M_DAC_R2 (0x1 << 4)414#define RT5645_M_DAC_R2_SFT 4415#define RT5645_DAC_R2_STO_R_VOL_MASK (0x1 << 3)416#define RT5645_DAC_R2_STO_R_VOL_SFT 3417#define RT5645_M_ANC_DAC_R (0x1 << 2)418#define RT5645_M_ANC_DAC_R_SFT 2419#define RT5645_M_DAC_L1_STO_R (0x1 << 1)420#define RT5645_M_DAC_L1_STO_R_SFT 1421#define RT5645_DAC_L1_STO_R_VOL_MASK (0x1)422#define RT5645_DAC_L1_STO_R_VOL_SFT 0423 424/* Mono DAC Mixer Control (0x2b) */425#define RT5645_M_DAC_L1_MONO_L (0x1 << 14)426#define RT5645_M_DAC_L1_MONO_L_SFT 14427#define RT5645_DAC_L1_MONO_L_VOL_MASK (0x1 << 13)428#define RT5645_DAC_L1_MONO_L_VOL_SFT 13429#define RT5645_M_DAC_L2_MONO_L (0x1 << 12)430#define RT5645_M_DAC_L2_MONO_L_SFT 12431#define RT5645_DAC_L2_MONO_L_VOL_MASK (0x1 << 11)432#define RT5645_DAC_L2_MONO_L_VOL_SFT 11433#define RT5645_M_DAC_R2_MONO_L (0x1 << 10)434#define RT5645_M_DAC_R2_MONO_L_SFT 10435#define RT5645_DAC_R2_MONO_L_VOL_MASK (0x1 << 9)436#define RT5645_DAC_R2_MONO_L_VOL_SFT 9437#define RT5645_M_DAC_R1_MONO_R (0x1 << 6)438#define RT5645_M_DAC_R1_MONO_R_SFT 6439#define RT5645_DAC_R1_MONO_R_VOL_MASK (0x1 << 5)440#define RT5645_DAC_R1_MONO_R_VOL_SFT 5441#define RT5645_M_DAC_R2_MONO_R (0x1 << 4)442#define RT5645_M_DAC_R2_MONO_R_SFT 4443#define RT5645_DAC_R2_MONO_R_VOL_MASK (0x1 << 3)444#define RT5645_DAC_R2_MONO_R_VOL_SFT 3445#define RT5645_M_DAC_L2_MONO_R (0x1 << 2)446#define RT5645_M_DAC_L2_MONO_R_SFT 2447#define RT5645_DAC_L2_MONO_R_VOL_MASK (0x1 << 1)448#define RT5645_DAC_L2_MONO_R_VOL_SFT 1449 450/* Digital Mixer Control (0x2c) */451#define RT5645_M_STO_L_DAC_L (0x1 << 15)452#define RT5645_M_STO_L_DAC_L_SFT 15453#define RT5645_STO_L_DAC_L_VOL_MASK (0x1 << 14)454#define RT5645_STO_L_DAC_L_VOL_SFT 14455#define RT5645_M_DAC_L2_DAC_L (0x1 << 13)456#define RT5645_M_DAC_L2_DAC_L_SFT 13457#define RT5645_DAC_L2_DAC_L_VOL_MASK (0x1 << 12)458#define RT5645_DAC_L2_DAC_L_VOL_SFT 12459#define RT5645_M_STO_R_DAC_R (0x1 << 11)460#define RT5645_M_STO_R_DAC_R_SFT 11461#define RT5645_STO_R_DAC_R_VOL_MASK (0x1 << 10)462#define RT5645_STO_R_DAC_R_VOL_SFT 10463#define RT5645_M_DAC_R2_DAC_R (0x1 << 9)464#define RT5645_M_DAC_R2_DAC_R_SFT 9465#define RT5645_DAC_R2_DAC_R_VOL_MASK (0x1 << 8)466#define RT5645_DAC_R2_DAC_R_VOL_SFT 8467#define RT5645_M_DAC_R2_DAC_L (0x1 << 7)468#define RT5645_M_DAC_R2_DAC_L_SFT 7469#define RT5645_DAC_R2_DAC_L_VOL_MASK (0x1 << 6)470#define RT5645_DAC_R2_DAC_L_VOL_SFT 6471#define RT5645_M_DAC_L2_DAC_R (0x1 << 5)472#define RT5645_M_DAC_L2_DAC_R_SFT 5473#define RT5645_DAC_L2_DAC_R_VOL_MASK (0x1 << 4)474#define RT5645_DAC_L2_DAC_R_VOL_SFT 4475 476/* Analog DAC1/2 Input Source Control (0x2d) */477#define RT5650_A_DAC1_L_IN_SFT 3478#define RT5650_A_DAC1_R_IN_SFT 2479#define RT5650_A_DAC2_L_IN_SFT 1480#define RT5650_A_DAC2_R_IN_SFT 0481 482/* Digital Interface Data Control (0x2f) */483#define RT5645_IF1_ADC2_IN_SEL (0x1 << 15)484#define RT5645_IF1_ADC2_IN_SFT 15485#define RT5645_IF2_ADC_IN_MASK (0x7 << 12)486#define RT5645_IF2_ADC_IN_SFT 12487#define RT5645_IF2_DAC_SEL_MASK (0x3 << 10)488#define RT5645_IF2_DAC_SEL_SFT 10489#define RT5645_IF2_ADC_SEL_MASK (0x3 << 8)490#define RT5645_IF2_ADC_SEL_SFT 8491#define RT5645_IF3_DAC_SEL_MASK (0x3 << 6)492#define RT5645_IF3_DAC_SEL_SFT 6493#define RT5645_IF3_ADC_SEL_MASK (0x3 << 4)494#define RT5645_IF3_ADC_SEL_SFT 4495#define RT5645_IF3_ADC_IN_MASK (0x7)496#define RT5645_IF3_ADC_IN_SFT 0497 498/* PDM Output Control (0x31) */499#define RT5645_PDM1_L_MASK (0x1 << 15)500#define RT5645_PDM1_L_SFT 15501#define RT5645_M_PDM1_L (0x1 << 14)502#define RT5645_M_PDM1_L_SFT 14503#define RT5645_PDM1_R_MASK (0x1 << 13)504#define RT5645_PDM1_R_SFT 13505#define RT5645_M_PDM1_R (0x1 << 12)506#define RT5645_M_PDM1_R_SFT 12507#define RT5645_PDM2_L_MASK (0x1 << 11)508#define RT5645_PDM2_L_SFT 11509#define RT5645_M_PDM2_L (0x1 << 10)510#define RT5645_M_PDM2_L_SFT 10511#define RT5645_PDM2_R_MASK (0x1 << 9)512#define RT5645_PDM2_R_SFT 9513#define RT5645_M_PDM2_R (0x1 << 8)514#define RT5645_M_PDM2_R_SFT 8515#define RT5645_PDM2_BUSY (0x1 << 7)516#define RT5645_PDM1_BUSY (0x1 << 6)517#define RT5645_PDM_PATTERN (0x1 << 5)518#define RT5645_PDM_GAIN (0x1 << 4)519#define RT5645_PDM_DIV_MASK (0x3)520 521/* REC Left Mixer Control 1 (0x3b) */522#define RT5645_G_HP_L_RM_L_MASK (0x7 << 13)523#define RT5645_G_HP_L_RM_L_SFT 13524#define RT5645_G_IN_L_RM_L_MASK (0x7 << 10)525#define RT5645_G_IN_L_RM_L_SFT 10526#define RT5645_G_BST4_RM_L_MASK (0x7 << 7)527#define RT5645_G_BST4_RM_L_SFT 7528#define RT5645_G_BST3_RM_L_MASK (0x7 << 4)529#define RT5645_G_BST3_RM_L_SFT 4530#define RT5645_G_BST2_RM_L_MASK (0x7 << 1)531#define RT5645_G_BST2_RM_L_SFT 1532 533/* REC Left Mixer Control 2 (0x3c) */534#define RT5645_G_BST1_RM_L_MASK (0x7 << 13)535#define RT5645_G_BST1_RM_L_SFT 13536#define RT5645_G_OM_L_RM_L_MASK (0x7 << 10)537#define RT5645_G_OM_L_RM_L_SFT 10538#define RT5645_M_MM_L_RM_L (0x1 << 6)539#define RT5645_M_MM_L_RM_L_SFT 6540#define RT5645_M_IN_L_RM_L (0x1 << 5)541#define RT5645_M_IN_L_RM_L_SFT 5542#define RT5645_M_HP_L_RM_L (0x1 << 4)543#define RT5645_M_HP_L_RM_L_SFT 4544#define RT5645_M_BST3_RM_L (0x1 << 3)545#define RT5645_M_BST3_RM_L_SFT 3546#define RT5645_M_BST2_RM_L (0x1 << 2)547#define RT5645_M_BST2_RM_L_SFT 2548#define RT5645_M_BST1_RM_L (0x1 << 1)549#define RT5645_M_BST1_RM_L_SFT 1550#define RT5645_M_OM_L_RM_L (0x1)551#define RT5645_M_OM_L_RM_L_SFT 0552 553/* REC Right Mixer Control 1 (0x3d) */554#define RT5645_G_HP_R_RM_R_MASK (0x7 << 13)555#define RT5645_G_HP_R_RM_R_SFT 13556#define RT5645_G_IN_R_RM_R_MASK (0x7 << 10)557#define RT5645_G_IN_R_RM_R_SFT 10558#define RT5645_G_BST4_RM_R_MASK (0x7 << 7)559#define RT5645_G_BST4_RM_R_SFT 7560#define RT5645_G_BST3_RM_R_MASK (0x7 << 4)561#define RT5645_G_BST3_RM_R_SFT 4562#define RT5645_G_BST2_RM_R_MASK (0x7 << 1)563#define RT5645_G_BST2_RM_R_SFT 1564 565/* REC Right Mixer Control 2 (0x3e) */566#define RT5645_G_BST1_RM_R_MASK (0x7 << 13)567#define RT5645_G_BST1_RM_R_SFT 13568#define RT5645_G_OM_R_RM_R_MASK (0x7 << 10)569#define RT5645_G_OM_R_RM_R_SFT 10570#define RT5645_M_MM_R_RM_R (0x1 << 6)571#define RT5645_M_MM_R_RM_R_SFT 6572#define RT5645_M_IN_R_RM_R (0x1 << 5)573#define RT5645_M_IN_R_RM_R_SFT 5574#define RT5645_M_HP_R_RM_R (0x1 << 4)575#define RT5645_M_HP_R_RM_R_SFT 4576#define RT5645_M_BST3_RM_R (0x1 << 3)577#define RT5645_M_BST3_RM_R_SFT 3578#define RT5645_M_BST2_RM_R (0x1 << 2)579#define RT5645_M_BST2_RM_R_SFT 2580#define RT5645_M_BST1_RM_R (0x1 << 1)581#define RT5645_M_BST1_RM_R_SFT 1582#define RT5645_M_OM_R_RM_R (0x1)583#define RT5645_M_OM_R_RM_R_SFT 0584 585/* HPOMIX Control (0x40) (0x42) */586#define RT5645_M_BST1_HV (0x1 << 4)587#define RT5645_M_BST1_HV_SFT 4588#define RT5645_M_BST2_HV (0x1 << 4)589#define RT5645_M_BST2_HV_SFT 4590#define RT5645_M_BST3_HV (0x1 << 3)591#define RT5645_M_BST3_HV_SFT 3592#define RT5645_M_IN_HV (0x1 << 2)593#define RT5645_M_IN_HV_SFT 2594#define RT5645_M_DAC2_HV (0x1 << 1)595#define RT5645_M_DAC2_HV_SFT 1596#define RT5645_M_DAC1_HV (0x1 << 0)597#define RT5645_M_DAC1_HV_SFT 0598 599/* HPMIX Control (0x45) */600#define RT5645_M_DAC1_HM (0x1 << 14)601#define RT5645_M_DAC1_HM_SFT 14602#define RT5645_M_HPVOL_HM (0x1 << 13)603#define RT5645_M_HPVOL_HM_SFT 13604#define RT5645_IRQ_PSV_MODE (0x1 << 12)605 606/* SPK Left Mixer Control (0x46) */607#define RT5645_G_RM_L_SM_L_MASK (0x3 << 14)608#define RT5645_G_RM_L_SM_L_SFT 14609#define RT5645_G_IN_L_SM_L_MASK (0x3 << 12)610#define RT5645_G_IN_L_SM_L_SFT 12611#define RT5645_G_DAC_L1_SM_L_MASK (0x3 << 10)612#define RT5645_G_DAC_L1_SM_L_SFT 10613#define RT5645_G_DAC_L2_SM_L_MASK (0x3 << 8)614#define RT5645_G_DAC_L2_SM_L_SFT 8615#define RT5645_G_OM_L_SM_L_MASK (0x3 << 6)616#define RT5645_G_OM_L_SM_L_SFT 6617#define RT5645_M_BST1_L_SM_L (0x1 << 5)618#define RT5645_M_BST1_L_SM_L_SFT 5619#define RT5645_M_BST3_L_SM_L (0x1 << 4)620#define RT5645_M_BST3_L_SM_L_SFT 4621#define RT5645_M_IN_L_SM_L (0x1 << 3)622#define RT5645_M_IN_L_SM_L_SFT 3623#define RT5645_M_DAC_L2_SM_L (0x1 << 2)624#define RT5645_M_DAC_L2_SM_L_SFT 2625#define RT5645_M_DAC_L1_SM_L (0x1 << 1)626#define RT5645_M_DAC_L1_SM_L_SFT 1627 628/* SPK Right Mixer Control (0x47) */629#define RT5645_G_RM_R_SM_R_MASK (0x3 << 14)630#define RT5645_G_RM_R_SM_R_SFT 14631#define RT5645_G_IN_R_SM_R_MASK (0x3 << 12)632#define RT5645_G_IN_R_SM_R_SFT 12633#define RT5645_G_DAC_R1_SM_R_MASK (0x3 << 10)634#define RT5645_G_DAC_R1_SM_R_SFT 10635#define RT5645_G_DAC_R2_SM_R_MASK (0x3 << 8)636#define RT5645_G_DAC_R2_SM_R_SFT 8637#define RT5645_G_OM_R_SM_R_MASK (0x3 << 6)638#define RT5645_G_OM_R_SM_R_SFT 6639#define RT5645_M_BST2_R_SM_R (0x1 << 5)640#define RT5645_M_BST2_R_SM_R_SFT 5641#define RT5645_M_BST3_R_SM_R (0x1 << 4)642#define RT5645_M_BST3_R_SM_R_SFT 4643#define RT5645_M_IN_R_SM_R (0x1 << 3)644#define RT5645_M_IN_R_SM_R_SFT 3645#define RT5645_M_DAC_R2_SM_R (0x1 << 2)646#define RT5645_M_DAC_R2_SM_R_SFT 2647#define RT5645_M_DAC_R1_SM_R (0x1 << 1)648#define RT5645_M_DAC_R1_SM_R_SFT 1649 650/* SPOLMIX Control (0x48) */651#define RT5645_M_DAC_L1_SPM_L (0x1 << 15)652#define RT5645_M_DAC_L1_SPM_L_SFT 15653#define RT5645_M_DAC_R1_SPM_L (0x1 << 14)654#define RT5645_M_DAC_R1_SPM_L_SFT 14655#define RT5645_M_SV_L_SPM_L (0x1 << 13)656#define RT5645_M_SV_L_SPM_L_SFT 13657#define RT5645_M_SV_R_SPM_L (0x1 << 12)658#define RT5645_M_SV_R_SPM_L_SFT 12659#define RT5645_M_BST3_SPM_L (0x1 << 11)660#define RT5645_M_BST3_SPM_L_SFT 11661#define RT5645_M_DAC_R1_SPM_R (0x1 << 2)662#define RT5645_M_DAC_R1_SPM_R_SFT 2663#define RT5645_M_BST3_SPM_R (0x1 << 1)664#define RT5645_M_BST3_SPM_R_SFT 1665#define RT5645_M_SV_R_SPM_R (0x1 << 0)666#define RT5645_M_SV_R_SPM_R_SFT 0667 668/* SPOMIX Ratio Control (0x4a) */669#define RT5645_SPK_G_CLSD_MASK (0x7 << 0)670#define RT5645_SPK_G_CLSD_SFT 0671 672/* Mono Output Mixer Control (0x4c) */673#define RT5645_G_MONOMIX_MASK (0x1 << 10)674#define RT5645_G_MONOMIX_SFT 10675#define RT5645_M_OV_L_MM (0x1 << 9)676#define RT5645_M_OV_L_MM_SFT 9677#define RT5645_M_DAC_L2_MA (0x1 << 8)678#define RT5645_M_DAC_L2_MA_SFT 8679#define RT5645_M_BST2_MM (0x1 << 4)680#define RT5645_M_BST2_MM_SFT 4681#define RT5645_M_DAC_R1_MM (0x1 << 3)682#define RT5645_M_DAC_R1_MM_SFT 3683#define RT5645_M_DAC_R2_MM (0x1 << 2)684#define RT5645_M_DAC_R2_MM_SFT 2685#define RT5645_M_DAC_L2_MM (0x1 << 1)686#define RT5645_M_DAC_L2_MM_SFT 1687#define RT5645_M_BST3_MM (0x1 << 0)688#define RT5645_M_BST3_MM_SFT 0689 690/* Output Left Mixer Control 1 (0x4d) */691#define RT5645_G_BST3_OM_L_MASK (0x7 << 13)692#define RT5645_G_BST3_OM_L_SFT 13693#define RT5645_G_BST2_OM_L_MASK (0x7 << 10)694#define RT5645_G_BST2_OM_L_SFT 10695#define RT5645_G_BST1_OM_L_MASK (0x7 << 7)696#define RT5645_G_BST1_OM_L_SFT 7697#define RT5645_G_IN_L_OM_L_MASK (0x7 << 4)698#define RT5645_G_IN_L_OM_L_SFT 4699#define RT5645_G_RM_L_OM_L_MASK (0x7 << 1)700#define RT5645_G_RM_L_OM_L_SFT 1701 702/* Output Left Mixer Control 2 (0x4e) */703#define RT5645_G_DAC_R2_OM_L_MASK (0x7 << 13)704#define RT5645_G_DAC_R2_OM_L_SFT 13705#define RT5645_G_DAC_L2_OM_L_MASK (0x7 << 10)706#define RT5645_G_DAC_L2_OM_L_SFT 10707#define RT5645_G_DAC_L1_OM_L_MASK (0x7 << 7)708#define RT5645_G_DAC_L1_OM_L_SFT 7709 710/* Output Left Mixer Control 3 (0x4f) */711#define RT5645_M_BST3_OM_L (0x1 << 4)712#define RT5645_M_BST3_OM_L_SFT 4713#define RT5645_M_BST1_OM_L (0x1 << 3)714#define RT5645_M_BST1_OM_L_SFT 3715#define RT5645_M_IN_L_OM_L (0x1 << 2)716#define RT5645_M_IN_L_OM_L_SFT 2717#define RT5645_M_DAC_L2_OM_L (0x1 << 1)718#define RT5645_M_DAC_L2_OM_L_SFT 1719#define RT5645_M_DAC_L1_OM_L (0x1)720#define RT5645_M_DAC_L1_OM_L_SFT 0721 722/* Output Right Mixer Control 1 (0x50) */723#define RT5645_G_BST4_OM_R_MASK (0x7 << 13)724#define RT5645_G_BST4_OM_R_SFT 13725#define RT5645_G_BST2_OM_R_MASK (0x7 << 10)726#define RT5645_G_BST2_OM_R_SFT 10727#define RT5645_G_BST1_OM_R_MASK (0x7 << 7)728#define RT5645_G_BST1_OM_R_SFT 7729#define RT5645_G_IN_R_OM_R_MASK (0x7 << 4)730#define RT5645_G_IN_R_OM_R_SFT 4731#define RT5645_G_RM_R_OM_R_MASK (0x7 << 1)732#define RT5645_G_RM_R_OM_R_SFT 1733 734/* Output Right Mixer Control 2 (0x51) */735#define RT5645_G_DAC_L2_OM_R_MASK (0x7 << 13)736#define RT5645_G_DAC_L2_OM_R_SFT 13737#define RT5645_G_DAC_R2_OM_R_MASK (0x7 << 10)738#define RT5645_G_DAC_R2_OM_R_SFT 10739#define RT5645_G_DAC_R1_OM_R_MASK (0x7 << 7)740#define RT5645_G_DAC_R1_OM_R_SFT 7741 742/* Output Right Mixer Control 3 (0x52) */743#define RT5645_M_BST3_OM_R (0x1 << 4)744#define RT5645_M_BST3_OM_R_SFT 4745#define RT5645_M_BST2_OM_R (0x1 << 3)746#define RT5645_M_BST2_OM_R_SFT 3747#define RT5645_M_IN_R_OM_R (0x1 << 2)748#define RT5645_M_IN_R_OM_R_SFT 2749#define RT5645_M_DAC_R2_OM_R (0x1 << 1)750#define RT5645_M_DAC_R2_OM_R_SFT 1751#define RT5645_M_DAC_R1_OM_R (0x1)752#define RT5645_M_DAC_R1_OM_R_SFT 0753 754/* LOUT Mixer Control (0x53) */755#define RT5645_M_DAC_L1_LM (0x1 << 15)756#define RT5645_M_DAC_L1_LM_SFT 15757#define RT5645_M_DAC_R1_LM (0x1 << 14)758#define RT5645_M_DAC_R1_LM_SFT 14759#define RT5645_M_OV_L_LM (0x1 << 13)760#define RT5645_M_OV_L_LM_SFT 13761#define RT5645_M_OV_R_LM (0x1 << 12)762#define RT5645_M_OV_R_LM_SFT 12763#define RT5645_G_LOUTMIX_MASK (0x1 << 11)764#define RT5645_G_LOUTMIX_SFT 11765 766/* Power Management for Digital 1 (0x61) */767#define RT5645_PWR_I2S1 (0x1 << 15)768#define RT5645_PWR_I2S1_BIT 15769#define RT5645_PWR_I2S2 (0x1 << 14)770#define RT5645_PWR_I2S2_BIT 14771#define RT5645_PWR_I2S3 (0x1 << 13)772#define RT5645_PWR_I2S3_BIT 13773#define RT5645_PWR_DAC_L1 (0x1 << 12)774#define RT5645_PWR_DAC_L1_BIT 12775#define RT5645_PWR_DAC_R1 (0x1 << 11)776#define RT5645_PWR_DAC_R1_BIT 11777#define RT5645_PWR_CLS_D_R (0x1 << 9)778#define RT5645_PWR_CLS_D_R_BIT 9779#define RT5645_PWR_CLS_D_L (0x1 << 8)780#define RT5645_PWR_CLS_D_L_BIT 8781#define RT5645_PWR_DAC_L2 (0x1 << 7)782#define RT5645_PWR_DAC_L2_BIT 7783#define RT5645_PWR_DAC_R2 (0x1 << 6)784#define RT5645_PWR_DAC_R2_BIT 6785#define RT5645_PWR_ADC_L (0x1 << 2)786#define RT5645_PWR_ADC_L_BIT 2787#define RT5645_PWR_ADC_R (0x1 << 1)788#define RT5645_PWR_ADC_R_BIT 1789#define RT5645_PWR_CLS_D (0x1)790#define RT5645_PWR_CLS_D_BIT 0791 792/* Power Management for Digital 2 (0x62) */793#define RT5645_PWR_ADC_S1F (0x1 << 15)794#define RT5645_PWR_ADC_S1F_BIT 15795#define RT5645_PWR_ADC_MF_L (0x1 << 14)796#define RT5645_PWR_ADC_MF_L_BIT 14797#define RT5645_PWR_ADC_MF_R (0x1 << 13)798#define RT5645_PWR_ADC_MF_R_BIT 13799#define RT5645_PWR_I2S_DSP (0x1 << 12)800#define RT5645_PWR_I2S_DSP_BIT 12801#define RT5645_PWR_DAC_S1F (0x1 << 11)802#define RT5645_PWR_DAC_S1F_BIT 11803#define RT5645_PWR_DAC_MF_L (0x1 << 10)804#define RT5645_PWR_DAC_MF_L_BIT 10805#define RT5645_PWR_DAC_MF_R (0x1 << 9)806#define RT5645_PWR_DAC_MF_R_BIT 9807#define RT5645_PWR_PDM1 (0x1 << 7)808#define RT5645_PWR_PDM1_BIT 7809#define RT5645_PWR_PDM2 (0x1 << 6)810#define RT5645_PWR_PDM2_BIT 6811#define RT5645_PWR_IPTV (0x1 << 1)812#define RT5645_PWR_IPTV_BIT 1813#define RT5645_PWR_PAD (0x1)814#define RT5645_PWR_PAD_BIT 0815 816/* Power Management for Analog 1 (0x63) */817#define RT5645_PWR_VREF1 (0x1 << 15)818#define RT5645_PWR_VREF1_BIT 15819#define RT5645_PWR_FV1 (0x1 << 14)820#define RT5645_PWR_FV1_BIT 14821#define RT5645_PWR_MB (0x1 << 13)822#define RT5645_PWR_MB_BIT 13823#define RT5645_PWR_LM (0x1 << 12)824#define RT5645_PWR_LM_BIT 12825#define RT5645_PWR_BG (0x1 << 11)826#define RT5645_PWR_BG_BIT 11827#define RT5645_PWR_MA (0x1 << 10)828#define RT5645_PWR_MA_BIT 10829#define RT5645_PWR_HP_L (0x1 << 7)830#define RT5645_PWR_HP_L_BIT 7831#define RT5645_PWR_HP_R (0x1 << 6)832#define RT5645_PWR_HP_R_BIT 6833#define RT5645_PWR_HA (0x1 << 5)834#define RT5645_PWR_HA_BIT 5835#define RT5645_PWR_VREF2 (0x1 << 4)836#define RT5645_PWR_VREF2_BIT 4837#define RT5645_PWR_FV2 (0x1 << 3)838#define RT5645_PWR_FV2_BIT 3839#define RT5645_LDO_SEL_MASK (0x3)840#define RT5645_LDO_SEL_SFT 0841 842/* Power Management for Analog 2 (0x64) */843#define RT5645_PWR_BST1 (0x1 << 15)844#define RT5645_PWR_BST1_BIT 15845#define RT5645_PWR_BST2 (0x1 << 14)846#define RT5645_PWR_BST2_BIT 14847#define RT5645_PWR_BST3 (0x1 << 13)848#define RT5645_PWR_BST3_BIT 13849#define RT5645_PWR_BST4 (0x1 << 12)850#define RT5645_PWR_BST4_BIT 12851#define RT5645_PWR_MB1 (0x1 << 11)852#define RT5645_PWR_MB1_BIT 11853#define RT5645_PWR_MB2 (0x1 << 10)854#define RT5645_PWR_MB2_BIT 10855#define RT5645_PWR_PLL (0x1 << 9)856#define RT5645_PWR_PLL_BIT 9857#define RT5645_PWR_BST2_P (0x1 << 5)858#define RT5645_PWR_BST2_P_BIT 5859#define RT5645_PWR_BST3_P (0x1 << 4)860#define RT5645_PWR_BST3_P_BIT 4861#define RT5645_PWR_BST4_P (0x1 << 3)862#define RT5645_PWR_BST4_P_BIT 3863#define RT5645_PWR_JD1 (0x1 << 2)864#define RT5645_PWR_JD1_BIT 2865#define RT5645_PWR_JD (0x1 << 1)866#define RT5645_PWR_JD_BIT 1867 868/* Power Management for Mixer (0x65) */869#define RT5645_PWR_OM_L (0x1 << 15)870#define RT5645_PWR_OM_L_BIT 15871#define RT5645_PWR_OM_R (0x1 << 14)872#define RT5645_PWR_OM_R_BIT 14873#define RT5645_PWR_SM_L (0x1 << 13)874#define RT5645_PWR_SM_L_BIT 13875#define RT5645_PWR_SM_R (0x1 << 12)876#define RT5645_PWR_SM_R_BIT 12877#define RT5645_PWR_RM_L (0x1 << 11)878#define RT5645_PWR_RM_L_BIT 11879#define RT5645_PWR_RM_R (0x1 << 10)880#define RT5645_PWR_RM_R_BIT 10881#define RT5645_PWR_MM (0x1 << 8)882#define RT5645_PWR_MM_BIT 8883#define RT5645_PWR_HM_L (0x1 << 7)884#define RT5645_PWR_HM_L_BIT 7885#define RT5645_PWR_HM_R (0x1 << 6)886#define RT5645_PWR_HM_R_BIT 6887#define RT5645_PWR_LDO2 (0x1 << 1)888#define RT5645_PWR_LDO2_BIT 1889 890/* Power Management for Volume (0x66) */891#define RT5645_PWR_SV_L (0x1 << 15)892#define RT5645_PWR_SV_L_BIT 15893#define RT5645_PWR_SV_R (0x1 << 14)894#define RT5645_PWR_SV_R_BIT 14895#define RT5645_PWR_HV_L (0x1 << 11)896#define RT5645_PWR_HV_L_BIT 11897#define RT5645_PWR_HV_R (0x1 << 10)898#define RT5645_PWR_HV_R_BIT 10899#define RT5645_PWR_IN_L (0x1 << 9)900#define RT5645_PWR_IN_L_BIT 9901#define RT5645_PWR_IN_R (0x1 << 8)902#define RT5645_PWR_IN_R_BIT 8903#define RT5645_PWR_MIC_DET (0x1 << 5)904#define RT5645_PWR_MIC_DET_BIT 5905 906/* I2S1/2 Audio Serial Data Port Control (0x70 0x71) */907#define RT5645_I2S_MS_MASK (0x1 << 15)908#define RT5645_I2S_MS_SFT 15909#define RT5645_I2S_MS_M (0x0 << 15)910#define RT5645_I2S_MS_S (0x1 << 15)911#define RT5645_I2S_O_CP_MASK (0x3 << 10)912#define RT5645_I2S_O_CP_SFT 10913#define RT5645_I2S_O_CP_OFF (0x0 << 10)914#define RT5645_I2S_O_CP_U_LAW (0x1 << 10)915#define RT5645_I2S_O_CP_A_LAW (0x2 << 10)916#define RT5645_I2S_I_CP_MASK (0x3 << 8)917#define RT5645_I2S_I_CP_SFT 8918#define RT5645_I2S_I_CP_OFF (0x0 << 8)919#define RT5645_I2S_I_CP_U_LAW (0x1 << 8)920#define RT5645_I2S_I_CP_A_LAW (0x2 << 8)921#define RT5645_I2S_BP_MASK (0x1 << 7)922#define RT5645_I2S_BP_SFT 7923#define RT5645_I2S_BP_NOR (0x0 << 7)924#define RT5645_I2S_BP_INV (0x1 << 7)925#define RT5645_I2S_DL_MASK (0x3 << 2)926#define RT5645_I2S_DL_SFT 2927#define RT5645_I2S_DL_16 (0x0 << 2)928#define RT5645_I2S_DL_20 (0x1 << 2)929#define RT5645_I2S_DL_24 (0x2 << 2)930#define RT5645_I2S_DL_8 (0x3 << 2)931#define RT5645_I2S_DF_MASK (0x3)932#define RT5645_I2S_DF_SFT 0933#define RT5645_I2S_DF_I2S (0x0)934#define RT5645_I2S_DF_LEFT (0x1)935#define RT5645_I2S_DF_PCM_A (0x2)936#define RT5645_I2S_DF_PCM_B (0x3)937 938/* I2S2 Audio Serial Data Port Control (0x71) */939#define RT5645_I2S2_SDI_MASK (0x1 << 6)940#define RT5645_I2S2_SDI_SFT 6941#define RT5645_I2S2_SDI_I2S1 (0x0 << 6)942#define RT5645_I2S2_SDI_I2S2 (0x1 << 6)943 944/* ADC/DAC Clock Control 1 (0x73) */945#define RT5645_I2S_PD1_MASK (0x7 << 12)946#define RT5645_I2S_PD1_SFT 12947#define RT5645_I2S_PD1_1 (0x0 << 12)948#define RT5645_I2S_PD1_2 (0x1 << 12)949#define RT5645_I2S_PD1_3 (0x2 << 12)950#define RT5645_I2S_PD1_4 (0x3 << 12)951#define RT5645_I2S_PD1_6 (0x4 << 12)952#define RT5645_I2S_PD1_8 (0x5 << 12)953#define RT5645_I2S_PD1_12 (0x6 << 12)954#define RT5645_I2S_PD1_16 (0x7 << 12)955#define RT5645_I2S_BCLK_MS2_MASK (0x1 << 11)956#define RT5645_I2S_BCLK_MS2_SFT 11957#define RT5645_I2S_BCLK_MS2_32 (0x0 << 11)958#define RT5645_I2S_BCLK_MS2_64 (0x1 << 11)959#define RT5645_I2S_PD2_MASK (0x7 << 8)960#define RT5645_I2S_PD2_SFT 8961#define RT5645_I2S_PD2_1 (0x0 << 8)962#define RT5645_I2S_PD2_2 (0x1 << 8)963#define RT5645_I2S_PD2_3 (0x2 << 8)964#define RT5645_I2S_PD2_4 (0x3 << 8)965#define RT5645_I2S_PD2_6 (0x4 << 8)966#define RT5645_I2S_PD2_8 (0x5 << 8)967#define RT5645_I2S_PD2_12 (0x6 << 8)968#define RT5645_I2S_PD2_16 (0x7 << 8)969#define RT5645_I2S_BCLK_MS3_MASK (0x1 << 7)970#define RT5645_I2S_BCLK_MS3_SFT 7971#define RT5645_I2S_BCLK_MS3_32 (0x0 << 7)972#define RT5645_I2S_BCLK_MS3_64 (0x1 << 7)973#define RT5645_I2S_PD3_MASK (0x7 << 4)974#define RT5645_I2S_PD3_SFT 4975#define RT5645_I2S_PD3_1 (0x0 << 4)976#define RT5645_I2S_PD3_2 (0x1 << 4)977#define RT5645_I2S_PD3_3 (0x2 << 4)978#define RT5645_I2S_PD3_4 (0x3 << 4)979#define RT5645_I2S_PD3_6 (0x4 << 4)980#define RT5645_I2S_PD3_8 (0x5 << 4)981#define RT5645_I2S_PD3_12 (0x6 << 4)982#define RT5645_I2S_PD3_16 (0x7 << 4)983#define RT5645_DAC_OSR_MASK (0x3 << 2)984#define RT5645_DAC_OSR_SFT 2985#define RT5645_DAC_OSR_128 (0x0 << 2)986#define RT5645_DAC_OSR_64 (0x1 << 2)987#define RT5645_DAC_OSR_32 (0x2 << 2)988#define RT5645_DAC_OSR_16 (0x3 << 2)989#define RT5645_ADC_OSR_MASK (0x3)990#define RT5645_ADC_OSR_SFT 0991#define RT5645_ADC_OSR_128 (0x0)992#define RT5645_ADC_OSR_64 (0x1)993#define RT5645_ADC_OSR_32 (0x2)994#define RT5645_ADC_OSR_16 (0x3)995 996/* ADC/DAC Clock Control 2 (0x74) */997#define RT5645_DAC_L_OSR_MASK (0x3 << 14)998#define RT5645_DAC_L_OSR_SFT 14999#define RT5645_DAC_L_OSR_128 (0x0 << 14)1000#define RT5645_DAC_L_OSR_64 (0x1 << 14)1001#define RT5645_DAC_L_OSR_32 (0x2 << 14)1002#define RT5645_DAC_L_OSR_16 (0x3 << 14)1003#define RT5645_ADC_R_OSR_MASK (0x3 << 12)1004#define RT5645_ADC_R_OSR_SFT 121005#define RT5645_ADC_R_OSR_128 (0x0 << 12)1006#define RT5645_ADC_R_OSR_64 (0x1 << 12)1007#define RT5645_ADC_R_OSR_32 (0x2 << 12)1008#define RT5645_ADC_R_OSR_16 (0x3 << 12)1009#define RT5645_DAHPF_EN (0x1 << 11)1010#define RT5645_DAHPF_EN_SFT 111011#define RT5645_ADHPF_EN (0x1 << 10)1012#define RT5645_ADHPF_EN_SFT 101013 1014/* Digital Microphone Control (0x75) */1015#define RT5645_DMIC_1_EN_MASK (0x1 << 15)1016#define RT5645_DMIC_1_EN_SFT 151017#define RT5645_DMIC_1_DIS (0x0 << 15)1018#define RT5645_DMIC_1_EN (0x1 << 15)1019#define RT5645_DMIC_2_EN_MASK (0x1 << 14)1020#define RT5645_DMIC_2_EN_SFT 141021#define RT5645_DMIC_2_DIS (0x0 << 14)1022#define RT5645_DMIC_2_EN (0x1 << 14)1023#define RT5645_DMIC_1L_LH_MASK (0x1 << 13)1024#define RT5645_DMIC_1L_LH_SFT 131025#define RT5645_DMIC_1L_LH_FALLING (0x0 << 13)1026#define RT5645_DMIC_1L_LH_RISING (0x1 << 13)1027#define RT5645_DMIC_1R_LH_MASK (0x1 << 12)1028#define RT5645_DMIC_1R_LH_SFT 121029#define RT5645_DMIC_1R_LH_FALLING (0x0 << 12)1030#define RT5645_DMIC_1R_LH_RISING (0x1 << 12)1031#define RT5645_DMIC_2_DP_MASK (0x3 << 10)1032#define RT5645_DMIC_2_DP_SFT 101033#define RT5645_DMIC_2_DP_GPIO6 (0x0 << 10)1034#define RT5645_DMIC_2_DP_GPIO10 (0x1 << 10)1035#define RT5645_DMIC_2_DP_GPIO12 (0x2 << 10)1036#define RT5645_DMIC_2_DP_IN2P (0x3 << 10)1037#define RT5645_DMIC_2L_LH_MASK (0x1 << 9)1038#define RT5645_DMIC_2L_LH_SFT 91039#define RT5645_DMIC_2L_LH_FALLING (0x0 << 9)1040#define RT5645_DMIC_2L_LH_RISING (0x1 << 9)1041#define RT5645_DMIC_2R_LH_MASK (0x1 << 8)1042#define RT5645_DMIC_2R_LH_SFT 81043#define RT5645_DMIC_2R_LH_FALLING (0x0 << 8)1044#define RT5645_DMIC_2R_LH_RISING (0x1 << 8)1045#define RT5645_DMIC_CLK_MASK (0x7 << 5)1046#define RT5645_DMIC_CLK_SFT 51047#define RT5645_DMIC_3_EN_MASK (0x1 << 4)1048#define RT5645_DMIC_3_EN_SFT 41049#define RT5645_DMIC_3_DIS (0x0 << 4)1050#define RT5645_DMIC_3_EN (0x1 << 4)1051#define RT5645_DMIC_1_DP_MASK (0x3 << 0)1052#define RT5645_DMIC_1_DP_SFT 01053#define RT5645_DMIC_1_DP_GPIO5 (0x0 << 0)1054#define RT5645_DMIC_1_DP_IN2N (0x1 << 0)1055#define RT5645_DMIC_1_DP_GPIO11 (0x2 << 0)1056 1057/* TDM Control 1 (0x77) */1058#define RT5645_IF1_ADC_IN_MASK (0x3 << 8)1059#define RT5645_IF1_ADC_IN_SFT 81060 1061/* Global Clock Control (0x80) */1062#define RT5645_SCLK_SRC_MASK (0x3 << 14)1063#define RT5645_SCLK_SRC_SFT 141064#define RT5645_SCLK_SRC_MCLK (0x0 << 14)1065#define RT5645_SCLK_SRC_PLL1 (0x1 << 14)1066#define RT5645_SCLK_SRC_RCCLK (0x2 << 14)1067#define RT5645_PLL1_SRC_MASK (0x7 << 11)1068#define RT5645_PLL1_SRC_SFT 111069#define RT5645_PLL1_SRC_MCLK (0x0 << 11)1070#define RT5645_PLL1_SRC_BCLK1 (0x1 << 11)1071#define RT5645_PLL1_SRC_BCLK2 (0x2 << 11)1072#define RT5645_PLL1_SRC_BCLK3 (0x3 << 11)1073#define RT5645_PLL1_SRC_RCCLK (0x4 << 11)1074#define RT5645_PLL1_PD_MASK (0x1 << 3)1075#define RT5645_PLL1_PD_SFT 31076#define RT5645_PLL1_PD_1 (0x0 << 3)1077#define RT5645_PLL1_PD_2 (0x1 << 3)1078 1079#define RT5645_PLL_INP_MAX 400000001080#define RT5645_PLL_INP_MIN 2560001081/* PLL M/N/K Code Control 1 (0x81) */1082#define RT5645_PLL_N_MAX 0x1ff1083#define RT5645_PLL_N_MASK (RT5645_PLL_N_MAX << 7)1084#define RT5645_PLL_N_SFT 71085#define RT5645_PLL_K_MAX 0x1f1086#define RT5645_PLL_K_MASK (RT5645_PLL_K_MAX)1087#define RT5645_PLL_K_SFT 01088 1089/* PLL M/N/K Code Control 2 (0x82) */1090#define RT5645_PLL_M_MAX 0xf1091#define RT5645_PLL_M_MASK (RT5645_PLL_M_MAX << 12)1092#define RT5645_PLL_M_SFT 121093#define RT5645_PLL_M_BP (0x1 << 11)1094#define RT5645_PLL_M_BP_SFT 111095 1096/* ASRC Control 1 (0x83) */1097#define RT5645_STO_T_MASK (0x1 << 15)1098#define RT5645_STO_T_SFT 151099#define RT5645_STO_T_SCLK (0x0 << 15)1100#define RT5645_STO_T_LRCK1 (0x1 << 15)1101#define RT5645_M1_T_MASK (0x1 << 14)1102#define RT5645_M1_T_SFT 141103#define RT5645_M1_T_I2S2 (0x0 << 14)1104#define RT5645_M1_T_I2S2_D3 (0x1 << 14)1105#define RT5645_I2S2_F_MASK (0x1 << 12)1106#define RT5645_I2S2_F_SFT 121107#define RT5645_I2S2_F_I2S2_D2 (0x0 << 12)1108#define RT5645_I2S2_F_I2S1_TCLK (0x1 << 12)1109#define RT5645_DMIC_1_M_MASK (0x1 << 9)1110#define RT5645_DMIC_1_M_SFT 91111#define RT5645_DMIC_1_M_NOR (0x0 << 9)1112#define RT5645_DMIC_1_M_ASYN (0x1 << 9)1113#define RT5645_DMIC_2_M_MASK (0x1 << 8)1114#define RT5645_DMIC_2_M_SFT 81115#define RT5645_DMIC_2_M_NOR (0x0 << 8)1116#define RT5645_DMIC_2_M_ASYN (0x1 << 8)1117 1118/* ASRC clock source selection (0x84, 0x85) */1119#define RT5645_CLK_SEL_SYS (0x0)1120#define RT5645_CLK_SEL_I2S1_ASRC (0x1)1121#define RT5645_CLK_SEL_I2S2_ASRC (0x2)1122#define RT5645_CLK_SEL_SYS2 (0x5)1123 1124/* ASRC Control 2 (0x84) */1125#define RT5645_DA_STO_CLK_SEL_MASK (0xf << 12)1126#define RT5645_DA_STO_CLK_SEL_SFT 121127#define RT5645_DA_MONOL_CLK_SEL_MASK (0xf << 8)1128#define RT5645_DA_MONOL_CLK_SEL_SFT 81129#define RT5645_DA_MONOR_CLK_SEL_MASK (0xf << 4)1130#define RT5645_DA_MONOR_CLK_SEL_SFT 41131#define RT5645_AD_STO1_CLK_SEL_MASK (0xf << 0)1132#define RT5645_AD_STO1_CLK_SEL_SFT 01133 1134/* ASRC Control 3 (0x85) */1135#define RT5645_AD_MONOL_CLK_SEL_MASK (0xf << 4)1136#define RT5645_AD_MONOL_CLK_SEL_SFT 41137#define RT5645_AD_MONOR_CLK_SEL_MASK (0xf << 0)1138#define RT5645_AD_MONOR_CLK_SEL_SFT 01139 1140/* ASRC Control 4 (0x89) */1141#define RT5645_I2S1_PD_MASK (0x7 << 12)1142#define RT5645_I2S1_PD_SFT 121143#define RT5645_I2S2_PD_MASK (0x7 << 8)1144#define RT5645_I2S2_PD_SFT 81145 1146/* HPOUT Over Current Detection (0x8b) */1147#define RT5645_HP_OVCD_MASK (0x1 << 10)1148#define RT5645_HP_OVCD_SFT 101149#define RT5645_HP_OVCD_DIS (0x0 << 10)1150#define RT5645_HP_OVCD_EN (0x1 << 10)1151#define RT5645_HP_OC_TH_MASK (0x3 << 8)1152#define RT5645_HP_OC_TH_SFT 81153#define RT5645_HP_OC_TH_90 (0x0 << 8)1154#define RT5645_HP_OC_TH_105 (0x1 << 8)1155#define RT5645_HP_OC_TH_120 (0x2 << 8)1156#define RT5645_HP_OC_TH_135 (0x3 << 8)1157 1158/* Class D Over Current Control (0x8c) */1159#define RT5645_CLSD_OC_MASK (0x1 << 9)1160#define RT5645_CLSD_OC_SFT 91161#define RT5645_CLSD_OC_PU (0x0 << 9)1162#define RT5645_CLSD_OC_PD (0x1 << 9)1163#define RT5645_AUTO_PD_MASK (0x1 << 8)1164#define RT5645_AUTO_PD_SFT 81165#define RT5645_AUTO_PD_DIS (0x0 << 8)1166#define RT5645_AUTO_PD_EN (0x1 << 8)1167#define RT5645_CLSD_OC_TH_MASK (0x3f)1168#define RT5645_CLSD_OC_TH_SFT 01169 1170/* Class D Output Control (0x8d) */1171#define RT5645_CLSD_RATIO_MASK (0xf << 12)1172#define RT5645_CLSD_RATIO_SFT 121173#define RT5645_CLSD_OM_MASK (0x1 << 11)1174#define RT5645_CLSD_OM_SFT 111175#define RT5645_CLSD_OM_MONO (0x0 << 11)1176#define RT5645_CLSD_OM_STO (0x1 << 11)1177#define RT5645_CLSD_SCH_MASK (0x1 << 10)1178#define RT5645_CLSD_SCH_SFT 101179#define RT5645_CLSD_SCH_L (0x0 << 10)1180#define RT5645_CLSD_SCH_S (0x1 << 10)1181 1182/* Depop Mode Control 1 (0x8e) */1183#define RT5645_SMT_TRIG_MASK (0x1 << 15)1184#define RT5645_SMT_TRIG_SFT 151185#define RT5645_SMT_TRIG_DIS (0x0 << 15)1186#define RT5645_SMT_TRIG_EN (0x1 << 15)1187#define RT5645_HP_L_SMT_MASK (0x1 << 9)1188#define RT5645_HP_L_SMT_SFT 91189#define RT5645_HP_L_SMT_DIS (0x0 << 9)1190#define RT5645_HP_L_SMT_EN (0x1 << 9)1191#define RT5645_HP_R_SMT_MASK (0x1 << 8)1192#define RT5645_HP_R_SMT_SFT 81193#define RT5645_HP_R_SMT_DIS (0x0 << 8)1194#define RT5645_HP_R_SMT_EN (0x1 << 8)1195#define RT5645_HP_CD_PD_MASK (0x1 << 7)1196#define RT5645_HP_CD_PD_SFT 71197#define RT5645_HP_CD_PD_DIS (0x0 << 7)1198#define RT5645_HP_CD_PD_EN (0x1 << 7)1199#define RT5645_RSTN_MASK (0x1 << 6)1200#define RT5645_RSTN_SFT 61201#define RT5645_RSTN_DIS (0x0 << 6)1202#define RT5645_RSTN_EN (0x1 << 6)1203#define RT5645_RSTP_MASK (0x1 << 5)1204#define RT5645_RSTP_SFT 51205#define RT5645_RSTP_DIS (0x0 << 5)1206#define RT5645_RSTP_EN (0x1 << 5)1207#define RT5645_HP_CO_MASK (0x1 << 4)1208#define RT5645_HP_CO_SFT 41209#define RT5645_HP_CO_DIS (0x0 << 4)1210#define RT5645_HP_CO_EN (0x1 << 4)1211#define RT5645_HP_CP_MASK (0x1 << 3)1212#define RT5645_HP_CP_SFT 31213#define RT5645_HP_CP_PD (0x0 << 3)1214#define RT5645_HP_CP_PU (0x1 << 3)1215#define RT5645_HP_SG_MASK (0x1 << 2)1216#define RT5645_HP_SG_SFT 21217#define RT5645_HP_SG_DIS (0x0 << 2)1218#define RT5645_HP_SG_EN (0x1 << 2)1219#define RT5645_HP_DP_MASK (0x1 << 1)1220#define RT5645_HP_DP_SFT 11221#define RT5645_HP_DP_PD (0x0 << 1)1222#define RT5645_HP_DP_PU (0x1 << 1)1223#define RT5645_HP_CB_MASK (0x1)1224#define RT5645_HP_CB_SFT 01225#define RT5645_HP_CB_PD (0x0)1226#define RT5645_HP_CB_PU (0x1)1227 1228/* Depop Mode Control 2 (0x8f) */1229#define RT5645_DEPOP_MASK (0x1 << 13)1230#define RT5645_DEPOP_SFT 131231#define RT5645_DEPOP_AUTO (0x0 << 13)1232#define RT5645_DEPOP_MAN (0x1 << 13)1233#define RT5645_RAMP_MASK (0x1 << 12)1234#define RT5645_RAMP_SFT 121235#define RT5645_RAMP_DIS (0x0 << 12)1236#define RT5645_RAMP_EN (0x1 << 12)1237#define RT5645_BPS_MASK (0x1 << 11)1238#define RT5645_BPS_SFT 111239#define RT5645_BPS_DIS (0x0 << 11)1240#define RT5645_BPS_EN (0x1 << 11)1241#define RT5645_FAST_UPDN_MASK (0x1 << 10)1242#define RT5645_FAST_UPDN_SFT 101243#define RT5645_FAST_UPDN_DIS (0x0 << 10)1244#define RT5645_FAST_UPDN_EN (0x1 << 10)1245#define RT5645_MRES_MASK (0x3 << 8)1246#define RT5645_MRES_SFT 81247#define RT5645_MRES_15MO (0x0 << 8)1248#define RT5645_MRES_25MO (0x1 << 8)1249#define RT5645_MRES_35MO (0x2 << 8)1250#define RT5645_MRES_45MO (0x3 << 8)1251#define RT5645_VLO_MASK (0x1 << 7)1252#define RT5645_VLO_SFT 71253#define RT5645_VLO_3V (0x0 << 7)1254#define RT5645_VLO_32V (0x1 << 7)1255#define RT5645_DIG_DP_MASK (0x1 << 6)1256#define RT5645_DIG_DP_SFT 61257#define RT5645_DIG_DP_DIS (0x0 << 6)1258#define RT5645_DIG_DP_EN (0x1 << 6)1259#define RT5645_DP_TH_MASK (0x3 << 4)1260#define RT5645_DP_TH_SFT 41261 1262/* Depop Mode Control 3 (0x90) */1263#define RT5645_CP_SYS_MASK (0x7 << 12)1264#define RT5645_CP_SYS_SFT 121265#define RT5645_CP_FQ1_MASK (0x7 << 8)1266#define RT5645_CP_FQ1_SFT 81267#define RT5645_CP_FQ2_MASK (0x7 << 4)1268#define RT5645_CP_FQ2_SFT 41269#define RT5645_CP_FQ3_MASK (0x7)1270#define RT5645_CP_FQ3_SFT 01271#define RT5645_CP_FQ_1_5_KHZ 01272#define RT5645_CP_FQ_3_KHZ 11273#define RT5645_CP_FQ_6_KHZ 21274#define RT5645_CP_FQ_12_KHZ 31275#define RT5645_CP_FQ_24_KHZ 41276#define RT5645_CP_FQ_48_KHZ 51277#define RT5645_CP_FQ_96_KHZ 61278#define RT5645_CP_FQ_192_KHZ 71279 1280/* PV detection and SPK gain control (0x92) */1281#define RT5645_PVDD_DET_MASK (0x1 << 15)1282#define RT5645_PVDD_DET_SFT 151283#define RT5645_PVDD_DET_DIS (0x0 << 15)1284#define RT5645_PVDD_DET_EN (0x1 << 15)1285#define RT5645_SPK_AG_MASK (0x1 << 14)1286#define RT5645_SPK_AG_SFT 141287#define RT5645_SPK_AG_DIS (0x0 << 14)1288#define RT5645_SPK_AG_EN (0x1 << 14)1289 1290/* Micbias Control (0x93) */1291#define RT5645_MIC1_BS_MASK (0x1 << 15)1292#define RT5645_MIC1_BS_SFT 151293#define RT5645_MIC1_BS_9AV (0x0 << 15)1294#define RT5645_MIC1_BS_75AV (0x1 << 15)1295#define RT5645_MIC2_BS_MASK (0x1 << 14)1296#define RT5645_MIC2_BS_SFT 141297#define RT5645_MIC2_BS_9AV (0x0 << 14)1298#define RT5645_MIC2_BS_75AV (0x1 << 14)1299#define RT5645_MIC1_CLK_MASK (0x1 << 13)1300#define RT5645_MIC1_CLK_SFT 131301#define RT5645_MIC1_CLK_DIS (0x0 << 13)1302#define RT5645_MIC1_CLK_EN (0x1 << 13)1303#define RT5645_MIC2_CLK_MASK (0x1 << 12)1304#define RT5645_MIC2_CLK_SFT 121305#define RT5645_MIC2_CLK_DIS (0x0 << 12)1306#define RT5645_MIC2_CLK_EN (0x1 << 12)1307#define RT5645_MIC1_OVCD_MASK (0x1 << 11)1308#define RT5645_MIC1_OVCD_SFT 111309#define RT5645_MIC1_OVCD_DIS (0x0 << 11)1310#define RT5645_MIC1_OVCD_EN (0x1 << 11)1311#define RT5645_MIC1_OVTH_MASK (0x3 << 9)1312#define RT5645_MIC1_OVTH_SFT 91313#define RT5645_MIC1_OVTH_600UA (0x0 << 9)1314#define RT5645_MIC1_OVTH_1500UA (0x1 << 9)1315#define RT5645_MIC1_OVTH_2000UA (0x2 << 9)1316#define RT5645_MIC2_OVCD_MASK (0x1 << 8)1317#define RT5645_MIC2_OVCD_SFT 81318#define RT5645_MIC2_OVCD_DIS (0x0 << 8)1319#define RT5645_MIC2_OVCD_EN (0x1 << 8)1320#define RT5645_MIC2_OVTH_MASK (0x3 << 6)1321#define RT5645_MIC2_OVTH_SFT 61322#define RT5645_MIC2_OVTH_600UA (0x0 << 6)1323#define RT5645_MIC2_OVTH_1500UA (0x1 << 6)1324#define RT5645_MIC2_OVTH_2000UA (0x2 << 6)1325#define RT5645_PWR_MB_MASK (0x1 << 5)1326#define RT5645_PWR_MB_SFT 51327#define RT5645_PWR_MB_PD (0x0 << 5)1328#define RT5645_PWR_MB_PU (0x1 << 5)1329#define RT5645_PWR_CLK25M_MASK (0x1 << 4)1330#define RT5645_PWR_CLK25M_SFT 41331#define RT5645_PWR_CLK25M_PD (0x0 << 4)1332#define RT5645_PWR_CLK25M_PU (0x1 << 4)1333#define RT5645_IRQ_CLK_MCLK (0x0 << 3)1334#define RT5645_IRQ_CLK_INT (0x1 << 3)1335#define RT5645_JD1_MODE_MASK (0x3 << 0)1336#define RT5645_JD1_MODE_0 (0x0 << 0)1337#define RT5645_JD1_MODE_1 (0x1 << 0)1338#define RT5645_JD1_MODE_2 (0x2 << 0)1339 1340/* VAD Control 4 (0x9d) */1341#define RT5645_VAD_SEL_MASK (0x3 << 8)1342#define RT5645_VAD_SEL_SFT 81343 1344/* EQ Control 1 (0xb0) */1345#define RT5645_EQ_SRC_MASK (0x1 << 15)1346#define RT5645_EQ_SRC_SFT 151347#define RT5645_EQ_SRC_DAC (0x0 << 15)1348#define RT5645_EQ_SRC_ADC (0x1 << 15)1349#define RT5645_EQ_UPD (0x1 << 14)1350#define RT5645_EQ_UPD_BIT 141351#define RT5645_EQ_CD_MASK (0x1 << 13)1352#define RT5645_EQ_CD_SFT 131353#define RT5645_EQ_CD_DIS (0x0 << 13)1354#define RT5645_EQ_CD_EN (0x1 << 13)1355#define RT5645_EQ_DITH_MASK (0x3 << 8)1356#define RT5645_EQ_DITH_SFT 81357#define RT5645_EQ_DITH_NOR (0x0 << 8)1358#define RT5645_EQ_DITH_LSB (0x1 << 8)1359#define RT5645_EQ_DITH_LSB_1 (0x2 << 8)1360#define RT5645_EQ_DITH_LSB_2 (0x3 << 8)1361 1362/* EQ Control 2 (0xb1) */1363#define RT5645_EQ_HPF1_M_MASK (0x1 << 8)1364#define RT5645_EQ_HPF1_M_SFT 81365#define RT5645_EQ_HPF1_M_HI (0x0 << 8)1366#define RT5645_EQ_HPF1_M_1ST (0x1 << 8)1367#define RT5645_EQ_LPF1_M_MASK (0x1 << 7)1368#define RT5645_EQ_LPF1_M_SFT 71369#define RT5645_EQ_LPF1_M_LO (0x0 << 7)1370#define RT5645_EQ_LPF1_M_1ST (0x1 << 7)1371#define RT5645_EQ_HPF2_MASK (0x1 << 6)1372#define RT5645_EQ_HPF2_SFT 61373#define RT5645_EQ_HPF2_DIS (0x0 << 6)1374#define RT5645_EQ_HPF2_EN (0x1 << 6)1375#define RT5645_EQ_HPF1_MASK (0x1 << 5)1376#define RT5645_EQ_HPF1_SFT 51377#define RT5645_EQ_HPF1_DIS (0x0 << 5)1378#define RT5645_EQ_HPF1_EN (0x1 << 5)1379#define RT5645_EQ_BPF4_MASK (0x1 << 4)1380#define RT5645_EQ_BPF4_SFT 41381#define RT5645_EQ_BPF4_DIS (0x0 << 4)1382#define RT5645_EQ_BPF4_EN (0x1 << 4)1383#define RT5645_EQ_BPF3_MASK (0x1 << 3)1384#define RT5645_EQ_BPF3_SFT 31385#define RT5645_EQ_BPF3_DIS (0x0 << 3)1386#define RT5645_EQ_BPF3_EN (0x1 << 3)1387#define RT5645_EQ_BPF2_MASK (0x1 << 2)1388#define RT5645_EQ_BPF2_SFT 21389#define RT5645_EQ_BPF2_DIS (0x0 << 2)1390#define RT5645_EQ_BPF2_EN (0x1 << 2)1391#define RT5645_EQ_BPF1_MASK (0x1 << 1)1392#define RT5645_EQ_BPF1_SFT 11393#define RT5645_EQ_BPF1_DIS (0x0 << 1)1394#define RT5645_EQ_BPF1_EN (0x1 << 1)1395#define RT5645_EQ_LPF_MASK (0x1)1396#define RT5645_EQ_LPF_SFT 01397#define RT5645_EQ_LPF_DIS (0x0)1398#define RT5645_EQ_LPF_EN (0x1)1399#define RT5645_EQ_CTRL_MASK (0x7f)1400 1401/* Memory Test (0xb2) */1402#define RT5645_MT_MASK (0x1 << 15)1403#define RT5645_MT_SFT 151404#define RT5645_MT_DIS (0x0 << 15)1405#define RT5645_MT_EN (0x1 << 15)1406 1407/* DRC/AGC Control 1 (0xb4) */1408#define RT5645_DRC_AGC_P_MASK (0x1 << 15)1409#define RT5645_DRC_AGC_P_SFT 151410#define RT5645_DRC_AGC_P_DAC (0x0 << 15)1411#define RT5645_DRC_AGC_P_ADC (0x1 << 15)1412#define RT5645_DRC_AGC_MASK (0x1 << 14)1413#define RT5645_DRC_AGC_SFT 141414#define RT5645_DRC_AGC_DIS (0x0 << 14)1415#define RT5645_DRC_AGC_EN (0x1 << 14)1416#define RT5645_DRC_AGC_UPD (0x1 << 13)1417#define RT5645_DRC_AGC_UPD_BIT 131418#define RT5645_DRC_AGC_AR_MASK (0x1f << 8)1419#define RT5645_DRC_AGC_AR_SFT 81420#define RT5645_DRC_AGC_R_MASK (0x7 << 5)1421#define RT5645_DRC_AGC_R_SFT 51422#define RT5645_DRC_AGC_R_48K (0x1 << 5)1423#define RT5645_DRC_AGC_R_96K (0x2 << 5)1424#define RT5645_DRC_AGC_R_192K (0x3 << 5)1425#define RT5645_DRC_AGC_R_441K (0x5 << 5)1426#define RT5645_DRC_AGC_R_882K (0x6 << 5)1427#define RT5645_DRC_AGC_R_1764K (0x7 << 5)1428#define RT5645_DRC_AGC_RC_MASK (0x1f)1429#define RT5645_DRC_AGC_RC_SFT 01430 1431/* DRC/AGC Control 2 (0xb5) */1432#define RT5645_DRC_AGC_POB_MASK (0x3f << 8)1433#define RT5645_DRC_AGC_POB_SFT 81434#define RT5645_DRC_AGC_CP_MASK (0x1 << 7)1435#define RT5645_DRC_AGC_CP_SFT 71436#define RT5645_DRC_AGC_CP_DIS (0x0 << 7)1437#define RT5645_DRC_AGC_CP_EN (0x1 << 7)1438#define RT5645_DRC_AGC_CPR_MASK (0x3 << 5)1439#define RT5645_DRC_AGC_CPR_SFT 51440#define RT5645_DRC_AGC_CPR_1_1 (0x0 << 5)1441#define RT5645_DRC_AGC_CPR_1_2 (0x1 << 5)1442#define RT5645_DRC_AGC_CPR_1_3 (0x2 << 5)1443#define RT5645_DRC_AGC_CPR_1_4 (0x3 << 5)1444#define RT5645_DRC_AGC_PRB_MASK (0x1f)1445#define RT5645_DRC_AGC_PRB_SFT 01446 1447/* DRC/AGC Control 3 (0xb6) */1448#define RT5645_DRC_AGC_NGB_MASK (0xf << 12)1449#define RT5645_DRC_AGC_NGB_SFT 121450#define RT5645_DRC_AGC_TAR_MASK (0x1f << 7)1451#define RT5645_DRC_AGC_TAR_SFT 71452#define RT5645_DRC_AGC_NG_MASK (0x1 << 6)1453#define RT5645_DRC_AGC_NG_SFT 61454#define RT5645_DRC_AGC_NG_DIS (0x0 << 6)1455#define RT5645_DRC_AGC_NG_EN (0x1 << 6)1456#define RT5645_DRC_AGC_NGH_MASK (0x1 << 5)1457#define RT5645_DRC_AGC_NGH_SFT 51458#define RT5645_DRC_AGC_NGH_DIS (0x0 << 5)1459#define RT5645_DRC_AGC_NGH_EN (0x1 << 5)1460#define RT5645_DRC_AGC_NGT_MASK (0x1f)1461#define RT5645_DRC_AGC_NGT_SFT 01462 1463/* ANC Control 1 (0xb8) */1464#define RT5645_ANC_M_MASK (0x1 << 15)1465#define RT5645_ANC_M_SFT 151466#define RT5645_ANC_M_NOR (0x0 << 15)1467#define RT5645_ANC_M_REV (0x1 << 15)1468#define RT5645_ANC_MASK (0x1 << 14)1469#define RT5645_ANC_SFT 141470#define RT5645_ANC_DIS (0x0 << 14)1471#define RT5645_ANC_EN (0x1 << 14)1472#define RT5645_ANC_MD_MASK (0x3 << 12)1473#define RT5645_ANC_MD_SFT 121474#define RT5645_ANC_MD_DIS (0x0 << 12)1475#define RT5645_ANC_MD_67MS (0x1 << 12)1476#define RT5645_ANC_MD_267MS (0x2 << 12)1477#define RT5645_ANC_MD_1067MS (0x3 << 12)1478#define RT5645_ANC_SN_MASK (0x1 << 11)1479#define RT5645_ANC_SN_SFT 111480#define RT5645_ANC_SN_DIS (0x0 << 11)1481#define RT5645_ANC_SN_EN (0x1 << 11)1482#define RT5645_ANC_CLK_MASK (0x1 << 10)1483#define RT5645_ANC_CLK_SFT 101484#define RT5645_ANC_CLK_ANC (0x0 << 10)1485#define RT5645_ANC_CLK_REG (0x1 << 10)1486#define RT5645_ANC_ZCD_MASK (0x3 << 8)1487#define RT5645_ANC_ZCD_SFT 81488#define RT5645_ANC_ZCD_DIS (0x0 << 8)1489#define RT5645_ANC_ZCD_T1 (0x1 << 8)1490#define RT5645_ANC_ZCD_T2 (0x2 << 8)1491#define RT5645_ANC_ZCD_WT (0x3 << 8)1492#define RT5645_ANC_CS_MASK (0x1 << 7)1493#define RT5645_ANC_CS_SFT 71494#define RT5645_ANC_CS_DIS (0x0 << 7)1495#define RT5645_ANC_CS_EN (0x1 << 7)1496#define RT5645_ANC_SW_MASK (0x1 << 6)1497#define RT5645_ANC_SW_SFT 61498#define RT5645_ANC_SW_NOR (0x0 << 6)1499#define RT5645_ANC_SW_AUTO (0x1 << 6)1500#define RT5645_ANC_CO_L_MASK (0x3f)1501#define RT5645_ANC_CO_L_SFT 01502 1503/* ANC Control 2 (0xb6) */1504#define RT5645_ANC_FG_R_MASK (0xf << 12)1505#define RT5645_ANC_FG_R_SFT 121506#define RT5645_ANC_FG_L_MASK (0xf << 8)1507#define RT5645_ANC_FG_L_SFT 81508#define RT5645_ANC_CG_R_MASK (0xf << 4)1509#define RT5645_ANC_CG_R_SFT 41510#define RT5645_ANC_CG_L_MASK (0xf)1511#define RT5645_ANC_CG_L_SFT 01512 1513/* ANC Control 3 (0xb6) */1514#define RT5645_ANC_CD_MASK (0x1 << 6)1515#define RT5645_ANC_CD_SFT 61516#define RT5645_ANC_CD_BOTH (0x0 << 6)1517#define RT5645_ANC_CD_IND (0x1 << 6)1518#define RT5645_ANC_CO_R_MASK (0x3f)1519#define RT5645_ANC_CO_R_SFT 01520 1521/* Jack Detect Control (0xbb) */1522#define RT5645_JD_MASK (0x7 << 13)1523#define RT5645_JD_SFT 131524#define RT5645_JD_DIS (0x0 << 13)1525#define RT5645_JD_GPIO1 (0x1 << 13)1526#define RT5645_JD_JD1_IN4P (0x2 << 13)1527#define RT5645_JD_JD2_IN4N (0x3 << 13)1528#define RT5645_JD_GPIO2 (0x4 << 13)1529#define RT5645_JD_GPIO3 (0x5 << 13)1530#define RT5645_JD_GPIO4 (0x6 << 13)1531#define RT5645_JD_HP_MASK (0x1 << 11)1532#define RT5645_JD_HP_SFT 111533#define RT5645_JD_HP_DIS (0x0 << 11)1534#define RT5645_JD_HP_EN (0x1 << 11)1535#define RT5645_JD_HP_TRG_MASK (0x1 << 10)1536#define RT5645_JD_HP_TRG_SFT 101537#define RT5645_JD_HP_TRG_LO (0x0 << 10)1538#define RT5645_JD_HP_TRG_HI (0x1 << 10)1539#define RT5645_JD_SPL_MASK (0x1 << 9)1540#define RT5645_JD_SPL_SFT 91541#define RT5645_JD_SPL_DIS (0x0 << 9)1542#define RT5645_JD_SPL_EN (0x1 << 9)1543#define RT5645_JD_SPL_TRG_MASK (0x1 << 8)1544#define RT5645_JD_SPL_TRG_SFT 81545#define RT5645_JD_SPL_TRG_LO (0x0 << 8)1546#define RT5645_JD_SPL_TRG_HI (0x1 << 8)1547#define RT5645_JD_SPR_MASK (0x1 << 7)1548#define RT5645_JD_SPR_SFT 71549#define RT5645_JD_SPR_DIS (0x0 << 7)1550#define RT5645_JD_SPR_EN (0x1 << 7)1551#define RT5645_JD_SPR_TRG_MASK (0x1 << 6)1552#define RT5645_JD_SPR_TRG_SFT 61553#define RT5645_JD_SPR_TRG_LO (0x0 << 6)1554#define RT5645_JD_SPR_TRG_HI (0x1 << 6)1555#define RT5645_JD_MO_MASK (0x1 << 5)1556#define RT5645_JD_MO_SFT 51557#define RT5645_JD_MO_DIS (0x0 << 5)1558#define RT5645_JD_MO_EN (0x1 << 5)1559#define RT5645_JD_MO_TRG_MASK (0x1 << 4)1560#define RT5645_JD_MO_TRG_SFT 41561#define RT5645_JD_MO_TRG_LO (0x0 << 4)1562#define RT5645_JD_MO_TRG_HI (0x1 << 4)1563#define RT5645_JD_LO_MASK (0x1 << 3)1564#define RT5645_JD_LO_SFT 31565#define RT5645_JD_LO_DIS (0x0 << 3)1566#define RT5645_JD_LO_EN (0x1 << 3)1567#define RT5645_JD_LO_TRG_MASK (0x1 << 2)1568#define RT5645_JD_LO_TRG_SFT 21569#define RT5645_JD_LO_TRG_LO (0x0 << 2)1570#define RT5645_JD_LO_TRG_HI (0x1 << 2)1571#define RT5645_JD1_IN4P_MASK (0x1 << 1)1572#define RT5645_JD1_IN4P_SFT 11573#define RT5645_JD1_IN4P_DIS (0x0 << 1)1574#define RT5645_JD1_IN4P_EN (0x1 << 1)1575#define RT5645_JD2_IN4N_MASK (0x1)1576#define RT5645_JD2_IN4N_SFT 01577#define RT5645_JD2_IN4N_DIS (0x0)1578#define RT5645_JD2_IN4N_EN (0x1)1579 1580/* Jack detect for ANC (0xbc) */1581#define RT5645_ANC_DET_MASK (0x3 << 4)1582#define RT5645_ANC_DET_SFT 41583#define RT5645_ANC_DET_DIS (0x0 << 4)1584#define RT5645_ANC_DET_MB1 (0x1 << 4)1585#define RT5645_ANC_DET_MB2 (0x2 << 4)1586#define RT5645_ANC_DET_JD (0x3 << 4)1587#define RT5645_AD_TRG_MASK (0x1 << 3)1588#define RT5645_AD_TRG_SFT 31589#define RT5645_AD_TRG_LO (0x0 << 3)1590#define RT5645_AD_TRG_HI (0x1 << 3)1591#define RT5645_ANCM_DET_MASK (0x3 << 4)1592#define RT5645_ANCM_DET_SFT 41593#define RT5645_ANCM_DET_DIS (0x0 << 4)1594#define RT5645_ANCM_DET_MB1 (0x1 << 4)1595#define RT5645_ANCM_DET_MB2 (0x2 << 4)1596#define RT5645_ANCM_DET_JD (0x3 << 4)1597#define RT5645_AMD_TRG_MASK (0x1 << 3)1598#define RT5645_AMD_TRG_SFT 31599#define RT5645_AMD_TRG_LO (0x0 << 3)1600#define RT5645_AMD_TRG_HI (0x1 << 3)1601 1602/* IRQ Control 1 (0xbd) */1603#define RT5645_IRQ_JD_MASK (0x1 << 15)1604#define RT5645_IRQ_JD_SFT 151605#define RT5645_IRQ_JD_BP (0x0 << 15)1606#define RT5645_IRQ_JD_NOR (0x1 << 15)1607#define RT5645_IRQ_OT_MASK (0x1 << 14)1608#define RT5645_IRQ_OT_SFT 141609#define RT5645_IRQ_OT_BP (0x0 << 14)1610#define RT5645_IRQ_OT_NOR (0x1 << 14)1611#define RT5645_JD_STKY_MASK (0x1 << 13)1612#define RT5645_JD_STKY_SFT 131613#define RT5645_JD_STKY_DIS (0x0 << 13)1614#define RT5645_JD_STKY_EN (0x1 << 13)1615#define RT5645_OT_STKY_MASK (0x1 << 12)1616#define RT5645_OT_STKY_SFT 121617#define RT5645_OT_STKY_DIS (0x0 << 12)1618#define RT5645_OT_STKY_EN (0x1 << 12)1619#define RT5645_JD_P_MASK (0x1 << 11)1620#define RT5645_JD_P_SFT 111621#define RT5645_JD_P_NOR (0x0 << 11)1622#define RT5645_JD_P_INV (0x1 << 11)1623#define RT5645_OT_P_MASK (0x1 << 10)1624#define RT5645_OT_P_SFT 101625#define RT5645_OT_P_NOR (0x0 << 10)1626#define RT5645_OT_P_INV (0x1 << 10)1627#define RT5645_IRQ_JD_1_1_EN (0x1 << 9)1628#define RT5645_JD_1_1_MASK (0x1 << 7)1629#define RT5645_JD_1_1_SFT 71630#define RT5645_JD_1_1_NOR (0x0 << 7)1631#define RT5645_JD_1_1_INV (0x1 << 7)1632 1633/* IRQ Control 2 (0xbe) */1634#define RT5645_IRQ_MB1_OC_MASK (0x1 << 15)1635#define RT5645_IRQ_MB1_OC_SFT 151636#define RT5645_IRQ_MB1_OC_BP (0x0 << 15)1637#define RT5645_IRQ_MB1_OC_NOR (0x1 << 15)1638#define RT5645_IRQ_MB2_OC_MASK (0x1 << 14)1639#define RT5645_IRQ_MB2_OC_SFT 141640#define RT5645_IRQ_MB2_OC_BP (0x0 << 14)1641#define RT5645_IRQ_MB2_OC_NOR (0x1 << 14)1642#define RT5645_MB1_OC_STKY_MASK (0x1 << 13)1643#define RT5645_MB1_OC_STKY_SFT 131644#define RT5645_MB1_OC_STKY_DIS (0x0 << 13)1645#define RT5645_MB1_OC_STKY_EN (0x1 << 13)1646#define RT5645_MB2_OC_STKY_MASK (0x1 << 12)1647#define RT5645_MB2_OC_STKY_SFT 121648#define RT5645_MB2_OC_STKY_DIS (0x0 << 12)1649#define RT5645_MB2_OC_STKY_EN (0x1 << 12)1650#define RT5645_MB1_OC_P_MASK (0x1 << 7)1651#define RT5645_MB1_OC_P_SFT 71652#define RT5645_MB1_OC_P_NOR (0x0 << 7)1653#define RT5645_MB1_OC_P_INV (0x1 << 7)1654#define RT5645_MB2_OC_P_MASK (0x1 << 6)1655#define RT5645_MB2_OC_P_SFT 61656#define RT5645_MB2_OC_P_NOR (0x0 << 6)1657#define RT5645_MB2_OC_P_INV (0x1 << 6)1658#define RT5645_MB1_OC_CLR (0x1 << 3)1659#define RT5645_MB1_OC_CLR_SFT 31660#define RT5645_MB2_OC_CLR (0x1 << 2)1661#define RT5645_MB2_OC_CLR_SFT 21662 1663/* GPIO Control 1 (0xc0) */1664#define RT5645_GP1_PIN_MASK (0x1 << 15)1665#define RT5645_GP1_PIN_SFT 151666#define RT5645_GP1_PIN_GPIO1 (0x0 << 15)1667#define RT5645_GP1_PIN_IRQ (0x1 << 15)1668#define RT5645_GP2_PIN_MASK (0x1 << 14)1669#define RT5645_GP2_PIN_SFT 141670#define RT5645_GP2_PIN_GPIO2 (0x0 << 14)1671#define RT5645_GP2_PIN_DMIC1_SCL (0x1 << 14)1672#define RT5645_GP3_PIN_MASK (0x3 << 12)1673#define RT5645_GP3_PIN_SFT 121674#define RT5645_GP3_PIN_GPIO3 (0x0 << 12)1675#define RT5645_GP3_PIN_DMIC1_SDA (0x1 << 12)1676#define RT5645_GP3_PIN_IRQ (0x2 << 12)1677#define RT5645_GP4_PIN_MASK (0x1 << 11)1678#define RT5645_GP4_PIN_SFT 111679#define RT5645_GP4_PIN_GPIO4 (0x0 << 11)1680#define RT5645_GP4_PIN_DMIC2_SDA (0x1 << 11)1681#define RT5645_DP_SIG_MASK (0x1 << 10)1682#define RT5645_DP_SIG_SFT 101683#define RT5645_DP_SIG_TEST (0x0 << 10)1684#define RT5645_DP_SIG_AP (0x1 << 10)1685#define RT5645_GPIO_M_MASK (0x1 << 9)1686#define RT5645_GPIO_M_SFT 91687#define RT5645_GPIO_M_FLT (0x0 << 9)1688#define RT5645_GPIO_M_PH (0x1 << 9)1689#define RT5645_I2S2_SEL (0x1 << 8)1690#define RT5645_I2S2_SEL_SFT 81691#define RT5645_GP5_PIN_MASK (0x1 << 7)1692#define RT5645_GP5_PIN_SFT 71693#define RT5645_GP5_PIN_GPIO5 (0x0 << 7)1694#define RT5645_GP5_PIN_DMIC1_SDA (0x1 << 7)1695#define RT5645_GP6_PIN_MASK (0x1 << 6)1696#define RT5645_GP6_PIN_SFT 61697#define RT5645_GP6_PIN_GPIO6 (0x0 << 6)1698#define RT5645_GP6_PIN_DMIC2_SDA (0x1 << 6)1699#define RT5645_I2S2_DAC_PIN_MASK (0x1 << 4)1700#define RT5645_I2S2_DAC_PIN_SFT 41701#define RT5645_I2S2_DAC_PIN_I2S (0x0 << 4)1702#define RT5645_I2S2_DAC_PIN_GPIO (0x1 << 4)1703#define RT5645_GP8_PIN_MASK (0x1 << 3)1704#define RT5645_GP8_PIN_SFT 31705#define RT5645_GP8_PIN_GPIO8 (0x0 << 3)1706#define RT5645_GP8_PIN_DMIC2_SDA (0x1 << 3)1707#define RT5645_GP12_PIN_MASK (0x1 << 2)1708#define RT5645_GP12_PIN_SFT 21709#define RT5645_GP12_PIN_GPIO12 (0x0 << 2)1710#define RT5645_GP12_PIN_DMIC2_SDA (0x1 << 2)1711#define RT5645_GP11_PIN_MASK (0x1 << 1)1712#define RT5645_GP11_PIN_SFT 11713#define RT5645_GP11_PIN_GPIO11 (0x0 << 1)1714#define RT5645_GP11_PIN_DMIC1_SDA (0x1 << 1)1715#define RT5645_GP10_PIN_MASK (0x1)1716#define RT5645_GP10_PIN_SFT 01717#define RT5645_GP10_PIN_GPIO10 (0x0)1718#define RT5645_GP10_PIN_DMIC2_SDA (0x1)1719 1720/* GPIO Control 3 (0xc2) */1721#define RT5645_GP4_PF_MASK (0x1 << 11)1722#define RT5645_GP4_PF_SFT 111723#define RT5645_GP4_PF_IN (0x0 << 11)1724#define RT5645_GP4_PF_OUT (0x1 << 11)1725#define RT5645_GP4_OUT_MASK (0x1 << 10)1726#define RT5645_GP4_OUT_SFT 101727#define RT5645_GP4_OUT_LO (0x0 << 10)1728#define RT5645_GP4_OUT_HI (0x1 << 10)1729#define RT5645_GP4_P_MASK (0x1 << 9)1730#define RT5645_GP4_P_SFT 91731#define RT5645_GP4_P_NOR (0x0 << 9)1732#define RT5645_GP4_P_INV (0x1 << 9)1733#define RT5645_GP3_PF_MASK (0x1 << 8)1734#define RT5645_GP3_PF_SFT 81735#define RT5645_GP3_PF_IN (0x0 << 8)1736#define RT5645_GP3_PF_OUT (0x1 << 8)1737#define RT5645_GP3_OUT_MASK (0x1 << 7)1738#define RT5645_GP3_OUT_SFT 71739#define RT5645_GP3_OUT_LO (0x0 << 7)1740#define RT5645_GP3_OUT_HI (0x1 << 7)1741#define RT5645_GP3_P_MASK (0x1 << 6)1742#define RT5645_GP3_P_SFT 61743#define RT5645_GP3_P_NOR (0x0 << 6)1744#define RT5645_GP3_P_INV (0x1 << 6)1745#define RT5645_GP2_PF_MASK (0x1 << 5)1746#define RT5645_GP2_PF_SFT 51747#define RT5645_GP2_PF_IN (0x0 << 5)1748#define RT5645_GP2_PF_OUT (0x1 << 5)1749#define RT5645_GP2_OUT_MASK (0x1 << 4)1750#define RT5645_GP2_OUT_SFT 41751#define RT5645_GP2_OUT_LO (0x0 << 4)1752#define RT5645_GP2_OUT_HI (0x1 << 4)1753#define RT5645_GP2_P_MASK (0x1 << 3)1754#define RT5645_GP2_P_SFT 31755#define RT5645_GP2_P_NOR (0x0 << 3)1756#define RT5645_GP2_P_INV (0x1 << 3)1757#define RT5645_GP1_PF_MASK (0x1 << 2)1758#define RT5645_GP1_PF_SFT 21759#define RT5645_GP1_PF_IN (0x0 << 2)1760#define RT5645_GP1_PF_OUT (0x1 << 2)1761#define RT5645_GP1_OUT_MASK (0x1 << 1)1762#define RT5645_GP1_OUT_SFT 11763#define RT5645_GP1_OUT_LO (0x0 << 1)1764#define RT5645_GP1_OUT_HI (0x1 << 1)1765#define RT5645_GP1_P_MASK (0x1)1766#define RT5645_GP1_P_SFT 01767#define RT5645_GP1_P_NOR (0x0)1768#define RT5645_GP1_P_INV (0x1)1769 1770/* Programmable Register Array Control 1 (0xc8) */1771#define RT5645_REG_SEQ_MASK (0xf << 12)1772#define RT5645_REG_SEQ_SFT 121773#define RT5645_SEQ1_ST_MASK (0x1 << 11) /*RO*/1774#define RT5645_SEQ1_ST_SFT 111775#define RT5645_SEQ1_ST_RUN (0x0 << 11)1776#define RT5645_SEQ1_ST_FIN (0x1 << 11)1777#define RT5645_SEQ2_ST_MASK (0x1 << 10) /*RO*/1778#define RT5645_SEQ2_ST_SFT 101779#define RT5645_SEQ2_ST_RUN (0x0 << 10)1780#define RT5645_SEQ2_ST_FIN (0x1 << 10)1781#define RT5645_REG_LV_MASK (0x1 << 9)1782#define RT5645_REG_LV_SFT 91783#define RT5645_REG_LV_MX (0x0 << 9)1784#define RT5645_REG_LV_PR (0x1 << 9)1785#define RT5645_SEQ_2_PT_MASK (0x1 << 8)1786#define RT5645_SEQ_2_PT_BIT 81787#define RT5645_REG_IDX_MASK (0xff)1788#define RT5645_REG_IDX_SFT 01789 1790/* Programmable Register Array Control 2 (0xc9) */1791#define RT5645_REG_DAT_MASK (0xffff)1792#define RT5645_REG_DAT_SFT 01793 1794/* Programmable Register Array Control 3 (0xca) */1795#define RT5645_SEQ_DLY_MASK (0xff << 8)1796#define RT5645_SEQ_DLY_SFT 81797#define RT5645_PROG_MASK (0x1 << 7)1798#define RT5645_PROG_SFT 71799#define RT5645_PROG_DIS (0x0 << 7)1800#define RT5645_PROG_EN (0x1 << 7)1801#define RT5645_SEQ1_PT_RUN (0x1 << 6)1802#define RT5645_SEQ1_PT_RUN_BIT 61803#define RT5645_SEQ2_PT_RUN (0x1 << 5)1804#define RT5645_SEQ2_PT_RUN_BIT 51805 1806/* Programmable Register Array Control 4 (0xcb) */1807#define RT5645_SEQ1_START_MASK (0xf << 8)1808#define RT5645_SEQ1_START_SFT 81809#define RT5645_SEQ1_END_MASK (0xf)1810#define RT5645_SEQ1_END_SFT 01811 1812/* Programmable Register Array Control 5 (0xcc) */1813#define RT5645_SEQ2_START_MASK (0xf << 8)1814#define RT5645_SEQ2_START_SFT 81815#define RT5645_SEQ2_END_MASK (0xf)1816#define RT5645_SEQ2_END_SFT 01817 1818/* Scramble Function (0xcd) */1819#define RT5645_SCB_KEY_MASK (0xff)1820#define RT5645_SCB_KEY_SFT 01821 1822/* Scramble Control (0xce) */1823#define RT5645_SCB_SWAP_MASK (0x1 << 15)1824#define RT5645_SCB_SWAP_SFT 151825#define RT5645_SCB_SWAP_DIS (0x0 << 15)1826#define RT5645_SCB_SWAP_EN (0x1 << 15)1827#define RT5645_SCB_MASK (0x1 << 14)1828#define RT5645_SCB_SFT 141829#define RT5645_SCB_DIS (0x0 << 14)1830#define RT5645_SCB_EN (0x1 << 14)1831 1832/* Baseback Control (0xcf) */1833#define RT5645_BB_MASK (0x1 << 15)1834#define RT5645_BB_SFT 151835#define RT5645_BB_DIS (0x0 << 15)1836#define RT5645_BB_EN (0x1 << 15)1837#define RT5645_BB_CT_MASK (0x7 << 12)1838#define RT5645_BB_CT_SFT 121839#define RT5645_BB_CT_A (0x0 << 12)1840#define RT5645_BB_CT_B (0x1 << 12)1841#define RT5645_BB_CT_C (0x2 << 12)1842#define RT5645_BB_CT_D (0x3 << 12)1843#define RT5645_M_BB_L_MASK (0x1 << 9)1844#define RT5645_M_BB_L_SFT 91845#define RT5645_M_BB_R_MASK (0x1 << 8)1846#define RT5645_M_BB_R_SFT 81847#define RT5645_M_BB_HPF_L_MASK (0x1 << 7)1848#define RT5645_M_BB_HPF_L_SFT 71849#define RT5645_M_BB_HPF_R_MASK (0x1 << 6)1850#define RT5645_M_BB_HPF_R_SFT 61851#define RT5645_G_BB_BST_MASK (0x3f)1852#define RT5645_G_BB_BST_SFT 01853#define RT5645_G_BB_BST_25DB 0x141854 1855/* MP3 Plus Control 1 (0xd0) */1856#define RT5645_M_MP3_L_MASK (0x1 << 15)1857#define RT5645_M_MP3_L_SFT 151858#define RT5645_M_MP3_R_MASK (0x1 << 14)1859#define RT5645_M_MP3_R_SFT 141860#define RT5645_M_MP3_MASK (0x1 << 13)1861#define RT5645_M_MP3_SFT 131862#define RT5645_M_MP3_DIS (0x0 << 13)1863#define RT5645_M_MP3_EN (0x1 << 13)1864#define RT5645_EG_MP3_MASK (0x1f << 8)1865#define RT5645_EG_MP3_SFT 81866#define RT5645_MP3_HLP_MASK (0x1 << 7)1867#define RT5645_MP3_HLP_SFT 71868#define RT5645_MP3_HLP_DIS (0x0 << 7)1869#define RT5645_MP3_HLP_EN (0x1 << 7)1870#define RT5645_M_MP3_ORG_L_MASK (0x1 << 6)1871#define RT5645_M_MP3_ORG_L_SFT 61872#define RT5645_M_MP3_ORG_R_MASK (0x1 << 5)1873#define RT5645_M_MP3_ORG_R_SFT 51874 1875/* MP3 Plus Control 2 (0xd1) */1876#define RT5645_MP3_WT_MASK (0x1 << 13)1877#define RT5645_MP3_WT_SFT 131878#define RT5645_MP3_WT_1_4 (0x0 << 13)1879#define RT5645_MP3_WT_1_2 (0x1 << 13)1880#define RT5645_OG_MP3_MASK (0x1f << 8)1881#define RT5645_OG_MP3_SFT 81882#define RT5645_HG_MP3_MASK (0x3f)1883#define RT5645_HG_MP3_SFT 01884 1885/* 3D HP Control 1 (0xd2) */1886#define RT5645_3D_CF_MASK (0x1 << 15)1887#define RT5645_3D_CF_SFT 151888#define RT5645_3D_CF_DIS (0x0 << 15)1889#define RT5645_3D_CF_EN (0x1 << 15)1890#define RT5645_3D_HP_MASK (0x1 << 14)1891#define RT5645_3D_HP_SFT 141892#define RT5645_3D_HP_DIS (0x0 << 14)1893#define RT5645_3D_HP_EN (0x1 << 14)1894#define RT5645_3D_BT_MASK (0x1 << 13)1895#define RT5645_3D_BT_SFT 131896#define RT5645_3D_BT_DIS (0x0 << 13)1897#define RT5645_3D_BT_EN (0x1 << 13)1898#define RT5645_3D_1F_MIX_MASK (0x3 << 11)1899#define RT5645_3D_1F_MIX_SFT 111900#define RT5645_3D_HP_M_MASK (0x1 << 10)1901#define RT5645_3D_HP_M_SFT 101902#define RT5645_3D_HP_M_SUR (0x0 << 10)1903#define RT5645_3D_HP_M_FRO (0x1 << 10)1904#define RT5645_M_3D_HRTF_MASK (0x1 << 9)1905#define RT5645_M_3D_HRTF_SFT 91906#define RT5645_M_3D_D2H_MASK (0x1 << 8)1907#define RT5645_M_3D_D2H_SFT 81908#define RT5645_M_3D_D2R_MASK (0x1 << 7)1909#define RT5645_M_3D_D2R_SFT 71910#define RT5645_M_3D_REVB_MASK (0x1 << 6)1911#define RT5645_M_3D_REVB_SFT 61912 1913/* Adjustable high pass filter control 1 (0xd3) */1914#define RT5645_2ND_HPF_MASK (0x1 << 15)1915#define RT5645_2ND_HPF_SFT 151916#define RT5645_2ND_HPF_DIS (0x0 << 15)1917#define RT5645_2ND_HPF_EN (0x1 << 15)1918#define RT5645_HPF_CF_L_MASK (0x7 << 12)1919#define RT5645_HPF_CF_L_SFT 121920#define RT5645_1ST_HPF_MASK (0x1 << 11)1921#define RT5645_1ST_HPF_SFT 111922#define RT5645_1ST_HPF_DIS (0x0 << 11)1923#define RT5645_1ST_HPF_EN (0x1 << 11)1924#define RT5645_HPF_CF_R_MASK (0x7 << 8)1925#define RT5645_HPF_CF_R_SFT 81926#define RT5645_ZD_T_MASK (0x3 << 6)1927#define RT5645_ZD_T_SFT 61928#define RT5645_ZD_F_MASK (0x3 << 4)1929#define RT5645_ZD_F_SFT 41930#define RT5645_ZD_F_IM (0x0 << 4)1931#define RT5645_ZD_F_ZC_IM (0x1 << 4)1932#define RT5645_ZD_F_ZC_IOD (0x2 << 4)1933#define RT5645_ZD_F_UN (0x3 << 4)1934 1935/* HP calibration control and Amp detection (0xd6) */1936#define RT5645_SI_DAC_MASK (0x1 << 11)1937#define RT5645_SI_DAC_SFT 111938#define RT5645_SI_DAC_AUTO (0x0 << 11)1939#define RT5645_SI_DAC_TEST (0x1 << 11)1940#define RT5645_DC_CAL_M_MASK (0x1 << 10)1941#define RT5645_DC_CAL_M_SFT 101942#define RT5645_DC_CAL_M_CAL (0x0 << 10)1943#define RT5645_DC_CAL_M_NOR (0x1 << 10)1944#define RT5645_DC_CAL_MASK (0x1 << 9)1945#define RT5645_DC_CAL_SFT 91946#define RT5645_DC_CAL_DIS (0x0 << 9)1947#define RT5645_DC_CAL_EN (0x1 << 9)1948#define RT5645_HPD_RCV_MASK (0x7 << 6)1949#define RT5645_HPD_RCV_SFT 61950#define RT5645_HPD_PS_MASK (0x1 << 5)1951#define RT5645_HPD_PS_SFT 51952#define RT5645_HPD_PS_DIS (0x0 << 5)1953#define RT5645_HPD_PS_EN (0x1 << 5)1954#define RT5645_CAL_M_MASK (0x1 << 4)1955#define RT5645_CAL_M_SFT 41956#define RT5645_CAL_M_DEP (0x0 << 4)1957#define RT5645_CAL_M_CAL (0x1 << 4)1958#define RT5645_CAL_MASK (0x1 << 3)1959#define RT5645_CAL_SFT 31960#define RT5645_CAL_DIS (0x0 << 3)1961#define RT5645_CAL_EN (0x1 << 3)1962#define RT5645_CAL_TEST_MASK (0x1 << 2)1963#define RT5645_CAL_TEST_SFT 21964#define RT5645_CAL_TEST_DIS (0x0 << 2)1965#define RT5645_CAL_TEST_EN (0x1 << 2)1966#define RT5645_CAL_P_MASK (0x3)1967#define RT5645_CAL_P_SFT 01968#define RT5645_CAL_P_NONE (0x0)1969#define RT5645_CAL_P_CAL (0x1)1970#define RT5645_CAL_P_DAC_CAL (0x2)1971 1972/* Soft volume and zero cross control 1 (0xd9) */1973#define RT5645_SV_MASK (0x1 << 15)1974#define RT5645_SV_SFT 151975#define RT5645_SV_DIS (0x0 << 15)1976#define RT5645_SV_EN (0x1 << 15)1977#define RT5645_SPO_SV_MASK (0x1 << 14)1978#define RT5645_SPO_SV_SFT 141979#define RT5645_SPO_SV_DIS (0x0 << 14)1980#define RT5645_SPO_SV_EN (0x1 << 14)1981#define RT5645_OUT_SV_MASK (0x1 << 13)1982#define RT5645_OUT_SV_SFT 131983#define RT5645_OUT_SV_DIS (0x0 << 13)1984#define RT5645_OUT_SV_EN (0x1 << 13)1985#define RT5645_HP_SV_MASK (0x1 << 12)1986#define RT5645_HP_SV_SFT 121987#define RT5645_HP_SV_DIS (0x0 << 12)1988#define RT5645_HP_SV_EN (0x1 << 12)1989#define RT5645_ZCD_DIG_MASK (0x1 << 11)1990#define RT5645_ZCD_DIG_SFT 111991#define RT5645_ZCD_DIG_DIS (0x0 << 11)1992#define RT5645_ZCD_DIG_EN (0x1 << 11)1993#define RT5645_ZCD_MASK (0x1 << 10)1994#define RT5645_ZCD_SFT 101995#define RT5645_ZCD_PD (0x0 << 10)1996#define RT5645_ZCD_PU (0x1 << 10)1997#define RT5645_M_ZCD_MASK (0x3f << 4)1998#define RT5645_M_ZCD_SFT 41999#define RT5645_M_ZCD_RM_L (0x1 << 9)2000#define RT5645_M_ZCD_RM_R (0x1 << 8)2001#define RT5645_M_ZCD_SM_L (0x1 << 7)2002#define RT5645_M_ZCD_SM_R (0x1 << 6)2003#define RT5645_M_ZCD_OM_L (0x1 << 5)2004#define RT5645_M_ZCD_OM_R (0x1 << 4)2005#define RT5645_SV_DLY_MASK (0xf)2006#define RT5645_SV_DLY_SFT 02007 2008/* Soft volume and zero cross control 2 (0xda) */2009#define RT5645_ZCD_HP_MASK (0x1 << 15)2010#define RT5645_ZCD_HP_SFT 152011#define RT5645_ZCD_HP_DIS (0x0 << 15)2012#define RT5645_ZCD_HP_EN (0x1 << 15)2013 2014/* Buttons Inline Command Function 2 (0xe0) */2015#define RT5645_EN_4BTN_IL_MASK (0x1 << 15)2016#define RT5645_EN_4BTN_IL_EN (0x1 << 15)2017#define RT5645_RST_4BTN_IL_MASK (0x1 << 14)2018#define RT5645_RST_4BTN_IL_RST (0x0 << 14)2019#define RT5645_RST_4BTN_IL_NORM (0x1 << 14)2020 2021/* Codec Private Register definition */2022/* DAC ADC Digital Volume (0x00) */2023#define RT5645_DA1_ZDET_SFT 62024 2025/* 3D Speaker Control (0x63) */2026#define RT5645_3D_SPK_MASK (0x1 << 15)2027#define RT5645_3D_SPK_SFT 152028#define RT5645_3D_SPK_DIS (0x0 << 15)2029#define RT5645_3D_SPK_EN (0x1 << 15)2030#define RT5645_3D_SPK_M_MASK (0x3 << 13)2031#define RT5645_3D_SPK_M_SFT 132032#define RT5645_3D_SPK_CG_MASK (0x1f << 8)2033#define RT5645_3D_SPK_CG_SFT 82034#define RT5645_3D_SPK_SG_MASK (0x1f)2035#define RT5645_3D_SPK_SG_SFT 02036 2037/* Wind Noise Detection Control 1 (0x6c) */2038#define RT5645_WND_MASK (0x1 << 15)2039#define RT5645_WND_SFT 152040#define RT5645_WND_DIS (0x0 << 15)2041#define RT5645_WND_EN (0x1 << 15)2042 2043/* Wind Noise Detection Control 2 (0x6d) */2044#define RT5645_WND_FC_NW_MASK (0x3f << 10)2045#define RT5645_WND_FC_NW_SFT 102046#define RT5645_WND_FC_WK_MASK (0x3f << 4)2047#define RT5645_WND_FC_WK_SFT 42048 2049/* Wind Noise Detection Control 3 (0x6e) */2050#define RT5645_HPF_FC_MASK (0x3f << 6)2051#define RT5645_HPF_FC_SFT 62052#define RT5645_WND_FC_ST_MASK (0x3f)2053#define RT5645_WND_FC_ST_SFT 02054 2055/* Wind Noise Detection Control 4 (0x6f) */2056#define RT5645_WND_TH_LO_MASK (0x3ff)2057#define RT5645_WND_TH_LO_SFT 02058 2059/* Wind Noise Detection Control 5 (0x70) */2060#define RT5645_WND_TH_HI_MASK (0x3ff)2061#define RT5645_WND_TH_HI_SFT 02062 2063/* Wind Noise Detection Control 8 (0x73) */2064#define RT5645_WND_WIND_MASK (0x1 << 13) /* Read-Only */2065#define RT5645_WND_WIND_SFT 132066#define RT5645_WND_STRONG_MASK (0x1 << 12) /* Read-Only */2067#define RT5645_WND_STRONG_SFT 122068enum {2069 RT5645_NO_WIND,2070 RT5645_BREEZE,2071 RT5645_STORM,2072};2073 2074/* Dipole Speaker Interface (0x75) */2075#define RT5645_DP_ATT_MASK (0x3 << 14)2076#define RT5645_DP_ATT_SFT 142077#define RT5645_DP_SPK_MASK (0x1 << 10)2078#define RT5645_DP_SPK_SFT 102079#define RT5645_DP_SPK_DIS (0x0 << 10)2080#define RT5645_DP_SPK_EN (0x1 << 10)2081 2082/* EQ Pre Volume Control (0xb3) */2083#define RT5645_EQ_PRE_VOL_MASK (0xffff)2084#define RT5645_EQ_PRE_VOL_SFT 02085 2086/* EQ Post Volume Control (0xb4) */2087#define RT5645_EQ_PST_VOL_MASK (0xffff)2088#define RT5645_EQ_PST_VOL_SFT 02089 2090/* Jack Detect Control 3 (0xf8) */2091#define RT5645_CMP_MIC_IN_DET_MASK (0x7 << 12)2092#define RT5645_JD_CBJ_EN (0x1 << 7)2093#define RT5645_JD_CBJ_POL (0x1 << 6)2094#define RT5645_JD_TRI_CBJ_SEL_MASK (0x7 << 3)2095#define RT5645_JD_TRI_CBJ_SEL_SFT (3)2096#define RT5645_JD_TRI_HPO_SEL_MASK (0x7)2097#define RT5645_JD_TRI_HPO_SEL_SFT (0)2098#define RT5645_JD_F_GPIO_JD1 (0x0)2099#define RT5645_JD_F_JD1_1 (0x1)2100#define RT5645_JD_F_JD1_2 (0x2)2101#define RT5645_JD_F_JD2 (0x3)2102#define RT5645_JD_F_JD3 (0x4)2103#define RT5645_JD_F_GPIO_JD2 (0x5)2104#define RT5645_JD_F_MX0B_12 (0x6)2105 2106/* Digital Misc Control (0xfa) */2107#define RT5645_RST_DSP (0x1 << 13)2108#define RT5645_IF1_ADC1_IN1_SEL (0x1 << 12)2109#define RT5645_IF1_ADC1_IN1_SFT 122110#define RT5645_IF1_ADC1_IN2_SEL (0x1 << 11)2111#define RT5645_IF1_ADC1_IN2_SFT 112112#define RT5645_IF1_ADC2_IN1_SEL (0x1 << 10)2113#define RT5645_IF1_ADC2_IN1_SFT 102114#define RT5645_DIG_GATE_CTRL 0x12115 2116/* General Control2 (0xfb) */2117#define RT5645_RXDC_SRC_MASK (0x1 << 7)2118#define RT5645_RXDC_SRC_STO (0x0 << 7)2119#define RT5645_RXDC_SRC_MONO (0x1 << 7)2120#define RT5645_RXDC_SRC_SFT (7)2121#define RT5645_MICBIAS1_POW_CTRL_SEL_MASK (0x1 << 5)2122#define RT5645_MICBIAS1_POW_CTRL_SEL_A (0x0 << 5)2123#define RT5645_MICBIAS1_POW_CTRL_SEL_M (0x1 << 5)2124#define RT5645_MICBIAS2_POW_CTRL_SEL_MASK (0x1 << 4)2125#define RT5645_MICBIAS2_POW_CTRL_SEL_A (0x0 << 4)2126#define RT5645_MICBIAS2_POW_CTRL_SEL_M (0x1 << 4)2127#define RT5645_RXDP2_SEL_MASK (0x1 << 3)2128#define RT5645_RXDP2_SEL_IF2 (0x0 << 3)2129#define RT5645_RXDP2_SEL_ADC (0x1 << 3)2130#define RT5645_RXDP2_SEL_SFT (3)2131 2132/* General Control3 (0xfc) */2133#define RT5645_JD_PSV_MODE (0x1 << 12)2134#define RT5645_IRQ_CLK_GATE_CTRL (0x1 << 11)2135#define RT5645_DET_CLK_MASK (0x3 << 9)2136#define RT5645_DET_CLK_DIS (0x0 << 9)2137#define RT5645_DET_CLK_MODE1 (0x1 << 9)2138#define RT5645_DET_CLK_MODE2 (0x2 << 9)2139#define RT5645_MICINDET_MANU (0x1 << 7)2140#define RT5645_RING2_SLEEVE_GND (0x1 << 5)2141 2142/* Vendor ID (0xfd) */2143#define RT5645_VER_C 0x22144#define RT5645_VER_D 0x32145 2146 2147/* Volume Rescale */2148#define RT5645_VOL_RSCL_MAX 0x272149#define RT5645_VOL_RSCL_RANGE 0x1F2150/* Debug String Length */2151#define RT5645_REG_DISP_LEN 232152 2153 2154/* System Clock Source */2155enum {2156 RT5645_SCLK_S_MCLK,2157 RT5645_SCLK_S_PLL1,2158 RT5645_SCLK_S_RCCLK,2159};2160 2161/* PLL1 Source */2162enum {2163 RT5645_PLL1_S_MCLK,2164 RT5645_PLL1_S_BCLK1,2165 RT5645_PLL1_S_BCLK2,2166};2167 2168enum {2169 RT5645_AIF1,2170 RT5645_AIF2,2171 RT5645_AIFS,2172};2173 2174enum {2175 RT5645_DMIC1_DISABLE,2176 RT5645_DMIC_DATA_IN2P,2177 RT5645_DMIC_DATA_GPIO6,2178 RT5645_DMIC_DATA_GPIO10,2179 RT5645_DMIC_DATA_GPIO12,2180};2181 2182enum {2183 RT5645_DMIC2_DISABLE,2184 RT5645_DMIC_DATA_IN2N,2185 RT5645_DMIC_DATA_GPIO5,2186 RT5645_DMIC_DATA_GPIO11,2187};2188 2189enum {2190 CODEC_TYPE_RT5645,2191 CODEC_TYPE_RT5650,2192};2193 2194/* filter mask */2195enum {2196 RT5645_DA_STEREO_FILTER = 0x1,2197 RT5645_DA_MONO_L_FILTER = (0x1 << 1),2198 RT5645_DA_MONO_R_FILTER = (0x1 << 2),2199 RT5645_AD_STEREO_FILTER = (0x1 << 3),2200 RT5645_AD_MONO_L_FILTER = (0x1 << 4),2201 RT5645_AD_MONO_R_FILTER = (0x1 << 5),2202};2203 2204int rt5645_sel_asrc_clk_src(struct snd_soc_component *component,2205 unsigned int filter_mask, unsigned int clk_src);2206 2207int rt5645_set_jack_detect(struct snd_soc_component *component,2208 struct snd_soc_jack *hp_jack, struct snd_soc_jack *mic_jack,2209 struct snd_soc_jack *btn_jack);2210 2211const char *rt5645_components(struct device *codec_dev);2212 2213#endif /* __RT5645_H__ */2214