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1/* SPDX-License-Identifier: GPL-2.0-only */2/*3 * rt5659.h -- RT5659/RT5658 ALSA SoC audio driver4 *5 * Copyright 2015 Realtek Microelectronics6 * Author: Bard Liao <bardliao@realtek.com>7 */8 9#ifndef __RT5659_H__10#define __RT5659_H__11 12#include <sound/rt5659.h>13 14#define DEVICE_ID 0x631115 16/* Info */17#define RT5659_RESET 0x000018#define RT5659_VENDOR_ID 0x00fd19#define RT5659_VENDOR_ID_1 0x00fe20#define RT5659_DEVICE_ID 0x00ff21/* I/O - Output */22#define RT5659_SPO_VOL 0x000123#define RT5659_HP_VOL 0x000224#define RT5659_LOUT 0x000325#define RT5659_MONO_OUT 0x000426#define RT5659_HPL_GAIN 0x000527#define RT5659_HPR_GAIN 0x000628#define RT5659_MONO_GAIN 0x000729#define RT5659_SPDIF_CTRL_1 0x000830#define RT5659_SPDIF_CTRL_2 0x000931/* I/O - Input */32#define RT5659_CAL_BST_CTRL 0x000a33#define RT5659_IN1_IN2 0x000c34#define RT5659_IN3_IN4 0x000d35#define RT5659_INL1_INR1_VOL 0x000f36/* I/O - Speaker */37#define RT5659_EJD_CTRL_1 0x001038#define RT5659_EJD_CTRL_2 0x001139#define RT5659_EJD_CTRL_3 0x001240#define RT5659_SILENCE_CTRL 0x001541#define RT5659_PSV_CTRL 0x001642/* I/O - Sidetone */43#define RT5659_SIDETONE_CTRL 0x001844/* I/O - ADC/DAC/DMIC */45#define RT5659_DAC1_DIG_VOL 0x001946#define RT5659_DAC2_DIG_VOL 0x001a47#define RT5659_DAC_CTRL 0x001b48#define RT5659_STO1_ADC_DIG_VOL 0x001c49#define RT5659_MONO_ADC_DIG_VOL 0x001d50#define RT5659_STO2_ADC_DIG_VOL 0x001e51#define RT5659_STO1_BOOST 0x001f52#define RT5659_MONO_BOOST 0x002053#define RT5659_STO2_BOOST 0x002154#define RT5659_HP_IMP_GAIN_1 0x002255#define RT5659_HP_IMP_GAIN_2 0x002356/* Mixer - D-D */57#define RT5659_STO1_ADC_MIXER 0x002658#define RT5659_MONO_ADC_MIXER 0x002759#define RT5659_AD_DA_MIXER 0x002960#define RT5659_STO_DAC_MIXER 0x002a61#define RT5659_MONO_DAC_MIXER 0x002b62#define RT5659_DIG_MIXER 0x002c63#define RT5659_A_DAC_MUX 0x002d64#define RT5659_DIG_INF23_DATA 0x002f65/* Mixer - PDM */66#define RT5659_PDM_OUT_CTRL 0x003167#define RT5659_PDM_DATA_CTRL_1 0x003268#define RT5659_PDM_DATA_CTRL_2 0x003369#define RT5659_PDM_DATA_CTRL_3 0x003470#define RT5659_PDM_DATA_CTRL_4 0x003571#define RT5659_SPDIF_CTRL 0x003672 73/* Mixer - ADC */74#define RT5659_REC1_GAIN 0x003a75#define RT5659_REC1_L1_MIXER 0x003b76#define RT5659_REC1_L2_MIXER 0x003c77#define RT5659_REC1_R1_MIXER 0x003d78#define RT5659_REC1_R2_MIXER 0x003e79#define RT5659_CAL_REC 0x004080#define RT5659_REC2_L1_MIXER 0x009b81#define RT5659_REC2_L2_MIXER 0x009c82#define RT5659_REC2_R1_MIXER 0x009d83#define RT5659_REC2_R2_MIXER 0x009e84#define RT5659_RC_CLK_CTRL 0x009f85/* Mixer - DAC */86#define RT5659_SPK_L_MIXER 0x004687#define RT5659_SPK_R_MIXER 0x004788#define RT5659_SPO_AMP_GAIN 0x004889#define RT5659_ALC_BACK_GAIN 0x004990#define RT5659_MONOMIX_GAIN 0x004a91#define RT5659_MONOMIX_IN_GAIN 0x004b92#define RT5659_OUT_L_GAIN 0x004d93#define RT5659_OUT_L_MIXER 0x004e94#define RT5659_OUT_R_GAIN 0x004f95#define RT5659_OUT_R_MIXER 0x005096#define RT5659_LOUT_MIXER 0x005297 98#define RT5659_HAPTIC_GEN_CTRL_1 0x005399#define RT5659_HAPTIC_GEN_CTRL_2 0x0054100#define RT5659_HAPTIC_GEN_CTRL_3 0x0055101#define RT5659_HAPTIC_GEN_CTRL_4 0x0056102#define RT5659_HAPTIC_GEN_CTRL_5 0x0057103#define RT5659_HAPTIC_GEN_CTRL_6 0x0058104#define RT5659_HAPTIC_GEN_CTRL_7 0x0059105#define RT5659_HAPTIC_GEN_CTRL_8 0x005a106#define RT5659_HAPTIC_GEN_CTRL_9 0x005b107#define RT5659_HAPTIC_GEN_CTRL_10 0x005c108#define RT5659_HAPTIC_GEN_CTRL_11 0x005d109#define RT5659_HAPTIC_LPF_CTRL_1 0x005e110#define RT5659_HAPTIC_LPF_CTRL_2 0x005f111#define RT5659_HAPTIC_LPF_CTRL_3 0x0060112/* Power */113#define RT5659_PWR_DIG_1 0x0061114#define RT5659_PWR_DIG_2 0x0062115#define RT5659_PWR_ANLG_1 0x0063116#define RT5659_PWR_ANLG_2 0x0064117#define RT5659_PWR_ANLG_3 0x0065118#define RT5659_PWR_MIXER 0x0066119#define RT5659_PWR_VOL 0x0067120/* Private Register Control */121#define RT5659_PRIV_INDEX 0x006a122#define RT5659_CLK_DET 0x006b123#define RT5659_PRIV_DATA 0x006c124/* System Clock Pre Divider Gating Control */125#define RT5659_PRE_DIV_1 0x006e126#define RT5659_PRE_DIV_2 0x006f127/* Format - ADC/DAC */128#define RT5659_I2S1_SDP 0x0070129#define RT5659_I2S2_SDP 0x0071130#define RT5659_I2S3_SDP 0x0072131#define RT5659_ADDA_CLK_1 0x0073132#define RT5659_ADDA_CLK_2 0x0074133#define RT5659_DMIC_CTRL_1 0x0075134#define RT5659_DMIC_CTRL_2 0x0076135/* Format - TDM Control */136#define RT5659_TDM_CTRL_1 0x0077137#define RT5659_TDM_CTRL_2 0x0078138#define RT5659_TDM_CTRL_3 0x0079139#define RT5659_TDM_CTRL_4 0x007a140#define RT5659_TDM_CTRL_5 0x007b141 142/* Function - Analog */143#define RT5659_GLB_CLK 0x0080144#define RT5659_PLL_CTRL_1 0x0081145#define RT5659_PLL_CTRL_2 0x0082146#define RT5659_ASRC_1 0x0083147#define RT5659_ASRC_2 0x0084148#define RT5659_ASRC_3 0x0085149#define RT5659_ASRC_4 0x0086150#define RT5659_ASRC_5 0x0087151#define RT5659_ASRC_6 0x0088152#define RT5659_ASRC_7 0x0089153#define RT5659_ASRC_8 0x008a154#define RT5659_ASRC_9 0x008b155#define RT5659_ASRC_10 0x008c156#define RT5659_DEPOP_1 0x008e157#define RT5659_DEPOP_2 0x008f158#define RT5659_DEPOP_3 0x0090159#define RT5659_HP_CHARGE_PUMP_1 0x0091160#define RT5659_HP_CHARGE_PUMP_2 0x0092161#define RT5659_MICBIAS_1 0x0093162#define RT5659_MICBIAS_2 0x0094163#define RT5659_ASRC_11 0x0097164#define RT5659_ASRC_12 0x0098165#define RT5659_ASRC_13 0x0099166#define RT5659_REC_M1_M2_GAIN_CTRL 0x009a167#define RT5659_CLASSD_CTRL_1 0x00a0168#define RT5659_CLASSD_CTRL_2 0x00a1169 170/* Function - Digital */171#define RT5659_ADC_EQ_CTRL_1 0x00ae172#define RT5659_ADC_EQ_CTRL_2 0x00af173#define RT5659_DAC_EQ_CTRL_1 0x00b0174#define RT5659_DAC_EQ_CTRL_2 0x00b1175#define RT5659_DAC_EQ_CTRL_3 0x00b2176 177#define RT5659_IRQ_CTRL_1 0x00b6178#define RT5659_IRQ_CTRL_2 0x00b7179#define RT5659_IRQ_CTRL_3 0x00b8180#define RT5659_IRQ_CTRL_4 0x00ba181#define RT5659_IRQ_CTRL_5 0x00bb182#define RT5659_IRQ_CTRL_6 0x00bc183#define RT5659_INT_ST_1 0x00be184#define RT5659_INT_ST_2 0x00bf185#define RT5659_GPIO_CTRL_1 0x00c0186#define RT5659_GPIO_CTRL_2 0x00c1187#define RT5659_GPIO_CTRL_3 0x00c2188#define RT5659_GPIO_CTRL_4 0x00c3189#define RT5659_GPIO_CTRL_5 0x00c4190#define RT5659_GPIO_STA 0x00c5191#define RT5659_SINE_GEN_CTRL_1 0x00cb192#define RT5659_SINE_GEN_CTRL_2 0x00cc193#define RT5659_SINE_GEN_CTRL_3 0x00cd194#define RT5659_HP_AMP_DET_CTRL_1 0x00d6195#define RT5659_HP_AMP_DET_CTRL_2 0x00d7196#define RT5659_SV_ZCD_1 0x00d9197#define RT5659_SV_ZCD_2 0x00da198#define RT5659_IL_CMD_1 0x00db199#define RT5659_IL_CMD_2 0x00dc200#define RT5659_IL_CMD_3 0x00dd201#define RT5659_IL_CMD_4 0x00de202#define RT5659_4BTN_IL_CMD_1 0x00df203#define RT5659_4BTN_IL_CMD_2 0x00e0204#define RT5659_4BTN_IL_CMD_3 0x00e1205#define RT5659_PSV_IL_CMD_1 0x00e4206#define RT5659_PSV_IL_CMD_2 0x00e5207 208#define RT5659_ADC_STO1_HP_CTRL_1 0x00ea209#define RT5659_ADC_STO1_HP_CTRL_2 0x00eb210#define RT5659_ADC_MONO_HP_CTRL_1 0x00ec211#define RT5659_ADC_MONO_HP_CTRL_2 0x00ed212#define RT5659_AJD1_CTRL 0x00f0213#define RT5659_AJD2_AJD3_CTRL 0x00f1214#define RT5659_JD1_THD 0x00f2215#define RT5659_JD2_THD 0x00f3216#define RT5659_JD3_THD 0x00f4217#define RT5659_JD_CTRL_1 0x00f6218#define RT5659_JD_CTRL_2 0x00f7219#define RT5659_JD_CTRL_3 0x00f8220#define RT5659_JD_CTRL_4 0x00f9221/* General Control */222#define RT5659_DIG_MISC 0x00fa223#define RT5659_DUMMY_2 0x00fb224#define RT5659_DUMMY_3 0x00fc225 226#define RT5659_DAC_ADC_DIG_VOL 0x0100227#define RT5659_BIAS_CUR_CTRL_1 0x010a228#define RT5659_BIAS_CUR_CTRL_2 0x010b229#define RT5659_BIAS_CUR_CTRL_3 0x010c230#define RT5659_BIAS_CUR_CTRL_4 0x010d231#define RT5659_BIAS_CUR_CTRL_5 0x010e232#define RT5659_BIAS_CUR_CTRL_6 0x010f233#define RT5659_BIAS_CUR_CTRL_7 0x0110234#define RT5659_BIAS_CUR_CTRL_8 0x0111235#define RT5659_BIAS_CUR_CTRL_9 0x0112236#define RT5659_BIAS_CUR_CTRL_10 0x0113237#define RT5659_MEMORY_TEST 0x0116238#define RT5659_VREF_REC_OP_FB_CAP_CTRL 0x0117239#define RT5659_CLASSD_0 0x011a240#define RT5659_CLASSD_1 0x011b241#define RT5659_CLASSD_2 0x011c242#define RT5659_CLASSD_3 0x011d243#define RT5659_CLASSD_4 0x011e244#define RT5659_CLASSD_5 0x011f245#define RT5659_CLASSD_6 0x0120246#define RT5659_CLASSD_7 0x0121247#define RT5659_CLASSD_8 0x0122248#define RT5659_CLASSD_9 0x0123249#define RT5659_CLASSD_10 0x0124250#define RT5659_CHARGE_PUMP_1 0x0125251#define RT5659_CHARGE_PUMP_2 0x0126252#define RT5659_DIG_IN_CTRL_1 0x0132253#define RT5659_DIG_IN_CTRL_2 0x0133254#define RT5659_PAD_DRIVING_CTRL 0x0137255#define RT5659_SOFT_RAMP_DEPOP 0x0138256#define RT5659_PLL 0x0139257#define RT5659_CHOP_DAC 0x013a258#define RT5659_CHOP_ADC 0x013b259#define RT5659_CALIB_ADC_CTRL 0x013c260#define RT5659_SOFT_RAMP_DEPOP_DAC_CLK_CTRL 0x013e261#define RT5659_VOL_TEST 0x013f262#define RT5659_TEST_MODE_CTRL_1 0x0145263#define RT5659_TEST_MODE_CTRL_2 0x0146264#define RT5659_TEST_MODE_CTRL_3 0x0147265#define RT5659_TEST_MODE_CTRL_4 0x0148266#define RT5659_BASSBACK_CTRL 0x0150267#define RT5659_MP3_PLUS_CTRL_1 0x0151268#define RT5659_MP3_PLUS_CTRL_2 0x0152269#define RT5659_MP3_HPF_A1 0x0153270#define RT5659_MP3_HPF_A2 0x0154271#define RT5659_MP3_HPF_H0 0x0155272#define RT5659_MP3_LPF_H0 0x0156273#define RT5659_3D_SPK_CTRL 0x0157274#define RT5659_3D_SPK_COEF_1 0x0158275#define RT5659_3D_SPK_COEF_2 0x0159276#define RT5659_3D_SPK_COEF_3 0x015a277#define RT5659_3D_SPK_COEF_4 0x015b278#define RT5659_3D_SPK_COEF_5 0x015c279#define RT5659_3D_SPK_COEF_6 0x015d280#define RT5659_3D_SPK_COEF_7 0x015e281#define RT5659_STO_NG2_CTRL_1 0x0160282#define RT5659_STO_NG2_CTRL_2 0x0161283#define RT5659_STO_NG2_CTRL_3 0x0162284#define RT5659_STO_NG2_CTRL_4 0x0163285#define RT5659_STO_NG2_CTRL_5 0x0164286#define RT5659_STO_NG2_CTRL_6 0x0165287#define RT5659_STO_NG2_CTRL_7 0x0166288#define RT5659_STO_NG2_CTRL_8 0x0167289#define RT5659_MONO_NG2_CTRL_1 0x0170290#define RT5659_MONO_NG2_CTRL_2 0x0171291#define RT5659_MONO_NG2_CTRL_3 0x0172292#define RT5659_MONO_NG2_CTRL_4 0x0173293#define RT5659_MONO_NG2_CTRL_5 0x0174294#define RT5659_MONO_NG2_CTRL_6 0x0175295#define RT5659_MID_HP_AMP_DET 0x0190296#define RT5659_LOW_HP_AMP_DET 0x0191297#define RT5659_LDO_CTRL 0x0192298#define RT5659_HP_DECROSS_CTRL_1 0x01b0299#define RT5659_HP_DECROSS_CTRL_2 0x01b1300#define RT5659_HP_DECROSS_CTRL_3 0x01b2301#define RT5659_HP_DECROSS_CTRL_4 0x01b3302#define RT5659_HP_IMP_SENS_CTRL_1 0x01c0303#define RT5659_HP_IMP_SENS_CTRL_2 0x01c1304#define RT5659_HP_IMP_SENS_CTRL_3 0x01c2305#define RT5659_HP_IMP_SENS_CTRL_4 0x01c3306#define RT5659_HP_IMP_SENS_MAP_1 0x01c7307#define RT5659_HP_IMP_SENS_MAP_2 0x01c8308#define RT5659_HP_IMP_SENS_MAP_3 0x01c9309#define RT5659_HP_IMP_SENS_MAP_4 0x01ca310#define RT5659_HP_IMP_SENS_MAP_5 0x01cb311#define RT5659_HP_IMP_SENS_MAP_6 0x01cc312#define RT5659_HP_IMP_SENS_MAP_7 0x01cd313#define RT5659_HP_IMP_SENS_MAP_8 0x01ce314#define RT5659_HP_LOGIC_CTRL_1 0x01da315#define RT5659_HP_LOGIC_CTRL_2 0x01db316#define RT5659_HP_CALIB_CTRL_1 0x01de317#define RT5659_HP_CALIB_CTRL_2 0x01df318#define RT5659_HP_CALIB_CTRL_3 0x01e0319#define RT5659_HP_CALIB_CTRL_4 0x01e1320#define RT5659_HP_CALIB_CTRL_5 0x01e2321#define RT5659_HP_CALIB_CTRL_6 0x01e3322#define RT5659_HP_CALIB_CTRL_7 0x01e4323#define RT5659_HP_CALIB_CTRL_9 0x01e6324#define RT5659_HP_CALIB_CTRL_10 0x01e7325#define RT5659_HP_CALIB_CTRL_11 0x01e8326#define RT5659_HP_CALIB_STA_1 0x01ea327#define RT5659_HP_CALIB_STA_2 0x01eb328#define RT5659_HP_CALIB_STA_3 0x01ec329#define RT5659_HP_CALIB_STA_4 0x01ed330#define RT5659_HP_CALIB_STA_5 0x01ee331#define RT5659_HP_CALIB_STA_6 0x01ef332#define RT5659_HP_CALIB_STA_7 0x01f0333#define RT5659_HP_CALIB_STA_8 0x01f1334#define RT5659_HP_CALIB_STA_9 0x01f2335#define RT5659_MONO_AMP_CALIB_CTRL_1 0x01f6336#define RT5659_MONO_AMP_CALIB_CTRL_2 0x01f7337#define RT5659_MONO_AMP_CALIB_CTRL_3 0x01f8338#define RT5659_MONO_AMP_CALIB_CTRL_4 0x01f9339#define RT5659_MONO_AMP_CALIB_CTRL_5 0x01fa340#define RT5659_MONO_AMP_CALIB_STA_1 0x01fb341#define RT5659_MONO_AMP_CALIB_STA_2 0x01fc342#define RT5659_MONO_AMP_CALIB_STA_3 0x01fd343#define RT5659_MONO_AMP_CALIB_STA_4 0x01fe344#define RT5659_SPK_PWR_LMT_CTRL_1 0x0200345#define RT5659_SPK_PWR_LMT_CTRL_2 0x0201346#define RT5659_SPK_PWR_LMT_CTRL_3 0x0202347#define RT5659_SPK_PWR_LMT_STA_1 0x0203348#define RT5659_SPK_PWR_LMT_STA_2 0x0204349#define RT5659_SPK_PWR_LMT_STA_3 0x0205350#define RT5659_SPK_PWR_LMT_STA_4 0x0206351#define RT5659_SPK_PWR_LMT_STA_5 0x0207352#define RT5659_SPK_PWR_LMT_STA_6 0x0208353#define RT5659_FLEX_SPK_BST_CTRL_1 0x0256354#define RT5659_FLEX_SPK_BST_CTRL_2 0x0257355#define RT5659_FLEX_SPK_BST_CTRL_3 0x0258356#define RT5659_FLEX_SPK_BST_CTRL_4 0x0259357#define RT5659_SPK_EX_LMT_CTRL_1 0x025a358#define RT5659_SPK_EX_LMT_CTRL_2 0x025b359#define RT5659_SPK_EX_LMT_CTRL_3 0x025c360#define RT5659_SPK_EX_LMT_CTRL_4 0x025d361#define RT5659_SPK_EX_LMT_CTRL_5 0x025e362#define RT5659_SPK_EX_LMT_CTRL_6 0x025f363#define RT5659_SPK_EX_LMT_CTRL_7 0x0260364#define RT5659_ADJ_HPF_CTRL_1 0x0261365#define RT5659_ADJ_HPF_CTRL_2 0x0262366#define RT5659_SPK_DC_CAILB_CTRL_1 0x0265367#define RT5659_SPK_DC_CAILB_CTRL_2 0x0266368#define RT5659_SPK_DC_CAILB_CTRL_3 0x0267369#define RT5659_SPK_DC_CAILB_CTRL_4 0x0268370#define RT5659_SPK_DC_CAILB_CTRL_5 0x0269371#define RT5659_SPK_DC_CAILB_STA_1 0x026a372#define RT5659_SPK_DC_CAILB_STA_2 0x026b373#define RT5659_SPK_DC_CAILB_STA_3 0x026c374#define RT5659_SPK_DC_CAILB_STA_4 0x026d375#define RT5659_SPK_DC_CAILB_STA_5 0x026e376#define RT5659_SPK_DC_CAILB_STA_6 0x026f377#define RT5659_SPK_DC_CAILB_STA_7 0x0270378#define RT5659_SPK_DC_CAILB_STA_8 0x0271379#define RT5659_SPK_DC_CAILB_STA_9 0x0272380#define RT5659_SPK_DC_CAILB_STA_10 0x0273381#define RT5659_SPK_VDD_STA_1 0x0280382#define RT5659_SPK_VDD_STA_2 0x0281383#define RT5659_SPK_DC_DET_CTRL_1 0x0282384#define RT5659_SPK_DC_DET_CTRL_2 0x0283385#define RT5659_SPK_DC_DET_CTRL_3 0x0284386#define RT5659_PURE_DC_DET_CTRL_1 0x0290387#define RT5659_PURE_DC_DET_CTRL_2 0x0291388#define RT5659_DUMMY_4 0x02fa389#define RT5659_DUMMY_5 0x02fb390#define RT5659_DUMMY_6 0x02fc391#define RT5659_DRC1_CTRL_1 0x0300392#define RT5659_DRC1_CTRL_2 0x0301393#define RT5659_DRC1_CTRL_3 0x0302394#define RT5659_DRC1_CTRL_4 0x0303395#define RT5659_DRC1_CTRL_5 0x0304396#define RT5659_DRC1_CTRL_6 0x0305397#define RT5659_DRC1_HARD_LMT_CTRL_1 0x0306398#define RT5659_DRC1_HARD_LMT_CTRL_2 0x0307399#define RT5659_DRC2_CTRL_1 0x0308400#define RT5659_DRC2_CTRL_2 0x0309401#define RT5659_DRC2_CTRL_3 0x030a402#define RT5659_DRC2_CTRL_4 0x030b403#define RT5659_DRC2_CTRL_5 0x030c404#define RT5659_DRC2_CTRL_6 0x030d405#define RT5659_DRC2_HARD_LMT_CTRL_1 0x030e406#define RT5659_DRC2_HARD_LMT_CTRL_2 0x030f407#define RT5659_DRC1_PRIV_1 0x0310408#define RT5659_DRC1_PRIV_2 0x0311409#define RT5659_DRC1_PRIV_3 0x0312410#define RT5659_DRC1_PRIV_4 0x0313411#define RT5659_DRC1_PRIV_5 0x0314412#define RT5659_DRC1_PRIV_6 0x0315413#define RT5659_DRC1_PRIV_7 0x0316414#define RT5659_DRC2_PRIV_1 0x0317415#define RT5659_DRC2_PRIV_2 0x0318416#define RT5659_DRC2_PRIV_3 0x0319417#define RT5659_DRC2_PRIV_4 0x031a418#define RT5659_DRC2_PRIV_5 0x031b419#define RT5659_DRC2_PRIV_6 0x031c420#define RT5659_DRC2_PRIV_7 0x031d421#define RT5659_MULTI_DRC_CTRL 0x0320422#define RT5659_CROSS_OVER_1 0x0321423#define RT5659_CROSS_OVER_2 0x0322424#define RT5659_CROSS_OVER_3 0x0323425#define RT5659_CROSS_OVER_4 0x0324426#define RT5659_CROSS_OVER_5 0x0325427#define RT5659_CROSS_OVER_6 0x0326428#define RT5659_CROSS_OVER_7 0x0327429#define RT5659_CROSS_OVER_8 0x0328430#define RT5659_CROSS_OVER_9 0x0329431#define RT5659_CROSS_OVER_10 0x032a432#define RT5659_ALC_PGA_CTRL_1 0x0330433#define RT5659_ALC_PGA_CTRL_2 0x0331434#define RT5659_ALC_PGA_CTRL_3 0x0332435#define RT5659_ALC_PGA_CTRL_4 0x0333436#define RT5659_ALC_PGA_CTRL_5 0x0334437#define RT5659_ALC_PGA_CTRL_6 0x0335438#define RT5659_ALC_PGA_CTRL_7 0x0336439#define RT5659_ALC_PGA_CTRL_8 0x0337440#define RT5659_ALC_PGA_STA_1 0x0338441#define RT5659_ALC_PGA_STA_2 0x0339442#define RT5659_ALC_PGA_STA_3 0x033a443#define RT5659_DAC_L_EQ_PRE_VOL 0x0340444#define RT5659_DAC_R_EQ_PRE_VOL 0x0341445#define RT5659_DAC_L_EQ_POST_VOL 0x0342446#define RT5659_DAC_R_EQ_POST_VOL 0x0343447#define RT5659_DAC_L_EQ_LPF1_A1 0x0344448#define RT5659_DAC_L_EQ_LPF1_H0 0x0345449#define RT5659_DAC_R_EQ_LPF1_A1 0x0346450#define RT5659_DAC_R_EQ_LPF1_H0 0x0347451#define RT5659_DAC_L_EQ_BPF2_A1 0x0348452#define RT5659_DAC_L_EQ_BPF2_A2 0x0349453#define RT5659_DAC_L_EQ_BPF2_H0 0x034a454#define RT5659_DAC_R_EQ_BPF2_A1 0x034b455#define RT5659_DAC_R_EQ_BPF2_A2 0x034c456#define RT5659_DAC_R_EQ_BPF2_H0 0x034d457#define RT5659_DAC_L_EQ_BPF3_A1 0x034e458#define RT5659_DAC_L_EQ_BPF3_A2 0x034f459#define RT5659_DAC_L_EQ_BPF3_H0 0x0350460#define RT5659_DAC_R_EQ_BPF3_A1 0x0351461#define RT5659_DAC_R_EQ_BPF3_A2 0x0352462#define RT5659_DAC_R_EQ_BPF3_H0 0x0353463#define RT5659_DAC_L_EQ_BPF4_A1 0x0354464#define RT5659_DAC_L_EQ_BPF4_A2 0x0355465#define RT5659_DAC_L_EQ_BPF4_H0 0x0356466#define RT5659_DAC_R_EQ_BPF4_A1 0x0357467#define RT5659_DAC_R_EQ_BPF4_A2 0x0358468#define RT5659_DAC_R_EQ_BPF4_H0 0x0359469#define RT5659_DAC_L_EQ_HPF1_A1 0x035a470#define RT5659_DAC_L_EQ_HPF1_H0 0x035b471#define RT5659_DAC_R_EQ_HPF1_A1 0x035c472#define RT5659_DAC_R_EQ_HPF1_H0 0x035d473#define RT5659_DAC_L_EQ_HPF2_A1 0x035e474#define RT5659_DAC_L_EQ_HPF2_A2 0x035f475#define RT5659_DAC_L_EQ_HPF2_H0 0x0360476#define RT5659_DAC_R_EQ_HPF2_A1 0x0361477#define RT5659_DAC_R_EQ_HPF2_A2 0x0362478#define RT5659_DAC_R_EQ_HPF2_H0 0x0363479#define RT5659_DAC_L_BI_EQ_BPF1_H0_1 0x0364480#define RT5659_DAC_L_BI_EQ_BPF1_H0_2 0x0365481#define RT5659_DAC_L_BI_EQ_BPF1_B1_1 0x0366482#define RT5659_DAC_L_BI_EQ_BPF1_B1_2 0x0367483#define RT5659_DAC_L_BI_EQ_BPF1_B2_1 0x0368484#define RT5659_DAC_L_BI_EQ_BPF1_B2_2 0x0369485#define RT5659_DAC_L_BI_EQ_BPF1_A1_1 0x036a486#define RT5659_DAC_L_BI_EQ_BPF1_A1_2 0x036b487#define RT5659_DAC_L_BI_EQ_BPF1_A2_1 0x036c488#define RT5659_DAC_L_BI_EQ_BPF1_A2_2 0x036d489#define RT5659_DAC_R_BI_EQ_BPF1_H0_1 0x036e490#define RT5659_DAC_R_BI_EQ_BPF1_H0_2 0x036f491#define RT5659_DAC_R_BI_EQ_BPF1_B1_1 0x0370492#define RT5659_DAC_R_BI_EQ_BPF1_B1_2 0x0371493#define RT5659_DAC_R_BI_EQ_BPF1_B2_1 0x0372494#define RT5659_DAC_R_BI_EQ_BPF1_B2_2 0x0373495#define RT5659_DAC_R_BI_EQ_BPF1_A1_1 0x0374496#define RT5659_DAC_R_BI_EQ_BPF1_A1_2 0x0375497#define RT5659_DAC_R_BI_EQ_BPF1_A2_1 0x0376498#define RT5659_DAC_R_BI_EQ_BPF1_A2_2 0x0377499#define RT5659_ADC_L_EQ_LPF1_A1 0x03d0500#define RT5659_ADC_R_EQ_LPF1_A1 0x03d1501#define RT5659_ADC_L_EQ_LPF1_H0 0x03d2502#define RT5659_ADC_R_EQ_LPF1_H0 0x03d3503#define RT5659_ADC_L_EQ_BPF1_A1 0x03d4504#define RT5659_ADC_R_EQ_BPF1_A1 0x03d5505#define RT5659_ADC_L_EQ_BPF1_A2 0x03d6506#define RT5659_ADC_R_EQ_BPF1_A2 0x03d7507#define RT5659_ADC_L_EQ_BPF1_H0 0x03d8508#define RT5659_ADC_R_EQ_BPF1_H0 0x03d9509#define RT5659_ADC_L_EQ_BPF2_A1 0x03da510#define RT5659_ADC_R_EQ_BPF2_A1 0x03db511#define RT5659_ADC_L_EQ_BPF2_A2 0x03dc512#define RT5659_ADC_R_EQ_BPF2_A2 0x03dd513#define RT5659_ADC_L_EQ_BPF2_H0 0x03de514#define RT5659_ADC_R_EQ_BPF2_H0 0x03df515#define RT5659_ADC_L_EQ_BPF3_A1 0x03e0516#define RT5659_ADC_R_EQ_BPF3_A1 0x03e1517#define RT5659_ADC_L_EQ_BPF3_A2 0x03e2518#define RT5659_ADC_R_EQ_BPF3_A2 0x03e3519#define RT5659_ADC_L_EQ_BPF3_H0 0x03e4520#define RT5659_ADC_R_EQ_BPF3_H0 0x03e5521#define RT5659_ADC_L_EQ_BPF4_A1 0x03e6522#define RT5659_ADC_R_EQ_BPF4_A1 0x03e7523#define RT5659_ADC_L_EQ_BPF4_A2 0x03e8524#define RT5659_ADC_R_EQ_BPF4_A2 0x03e9525#define RT5659_ADC_L_EQ_BPF4_H0 0x03ea526#define RT5659_ADC_R_EQ_BPF4_H0 0x03eb527#define RT5659_ADC_L_EQ_HPF1_A1 0x03ec528#define RT5659_ADC_R_EQ_HPF1_A1 0x03ed529#define RT5659_ADC_L_EQ_HPF1_H0 0x03ee530#define RT5659_ADC_R_EQ_HPF1_H0 0x03ef531#define RT5659_ADC_L_EQ_PRE_VOL 0x03f0532#define RT5659_ADC_R_EQ_PRE_VOL 0x03f1533#define RT5659_ADC_L_EQ_POST_VOL 0x03f2534#define RT5659_ADC_R_EQ_POST_VOL 0x03f3535 536 537 538/* global definition */539#define RT5659_L_MUTE (0x1 << 15)540#define RT5659_L_MUTE_SFT 15541#define RT5659_VOL_L_MUTE (0x1 << 14)542#define RT5659_VOL_L_SFT 14543#define RT5659_R_MUTE (0x1 << 7)544#define RT5659_R_MUTE_SFT 7545#define RT5659_VOL_R_MUTE (0x1 << 6)546#define RT5659_VOL_R_SFT 6547#define RT5659_L_VOL_MASK (0x3f << 8)548#define RT5659_L_VOL_SFT 8549#define RT5659_R_VOL_MASK (0x3f)550#define RT5659_R_VOL_SFT 0551 552/*Headphone Amp L/R Analog Gain and Digital NG2 Gain Control (0x0005 0x0006)*/553#define RT5659_G_HP (0x1f << 8)554#define RT5659_G_HP_SFT 8555#define RT5659_G_STO_DA_DMIX (0x1f)556#define RT5659_G_STO_DA_SFT 0557 558/* IN1/IN2 Control (0x000c) */559#define RT5659_IN1_DF_MASK (0x1 << 15)560#define RT5659_IN1_DF 15561#define RT5659_BST1_MASK (0x7f << 8)562#define RT5659_BST1_SFT 8563#define RT5659_BST2_MASK (0x7f)564#define RT5659_BST2_SFT 0565 566/* IN3/IN4 Control (0x000d) */567#define RT5659_IN3_DF_MASK (0x1 << 15)568#define RT5659_IN3_DF 15569#define RT5659_BST3_MASK (0x7f << 8)570#define RT5659_BST3_SFT 8571#define RT5659_IN4_DF_MASK (0x1 << 7)572#define RT5659_IN4_DF 7573#define RT5659_BST4_MASK (0x7f)574#define RT5659_BST4_SFT 0575 576/* INL and INR Volume Control (0x000f) */577#define RT5659_INL_VOL_MASK (0x1f << 8)578#define RT5659_INL_VOL_SFT 8579#define RT5659_INR_VOL_MASK (0x1f)580#define RT5659_INR_VOL_SFT 0581 582/* Embeeded Jack and Type Detection Control 1 (0x0010) */583#define RT5659_EMB_JD_EN (0x1 << 15)584#define RT5659_EMB_JD_EN_SFT 15585#define RT5659_JD_MODE (0x1 << 13)586#define RT5659_JD_MODE_SFT 13587#define RT5659_EXT_JD_EN (0x1 << 11)588#define RT5659_EXT_JD_EN_SFT 11589#define RT5659_EXT_JD_DIG (0x1 << 9)590 591/* Embeeded Jack and Type Detection Control 2 (0x0011) */592#define RT5659_EXT_JD_SRC (0x7 << 4)593#define RT5659_EXT_JD_SRC_SFT 4594#define RT5659_EXT_JD_SRC_GPIO_JD1 (0x0 << 4)595#define RT5659_EXT_JD_SRC_GPIO_JD2 (0x1 << 4)596#define RT5659_EXT_JD_SRC_JD1_1 (0x2 << 4)597#define RT5659_EXT_JD_SRC_JD1_2 (0x3 << 4)598#define RT5659_EXT_JD_SRC_JD2 (0x4 << 4)599#define RT5659_EXT_JD_SRC_JD3 (0x5 << 4)600#define RT5659_EXT_JD_SRC_MANUAL (0x6 << 4)601 602/* Slience Detection Control (0x0015) */603#define RT5659_SIL_DET_MASK (0x1 << 15)604#define RT5659_SIL_DET_DIS (0x0 << 15)605#define RT5659_SIL_DET_EN (0x1 << 15)606 607/* Sidetone Control (0x0018) */608#define RT5659_ST_SEL_MASK (0x7 << 9)609#define RT5659_ST_SEL_SFT 9610#define RT5659_ST_EN (0x1 << 6)611#define RT5659_ST_EN_SFT 6612 613/* DAC1 Digital Volume (0x0019) */614#define RT5659_DAC_L1_VOL_MASK (0xff << 8)615#define RT5659_DAC_L1_VOL_SFT 8616#define RT5659_DAC_R1_VOL_MASK (0xff)617#define RT5659_DAC_R1_VOL_SFT 0618 619/* DAC2 Digital Volume (0x001a) */620#define RT5659_DAC_L2_VOL_MASK (0xff << 8)621#define RT5659_DAC_L2_VOL_SFT 8622#define RT5659_DAC_R2_VOL_MASK (0xff)623#define RT5659_DAC_R2_VOL_SFT 0624 625/* DAC2 Control (0x001b) */626#define RT5659_M_DAC2_L_VOL (0x1 << 13)627#define RT5659_M_DAC2_L_VOL_SFT 13628#define RT5659_M_DAC2_R_VOL (0x1 << 12)629#define RT5659_M_DAC2_R_VOL_SFT 12630#define RT5659_DAC_L2_SEL_MASK (0x7 << 4)631#define RT5659_DAC_L2_SEL_SFT 4632#define RT5659_DAC_R2_SEL_MASK (0x7 << 0)633#define RT5659_DAC_R2_SEL_SFT 0634 635/* ADC Digital Volume Control (0x001c) */636#define RT5659_ADC_L_VOL_MASK (0x7f << 8)637#define RT5659_ADC_L_VOL_SFT 8638#define RT5659_ADC_R_VOL_MASK (0x7f)639#define RT5659_ADC_R_VOL_SFT 0640 641/* Mono ADC Digital Volume Control (0x001d) */642#define RT5659_MONO_ADC_L_VOL_MASK (0x7f << 8)643#define RT5659_MONO_ADC_L_VOL_SFT 8644#define RT5659_MONO_ADC_R_VOL_MASK (0x7f)645#define RT5659_MONO_ADC_R_VOL_SFT 0646 647/* Stereo1 ADC Boost Gain Control (0x001f) */648#define RT5659_STO1_ADC_L_BST_MASK (0x3 << 14)649#define RT5659_STO1_ADC_L_BST_SFT 14650#define RT5659_STO1_ADC_R_BST_MASK (0x3 << 12)651#define RT5659_STO1_ADC_R_BST_SFT 12652 653/* Mono ADC Boost Gain Control (0x0020) */654#define RT5659_MONO_ADC_L_BST_MASK (0x3 << 14)655#define RT5659_MONO_ADC_L_BST_SFT 14656#define RT5659_MONO_ADC_R_BST_MASK (0x3 << 12)657#define RT5659_MONO_ADC_R_BST_SFT 12658 659/* Stereo1 ADC Boost Gain Control (0x001f) */660#define RT5659_STO2_ADC_L_BST_MASK (0x3 << 14)661#define RT5659_STO2_ADC_L_BST_SFT 14662#define RT5659_STO2_ADC_R_BST_MASK (0x3 << 12)663#define RT5659_STO2_ADC_R_BST_SFT 12664 665/* Stereo ADC Mixer Control (0x0026) */666#define RT5659_M_STO1_ADC_L1 (0x1 << 15)667#define RT5659_M_STO1_ADC_L1_SFT 15668#define RT5659_M_STO1_ADC_L2 (0x1 << 14)669#define RT5659_M_STO1_ADC_L2_SFT 14670#define RT5659_STO1_ADC1_SRC_MASK (0x1 << 13)671#define RT5659_STO1_ADC1_SRC_SFT 13672#define RT5659_STO1_ADC1_SRC_ADC (0x1 << 13)673#define RT5659_STO1_ADC1_SRC_DACMIX (0x0 << 13)674#define RT5659_STO1_ADC_SRC_MASK (0x1 << 12)675#define RT5659_STO1_ADC_SRC_SFT 12676#define RT5659_STO1_ADC_SRC_ADC1 (0x1 << 12)677#define RT5659_STO1_ADC_SRC_ADC2 (0x0 << 12)678#define RT5659_STO1_ADC2_SRC_MASK (0x1 << 11)679#define RT5659_STO1_ADC2_SRC_SFT 11680#define RT5659_STO1_DMIC_SRC_MASK (0x1 << 8)681#define RT5659_STO1_DMIC_SRC_SFT 8682#define RT5659_STO1_DMIC_SRC_DMIC2 (0x1 << 8)683#define RT5659_STO1_DMIC_SRC_DMIC1 (0x0 << 8)684#define RT5659_M_STO1_ADC_R1 (0x1 << 6)685#define RT5659_M_STO1_ADC_R1_SFT 6686#define RT5659_M_STO1_ADC_R2 (0x1 << 5)687#define RT5659_M_STO1_ADC_R2_SFT 5688 689/* Mono1 ADC Mixer control (0x0027) */690#define RT5659_M_MONO_ADC_L1 (0x1 << 15)691#define RT5659_M_MONO_ADC_L1_SFT 15692#define RT5659_M_MONO_ADC_L2 (0x1 << 14)693#define RT5659_M_MONO_ADC_L2_SFT 14694#define RT5659_MONO_ADC_L2_SRC_MASK (0x1 << 12)695#define RT5659_MONO_ADC_L2_SRC_SFT 12696#define RT5659_MONO_ADC_L1_SRC_MASK (0x1 << 11)697#define RT5659_MONO_ADC_L1_SRC_SFT 11698#define RT5659_MONO_ADC_L_SRC_MASK (0x3 << 9)699#define RT5659_MONO_ADC_L_SRC_SFT 9700#define RT5659_MONO_DMIC_L_SRC_MASK (0x1 << 8)701#define RT5659_MONO_DMIC_L_SRC_SFT 8702#define RT5659_M_MONO_ADC_R1 (0x1 << 7)703#define RT5659_M_MONO_ADC_R1_SFT 7704#define RT5659_M_MONO_ADC_R2 (0x1 << 6)705#define RT5659_M_MONO_ADC_R2_SFT 6706#define RT5659_STO2_ADC_SRC_MASK (0x1 << 5)707#define RT5659_STO2_ADC_SRC_SFT 5708#define RT5659_MONO_ADC_R2_SRC_MASK (0x1 << 4)709#define RT5659_MONO_ADC_R2_SRC_SFT 4710#define RT5659_MONO_ADC_R1_SRC_MASK (0x1 << 3)711#define RT5659_MONO_ADC_R1_SRC_SFT 3712#define RT5659_MONO_ADC_R_SRC_MASK (0x3 << 1)713#define RT5659_MONO_ADC_R_SRC_SFT 1714#define RT5659_MONO_DMIC_R_SRC_MASK 0x1715#define RT5659_MONO_DMIC_R_SRC_SFT 0716 717/* ADC Mixer to DAC Mixer Control (0x0029) */718#define RT5659_M_ADCMIX_L (0x1 << 15)719#define RT5659_M_ADCMIX_L_SFT 15720#define RT5659_M_DAC1_L (0x1 << 14)721#define RT5659_M_DAC1_L_SFT 14722#define RT5659_DAC1_R_SEL_MASK (0x3 << 10)723#define RT5659_DAC1_R_SEL_SFT 10724#define RT5659_DAC1_R_SEL_IF1 (0x0 << 10)725#define RT5659_DAC1_R_SEL_IF2 (0x1 << 10)726#define RT5659_DAC1_R_SEL_IF3 (0x2 << 10)727#define RT5659_DAC1_L_SEL_MASK (0x3 << 8)728#define RT5659_DAC1_L_SEL_SFT 8729#define RT5659_DAC1_L_SEL_IF1 (0x0 << 8)730#define RT5659_DAC1_L_SEL_IF2 (0x1 << 8)731#define RT5659_DAC1_L_SEL_IF3 (0x2 << 8)732#define RT5659_M_ADCMIX_R (0x1 << 7)733#define RT5659_M_ADCMIX_R_SFT 7734#define RT5659_M_DAC1_R (0x1 << 6)735#define RT5659_M_DAC1_R_SFT 6736 737/* Stereo DAC Mixer Control (0x002a) */738#define RT5659_M_DAC_L1_STO_L (0x1 << 15)739#define RT5659_M_DAC_L1_STO_L_SFT 15740#define RT5659_G_DAC_L1_STO_L_MASK (0x1 << 14)741#define RT5659_G_DAC_L1_STO_L_SFT 14742#define RT5659_M_DAC_R1_STO_L (0x1 << 13)743#define RT5659_M_DAC_R1_STO_L_SFT 13744#define RT5659_G_DAC_R1_STO_L_MASK (0x1 << 12)745#define RT5659_G_DAC_R1_STO_L_SFT 12746#define RT5659_M_DAC_L2_STO_L (0x1 << 11)747#define RT5659_M_DAC_L2_STO_L_SFT 11748#define RT5659_G_DAC_L2_STO_L_MASK (0x1 << 10)749#define RT5659_G_DAC_L2_STO_L_SFT 10750#define RT5659_M_DAC_R2_STO_L (0x1 << 9)751#define RT5659_M_DAC_R2_STO_L_SFT 9752#define RT5659_G_DAC_R2_STO_L_MASK (0x1 << 8)753#define RT5659_G_DAC_R2_STO_L_SFT 8754#define RT5659_M_DAC_L1_STO_R (0x1 << 7)755#define RT5659_M_DAC_L1_STO_R_SFT 7756#define RT5659_G_DAC_L1_STO_R_MASK (0x1 << 6)757#define RT5659_G_DAC_L1_STO_R_SFT 6758#define RT5659_M_DAC_R1_STO_R (0x1 << 5)759#define RT5659_M_DAC_R1_STO_R_SFT 5760#define RT5659_G_DAC_R1_STO_R_MASK (0x1 << 4)761#define RT5659_G_DAC_R1_STO_R_SFT 4762#define RT5659_M_DAC_L2_STO_R (0x1 << 3)763#define RT5659_M_DAC_L2_STO_R_SFT 3764#define RT5659_G_DAC_L2_STO_R_MASK (0x1 << 2)765#define RT5659_G_DAC_L2_STO_R_SFT 2766#define RT5659_M_DAC_R2_STO_R (0x1 << 1)767#define RT5659_M_DAC_R2_STO_R_SFT 1768#define RT5659_G_DAC_R2_STO_R_MASK (0x1)769#define RT5659_G_DAC_R2_STO_R_SFT 0770 771/* Mono DAC Mixer Control (0x002b) */772#define RT5659_M_DAC_L1_MONO_L (0x1 << 15)773#define RT5659_M_DAC_L1_MONO_L_SFT 15774#define RT5659_G_DAC_L1_MONO_L_MASK (0x1 << 14)775#define RT5659_G_DAC_L1_MONO_L_SFT 14776#define RT5659_M_DAC_R1_MONO_L (0x1 << 13)777#define RT5659_M_DAC_R1_MONO_L_SFT 13778#define RT5659_G_DAC_R1_MONO_L_MASK (0x1 << 12)779#define RT5659_G_DAC_R1_MONO_L_SFT 12780#define RT5659_M_DAC_L2_MONO_L (0x1 << 11)781#define RT5659_M_DAC_L2_MONO_L_SFT 11782#define RT5659_G_DAC_L2_MONO_L_MASK (0x1 << 10)783#define RT5659_G_DAC_L2_MONO_L_SFT 10784#define RT5659_M_DAC_R2_MONO_L (0x1 << 9)785#define RT5659_M_DAC_R2_MONO_L_SFT 9786#define RT5659_G_DAC_R2_MONO_L_MASK (0x1 << 8)787#define RT5659_G_DAC_R2_MONO_L_SFT 8788#define RT5659_M_DAC_L1_MONO_R (0x1 << 7)789#define RT5659_M_DAC_L1_MONO_R_SFT 7790#define RT5659_G_DAC_L1_MONO_R_MASK (0x1 << 6)791#define RT5659_G_DAC_L1_MONO_R_SFT 6792#define RT5659_M_DAC_R1_MONO_R (0x1 << 5)793#define RT5659_M_DAC_R1_MONO_R_SFT 5794#define RT5659_G_DAC_R1_MONO_R_MASK (0x1 << 4)795#define RT5659_G_DAC_R1_MONO_R_SFT 4796#define RT5659_M_DAC_L2_MONO_R (0x1 << 3)797#define RT5659_M_DAC_L2_MONO_R_SFT 3798#define RT5659_G_DAC_L2_MONO_R_MASK (0x1 << 2)799#define RT5659_G_DAC_L2_MONO_R_SFT 2800#define RT5659_M_DAC_R2_MONO_R (0x1 << 1)801#define RT5659_M_DAC_R2_MONO_R_SFT 1802#define RT5659_G_DAC_R2_MONO_R_MASK (0x1)803#define RT5659_G_DAC_R2_MONO_R_SFT 0804 805/* Digital Mixer Control (0x002c) */806#define RT5659_M_DAC_MIX_L (0x1 << 7)807#define RT5659_M_DAC_MIX_L_SFT 7808#define RT5659_DAC_MIX_L_MASK (0x1 << 6)809#define RT5659_DAC_MIX_L_SFT 6810#define RT5659_M_DAC_MIX_R (0x1 << 5)811#define RT5659_M_DAC_MIX_R_SFT 5812#define RT5659_DAC_MIX_R_MASK (0x1 << 4)813#define RT5659_DAC_MIX_R_SFT 4814 815/* Analog DAC Input Source Control (0x002d) */816#define RT5659_A_DACL1_SEL (0x1 << 3)817#define RT5659_A_DACL1_SFT 3818#define RT5659_A_DACR1_SEL (0x1 << 2)819#define RT5659_A_DACR1_SFT 2820#define RT5659_A_DACL2_SEL (0x1 << 1)821#define RT5659_A_DACL2_SFT 1822#define RT5659_A_DACR2_SEL (0x1 << 0)823#define RT5659_A_DACR2_SFT 0824 825/* Digital Interface Data Control (0x002f) */826#define RT5659_IF2_ADC3_IN_MASK (0x3 << 14)827#define RT5659_IF2_ADC3_IN_SFT 14828#define RT5659_IF2_ADC_IN_MASK (0x3 << 12)829#define RT5659_IF2_ADC_IN_SFT 12830#define RT5659_IF2_DAC_SEL_MASK (0x3 << 10)831#define RT5659_IF2_DAC_SEL_SFT 10832#define RT5659_IF2_ADC_SEL_MASK (0x3 << 8)833#define RT5659_IF2_ADC_SEL_SFT 8834#define RT5659_IF3_DAC_SEL_MASK (0x3 << 6)835#define RT5659_IF3_DAC_SEL_SFT 6836#define RT5659_IF3_ADC_SEL_MASK (0x3 << 4)837#define RT5659_IF3_ADC_SEL_SFT 4838#define RT5659_IF3_ADC_IN_MASK (0x3 << 0)839#define RT5659_IF3_ADC_IN_SFT 0840 841/* PDM Output Control (0x0031) */842#define RT5659_PDM1_L_MASK (0x1 << 15)843#define RT5659_PDM1_L_SFT 15844#define RT5659_M_PDM1_L (0x1 << 14)845#define RT5659_M_PDM1_L_SFT 14846#define RT5659_PDM1_R_MASK (0x1 << 13)847#define RT5659_PDM1_R_SFT 13848#define RT5659_M_PDM1_R (0x1 << 12)849#define RT5659_M_PDM1_R_SFT 12850#define RT5659_PDM2_BUSY (0x1 << 7)851#define RT5659_PDM1_BUSY (0x1 << 6)852#define RT5659_PDM_PATTERN (0x1 << 5)853#define RT5659_PDM_GAIN (0x1 << 4)854#define RT5659_PDM_DIV_MASK (0x3)855 856/*S/PDIF Output Control (0x0036) */857#define RT5659_SPDIF_SEL_MASK (0x3 << 0)858#define RT5659_SPDIF_SEL_SFT 0859 860/* REC Left Mixer Control 2 (0x003c) */861#define RT5659_M_BST1_RM1_L (0x1 << 5)862#define RT5659_M_BST1_RM1_L_SFT 5863#define RT5659_M_BST2_RM1_L (0x1 << 4)864#define RT5659_M_BST2_RM1_L_SFT 4865#define RT5659_M_BST3_RM1_L (0x1 << 3)866#define RT5659_M_BST3_RM1_L_SFT 3867#define RT5659_M_BST4_RM1_L (0x1 << 2)868#define RT5659_M_BST4_RM1_L_SFT 2869#define RT5659_M_INL_RM1_L (0x1 << 1)870#define RT5659_M_INL_RM1_L_SFT 1871#define RT5659_M_SPKVOLL_RM1_L (0x1)872#define RT5659_M_SPKVOLL_RM1_L_SFT 0873 874/* REC Right Mixer Control 2 (0x003e) */875#define RT5659_M_BST1_RM1_R (0x1 << 5)876#define RT5659_M_BST1_RM1_R_SFT 5877#define RT5659_M_BST2_RM1_R (0x1 << 4)878#define RT5659_M_BST2_RM1_R_SFT 4879#define RT5659_M_BST3_RM1_R (0x1 << 3)880#define RT5659_M_BST3_RM1_R_SFT 3881#define RT5659_M_BST4_RM1_R (0x1 << 2)882#define RT5659_M_BST4_RM1_R_SFT 2883#define RT5659_M_INR_RM1_R (0x1 << 1)884#define RT5659_M_INR_RM1_R_SFT 1885#define RT5659_M_HPOVOLR_RM1_R (0x1)886#define RT5659_M_HPOVOLR_RM1_R_SFT 0887 888/* SPK Left Mixer Control (0x0046) */889#define RT5659_M_BST3_SM_L (0x1 << 4)890#define RT5659_M_BST3_SM_L_SFT 4891#define RT5659_M_IN_R_SM_L (0x1 << 3)892#define RT5659_M_IN_R_SM_L_SFT 3893#define RT5659_M_IN_L_SM_L (0x1 << 2)894#define RT5659_M_IN_L_SM_L_SFT 2895#define RT5659_M_BST1_SM_L (0x1 << 1)896#define RT5659_M_BST1_SM_L_SFT 1897#define RT5659_M_DAC_L2_SM_L (0x1)898#define RT5659_M_DAC_L2_SM_L_SFT 0899 900/* SPK Right Mixer Control (0x0047) */901#define RT5659_M_BST3_SM_R (0x1 << 4)902#define RT5659_M_BST3_SM_R_SFT 4903#define RT5659_M_IN_R_SM_R (0x1 << 3)904#define RT5659_M_IN_R_SM_R_SFT 3905#define RT5659_M_IN_L_SM_R (0x1 << 2)906#define RT5659_M_IN_L_SM_R_SFT 2907#define RT5659_M_BST4_SM_R (0x1 << 1)908#define RT5659_M_BST4_SM_R_SFT 1909#define RT5659_M_DAC_R2_SM_R (0x1)910#define RT5659_M_DAC_R2_SM_R_SFT 0911 912/* SPO Amp Input and Gain Control (0x0048) */913#define RT5659_M_DAC_L2_SPKOMIX (0x1 << 13)914#define RT5659_M_DAC_L2_SPKOMIX_SFT 13915#define RT5659_M_SPKVOLL_SPKOMIX (0x1 << 12)916#define RT5659_M_SPKVOLL_SPKOMIX_SFT 12917#define RT5659_M_DAC_R2_SPKOMIX (0x1 << 9)918#define RT5659_M_DAC_R2_SPKOMIX_SFT 9919#define RT5659_M_SPKVOLR_SPKOMIX (0x1 << 8)920#define RT5659_M_SPKVOLR_SPKOMIX_SFT 8921 922/* MONOMIX Input and Gain Control (0x004b) */923#define RT5659_M_MONOVOL_MA (0x1 << 9)924#define RT5659_M_MONOVOL_MA_SFT 9925#define RT5659_M_DAC_L2_MA (0x1 << 8)926#define RT5659_M_DAC_L2_MA_SFT 8927#define RT5659_M_BST3_MM (0x1 << 4)928#define RT5659_M_BST3_MM_SFT 4929#define RT5659_M_BST2_MM (0x1 << 3)930#define RT5659_M_BST2_MM_SFT 3931#define RT5659_M_BST1_MM (0x1 << 2)932#define RT5659_M_BST1_MM_SFT 2933#define RT5659_M_DAC_R2_MM (0x1 << 1)934#define RT5659_M_DAC_R2_MM_SFT 1935#define RT5659_M_DAC_L2_MM (0x1)936#define RT5659_M_DAC_L2_MM_SFT 0937 938/* Output Left Mixer Control 1 (0x004d) */939#define RT5659_G_BST3_OM_L_MASK (0x7 << 12)940#define RT5659_G_BST3_OM_L_SFT 12941#define RT5659_G_BST2_OM_L_MASK (0x7 << 9)942#define RT5659_G_BST2_OM_L_SFT 9943#define RT5659_G_BST1_OM_L_MASK (0x7 << 6)944#define RT5659_G_BST1_OM_L_SFT 6945#define RT5659_G_IN_L_OM_L_MASK (0x7 << 3)946#define RT5659_G_IN_L_OM_L_SFT 3947#define RT5659_G_DAC_L2_OM_L_MASK (0x7 << 0)948#define RT5659_G_DAC_L2_OM_L_SFT 0949 950/* Output Left Mixer Input Control (0x004e) */951#define RT5659_M_BST3_OM_L (0x1 << 4)952#define RT5659_M_BST3_OM_L_SFT 4953#define RT5659_M_BST2_OM_L (0x1 << 3)954#define RT5659_M_BST2_OM_L_SFT 3955#define RT5659_M_BST1_OM_L (0x1 << 2)956#define RT5659_M_BST1_OM_L_SFT 2957#define RT5659_M_IN_L_OM_L (0x1 << 1)958#define RT5659_M_IN_L_OM_L_SFT 1959#define RT5659_M_DAC_L2_OM_L (0x1)960#define RT5659_M_DAC_L2_OM_L_SFT 0961 962/* Output Right Mixer Input Control (0x0050) */963#define RT5659_M_BST4_OM_R (0x1 << 4)964#define RT5659_M_BST4_OM_R_SFT 4965#define RT5659_M_BST3_OM_R (0x1 << 3)966#define RT5659_M_BST3_OM_R_SFT 3967#define RT5659_M_BST2_OM_R (0x1 << 2)968#define RT5659_M_BST2_OM_R_SFT 2969#define RT5659_M_IN_R_OM_R (0x1 << 1)970#define RT5659_M_IN_R_OM_R_SFT 1971#define RT5659_M_DAC_R2_OM_R (0x1)972#define RT5659_M_DAC_R2_OM_R_SFT 0973 974/* LOUT Mixer Control (0x0052) */975#define RT5659_M_DAC_L2_LM (0x1 << 15)976#define RT5659_M_DAC_L2_LM_SFT 15977#define RT5659_M_DAC_R2_LM (0x1 << 14)978#define RT5659_M_DAC_R2_LM_SFT 14979#define RT5659_M_OV_L_LM (0x1 << 13)980#define RT5659_M_OV_L_LM_SFT 13981#define RT5659_M_OV_R_LM (0x1 << 12)982#define RT5659_M_OV_R_LM_SFT 12983 984/* Power Management for Digital 1 (0x0061) */985#define RT5659_PWR_I2S1 (0x1 << 15)986#define RT5659_PWR_I2S1_BIT 15987#define RT5659_PWR_I2S2 (0x1 << 14)988#define RT5659_PWR_I2S2_BIT 14989#define RT5659_PWR_I2S3 (0x1 << 13)990#define RT5659_PWR_I2S3_BIT 13991#define RT5659_PWR_SPDIF (0x1 << 12)992#define RT5659_PWR_SPDIF_BIT 12993#define RT5659_PWR_DAC_L1 (0x1 << 11)994#define RT5659_PWR_DAC_L1_BIT 11995#define RT5659_PWR_DAC_R1 (0x1 << 10)996#define RT5659_PWR_DAC_R1_BIT 10997#define RT5659_PWR_DAC_L2 (0x1 << 9)998#define RT5659_PWR_DAC_L2_BIT 9999#define RT5659_PWR_DAC_R2 (0x1 << 8)1000#define RT5659_PWR_DAC_R2_BIT 81001#define RT5659_PWR_LDO (0x1 << 7)1002#define RT5659_PWR_LDO_BIT 71003#define RT5659_PWR_ADC_L1 (0x1 << 4)1004#define RT5659_PWR_ADC_L1_BIT 41005#define RT5659_PWR_ADC_R1 (0x1 << 3)1006#define RT5659_PWR_ADC_R1_BIT 31007#define RT5659_PWR_ADC_L2 (0x1 << 2)1008#define RT5659_PWR_ADC_L2_BIT 21009#define RT5659_PWR_ADC_R2 (0x1 << 1)1010#define RT5659_PWR_ADC_R2_BIT 11011#define RT5659_PWR_CLS_D (0x1)1012#define RT5659_PWR_CLS_D_BIT 01013 1014/* Power Management for Digital 2 (0x0062) */1015#define RT5659_PWR_ADC_S1F (0x1 << 15)1016#define RT5659_PWR_ADC_S1F_BIT 151017#define RT5659_PWR_ADC_S2F (0x1 << 14)1018#define RT5659_PWR_ADC_S2F_BIT 141019#define RT5659_PWR_ADC_MF_L (0x1 << 13)1020#define RT5659_PWR_ADC_MF_L_BIT 131021#define RT5659_PWR_ADC_MF_R (0x1 << 12)1022#define RT5659_PWR_ADC_MF_R_BIT 121023#define RT5659_PWR_DAC_S1F (0x1 << 10)1024#define RT5659_PWR_DAC_S1F_BIT 101025#define RT5659_PWR_DAC_MF_L (0x1 << 9)1026#define RT5659_PWR_DAC_MF_L_BIT 91027#define RT5659_PWR_DAC_MF_R (0x1 << 8)1028#define RT5659_PWR_DAC_MF_R_BIT 81029#define RT5659_PWR_PDM1 (0x1 << 7)1030#define RT5659_PWR_PDM1_BIT 71031 1032/* Power Management for Analog 1 (0x0063) */1033#define RT5659_PWR_VREF1 (0x1 << 15)1034#define RT5659_PWR_VREF1_BIT 151035#define RT5659_PWR_FV1 (0x1 << 14)1036#define RT5659_PWR_FV1_BIT 141037#define RT5659_PWR_VREF2 (0x1 << 13)1038#define RT5659_PWR_VREF2_BIT 131039#define RT5659_PWR_FV2 (0x1 << 12)1040#define RT5659_PWR_FV2_BIT 121041#define RT5659_PWR_VREF3 (0x1 << 11)1042#define RT5659_PWR_VREF3_BIT 111043#define RT5659_PWR_FV3 (0x1 << 10)1044#define RT5659_PWR_FV3_BIT 101045#define RT5659_PWR_MB (0x1 << 9)1046#define RT5659_PWR_MB_BIT 91047#define RT5659_PWR_LM (0x1 << 8)1048#define RT5659_PWR_LM_BIT 81049#define RT5659_PWR_BG (0x1 << 7)1050#define RT5659_PWR_BG_BIT 71051#define RT5659_PWR_MA (0x1 << 6)1052#define RT5659_PWR_MA_BIT 61053#define RT5659_PWR_HA_L (0x1 << 5)1054#define RT5659_PWR_HA_L_BIT 51055#define RT5659_PWR_HA_R (0x1 << 4)1056#define RT5659_PWR_HA_R_BIT 41057 1058/* Power Management for Analog 2 (0x0064) */1059#define RT5659_PWR_BST1 (0x1 << 15)1060#define RT5659_PWR_BST1_BIT 151061#define RT5659_PWR_BST2 (0x1 << 14)1062#define RT5659_PWR_BST2_BIT 141063#define RT5659_PWR_BST3 (0x1 << 13)1064#define RT5659_PWR_BST3_BIT 131065#define RT5659_PWR_BST4 (0x1 << 12)1066#define RT5659_PWR_BST4_BIT 121067#define RT5659_PWR_MB1 (0x1 << 11)1068#define RT5659_PWR_MB1_BIT 111069#define RT5659_PWR_MB2 (0x1 << 10)1070#define RT5659_PWR_MB2_BIT 101071#define RT5659_PWR_MB3 (0x1 << 9)1072#define RT5659_PWR_MB3_BIT 91073#define RT5659_PWR_BST1_P (0x1 << 6)1074#define RT5659_PWR_BST1_P_BIT 61075#define RT5659_PWR_BST2_P (0x1 << 5)1076#define RT5659_PWR_BST2_P_BIT 51077#define RT5659_PWR_BST3_P (0x1 << 4)1078#define RT5659_PWR_BST3_P_BIT 41079#define RT5659_PWR_BST4_P (0x1 << 3)1080#define RT5659_PWR_BST4_P_BIT 31081#define RT5659_PWR_JD1 (0x1 << 2)1082#define RT5659_PWR_JD1_BIT 21083#define RT5659_PWR_JD2 (0x1 << 1)1084#define RT5659_PWR_JD2_BIT 11085#define RT5659_PWR_JD3 (0x1)1086#define RT5659_PWR_JD3_BIT 01087 1088/* Power Management for Analog 3 (0x0065) */1089#define RT5659_PWR_BST_L (0x1 << 8)1090#define RT5659_PWR_BST_L_BIT 81091#define RT5659_PWR_BST_R (0x1 << 7)1092#define RT5659_PWR_BST_R_BIT 71093#define RT5659_PWR_PLL (0x1 << 6)1094#define RT5659_PWR_PLL_BIT 61095#define RT5659_PWR_LDO5 (0x1 << 5)1096#define RT5659_PWR_LDO5_BIT 51097#define RT5659_PWR_LDO4 (0x1 << 4)1098#define RT5659_PWR_LDO4_BIT 41099#define RT5659_PWR_LDO3 (0x1 << 3)1100#define RT5659_PWR_LDO3_BIT 31101#define RT5659_PWR_LDO2 (0x1 << 2)1102#define RT5659_PWR_LDO2_BIT 21103#define RT5659_PWR_SVD (0x1 << 1)1104#define RT5659_PWR_SVD_BIT 11105 1106/* Power Management for Mixer (0x0066) */1107#define RT5659_PWR_OM_L (0x1 << 15)1108#define RT5659_PWR_OM_L_BIT 151109#define RT5659_PWR_OM_R (0x1 << 14)1110#define RT5659_PWR_OM_R_BIT 141111#define RT5659_PWR_SM_L (0x1 << 13)1112#define RT5659_PWR_SM_L_BIT 131113#define RT5659_PWR_SM_R (0x1 << 12)1114#define RT5659_PWR_SM_R_BIT 121115#define RT5659_PWR_RM1_L (0x1 << 11)1116#define RT5659_PWR_RM1_L_BIT 111117#define RT5659_PWR_RM1_R (0x1 << 10)1118#define RT5659_PWR_RM1_R_BIT 101119#define RT5659_PWR_MM (0x1 << 8)1120#define RT5659_PWR_MM_BIT 81121#define RT5659_PWR_RM2_L (0x1 << 3)1122#define RT5659_PWR_RM2_L_BIT 31123#define RT5659_PWR_RM2_R (0x1 << 2)1124#define RT5659_PWR_RM2_R_BIT 21125 1126/* Power Management for Volume (0x0067) */1127#define RT5659_PWR_SV_L (0x1 << 15)1128#define RT5659_PWR_SV_L_BIT 151129#define RT5659_PWR_SV_R (0x1 << 14)1130#define RT5659_PWR_SV_R_BIT 141131#define RT5659_PWR_OV_L (0x1 << 13)1132#define RT5659_PWR_OV_L_BIT 131133#define RT5659_PWR_OV_R (0x1 << 12)1134#define RT5659_PWR_OV_R_BIT 121135#define RT5659_PWR_IN_L (0x1 << 9)1136#define RT5659_PWR_IN_L_BIT 91137#define RT5659_PWR_IN_R (0x1 << 8)1138#define RT5659_PWR_IN_R_BIT 81139#define RT5659_PWR_MV (0x1 << 7)1140#define RT5659_PWR_MV_BIT 71141#define RT5659_PWR_MIC_DET (0x1 << 5)1142#define RT5659_PWR_MIC_DET_BIT 51143 1144/* I2S1/2/3 Audio Serial Data Port Control (0x0070 0x0071 0x0072) */1145#define RT5659_I2S_MS_MASK (0x1 << 15)1146#define RT5659_I2S_MS_SFT 151147#define RT5659_I2S_MS_M (0x0 << 15)1148#define RT5659_I2S_MS_S (0x1 << 15)1149#define RT5659_I2S_O_CP_MASK (0x3 << 12)1150#define RT5659_I2S_O_CP_SFT 121151#define RT5659_I2S_O_CP_OFF (0x0 << 12)1152#define RT5659_I2S_O_CP_U_LAW (0x1 << 12)1153#define RT5659_I2S_O_CP_A_LAW (0x2 << 12)1154#define RT5659_I2S_I_CP_MASK (0x3 << 10)1155#define RT5659_I2S_I_CP_SFT 101156#define RT5659_I2S_I_CP_OFF (0x0 << 10)1157#define RT5659_I2S_I_CP_U_LAW (0x1 << 10)1158#define RT5659_I2S_I_CP_A_LAW (0x2 << 10)1159#define RT5659_I2S_BP_MASK (0x1 << 8)1160#define RT5659_I2S_BP_SFT 81161#define RT5659_I2S_BP_NOR (0x0 << 8)1162#define RT5659_I2S_BP_INV (0x1 << 8)1163#define RT5659_I2S_DL_MASK (0x3 << 4)1164#define RT5659_I2S_DL_SFT 41165#define RT5659_I2S_DL_16 (0x0 << 4)1166#define RT5659_I2S_DL_20 (0x1 << 4)1167#define RT5659_I2S_DL_24 (0x2 << 4)1168#define RT5659_I2S_DL_8 (0x3 << 4)1169#define RT5659_I2S_DF_MASK (0x7)1170#define RT5659_I2S_DF_SFT 01171#define RT5659_I2S_DF_I2S (0x0)1172#define RT5659_I2S_DF_LEFT (0x1)1173#define RT5659_I2S_DF_PCM_A (0x2)1174#define RT5659_I2S_DF_PCM_B (0x3)1175#define RT5659_I2S_DF_PCM_A_N (0x6)1176#define RT5659_I2S_DF_PCM_B_N (0x7)1177 1178/* ADC/DAC Clock Control 1 (0x0073) */1179#define RT5659_I2S_PD1_MASK (0x7 << 12)1180#define RT5659_I2S_PD1_SFT 121181#define RT5659_I2S_PD1_1 (0x0 << 12)1182#define RT5659_I2S_PD1_2 (0x1 << 12)1183#define RT5659_I2S_PD1_3 (0x2 << 12)1184#define RT5659_I2S_PD1_4 (0x3 << 12)1185#define RT5659_I2S_PD1_6 (0x4 << 12)1186#define RT5659_I2S_PD1_8 (0x5 << 12)1187#define RT5659_I2S_PD1_12 (0x6 << 12)1188#define RT5659_I2S_PD1_16 (0x7 << 12)1189#define RT5659_I2S_BCLK_MS2_MASK (0x1 << 11)1190#define RT5659_I2S_BCLK_MS2_SFT 111191#define RT5659_I2S_BCLK_MS2_32 (0x0 << 11)1192#define RT5659_I2S_BCLK_MS2_64 (0x1 << 11)1193#define RT5659_I2S_PD2_MASK (0x7 << 8)1194#define RT5659_I2S_PD2_SFT 81195#define RT5659_I2S_PD2_1 (0x0 << 8)1196#define RT5659_I2S_PD2_2 (0x1 << 8)1197#define RT5659_I2S_PD2_3 (0x2 << 8)1198#define RT5659_I2S_PD2_4 (0x3 << 8)1199#define RT5659_I2S_PD2_6 (0x4 << 8)1200#define RT5659_I2S_PD2_8 (0x5 << 8)1201#define RT5659_I2S_PD2_12 (0x6 << 8)1202#define RT5659_I2S_PD2_16 (0x7 << 8)1203#define RT5659_I2S_BCLK_MS3_MASK (0x1 << 7)1204#define RT5659_I2S_BCLK_MS3_SFT 71205#define RT5659_I2S_BCLK_MS3_32 (0x0 << 7)1206#define RT5659_I2S_BCLK_MS3_64 (0x1 << 7)1207#define RT5659_I2S_PD3_MASK (0x7 << 4)1208#define RT5659_I2S_PD3_SFT 41209#define RT5659_I2S_PD3_1 (0x0 << 4)1210#define RT5659_I2S_PD3_2 (0x1 << 4)1211#define RT5659_I2S_PD3_3 (0x2 << 4)1212#define RT5659_I2S_PD3_4 (0x3 << 4)1213#define RT5659_I2S_PD3_6 (0x4 << 4)1214#define RT5659_I2S_PD3_8 (0x5 << 4)1215#define RT5659_I2S_PD3_12 (0x6 << 4)1216#define RT5659_I2S_PD3_16 (0x7 << 4)1217#define RT5659_DAC_OSR_MASK (0x3 << 2)1218#define RT5659_DAC_OSR_SFT 21219#define RT5659_DAC_OSR_128 (0x0 << 2)1220#define RT5659_DAC_OSR_64 (0x1 << 2)1221#define RT5659_DAC_OSR_32 (0x2 << 2)1222#define RT5659_DAC_OSR_16 (0x3 << 2)1223#define RT5659_ADC_OSR_MASK (0x3)1224#define RT5659_ADC_OSR_SFT 01225#define RT5659_ADC_OSR_128 (0x0)1226#define RT5659_ADC_OSR_64 (0x1)1227#define RT5659_ADC_OSR_32 (0x2)1228#define RT5659_ADC_OSR_16 (0x3)1229 1230/* Digital Microphone Control (0x0075) */1231#define RT5659_DMIC_1_EN_MASK (0x1 << 15)1232#define RT5659_DMIC_1_EN_SFT 151233#define RT5659_DMIC_1_DIS (0x0 << 15)1234#define RT5659_DMIC_1_EN (0x1 << 15)1235#define RT5659_DMIC_2_EN_MASK (0x1 << 14)1236#define RT5659_DMIC_2_EN_SFT 141237#define RT5659_DMIC_2_DIS (0x0 << 14)1238#define RT5659_DMIC_2_EN (0x1 << 14)1239#define RT5659_DMIC_1L_LH_MASK (0x1 << 13)1240#define RT5659_DMIC_1L_LH_SFT 131241#define RT5659_DMIC_1L_LH_RISING (0x0 << 13)1242#define RT5659_DMIC_1L_LH_FALLING (0x1 << 13)1243#define RT5659_DMIC_1R_LH_MASK (0x1 << 12)1244#define RT5659_DMIC_1R_LH_SFT 121245#define RT5659_DMIC_1R_LH_RISING (0x0 << 12)1246#define RT5659_DMIC_1R_LH_FALLING (0x1 << 12)1247#define RT5659_DMIC_2_DP_MASK (0x3 << 10)1248#define RT5659_DMIC_2_DP_SFT 101249#define RT5659_DMIC_2_DP_GPIO6 (0x0 << 10)1250#define RT5659_DMIC_2_DP_GPIO10 (0x1 << 10)1251#define RT5659_DMIC_2_DP_GPIO12 (0x2 << 10)1252#define RT5659_DMIC_2_DP_IN2P (0x3 << 10)1253#define RT5659_DMIC_CLK_MASK (0x7 << 5)1254#define RT5659_DMIC_CLK_SFT 51255#define RT5659_DMIC_1_DP_MASK (0x3 << 0)1256#define RT5659_DMIC_1_DP_SFT 01257#define RT5659_DMIC_1_DP_GPIO5 (0x0 << 0)1258#define RT5659_DMIC_1_DP_GPIO9 (0x1 << 0)1259#define RT5659_DMIC_1_DP_GPIO11 (0x2 << 0)1260#define RT5659_DMIC_1_DP_IN2N (0x3 << 0)1261 1262/* TDM control 1 (0x0078)*/1263#define RT5659_DS_ADC_SLOT01_SFT 141264#define RT5659_DS_ADC_SLOT23_SFT 121265#define RT5659_DS_ADC_SLOT45_SFT 101266#define RT5659_DS_ADC_SLOT67_SFT 81267#define RT5659_ADCDAT_SRC_MASK 0x1f1268#define RT5659_ADCDAT_SRC_SFT 01269 1270/* Global Clock Control (0x0080) */1271#define RT5659_SCLK_SRC_MASK (0x3 << 14)1272#define RT5659_SCLK_SRC_SFT 141273#define RT5659_SCLK_SRC_MCLK (0x0 << 14)1274#define RT5659_SCLK_SRC_PLL1 (0x1 << 14)1275#define RT5659_SCLK_SRC_RCCLK (0x2 << 14)1276#define RT5659_PLL1_SRC_MASK (0x7 << 11)1277#define RT5659_PLL1_SRC_SFT 111278#define RT5659_PLL1_SRC_MCLK (0x0 << 11)1279#define RT5659_PLL1_SRC_BCLK1 (0x1 << 11)1280#define RT5659_PLL1_SRC_BCLK2 (0x2 << 11)1281#define RT5659_PLL1_SRC_BCLK3 (0x3 << 11)1282#define RT5659_PLL1_PD_MASK (0x1 << 3)1283#define RT5659_PLL1_PD_SFT 31284#define RT5659_PLL1_PD_1 (0x0 << 3)1285#define RT5659_PLL1_PD_2 (0x1 << 3)1286 1287#define RT5659_PLL_INP_MAX 400000001288#define RT5659_PLL_INP_MIN 2560001289/* PLL M/N/K Code Control 1 (0x0081) */1290#define RT5659_PLL_N_MAX 0x001ff1291#define RT5659_PLL_N_MASK (RT5659_PLL_N_MAX << 7)1292#define RT5659_PLL_N_SFT 71293#define RT5659_PLL_K_MAX 0x001f1294#define RT5659_PLL_K_MASK (RT5659_PLL_K_MAX)1295#define RT5659_PLL_K_SFT 01296 1297/* PLL M/N/K Code Control 2 (0x0082) */1298#define RT5659_PLL_M_MAX 0x00f1299#define RT5659_PLL_M_MASK (RT5659_PLL_M_MAX << 12)1300#define RT5659_PLL_M_SFT 121301#define RT5659_PLL_M_BP (0x1 << 11)1302#define RT5659_PLL_M_BP_SFT 111303 1304/* PLL tracking mode 1 (0x0083) */1305#define RT5659_I2S3_ASRC_MASK (0x1 << 13)1306#define RT5659_I2S3_ASRC_SFT 131307#define RT5659_I2S2_ASRC_MASK (0x1 << 12)1308#define RT5659_I2S2_ASRC_SFT 121309#define RT5659_I2S1_ASRC_MASK (0x1 << 11)1310#define RT5659_I2S1_ASRC_SFT 111311#define RT5659_DAC_STO_ASRC_MASK (0x1 << 10)1312#define RT5659_DAC_STO_ASRC_SFT 101313#define RT5659_DAC_MONO_L_ASRC_MASK (0x1 << 9)1314#define RT5659_DAC_MONO_L_ASRC_SFT 91315#define RT5659_DAC_MONO_R_ASRC_MASK (0x1 << 8)1316#define RT5659_DAC_MONO_R_ASRC_SFT 81317#define RT5659_DMIC_STO1_ASRC_MASK (0x1 << 7)1318#define RT5659_DMIC_STO1_ASRC_SFT 71319#define RT5659_DMIC_MONO_L_ASRC_MASK (0x1 << 5)1320#define RT5659_DMIC_MONO_L_ASRC_SFT 51321#define RT5659_DMIC_MONO_R_ASRC_MASK (0x1 << 4)1322#define RT5659_DMIC_MONO_R_ASRC_SFT 41323#define RT5659_ADC_STO1_ASRC_MASK (0x1 << 3)1324#define RT5659_ADC_STO1_ASRC_SFT 31325#define RT5659_ADC_MONO_L_ASRC_MASK (0x1 << 1)1326#define RT5659_ADC_MONO_L_ASRC_SFT 11327#define RT5659_ADC_MONO_R_ASRC_MASK (0x1)1328#define RT5659_ADC_MONO_R_ASRC_SFT 01329 1330/* PLL tracking mode 2 (0x0084)*/1331#define RT5659_DA_STO_T_MASK (0x7 << 12)1332#define RT5659_DA_STO_T_SFT 121333#define RT5659_DA_MONO_L_T_MASK (0x7 << 8)1334#define RT5659_DA_MONO_L_T_SFT 81335#define RT5659_DA_MONO_R_T_MASK (0x7 << 4)1336#define RT5659_DA_MONO_R_T_SFT 41337#define RT5659_AD_STO1_T_MASK (0x7)1338#define RT5659_AD_STO1_T_SFT 01339 1340/* PLL tracking mode 3 (0x0085)*/1341#define RT5659_AD_STO2_T_MASK (0x7 << 8)1342#define RT5659_AD_STO2_T_SFT 81343#define RT5659_AD_MONO_L_T_MASK (0x7 << 4)1344#define RT5659_AD_MONO_L_T_SFT 41345#define RT5659_AD_MONO_R_T_MASK (0x7)1346#define RT5659_AD_MONO_R_T_SFT 01347 1348/* ASRC Control 4 (0x0086) */1349#define RT5659_I2S1_RATE_MASK (0xf << 12)1350#define RT5659_I2S1_RATE_SFT 121351#define RT5659_I2S2_RATE_MASK (0xf << 8)1352#define RT5659_I2S2_RATE_SFT 81353#define RT5659_I2S3_RATE_MASK (0xf << 4)1354#define RT5659_I2S3_RATE_SFT 41355 1356/* Depop Mode Control 1 (0x8e) */1357#define RT5659_SMT_TRIG_MASK (0x1 << 15)1358#define RT5659_SMT_TRIG_SFT 151359#define RT5659_SMT_TRIG_DIS (0x0 << 15)1360#define RT5659_SMT_TRIG_EN (0x1 << 15)1361#define RT5659_HP_L_SMT_MASK (0x1 << 9)1362#define RT5659_HP_L_SMT_SFT 91363#define RT5659_HP_L_SMT_DIS (0x0 << 9)1364#define RT5659_HP_L_SMT_EN (0x1 << 9)1365#define RT5659_HP_R_SMT_MASK (0x1 << 8)1366#define RT5659_HP_R_SMT_SFT 81367#define RT5659_HP_R_SMT_DIS (0x0 << 8)1368#define RT5659_HP_R_SMT_EN (0x1 << 8)1369#define RT5659_HP_CD_PD_MASK (0x1 << 7)1370#define RT5659_HP_CD_PD_SFT 71371#define RT5659_HP_CD_PD_DIS (0x0 << 7)1372#define RT5659_HP_CD_PD_EN (0x1 << 7)1373#define RT5659_RSTN_MASK (0x1 << 6)1374#define RT5659_RSTN_SFT 61375#define RT5659_RSTN_DIS (0x0 << 6)1376#define RT5659_RSTN_EN (0x1 << 6)1377#define RT5659_RSTP_MASK (0x1 << 5)1378#define RT5659_RSTP_SFT 51379#define RT5659_RSTP_DIS (0x0 << 5)1380#define RT5659_RSTP_EN (0x1 << 5)1381#define RT5659_HP_CO_MASK (0x1 << 4)1382#define RT5659_HP_CO_SFT 41383#define RT5659_HP_CO_DIS (0x0 << 4)1384#define RT5659_HP_CO_EN (0x1 << 4)1385#define RT5659_HP_CP_MASK (0x1 << 3)1386#define RT5659_HP_CP_SFT 31387#define RT5659_HP_CP_PD (0x0 << 3)1388#define RT5659_HP_CP_PU (0x1 << 3)1389#define RT5659_HP_SG_MASK (0x1 << 2)1390#define RT5659_HP_SG_SFT 21391#define RT5659_HP_SG_DIS (0x0 << 2)1392#define RT5659_HP_SG_EN (0x1 << 2)1393#define RT5659_HP_DP_MASK (0x1 << 1)1394#define RT5659_HP_DP_SFT 11395#define RT5659_HP_DP_PD (0x0 << 1)1396#define RT5659_HP_DP_PU (0x1 << 1)1397#define RT5659_HP_CB_MASK (0x1)1398#define RT5659_HP_CB_SFT 01399#define RT5659_HP_CB_PD (0x0)1400#define RT5659_HP_CB_PU (0x1)1401 1402/* Depop Mode Control 2 (0x8f) */1403#define RT5659_DEPOP_MASK (0x1 << 13)1404#define RT5659_DEPOP_SFT 131405#define RT5659_DEPOP_AUTO (0x0 << 13)1406#define RT5659_DEPOP_MAN (0x1 << 13)1407#define RT5659_RAMP_MASK (0x1 << 12)1408#define RT5659_RAMP_SFT 121409#define RT5659_RAMP_DIS (0x0 << 12)1410#define RT5659_RAMP_EN (0x1 << 12)1411#define RT5659_BPS_MASK (0x1 << 11)1412#define RT5659_BPS_SFT 111413#define RT5659_BPS_DIS (0x0 << 11)1414#define RT5659_BPS_EN (0x1 << 11)1415#define RT5659_FAST_UPDN_MASK (0x1 << 10)1416#define RT5659_FAST_UPDN_SFT 101417#define RT5659_FAST_UPDN_DIS (0x0 << 10)1418#define RT5659_FAST_UPDN_EN (0x1 << 10)1419#define RT5659_MRES_MASK (0x3 << 8)1420#define RT5659_MRES_SFT 81421#define RT5659_MRES_15MO (0x0 << 8)1422#define RT5659_MRES_25MO (0x1 << 8)1423#define RT5659_MRES_35MO (0x2 << 8)1424#define RT5659_MRES_45MO (0x3 << 8)1425#define RT5659_VLO_MASK (0x1 << 7)1426#define RT5659_VLO_SFT 71427#define RT5659_VLO_3V (0x0 << 7)1428#define RT5659_VLO_32V (0x1 << 7)1429#define RT5659_DIG_DP_MASK (0x1 << 6)1430#define RT5659_DIG_DP_SFT 61431#define RT5659_DIG_DP_DIS (0x0 << 6)1432#define RT5659_DIG_DP_EN (0x1 << 6)1433#define RT5659_DP_TH_MASK (0x3 << 4)1434#define RT5659_DP_TH_SFT 41435 1436/* Depop Mode Control 3 (0x90) */1437#define RT5659_CP_SYS_MASK (0x7 << 12)1438#define RT5659_CP_SYS_SFT 121439#define RT5659_CP_FQ1_MASK (0x7 << 8)1440#define RT5659_CP_FQ1_SFT 81441#define RT5659_CP_FQ2_MASK (0x7 << 4)1442#define RT5659_CP_FQ2_SFT 41443#define RT5659_CP_FQ3_MASK (0x7)1444#define RT5659_CP_FQ3_SFT 01445#define RT5659_CP_FQ_1_5_KHZ 01446#define RT5659_CP_FQ_3_KHZ 11447#define RT5659_CP_FQ_6_KHZ 21448#define RT5659_CP_FQ_12_KHZ 31449#define RT5659_CP_FQ_24_KHZ 41450#define RT5659_CP_FQ_48_KHZ 51451#define RT5659_CP_FQ_96_KHZ 61452#define RT5659_CP_FQ_192_KHZ 71453 1454/* HPOUT charge pump 1 (0x0091) */1455#define RT5659_OSW_L_MASK (0x1 << 11)1456#define RT5659_OSW_L_SFT 111457#define RT5659_OSW_L_DIS (0x0 << 11)1458#define RT5659_OSW_L_EN (0x1 << 11)1459#define RT5659_OSW_R_MASK (0x1 << 10)1460#define RT5659_OSW_R_SFT 101461#define RT5659_OSW_R_DIS (0x0 << 10)1462#define RT5659_OSW_R_EN (0x1 << 10)1463#define RT5659_PM_HP_MASK (0x3 << 8)1464#define RT5659_PM_HP_SFT 81465#define RT5659_PM_HP_LV (0x0 << 8)1466#define RT5659_PM_HP_MV (0x1 << 8)1467#define RT5659_PM_HP_HV (0x2 << 8)1468#define RT5659_IB_HP_MASK (0x3 << 6)1469#define RT5659_IB_HP_SFT 61470#define RT5659_IB_HP_125IL (0x0 << 6)1471#define RT5659_IB_HP_25IL (0x1 << 6)1472#define RT5659_IB_HP_5IL (0x2 << 6)1473#define RT5659_IB_HP_1IL (0x3 << 6)1474 1475/* PV detection and SPK gain control (0x92) */1476#define RT5659_PVDD_DET_MASK (0x1 << 15)1477#define RT5659_PVDD_DET_SFT 151478#define RT5659_PVDD_DET_DIS (0x0 << 15)1479#define RT5659_PVDD_DET_EN (0x1 << 15)1480#define RT5659_SPK_AG_MASK (0x1 << 14)1481#define RT5659_SPK_AG_SFT 141482#define RT5659_SPK_AG_DIS (0x0 << 14)1483#define RT5659_SPK_AG_EN (0x1 << 14)1484 1485/* Micbias Control (0x93) */1486#define RT5659_MIC1_BS_MASK (0x1 << 15)1487#define RT5659_MIC1_BS_SFT 151488#define RT5659_MIC1_BS_9AV (0x0 << 15)1489#define RT5659_MIC1_BS_75AV (0x1 << 15)1490#define RT5659_MIC2_BS_MASK (0x1 << 14)1491#define RT5659_MIC2_BS_SFT 141492#define RT5659_MIC2_BS_9AV (0x0 << 14)1493#define RT5659_MIC2_BS_75AV (0x1 << 14)1494#define RT5659_MIC1_CLK_MASK (0x1 << 13)1495#define RT5659_MIC1_CLK_SFT 131496#define RT5659_MIC1_CLK_DIS (0x0 << 13)1497#define RT5659_MIC1_CLK_EN (0x1 << 13)1498#define RT5659_MIC2_CLK_MASK (0x1 << 12)1499#define RT5659_MIC2_CLK_SFT 121500#define RT5659_MIC2_CLK_DIS (0x0 << 12)1501#define RT5659_MIC2_CLK_EN (0x1 << 12)1502#define RT5659_MIC1_OVCD_MASK (0x1 << 11)1503#define RT5659_MIC1_OVCD_SFT 111504#define RT5659_MIC1_OVCD_DIS (0x0 << 11)1505#define RT5659_MIC1_OVCD_EN (0x1 << 11)1506#define RT5659_MIC1_OVTH_MASK (0x3 << 9)1507#define RT5659_MIC1_OVTH_SFT 91508#define RT5659_MIC1_OVTH_600UA (0x0 << 9)1509#define RT5659_MIC1_OVTH_1500UA (0x1 << 9)1510#define RT5659_MIC1_OVTH_2000UA (0x2 << 9)1511#define RT5659_MIC2_OVCD_MASK (0x1 << 8)1512#define RT5659_MIC2_OVCD_SFT 81513#define RT5659_MIC2_OVCD_DIS (0x0 << 8)1514#define RT5659_MIC2_OVCD_EN (0x1 << 8)1515#define RT5659_MIC2_OVTH_MASK (0x3 << 6)1516#define RT5659_MIC2_OVTH_SFT 61517#define RT5659_MIC2_OVTH_600UA (0x0 << 6)1518#define RT5659_MIC2_OVTH_1500UA (0x1 << 6)1519#define RT5659_MIC2_OVTH_2000UA (0x2 << 6)1520#define RT5659_PWR_MB_MASK (0x1 << 5)1521#define RT5659_PWR_MB_SFT 51522#define RT5659_PWR_MB_PD (0x0 << 5)1523#define RT5659_PWR_MB_PU (0x1 << 5)1524#define RT5659_PWR_CLK25M_MASK (0x1 << 4)1525#define RT5659_PWR_CLK25M_SFT 41526#define RT5659_PWR_CLK25M_PD (0x0 << 4)1527#define RT5659_PWR_CLK25M_PU (0x1 << 4)1528 1529/* REC Mixer 2 Left Control 2 (0x009c) */1530#define RT5659_M_BST1_RM2_L (0x1 << 5)1531#define RT5659_M_BST1_RM2_L_SFT 51532#define RT5659_M_BST2_RM2_L (0x1 << 4)1533#define RT5659_M_BST2_RM2_L_SFT 41534#define RT5659_M_BST3_RM2_L (0x1 << 3)1535#define RT5659_M_BST3_RM2_L_SFT 31536#define RT5659_M_BST4_RM2_L (0x1 << 2)1537#define RT5659_M_BST4_RM2_L_SFT 21538#define RT5659_M_OUTVOLL_RM2_L (0x1 << 1)1539#define RT5659_M_OUTVOLL_RM2_L_SFT 11540#define RT5659_M_SPKVOL_RM2_L (0x1)1541#define RT5659_M_SPKVOL_RM2_L_SFT 01542 1543/* REC Mixer 2 Right Control 2 (0x009e) */1544#define RT5659_M_BST1_RM2_R (0x1 << 5)1545#define RT5659_M_BST1_RM2_R_SFT 51546#define RT5659_M_BST2_RM2_R (0x1 << 4)1547#define RT5659_M_BST2_RM2_R_SFT 41548#define RT5659_M_BST3_RM2_R (0x1 << 3)1549#define RT5659_M_BST3_RM2_R_SFT 31550#define RT5659_M_BST4_RM2_R (0x1 << 2)1551#define RT5659_M_BST4_RM2_R_SFT 21552#define RT5659_M_OUTVOLR_RM2_R (0x1 << 1)1553#define RT5659_M_OUTVOLR_RM2_R_SFT 11554#define RT5659_M_MONOVOL_RM2_R (0x1)1555#define RT5659_M_MONOVOL_RM2_R_SFT 01556 1557/* Class D Output Control (0x00a0) */1558#define RT5659_POW_CLSD_DB_MASK (0x1 << 9)1559#define RT5659_POW_CLSD_DB_EN (0x1 << 9)1560#define RT5659_POW_CLSD_DB_DIS (0x0 << 9)1561 1562/* EQ Control 1 (0x00b0) */1563#define RT5659_EQ_SRC_DAC (0x0 << 15)1564#define RT5659_EQ_SRC_ADC (0x1 << 15)1565#define RT5659_EQ_UPD (0x1 << 14)1566#define RT5659_EQ_UPD_BIT 141567#define RT5659_EQ_CD_MASK (0x1 << 13)1568#define RT5659_EQ_CD_SFT 131569#define RT5659_EQ_CD_DIS (0x0 << 13)1570#define RT5659_EQ_CD_EN (0x1 << 13)1571#define RT5659_EQ_DITH_MASK (0x3 << 8)1572#define RT5659_EQ_DITH_SFT 81573#define RT5659_EQ_DITH_NOR (0x0 << 8)1574#define RT5659_EQ_DITH_LSB (0x1 << 8)1575#define RT5659_EQ_DITH_LSB_1 (0x2 << 8)1576#define RT5659_EQ_DITH_LSB_2 (0x3 << 8)1577 1578/* IRQ Control 1 (0x00b7) */1579#define RT5659_JD1_1_EN_MASK (0x1 << 15)1580#define RT5659_JD1_1_EN_SFT 151581#define RT5659_JD1_1_DIS (0x0 << 15)1582#define RT5659_JD1_1_EN (0x1 << 15)1583#define RT5659_JD1_2_EN_MASK (0x1 << 12)1584#define RT5659_JD1_2_EN_SFT 121585#define RT5659_JD1_2_DIS (0x0 << 12)1586#define RT5659_JD1_2_EN (0x1 << 12)1587#define RT5659_IL_IRQ_MASK (0x1 << 3)1588#define RT5659_IL_IRQ_DIS (0x0 << 3)1589#define RT5659_IL_IRQ_EN (0x1 << 3)1590 1591/* IRQ Control 5 (0x00ba) */1592#define RT5659_IRQ_JD_EN (0x1 << 3)1593#define RT5659_IRQ_JD_EN_SFT 31594 1595/* GPIO Control 1 (0x00c0) */1596#define RT5659_GP1_PIN_MASK (0x1 << 15)1597#define RT5659_GP1_PIN_SFT 151598#define RT5659_GP1_PIN_GPIO1 (0x0 << 15)1599#define RT5659_GP1_PIN_IRQ (0x1 << 15)1600#define RT5659_GP2_PIN_MASK (0x1 << 14)1601#define RT5659_GP2_PIN_SFT 141602#define RT5659_GP2_PIN_GPIO2 (0x0 << 14)1603#define RT5659_GP2_PIN_DMIC1_SCL (0x1 << 14)1604#define RT5659_GP3_PIN_MASK (0x1 << 13)1605#define RT5659_GP3_PIN_SFT 131606#define RT5659_GP3_PIN_GPIO3 (0x0 << 13)1607#define RT5659_GP3_PIN_PDM_SCL (0x1 << 13)1608#define RT5659_GP4_PIN_MASK (0x1 << 12)1609#define RT5659_GP4_PIN_SFT 121610#define RT5659_GP4_PIN_GPIO4 (0x0 << 12)1611#define RT5659_GP4_PIN_PDM_SDA (0x1 << 12)1612#define RT5659_GP5_PIN_MASK (0x1 << 11)1613#define RT5659_GP5_PIN_SFT 111614#define RT5659_GP5_PIN_GPIO5 (0x0 << 11)1615#define RT5659_GP5_PIN_DMIC1_SDA (0x1 << 11)1616#define RT5659_GP6_PIN_MASK (0x1 << 10)1617#define RT5659_GP6_PIN_SFT 101618#define RT5659_GP6_PIN_GPIO6 (0x0 << 10)1619#define RT5659_GP6_PIN_DMIC2_SDA (0x1 << 10)1620#define RT5659_GP7_PIN_MASK (0x1 << 9)1621#define RT5659_GP7_PIN_SFT 91622#define RT5659_GP7_PIN_GPIO7 (0x0 << 9)1623#define RT5659_GP7_PIN_PDM_SCL (0x1 << 9)1624#define RT5659_GP8_PIN_MASK (0x1 << 8)1625#define RT5659_GP8_PIN_SFT 81626#define RT5659_GP8_PIN_GPIO8 (0x0 << 8)1627#define RT5659_GP8_PIN_PDM_SDA (0x1 << 8)1628#define RT5659_GP9_PIN_MASK (0x1 << 7)1629#define RT5659_GP9_PIN_SFT 71630#define RT5659_GP9_PIN_GPIO9 (0x0 << 7)1631#define RT5659_GP9_PIN_DMIC1_SDA (0x1 << 7)1632#define RT5659_GP10_PIN_MASK (0x1 << 6)1633#define RT5659_GP10_PIN_SFT 61634#define RT5659_GP10_PIN_GPIO10 (0x0 << 6)1635#define RT5659_GP10_PIN_DMIC2_SDA (0x1 << 6)1636#define RT5659_GP11_PIN_MASK (0x1 << 5)1637#define RT5659_GP11_PIN_SFT 51638#define RT5659_GP11_PIN_GPIO11 (0x0 << 5)1639#define RT5659_GP11_PIN_DMIC1_SDA (0x1 << 5)1640#define RT5659_GP12_PIN_MASK (0x1 << 4)1641#define RT5659_GP12_PIN_SFT 41642#define RT5659_GP12_PIN_GPIO12 (0x0 << 4)1643#define RT5659_GP12_PIN_DMIC2_SDA (0x1 << 4)1644#define RT5659_GP13_PIN_MASK (0x3 << 2)1645#define RT5659_GP13_PIN_SFT 21646#define RT5659_GP13_PIN_GPIO13 (0x0 << 2)1647#define RT5659_GP13_PIN_SPDIF_SDA (0x1 << 2)1648#define RT5659_GP13_PIN_DMIC2_SCL (0x2 << 2)1649#define RT5659_GP13_PIN_PDM_SCL (0x3 << 2)1650#define RT5659_GP15_PIN_MASK (0x3)1651#define RT5659_GP15_PIN_SFT 01652#define RT5659_GP15_PIN_GPIO15 (0x0)1653#define RT5659_GP15_PIN_DMIC3_SCL (0x1)1654#define RT5659_GP15_PIN_PDM_SDA (0x2)1655 1656/* GPIO Control 2 (0x00c1)*/1657#define RT5659_GP1_PF_IN (0x0 << 2)1658#define RT5659_GP1_PF_OUT (0x1 << 2)1659#define RT5659_GP1_PF_MASK (0x1 << 2)1660#define RT5659_GP1_PF_SFT 21661 1662/* GPIO Control 3 (0x00c2) */1663#define RT5659_I2S2_PIN_MASK (0x1 << 15)1664#define RT5659_I2S2_PIN_SFT 151665#define RT5659_I2S2_PIN_I2S (0x0 << 15)1666#define RT5659_I2S2_PIN_GPIO (0x1 << 15)1667 1668/* Soft volume and zero cross control 1 (0x00d9) */1669#define RT5659_SV_MASK (0x1 << 15)1670#define RT5659_SV_SFT 151671#define RT5659_SV_DIS (0x0 << 15)1672#define RT5659_SV_EN (0x1 << 15)1673#define RT5659_OUT_SV_MASK (0x1 << 13)1674#define RT5659_OUT_SV_SFT 131675#define RT5659_OUT_SV_DIS (0x0 << 13)1676#define RT5659_OUT_SV_EN (0x1 << 13)1677#define RT5659_HP_SV_MASK (0x1 << 12)1678#define RT5659_HP_SV_SFT 121679#define RT5659_HP_SV_DIS (0x0 << 12)1680#define RT5659_HP_SV_EN (0x1 << 12)1681#define RT5659_ZCD_DIG_MASK (0x1 << 11)1682#define RT5659_ZCD_DIG_SFT 111683#define RT5659_ZCD_DIG_DIS (0x0 << 11)1684#define RT5659_ZCD_DIG_EN (0x1 << 11)1685#define RT5659_ZCD_MASK (0x1 << 10)1686#define RT5659_ZCD_SFT 101687#define RT5659_ZCD_PD (0x0 << 10)1688#define RT5659_ZCD_PU (0x1 << 10)1689#define RT5659_SV_DLY_MASK (0xf)1690#define RT5659_SV_DLY_SFT 01691 1692/* Soft volume and zero cross control 2 (0x00da) */1693#define RT5659_ZCD_HP_MASK (0x1 << 15)1694#define RT5659_ZCD_HP_SFT 151695#define RT5659_ZCD_HP_DIS (0x0 << 15)1696#define RT5659_ZCD_HP_EN (0x1 << 15)1697 1698/* 4 Button Inline Command Control 2 (0x00e0) */1699#define RT5659_4BTN_IL_MASK (0x1 << 15)1700#define RT5659_4BTN_IL_EN (0x1 << 15)1701#define RT5659_4BTN_IL_DIS (0x0 << 15)1702 1703/* Analog JD Control 1 (0x00f0) */1704#define RT5659_JD1_MODE_MASK (0x3 << 0)1705#define RT5659_JD1_MODE_0 (0x0 << 0)1706#define RT5659_JD1_MODE_1 (0x1 << 0)1707#define RT5659_JD1_MODE_2 (0x2 << 0)1708 1709/* Jack Detect Control 3 (0x00f8) */1710#define RT5659_JD_TRI_HPO_SEL_MASK (0x7)1711#define RT5659_JD_TRI_HPO_SEL_SFT (0)1712#define RT5659_JD_HPO_GPIO_JD1 (0x0)1713#define RT5659_JD_HPO_JD1_1 (0x1)1714#define RT5659_JD_HPO_JD1_2 (0x2)1715#define RT5659_JD_HPO_JD2 (0x3)1716#define RT5659_JD_HPO_GPIO_JD2 (0x4)1717#define RT5659_JD_HPO_JD3 (0x5)1718#define RT5659_JD_HPO_JD_D (0x6)1719 1720/* Digital Misc Control (0x00fa) */1721#define RT5659_AM_MASK (0x1 << 7)1722#define RT5659_AM_EN (0x1 << 7)1723#define RT5659_AM_DIS (0x1 << 7)1724#define RT5659_DIG_GATE_CTRL 0x11725#define RT5659_DIG_GATE_CTRL_SFT (0)1726 1727/* Chopper and Clock control for ADC (0x011c)*/1728#define RT5659_M_RF_DIG_MASK (0x1 << 12)1729#define RT5659_M_RF_DIG_SFT 121730#define RT5659_M_RI_DIG (0x1 << 11)1731 1732/* Chopper and Clock control for DAC (0x013a)*/1733#define RT5659_CKXEN_DAC1_MASK (0x1 << 13)1734#define RT5659_CKXEN_DAC1_SFT 131735#define RT5659_CKGEN_DAC1_MASK (0x1 << 12)1736#define RT5659_CKGEN_DAC1_SFT 121737#define RT5659_CKXEN_DAC2_MASK (0x1 << 5)1738#define RT5659_CKXEN_DAC2_SFT 51739#define RT5659_CKGEN_DAC2_MASK (0x1 << 4)1740#define RT5659_CKGEN_DAC2_SFT 41741 1742/* Chopper and Clock control for ADC (0x013b)*/1743#define RT5659_CKXEN_ADC1_MASK (0x1 << 13)1744#define RT5659_CKXEN_ADC1_SFT 131745#define RT5659_CKGEN_ADC1_MASK (0x1 << 12)1746#define RT5659_CKGEN_ADC1_SFT 121747#define RT5659_CKXEN_ADC2_MASK (0x1 << 5)1748#define RT5659_CKXEN_ADC2_SFT 51749#define RT5659_CKGEN_ADC2_MASK (0x1 << 4)1750#define RT5659_CKGEN_ADC2_SFT 41751 1752/* Test Mode Control 1 (0x0145) */1753#define RT5659_AD2DA_LB_MASK (0x1 << 9)1754#define RT5659_AD2DA_LB_SFT 91755 1756/* Stereo Noise Gate Control 1 (0x0160) */1757#define RT5659_NG2_EN_MASK (0x1 << 15)1758#define RT5659_NG2_EN (0x1 << 15)1759#define RT5659_NG2_DIS (0x0 << 15)1760 1761/* System Clock Source */1762enum {1763 RT5659_SCLK_S_MCLK,1764 RT5659_SCLK_S_PLL1,1765 RT5659_SCLK_S_RCCLK,1766};1767 1768/* PLL1 Source */1769enum {1770 RT5659_PLL1_S_MCLK,1771 RT5659_PLL1_S_BCLK1,1772 RT5659_PLL1_S_BCLK2,1773 RT5659_PLL1_S_BCLK3,1774 RT5659_PLL1_S_BCLK4,1775};1776 1777enum {1778 RT5659_AIF1,1779 RT5659_AIF2,1780 RT5659_AIF3,1781 RT5659_AIF4,1782 RT5659_AIFS,1783};1784 1785struct rt5659_pll_code {1786 bool m_bp;1787 int m_code;1788 int n_code;1789 int k_code;1790};1791 1792struct rt5659_priv {1793 struct snd_soc_component *component;1794 struct rt5659_platform_data pdata;1795 struct regmap *regmap;1796 struct gpio_desc *gpiod_ldo1_en;1797 struct gpio_desc *gpiod_reset;1798 struct snd_soc_jack *hs_jack;1799 struct delayed_work jack_detect_work;1800 struct clk *mclk;1801 1802 int sysclk;1803 int sysclk_src;1804 int lrck[RT5659_AIFS];1805 int bclk[RT5659_AIFS];1806 int master[RT5659_AIFS];1807 int v_id;1808 1809 int pll_src;1810 int pll_in;1811 int pll_out;1812 1813 int jack_type;1814 bool hda_hp_plugged;1815 bool hda_mic_plugged;1816};1817 1818int rt5659_set_jack_detect(struct snd_soc_component *component,1819 struct snd_soc_jack *hs_jack);1820 1821#endif /* __RT5659_H__ */1822