2006 lines · c
1/* SPDX-License-Identifier: GPL-2.0-only */2/*3 * rt5665.h -- RT5665/RT5658 ALSA SoC audio driver4 *5 * Copyright 2016 Realtek Microelectronics6 * Author: Bard Liao <bardliao@realtek.com>7 */8 9#ifndef __RT5665_H__10#define __RT5665_H__11 12#include <sound/rt5665.h>13 14#define DEVICE_ID 0x645115 16/* Info */17#define RT5665_RESET 0x000018#define RT5665_VENDOR_ID 0x00fd19#define RT5665_VENDOR_ID_1 0x00fe20#define RT5665_DEVICE_ID 0x00ff21/* I/O - Output */22#define RT5665_LOUT 0x000123#define RT5665_HP_CTRL_1 0x000224#define RT5665_HP_CTRL_2 0x000325#define RT5665_MONO_OUT 0x000426#define RT5665_HPL_GAIN 0x000527#define RT5665_HPR_GAIN 0x000628#define RT5665_MONO_GAIN 0x000729 30/* I/O - Input */31#define RT5665_CAL_BST_CTRL 0x000a32#define RT5665_CBJ_BST_CTRL 0x000b33#define RT5665_IN1_IN2 0x000c34#define RT5665_IN3_IN4 0x000d35#define RT5665_INL1_INR1_VOL 0x000f36/* I/O - Speaker */37#define RT5665_EJD_CTRL_1 0x001038#define RT5665_EJD_CTRL_2 0x001139#define RT5665_EJD_CTRL_3 0x001240#define RT5665_EJD_CTRL_4 0x001341#define RT5665_EJD_CTRL_5 0x001442#define RT5665_EJD_CTRL_6 0x001543#define RT5665_EJD_CTRL_7 0x001644/* I/O - ADC/DAC/DMIC */45#define RT5665_DAC2_CTRL 0x001746#define RT5665_DAC2_DIG_VOL 0x001847#define RT5665_DAC1_DIG_VOL 0x001948#define RT5665_DAC3_DIG_VOL 0x001a49#define RT5665_DAC3_CTRL 0x001b50#define RT5665_STO1_ADC_DIG_VOL 0x001c51#define RT5665_MONO_ADC_DIG_VOL 0x001d52#define RT5665_STO2_ADC_DIG_VOL 0x001e53#define RT5665_STO1_ADC_BOOST 0x001f54#define RT5665_MONO_ADC_BOOST 0x002055#define RT5665_STO2_ADC_BOOST 0x002156#define RT5665_HP_IMP_GAIN_1 0x002257#define RT5665_HP_IMP_GAIN_2 0x002358/* Mixer - D-D */59#define RT5665_STO1_ADC_MIXER 0x002660#define RT5665_MONO_ADC_MIXER 0x002761#define RT5665_STO2_ADC_MIXER 0x002862#define RT5665_AD_DA_MIXER 0x002963#define RT5665_STO1_DAC_MIXER 0x002a64#define RT5665_MONO_DAC_MIXER 0x002b65#define RT5665_STO2_DAC_MIXER 0x002c66#define RT5665_A_DAC1_MUX 0x002d67#define RT5665_A_DAC2_MUX 0x002e68#define RT5665_DIG_INF2_DATA 0x002f69#define RT5665_DIG_INF3_DATA 0x003070/* Mixer - PDM */71#define RT5665_PDM_OUT_CTRL 0x003172#define RT5665_PDM_DATA_CTRL_1 0x003273#define RT5665_PDM_DATA_CTRL_2 0x003374#define RT5665_PDM_DATA_CTRL_3 0x003475#define RT5665_PDM_DATA_CTRL_4 0x003576/* Mixer - ADC */77#define RT5665_REC1_GAIN 0x003a78#define RT5665_REC1_L1_MIXER 0x003b79#define RT5665_REC1_L2_MIXER 0x003c80#define RT5665_REC1_R1_MIXER 0x003d81#define RT5665_REC1_R2_MIXER 0x003e82#define RT5665_REC2_GAIN 0x003f83#define RT5665_REC2_L1_MIXER 0x004084#define RT5665_REC2_L2_MIXER 0x004185#define RT5665_REC2_R1_MIXER 0x004286#define RT5665_REC2_R2_MIXER 0x004387#define RT5665_CAL_REC 0x004488/* Mixer - DAC */89#define RT5665_ALC_BACK_GAIN 0x004990#define RT5665_MONOMIX_GAIN 0x004a91#define RT5665_MONOMIX_IN_GAIN 0x004b92#define RT5665_OUT_L_GAIN 0x004d93#define RT5665_OUT_L_MIXER 0x004e94#define RT5665_OUT_R_GAIN 0x004f95#define RT5665_OUT_R_MIXER 0x005096#define RT5665_LOUT_MIXER 0x005297/* Power */98#define RT5665_PWR_DIG_1 0x006199#define RT5665_PWR_DIG_2 0x0062100#define RT5665_PWR_ANLG_1 0x0063101#define RT5665_PWR_ANLG_2 0x0064102#define RT5665_PWR_ANLG_3 0x0065103#define RT5665_PWR_MIXER 0x0066104#define RT5665_PWR_VOL 0x0067105/* Clock Detect */106#define RT5665_CLK_DET 0x006b107/* Filter */108#define RT5665_HPF_CTRL1 0x006d109/* DMIC */110#define RT5665_DMIC_CTRL_1 0x006e111#define RT5665_DMIC_CTRL_2 0x006f112/* Format - ADC/DAC */113#define RT5665_I2S1_SDP 0x0070114#define RT5665_I2S2_SDP 0x0071115#define RT5665_I2S3_SDP 0x0072116#define RT5665_ADDA_CLK_1 0x0073117#define RT5665_ADDA_CLK_2 0x0074118#define RT5665_I2S1_F_DIV_CTRL_1 0x0075119#define RT5665_I2S1_F_DIV_CTRL_2 0x0076120/* Format - TDM Control */121#define RT5665_TDM_CTRL_1 0x0078122#define RT5665_TDM_CTRL_2 0x0079123#define RT5665_TDM_CTRL_3 0x007a124#define RT5665_TDM_CTRL_4 0x007b125#define RT5665_TDM_CTRL_5 0x007c126#define RT5665_TDM_CTRL_6 0x007d127#define RT5665_TDM_CTRL_7 0x007e128#define RT5665_TDM_CTRL_8 0x007f129/* Function - Analog */130#define RT5665_GLB_CLK 0x0080131#define RT5665_PLL_CTRL_1 0x0081132#define RT5665_PLL_CTRL_2 0x0082133#define RT5665_ASRC_1 0x0083134#define RT5665_ASRC_2 0x0084135#define RT5665_ASRC_3 0x0085136#define RT5665_ASRC_4 0x0086137#define RT5665_ASRC_5 0x0087138#define RT5665_ASRC_6 0x0088139#define RT5665_ASRC_7 0x0089140#define RT5665_ASRC_8 0x008a141#define RT5665_ASRC_9 0x008b142#define RT5665_ASRC_10 0x008c143#define RT5665_DEPOP_1 0x008e144#define RT5665_DEPOP_2 0x008f145#define RT5665_HP_CHARGE_PUMP_1 0x0091146#define RT5665_HP_CHARGE_PUMP_2 0x0092147#define RT5665_MICBIAS_1 0x0093148#define RT5665_MICBIAS_2 0x0094149#define RT5665_ASRC_12 0x0098150#define RT5665_ASRC_13 0x0099151#define RT5665_ASRC_14 0x009a152#define RT5665_RC_CLK_CTRL 0x009f153#define RT5665_I2S_M_CLK_CTRL_1 0x00a0154#define RT5665_I2S2_F_DIV_CTRL_1 0x00a1155#define RT5665_I2S2_F_DIV_CTRL_2 0x00a2156#define RT5665_I2S3_F_DIV_CTRL_1 0x00a3157#define RT5665_I2S3_F_DIV_CTRL_2 0x00a4158/* Function - Digital */159#define RT5665_EQ_CTRL_1 0x00ae160#define RT5665_EQ_CTRL_2 0x00af161#define RT5665_IRQ_CTRL_1 0x00b6162#define RT5665_IRQ_CTRL_2 0x00b7163#define RT5665_IRQ_CTRL_3 0x00b8164#define RT5665_IRQ_CTRL_4 0x00b9165#define RT5665_IRQ_CTRL_5 0x00ba166#define RT5665_IRQ_CTRL_6 0x00bb167#define RT5665_INT_ST_1 0x00be168#define RT5665_GPIO_CTRL_1 0x00c0169#define RT5665_GPIO_CTRL_2 0x00c1170#define RT5665_GPIO_CTRL_3 0x00c2171#define RT5665_GPIO_CTRL_4 0x00c3172#define RT5665_GPIO_STA 0x00c4173#define RT5665_HP_AMP_DET_CTRL_1 0x00d0174#define RT5665_HP_AMP_DET_CTRL_2 0x00d1175#define RT5665_MID_HP_AMP_DET 0x00d3176#define RT5665_LOW_HP_AMP_DET 0x00d4177#define RT5665_SV_ZCD_1 0x00d9178#define RT5665_SV_ZCD_2 0x00da179#define RT5665_IL_CMD_1 0x00db180#define RT5665_IL_CMD_2 0x00dc181#define RT5665_IL_CMD_3 0x00dd182#define RT5665_IL_CMD_4 0x00de183#define RT5665_4BTN_IL_CMD_1 0x00df184#define RT5665_4BTN_IL_CMD_2 0x00e0185#define RT5665_4BTN_IL_CMD_3 0x00e1186#define RT5665_PSV_IL_CMD_1 0x00e2187 188#define RT5665_ADC_STO1_HP_CTRL_1 0x00ea189#define RT5665_ADC_STO1_HP_CTRL_2 0x00eb190#define RT5665_ADC_MONO_HP_CTRL_1 0x00ec191#define RT5665_ADC_MONO_HP_CTRL_2 0x00ed192#define RT5665_ADC_STO2_HP_CTRL_1 0x00ee193#define RT5665_ADC_STO2_HP_CTRL_2 0x00ef194#define RT5665_AJD1_CTRL 0x00f0195#define RT5665_JD1_THD 0x00f1196#define RT5665_JD2_THD 0x00f2197#define RT5665_JD_CTRL_1 0x00f6198#define RT5665_JD_CTRL_2 0x00f7199#define RT5665_JD_CTRL_3 0x00f8200/* General Control */201#define RT5665_DIG_MISC 0x00fa202#define RT5665_DUMMY_2 0x00fb203#define RT5665_DUMMY_3 0x00fc204 205#define RT5665_DAC_ADC_DIG_VOL1 0x0100206#define RT5665_DAC_ADC_DIG_VOL2 0x0101207#define RT5665_BIAS_CUR_CTRL_1 0x010a208#define RT5665_BIAS_CUR_CTRL_2 0x010b209#define RT5665_BIAS_CUR_CTRL_3 0x010c210#define RT5665_BIAS_CUR_CTRL_4 0x010d211#define RT5665_BIAS_CUR_CTRL_5 0x010e212#define RT5665_BIAS_CUR_CTRL_6 0x010f213#define RT5665_BIAS_CUR_CTRL_7 0x0110214#define RT5665_BIAS_CUR_CTRL_8 0x0111215#define RT5665_BIAS_CUR_CTRL_9 0x0112216#define RT5665_BIAS_CUR_CTRL_10 0x0113217#define RT5665_VREF_REC_OP_FB_CAP_CTRL 0x0117218#define RT5665_CHARGE_PUMP_1 0x0125219#define RT5665_DIG_IN_CTRL_1 0x0132220#define RT5665_DIG_IN_CTRL_2 0x0133221#define RT5665_PAD_DRIVING_CTRL 0x0137222#define RT5665_SOFT_RAMP_DEPOP 0x0138223#define RT5665_PLL 0x0139224#define RT5665_CHOP_DAC 0x013a225#define RT5665_CHOP_ADC 0x013b226#define RT5665_CALIB_ADC_CTRL 0x013c227#define RT5665_VOL_TEST 0x013f228#define RT5665_TEST_MODE_CTRL_1 0x0145229#define RT5665_TEST_MODE_CTRL_2 0x0146230#define RT5665_TEST_MODE_CTRL_3 0x0147231#define RT5665_TEST_MODE_CTRL_4 0x0148232#define RT5665_BASSBACK_CTRL 0x0150233#define RT5665_STO_NG2_CTRL_1 0x0160234#define RT5665_STO_NG2_CTRL_2 0x0161235#define RT5665_STO_NG2_CTRL_3 0x0162236#define RT5665_STO_NG2_CTRL_4 0x0163237#define RT5665_STO_NG2_CTRL_5 0x0164238#define RT5665_STO_NG2_CTRL_6 0x0165239#define RT5665_STO_NG2_CTRL_7 0x0166240#define RT5665_STO_NG2_CTRL_8 0x0167241#define RT5665_MONO_NG2_CTRL_1 0x0170242#define RT5665_MONO_NG2_CTRL_2 0x0171243#define RT5665_MONO_NG2_CTRL_3 0x0172244#define RT5665_MONO_NG2_CTRL_4 0x0173245#define RT5665_MONO_NG2_CTRL_5 0x0174246#define RT5665_MONO_NG2_CTRL_6 0x0175247#define RT5665_STO1_DAC_SIL_DET 0x0190248#define RT5665_MONOL_DAC_SIL_DET 0x0191249#define RT5665_MONOR_DAC_SIL_DET 0x0192250#define RT5665_STO2_DAC_SIL_DET 0x0193251#define RT5665_SIL_PSV_CTRL1 0x0194252#define RT5665_SIL_PSV_CTRL2 0x0195253#define RT5665_SIL_PSV_CTRL3 0x0196254#define RT5665_SIL_PSV_CTRL4 0x0197255#define RT5665_SIL_PSV_CTRL5 0x0198256#define RT5665_SIL_PSV_CTRL6 0x0199257#define RT5665_MONO_AMP_CALIB_CTRL_1 0x01a0258#define RT5665_MONO_AMP_CALIB_CTRL_2 0x01a1259#define RT5665_MONO_AMP_CALIB_CTRL_3 0x01a2260#define RT5665_MONO_AMP_CALIB_CTRL_4 0x01a3261#define RT5665_MONO_AMP_CALIB_CTRL_5 0x01a4262#define RT5665_MONO_AMP_CALIB_CTRL_6 0x01a5263#define RT5665_MONO_AMP_CALIB_CTRL_7 0x01a6264#define RT5665_MONO_AMP_CALIB_STA1 0x01a7265#define RT5665_MONO_AMP_CALIB_STA2 0x01a8266#define RT5665_MONO_AMP_CALIB_STA3 0x01a9267#define RT5665_MONO_AMP_CALIB_STA4 0x01aa268#define RT5665_MONO_AMP_CALIB_STA6 0x01ab269#define RT5665_HP_IMP_SENS_CTRL_01 0x01b5270#define RT5665_HP_IMP_SENS_CTRL_02 0x01b6271#define RT5665_HP_IMP_SENS_CTRL_03 0x01b7272#define RT5665_HP_IMP_SENS_CTRL_04 0x01b8273#define RT5665_HP_IMP_SENS_CTRL_05 0x01b9274#define RT5665_HP_IMP_SENS_CTRL_06 0x01ba275#define RT5665_HP_IMP_SENS_CTRL_07 0x01bb276#define RT5665_HP_IMP_SENS_CTRL_08 0x01bc277#define RT5665_HP_IMP_SENS_CTRL_09 0x01bd278#define RT5665_HP_IMP_SENS_CTRL_10 0x01be279#define RT5665_HP_IMP_SENS_CTRL_11 0x01bf280#define RT5665_HP_IMP_SENS_CTRL_12 0x01c0281#define RT5665_HP_IMP_SENS_CTRL_13 0x01c1282#define RT5665_HP_IMP_SENS_CTRL_14 0x01c2283#define RT5665_HP_IMP_SENS_CTRL_15 0x01c3284#define RT5665_HP_IMP_SENS_CTRL_16 0x01c4285#define RT5665_HP_IMP_SENS_CTRL_17 0x01c5286#define RT5665_HP_IMP_SENS_CTRL_18 0x01c6287#define RT5665_HP_IMP_SENS_CTRL_19 0x01c7288#define RT5665_HP_IMP_SENS_CTRL_20 0x01c8289#define RT5665_HP_IMP_SENS_CTRL_21 0x01c9290#define RT5665_HP_IMP_SENS_CTRL_22 0x01ca291#define RT5665_HP_IMP_SENS_CTRL_23 0x01cb292#define RT5665_HP_IMP_SENS_CTRL_24 0x01cc293#define RT5665_HP_IMP_SENS_CTRL_25 0x01cd294#define RT5665_HP_IMP_SENS_CTRL_26 0x01ce295#define RT5665_HP_IMP_SENS_CTRL_27 0x01cf296#define RT5665_HP_IMP_SENS_CTRL_28 0x01d0297#define RT5665_HP_IMP_SENS_CTRL_29 0x01d1298#define RT5665_HP_IMP_SENS_CTRL_30 0x01d2299#define RT5665_HP_IMP_SENS_CTRL_31 0x01d3300#define RT5665_HP_IMP_SENS_CTRL_32 0x01d4301#define RT5665_HP_IMP_SENS_CTRL_33 0x01d5302#define RT5665_HP_IMP_SENS_CTRL_34 0x01d6303#define RT5665_HP_LOGIC_CTRL_1 0x01da304#define RT5665_HP_LOGIC_CTRL_2 0x01db305#define RT5665_HP_LOGIC_CTRL_3 0x01dc306#define RT5665_HP_CALIB_CTRL_1 0x01de307#define RT5665_HP_CALIB_CTRL_2 0x01df308#define RT5665_HP_CALIB_CTRL_3 0x01e0309#define RT5665_HP_CALIB_CTRL_4 0x01e1310#define RT5665_HP_CALIB_CTRL_5 0x01e2311#define RT5665_HP_CALIB_CTRL_6 0x01e3312#define RT5665_HP_CALIB_CTRL_7 0x01e4313#define RT5665_HP_CALIB_CTRL_9 0x01e6314#define RT5665_HP_CALIB_CTRL_10 0x01e7315#define RT5665_HP_CALIB_CTRL_11 0x01e8316#define RT5665_HP_CALIB_STA_1 0x01ea317#define RT5665_HP_CALIB_STA_2 0x01eb318#define RT5665_HP_CALIB_STA_3 0x01ec319#define RT5665_HP_CALIB_STA_4 0x01ed320#define RT5665_HP_CALIB_STA_5 0x01ee321#define RT5665_HP_CALIB_STA_6 0x01ef322#define RT5665_HP_CALIB_STA_7 0x01f0323#define RT5665_HP_CALIB_STA_8 0x01f1324#define RT5665_HP_CALIB_STA_9 0x01f2325#define RT5665_HP_CALIB_STA_10 0x01f3326#define RT5665_HP_CALIB_STA_11 0x01f4327#define RT5665_PGM_TAB_CTRL1 0x0200328#define RT5665_PGM_TAB_CTRL2 0x0201329#define RT5665_PGM_TAB_CTRL3 0x0202330#define RT5665_PGM_TAB_CTRL4 0x0203331#define RT5665_PGM_TAB_CTRL5 0x0204332#define RT5665_PGM_TAB_CTRL6 0x0205333#define RT5665_PGM_TAB_CTRL7 0x0206334#define RT5665_PGM_TAB_CTRL8 0x0207335#define RT5665_PGM_TAB_CTRL9 0x0208336#define RT5665_SAR_IL_CMD_1 0x0210337#define RT5665_SAR_IL_CMD_2 0x0211338#define RT5665_SAR_IL_CMD_3 0x0212339#define RT5665_SAR_IL_CMD_4 0x0213340#define RT5665_SAR_IL_CMD_5 0x0214341#define RT5665_SAR_IL_CMD_6 0x0215342#define RT5665_SAR_IL_CMD_7 0x0216343#define RT5665_SAR_IL_CMD_8 0x0217344#define RT5665_SAR_IL_CMD_9 0x0218345#define RT5665_SAR_IL_CMD_10 0x0219346#define RT5665_SAR_IL_CMD_11 0x021a347#define RT5665_SAR_IL_CMD_12 0x021b348#define RT5665_DRC1_CTRL_0 0x02ff349#define RT5665_DRC1_CTRL_1 0x0300350#define RT5665_DRC1_CTRL_2 0x0301351#define RT5665_DRC1_CTRL_3 0x0302352#define RT5665_DRC1_CTRL_4 0x0303353#define RT5665_DRC1_CTRL_5 0x0304354#define RT5665_DRC1_CTRL_6 0x0305355#define RT5665_DRC1_HARD_LMT_CTRL_1 0x0306356#define RT5665_DRC1_HARD_LMT_CTRL_2 0x0307357#define RT5665_DRC1_PRIV_1 0x0310358#define RT5665_DRC1_PRIV_2 0x0311359#define RT5665_DRC1_PRIV_3 0x0312360#define RT5665_DRC1_PRIV_4 0x0313361#define RT5665_DRC1_PRIV_5 0x0314362#define RT5665_DRC1_PRIV_6 0x0315363#define RT5665_DRC1_PRIV_7 0x0316364#define RT5665_DRC1_PRIV_8 0x0317365#define RT5665_ALC_PGA_CTRL_1 0x0330366#define RT5665_ALC_PGA_CTRL_2 0x0331367#define RT5665_ALC_PGA_CTRL_3 0x0332368#define RT5665_ALC_PGA_CTRL_4 0x0333369#define RT5665_ALC_PGA_CTRL_5 0x0334370#define RT5665_ALC_PGA_CTRL_6 0x0335371#define RT5665_ALC_PGA_CTRL_7 0x0336372#define RT5665_ALC_PGA_CTRL_8 0x0337373#define RT5665_ALC_PGA_STA_1 0x0338374#define RT5665_ALC_PGA_STA_2 0x0339375#define RT5665_ALC_PGA_STA_3 0x033a376#define RT5665_EQ_AUTO_RCV_CTRL1 0x03c0377#define RT5665_EQ_AUTO_RCV_CTRL2 0x03c1378#define RT5665_EQ_AUTO_RCV_CTRL3 0x03c2379#define RT5665_EQ_AUTO_RCV_CTRL4 0x03c3380#define RT5665_EQ_AUTO_RCV_CTRL5 0x03c4381#define RT5665_EQ_AUTO_RCV_CTRL6 0x03c5382#define RT5665_EQ_AUTO_RCV_CTRL7 0x03c6383#define RT5665_EQ_AUTO_RCV_CTRL8 0x03c7384#define RT5665_EQ_AUTO_RCV_CTRL9 0x03c8385#define RT5665_EQ_AUTO_RCV_CTRL10 0x03c9386#define RT5665_EQ_AUTO_RCV_CTRL11 0x03ca387#define RT5665_EQ_AUTO_RCV_CTRL12 0x03cb388#define RT5665_EQ_AUTO_RCV_CTRL13 0x03cc389#define RT5665_ADC_L_EQ_LPF1_A1 0x03d0390#define RT5665_R_EQ_LPF1_A1 0x03d1391#define RT5665_L_EQ_LPF1_H0 0x03d2392#define RT5665_R_EQ_LPF1_H0 0x03d3393#define RT5665_L_EQ_BPF1_A1 0x03d4394#define RT5665_R_EQ_BPF1_A1 0x03d5395#define RT5665_L_EQ_BPF1_A2 0x03d6396#define RT5665_R_EQ_BPF1_A2 0x03d7397#define RT5665_L_EQ_BPF1_H0 0x03d8398#define RT5665_R_EQ_BPF1_H0 0x03d9399#define RT5665_L_EQ_BPF2_A1 0x03da400#define RT5665_R_EQ_BPF2_A1 0x03db401#define RT5665_L_EQ_BPF2_A2 0x03dc402#define RT5665_R_EQ_BPF2_A2 0x03dd403#define RT5665_L_EQ_BPF2_H0 0x03de404#define RT5665_R_EQ_BPF2_H0 0x03df405#define RT5665_L_EQ_BPF3_A1 0x03e0406#define RT5665_R_EQ_BPF3_A1 0x03e1407#define RT5665_L_EQ_BPF3_A2 0x03e2408#define RT5665_R_EQ_BPF3_A2 0x03e3409#define RT5665_L_EQ_BPF3_H0 0x03e4410#define RT5665_R_EQ_BPF3_H0 0x03e5411#define RT5665_L_EQ_BPF4_A1 0x03e6412#define RT5665_R_EQ_BPF4_A1 0x03e7413#define RT5665_L_EQ_BPF4_A2 0x03e8414#define RT5665_R_EQ_BPF4_A2 0x03e9415#define RT5665_L_EQ_BPF4_H0 0x03ea416#define RT5665_R_EQ_BPF4_H0 0x03eb417#define RT5665_L_EQ_HPF1_A1 0x03ec418#define RT5665_R_EQ_HPF1_A1 0x03ed419#define RT5665_L_EQ_HPF1_H0 0x03ee420#define RT5665_R_EQ_HPF1_H0 0x03ef421#define RT5665_L_EQ_PRE_VOL 0x03f0422#define RT5665_R_EQ_PRE_VOL 0x03f1423#define RT5665_L_EQ_POST_VOL 0x03f2424#define RT5665_R_EQ_POST_VOL 0x03f3425#define RT5665_SCAN_MODE_CTRL 0x07f0426#define RT5665_I2C_MODE 0x07fa427 428 429 430/* global definition */431#define RT5665_L_MUTE (0x1 << 15)432#define RT5665_L_MUTE_SFT 15433#define RT5665_VOL_L_MUTE (0x1 << 14)434#define RT5665_VOL_L_SFT 14435#define RT5665_R_MUTE (0x1 << 7)436#define RT5665_R_MUTE_SFT 7437#define RT5665_VOL_R_MUTE (0x1 << 6)438#define RT5665_VOL_R_SFT 6439#define RT5665_L_VOL_MASK (0x3f << 8)440#define RT5665_L_VOL_SFT 8441#define RT5665_R_VOL_MASK (0x3f)442#define RT5665_R_VOL_SFT 0443 444/*Headphone Amp L/R Analog Gain and Digital NG2 Gain Control (0x0005 0x0006)*/445#define RT5665_G_HP (0xf << 8)446#define RT5665_G_HP_SFT 8447#define RT5665_G_STO_DA_DMIX (0xf)448#define RT5665_G_STO_DA_SFT 0449 450/* CBJ Control (0x000b) */451#define RT5665_BST_CBJ_MASK (0xf << 8)452#define RT5665_BST_CBJ_SFT 8453 454/* IN1/IN2 Control (0x000c) */455#define RT5665_IN1_DF_MASK (0x1 << 15)456#define RT5665_IN1_DF 15457#define RT5665_BST1_MASK (0x7f << 8)458#define RT5665_BST1_SFT 8459#define RT5665_IN2_DF_MASK (0x1 << 7)460#define RT5665_IN2_DF 7461#define RT5665_BST2_MASK (0x7f)462#define RT5665_BST2_SFT 0463 464/* IN3/IN4 Control (0x000d) */465#define RT5665_IN3_DF_MASK (0x1 << 15)466#define RT5665_IN3_DF 15467#define RT5665_BST3_MASK (0x7f << 8)468#define RT5665_BST3_SFT 8469#define RT5665_IN4_DF_MASK (0x1 << 7)470#define RT5665_IN4_DF 7471#define RT5665_BST4_MASK (0x7f)472#define RT5665_BST4_SFT 0473 474/* INL and INR Volume Control (0x000f) */475#define RT5665_INL_VOL_MASK (0x1f << 8)476#define RT5665_INL_VOL_SFT 8477#define RT5665_INR_VOL_MASK (0x1f)478#define RT5665_INR_VOL_SFT 0479 480/* Embeeded Jack and Type Detection Control 1 (0x0010) */481#define RT5665_EMB_JD_EN (0x1 << 15)482#define RT5665_EMB_JD_EN_SFT 15483#define RT5665_JD_MODE (0x1 << 13)484#define RT5665_JD_MODE_SFT 13485#define RT5665_POLA_EXT_JD_MASK (0x1 << 11)486#define RT5665_POLA_EXT_JD_LOW (0x1 << 11)487#define RT5665_POLA_EXT_JD_HIGH (0x0 << 11)488#define RT5665_EXT_JD_DIG (0x1 << 9)489#define RT5665_POL_FAST_OFF_MASK (0x1 << 8)490#define RT5665_POL_FAST_OFF_HIGH (0x1 << 8)491#define RT5665_POL_FAST_OFF_LOW (0x0 << 8)492#define RT5665_VREF_POW_MASK (0x1 << 6)493#define RT5665_VREF_POW_FSM (0x0 << 6)494#define RT5665_VREF_POW_REG (0x1 << 6)495#define RT5665_MB1_PATH_MASK (0x1 << 5)496#define RT5665_CTRL_MB1_REG (0x1 << 5)497#define RT5665_CTRL_MB1_FSM (0x0 << 5)498#define RT5665_MB2_PATH_MASK (0x1 << 4)499#define RT5665_CTRL_MB2_REG (0x1 << 4)500#define RT5665_CTRL_MB2_FSM (0x0 << 4)501#define RT5665_TRIG_JD_MASK (0x1 << 3)502#define RT5665_TRIG_JD_HIGH (0x1 << 3)503#define RT5665_TRIG_JD_LOW (0x0 << 3)504 505/* Embeeded Jack and Type Detection Control 2 (0x0011) */506#define RT5665_EXT_JD_SRC (0x7 << 4)507#define RT5665_EXT_JD_SRC_SFT 4508#define RT5665_EXT_JD_SRC_GPIO_JD1 (0x0 << 4)509#define RT5665_EXT_JD_SRC_GPIO_JD2 (0x1 << 4)510#define RT5665_EXT_JD_SRC_JD1_1 (0x2 << 4)511#define RT5665_EXT_JD_SRC_JD1_2 (0x3 << 4)512#define RT5665_EXT_JD_SRC_JD2 (0x4 << 4)513#define RT5665_EXT_JD_SRC_JD3 (0x5 << 4)514#define RT5665_EXT_JD_SRC_MANUAL (0x6 << 4)515 516/* Combo Jack and Type Detection Control 4 (0x0013) */517#define RT5665_SEL_SHT_MID_TON_MASK (0x3 << 12)518#define RT5665_SEL_SHT_MID_TON_2 (0x0 << 12)519#define RT5665_SEL_SHT_MID_TON_3 (0x1 << 12)520#define RT5665_CBJ_JD_TEST_MASK (0x1 << 6)521#define RT5665_CBJ_JD_TEST_NORM (0x0 << 6)522#define RT5665_CBJ_JD_TEST_MODE (0x1 << 6)523 524/* Slience Detection Control (0x0015) */525#define RT5665_SIL_DET_MASK (0x1 << 15)526#define RT5665_SIL_DET_DIS (0x0 << 15)527#define RT5665_SIL_DET_EN (0x1 << 15)528 529/* DAC2 Control (0x0017) */530#define RT5665_M_DAC2_L_VOL (0x1 << 13)531#define RT5665_M_DAC2_L_VOL_SFT 13532#define RT5665_M_DAC2_R_VOL (0x1 << 12)533#define RT5665_M_DAC2_R_VOL_SFT 12534#define RT5665_DAC_L2_SEL_MASK (0x7 << 4)535#define RT5665_DAC_L2_SEL_SFT 4536#define RT5665_DAC_R2_SEL_MASK (0x7 << 0)537#define RT5665_DAC_R2_SEL_SFT 0538 539/* Sidetone Control (0x0018) */540#define RT5665_ST_SEL_MASK (0x7 << 9)541#define RT5665_ST_SEL_SFT 9542#define RT5665_ST_EN (0x1 << 6)543#define RT5665_ST_EN_SFT 6544 545/* DAC1 Digital Volume (0x0019) */546#define RT5665_DAC_L1_VOL_MASK (0xff << 8)547#define RT5665_DAC_L1_VOL_SFT 8548#define RT5665_DAC_R1_VOL_MASK (0xff)549#define RT5665_DAC_R1_VOL_SFT 0550 551/* DAC2 Digital Volume (0x001a) */552#define RT5665_DAC_L2_VOL_MASK (0xff << 8)553#define RT5665_DAC_L2_VOL_SFT 8554#define RT5665_DAC_R2_VOL_MASK (0xff)555#define RT5665_DAC_R2_VOL_SFT 0556 557/* DAC3 Control (0x001b) */558#define RT5665_M_DAC3_L_VOL (0x1 << 13)559#define RT5665_M_DAC3_L_VOL_SFT 13560#define RT5665_M_DAC3_R_VOL (0x1 << 12)561#define RT5665_M_DAC3_R_VOL_SFT 12562#define RT5665_DAC_L3_SEL_MASK (0x7 << 4)563#define RT5665_DAC_L3_SEL_SFT 4564#define RT5665_DAC_R3_SEL_MASK (0x7 << 0)565#define RT5665_DAC_R3_SEL_SFT 0566 567/* ADC Digital Volume Control (0x001c) */568#define RT5665_ADC_L_VOL_MASK (0x7f << 8)569#define RT5665_ADC_L_VOL_SFT 8570#define RT5665_ADC_R_VOL_MASK (0x7f)571#define RT5665_ADC_R_VOL_SFT 0572 573/* Mono ADC Digital Volume Control (0x001d) */574#define RT5665_MONO_ADC_L_VOL_MASK (0x7f << 8)575#define RT5665_MONO_ADC_L_VOL_SFT 8576#define RT5665_MONO_ADC_R_VOL_MASK (0x7f)577#define RT5665_MONO_ADC_R_VOL_SFT 0578 579/* Stereo1 ADC Boost Gain Control (0x001f) */580#define RT5665_STO1_ADC_L_BST_MASK (0x3 << 14)581#define RT5665_STO1_ADC_L_BST_SFT 14582#define RT5665_STO1_ADC_R_BST_MASK (0x3 << 12)583#define RT5665_STO1_ADC_R_BST_SFT 12584 585/* Mono ADC Boost Gain Control (0x0020) */586#define RT5665_MONO_ADC_L_BST_MASK (0x3 << 14)587#define RT5665_MONO_ADC_L_BST_SFT 14588#define RT5665_MONO_ADC_R_BST_MASK (0x3 << 12)589#define RT5665_MONO_ADC_R_BST_SFT 12590 591/* Stereo1 ADC Boost Gain Control (0x001f) */592#define RT5665_STO2_ADC_L_BST_MASK (0x3 << 14)593#define RT5665_STO2_ADC_L_BST_SFT 14594#define RT5665_STO2_ADC_R_BST_MASK (0x3 << 12)595#define RT5665_STO2_ADC_R_BST_SFT 12596 597/* Stereo1 ADC Mixer Control (0x0026) */598#define RT5665_M_STO1_ADC_L1 (0x1 << 15)599#define RT5665_M_STO1_ADC_L1_SFT 15600#define RT5665_M_STO1_ADC_L2 (0x1 << 14)601#define RT5665_M_STO1_ADC_L2_SFT 14602#define RT5665_STO1_ADC1L_SRC_MASK (0x1 << 13)603#define RT5665_STO1_ADC1L_SRC_SFT 13604#define RT5665_STO1_ADC1_SRC_ADC (0x1 << 13)605#define RT5665_STO1_ADC1_SRC_DACMIX (0x0 << 13)606#define RT5665_STO1_ADC2L_SRC_MASK (0x1 << 12)607#define RT5665_STO1_ADC2L_SRC_SFT 12608#define RT5665_STO1_ADCL_SRC_MASK (0x3 << 10)609#define RT5665_STO1_ADCL_SRC_SFT 10610#define RT5665_STO1_DD_L_SRC_MASK (0x1 << 9)611#define RT5665_STO1_DD_L_SRC_SFT 9612#define RT5665_STO1_DMIC_SRC_MASK (0x1 << 8)613#define RT5665_STO1_DMIC_SRC_SFT 8614#define RT5665_STO1_DMIC_SRC_DMIC2 (0x1 << 8)615#define RT5665_STO1_DMIC_SRC_DMIC1 (0x0 << 8)616#define RT5665_M_STO1_ADC_R1 (0x1 << 7)617#define RT5665_M_STO1_ADC_R1_SFT 7618#define RT5665_M_STO1_ADC_R2 (0x1 << 6)619#define RT5665_M_STO1_ADC_R2_SFT 6620#define RT5665_STO1_ADC1R_SRC_MASK (0x1 << 5)621#define RT5665_STO1_ADC1R_SRC_SFT 5622#define RT5665_STO1_ADC2R_SRC_MASK (0x1 << 4)623#define RT5665_STO1_ADC2R_SRC_SFT 4624#define RT5665_STO1_ADCR_SRC_MASK (0x3 << 2)625#define RT5665_STO1_ADCR_SRC_SFT 2626#define RT5665_STO1_DD_R_SRC_MASK (0x3)627#define RT5665_STO1_DD_R_SRC_SFT 0628 629 630/* Mono1 ADC Mixer control (0x0027) */631#define RT5665_M_MONO_ADC_L1 (0x1 << 15)632#define RT5665_M_MONO_ADC_L1_SFT 15633#define RT5665_M_MONO_ADC_L2 (0x1 << 14)634#define RT5665_M_MONO_ADC_L2_SFT 14635#define RT5665_MONO_ADC_L1_SRC_MASK (0x1 << 13)636#define RT5665_MONO_ADC_L1_SRC_SFT 13637#define RT5665_MONO_ADC_L2_SRC_MASK (0x1 << 12)638#define RT5665_MONO_ADC_L2_SRC_SFT 12639#define RT5665_MONO_ADC_L_SRC_MASK (0x3 << 10)640#define RT5665_MONO_ADC_L_SRC_SFT 10641#define RT5665_MONO_DD_L_SRC_MASK (0x1 << 9)642#define RT5665_MONO_DD_L_SRC_SFT 9643#define RT5665_MONO_DMIC_L_SRC_MASK (0x1 << 8)644#define RT5665_MONO_DMIC_L_SRC_SFT 8645#define RT5665_M_MONO_ADC_R1 (0x1 << 7)646#define RT5665_M_MONO_ADC_R1_SFT 7647#define RT5665_M_MONO_ADC_R2 (0x1 << 6)648#define RT5665_M_MONO_ADC_R2_SFT 6649#define RT5665_MONO_ADC_R1_SRC_MASK (0x1 << 5)650#define RT5665_MONO_ADC_R1_SRC_SFT 5651#define RT5665_MONO_ADC_R2_SRC_MASK (0x1 << 4)652#define RT5665_MONO_ADC_R2_SRC_SFT 4653#define RT5665_MONO_ADC_R_SRC_MASK (0x3 << 2)654#define RT5665_MONO_ADC_R_SRC_SFT 2655#define RT5665_MONO_DD_R_SRC_MASK (0x1 << 1)656#define RT5665_MONO_DD_R_SRC_SFT 1657#define RT5665_MONO_DMIC_R_SRC_MASK 0x1658#define RT5665_MONO_DMIC_R_SRC_SFT 0659 660/* Stereo2 ADC Mixer Control (0x0028) */661#define RT5665_M_STO2_ADC_L1 (0x1 << 15)662#define RT5665_M_STO2_ADC_L1_UN (0x0 << 15)663#define RT5665_M_STO2_ADC_L1_SFT 15664#define RT5665_M_STO2_ADC_L2 (0x1 << 14)665#define RT5665_M_STO2_ADC_L2_SFT 14666#define RT5665_STO2_ADC1L_SRC_MASK (0x1 << 13)667#define RT5665_STO2_ADC1L_SRC_SFT 13668#define RT5665_STO2_ADC1_SRC_ADC (0x1 << 13)669#define RT5665_STO2_ADC1_SRC_DACMIX (0x0 << 13)670#define RT5665_STO2_ADC2L_SRC_MASK (0x1 << 12)671#define RT5665_STO2_ADC2L_SRC_SFT 12672#define RT5665_STO2_ADCL_SRC_MASK (0x3 << 10)673#define RT5665_STO2_ADCL_SRC_SFT 10674#define RT5665_STO2_DD_L_SRC_MASK (0x1 << 9)675#define RT5665_STO2_DD_L_SRC_SFT 9676#define RT5665_STO2_DMIC_SRC_MASK (0x1 << 8)677#define RT5665_STO2_DMIC_SRC_SFT 8678#define RT5665_STO2_DMIC_SRC_DMIC2 (0x1 << 8)679#define RT5665_STO2_DMIC_SRC_DMIC1 (0x0 << 8)680#define RT5665_M_STO2_ADC_R1 (0x1 << 7)681#define RT5665_M_STO2_ADC_R1_UN (0x0 << 7)682#define RT5665_M_STO2_ADC_R1_SFT 7683#define RT5665_M_STO2_ADC_R2 (0x1 << 6)684#define RT5665_M_STO2_ADC_R2_SFT 6685#define RT5665_STO2_ADC1R_SRC_MASK (0x1 << 5)686#define RT5665_STO2_ADC1R_SRC_SFT 5687#define RT5665_STO2_ADC2R_SRC_MASK (0x1 << 4)688#define RT5665_STO2_ADC2R_SRC_SFT 4689#define RT5665_STO2_ADCR_SRC_MASK (0x3 << 2)690#define RT5665_STO2_ADCR_SRC_SFT 2691#define RT5665_STO2_DD_R_SRC_MASK (0x1 << 1)692#define RT5665_STO2_DD_R_SRC_SFT 1693 694/* ADC Mixer to DAC Mixer Control (0x0029) */695#define RT5665_M_ADCMIX_L (0x1 << 15)696#define RT5665_M_ADCMIX_L_SFT 15697#define RT5665_M_DAC1_L (0x1 << 14)698#define RT5665_M_DAC1_L_SFT 14699#define RT5665_DAC1_R_SEL_MASK (0x3 << 10)700#define RT5665_DAC1_R_SEL_SFT 10701#define RT5665_DAC1_L_SEL_MASK (0x3 << 8)702#define RT5665_DAC1_L_SEL_SFT 8703#define RT5665_M_ADCMIX_R (0x1 << 7)704#define RT5665_M_ADCMIX_R_SFT 7705#define RT5665_M_DAC1_R (0x1 << 6)706#define RT5665_M_DAC1_R_SFT 6707 708/* Stereo1 DAC Mixer Control (0x002a) */709#define RT5665_M_DAC_L1_STO_L (0x1 << 15)710#define RT5665_M_DAC_L1_STO_L_SFT 15711#define RT5665_G_DAC_L1_STO_L_MASK (0x1 << 14)712#define RT5665_G_DAC_L1_STO_L_SFT 14713#define RT5665_M_DAC_R1_STO_L (0x1 << 13)714#define RT5665_M_DAC_R1_STO_L_SFT 13715#define RT5665_G_DAC_R1_STO_L_MASK (0x1 << 12)716#define RT5665_G_DAC_R1_STO_L_SFT 12717#define RT5665_M_DAC_L2_STO_L (0x1 << 11)718#define RT5665_M_DAC_L2_STO_L_SFT 11719#define RT5665_G_DAC_L2_STO_L_MASK (0x1 << 10)720#define RT5665_G_DAC_L2_STO_L_SFT 10721#define RT5665_M_DAC_R2_STO_L (0x1 << 9)722#define RT5665_M_DAC_R2_STO_L_SFT 9723#define RT5665_G_DAC_R2_STO_L_MASK (0x1 << 8)724#define RT5665_G_DAC_R2_STO_L_SFT 8725#define RT5665_M_DAC_L1_STO_R (0x1 << 7)726#define RT5665_M_DAC_L1_STO_R_SFT 7727#define RT5665_G_DAC_L1_STO_R_MASK (0x1 << 6)728#define RT5665_G_DAC_L1_STO_R_SFT 6729#define RT5665_M_DAC_R1_STO_R (0x1 << 5)730#define RT5665_M_DAC_R1_STO_R_SFT 5731#define RT5665_G_DAC_R1_STO_R_MASK (0x1 << 4)732#define RT5665_G_DAC_R1_STO_R_SFT 4733#define RT5665_M_DAC_L2_STO_R (0x1 << 3)734#define RT5665_M_DAC_L2_STO_R_SFT 3735#define RT5665_G_DAC_L2_STO_R_MASK (0x1 << 2)736#define RT5665_G_DAC_L2_STO_R_SFT 2737#define RT5665_M_DAC_R2_STO_R (0x1 << 1)738#define RT5665_M_DAC_R2_STO_R_SFT 1739#define RT5665_G_DAC_R2_STO_R_MASK (0x1)740#define RT5665_G_DAC_R2_STO_R_SFT 0741 742/* Mono DAC Mixer Control (0x002b) */743#define RT5665_M_DAC_L1_MONO_L (0x1 << 15)744#define RT5665_M_DAC_L1_MONO_L_SFT 15745#define RT5665_G_DAC_L1_MONO_L_MASK (0x1 << 14)746#define RT5665_G_DAC_L1_MONO_L_SFT 14747#define RT5665_M_DAC_R1_MONO_L (0x1 << 13)748#define RT5665_M_DAC_R1_MONO_L_SFT 13749#define RT5665_G_DAC_R1_MONO_L_MASK (0x1 << 12)750#define RT5665_G_DAC_R1_MONO_L_SFT 12751#define RT5665_M_DAC_L2_MONO_L (0x1 << 11)752#define RT5665_M_DAC_L2_MONO_L_SFT 11753#define RT5665_G_DAC_L2_MONO_L_MASK (0x1 << 10)754#define RT5665_G_DAC_L2_MONO_L_SFT 10755#define RT5665_M_DAC_R2_MONO_L (0x1 << 9)756#define RT5665_M_DAC_R2_MONO_L_SFT 9757#define RT5665_G_DAC_R2_MONO_L_MASK (0x1 << 8)758#define RT5665_G_DAC_R2_MONO_L_SFT 8759#define RT5665_M_DAC_L1_MONO_R (0x1 << 7)760#define RT5665_M_DAC_L1_MONO_R_SFT 7761#define RT5665_G_DAC_L1_MONO_R_MASK (0x1 << 6)762#define RT5665_G_DAC_L1_MONO_R_SFT 6763#define RT5665_M_DAC_R1_MONO_R (0x1 << 5)764#define RT5665_M_DAC_R1_MONO_R_SFT 5765#define RT5665_G_DAC_R1_MONO_R_MASK (0x1 << 4)766#define RT5665_G_DAC_R1_MONO_R_SFT 4767#define RT5665_M_DAC_L2_MONO_R (0x1 << 3)768#define RT5665_M_DAC_L2_MONO_R_SFT 3769#define RT5665_G_DAC_L2_MONO_R_MASK (0x1 << 2)770#define RT5665_G_DAC_L2_MONO_R_SFT 2771#define RT5665_M_DAC_R2_MONO_R (0x1 << 1)772#define RT5665_M_DAC_R2_MONO_R_SFT 1773#define RT5665_G_DAC_R2_MONO_R_MASK (0x1)774#define RT5665_G_DAC_R2_MONO_R_SFT 0775 776/* Stereo2 DAC Mixer Control (0x002c) */777#define RT5665_M_DAC_L1_STO2_L (0x1 << 15)778#define RT5665_M_DAC_L1_STO2_L_SFT 15779#define RT5665_G_DAC_L1_STO2_L_MASK (0x1 << 14)780#define RT5665_G_DAC_L1_STO2_L_SFT 14781#define RT5665_M_DAC_L2_STO2_L (0x1 << 13)782#define RT5665_M_DAC_L2_STO2_L_SFT 13783#define RT5665_G_DAC_L2_STO2_L_MASK (0x1 << 12)784#define RT5665_G_DAC_L2_STO2_L_SFT 12785#define RT5665_M_DAC_L3_STO2_L (0x1 << 11)786#define RT5665_M_DAC_L3_STO2_L_SFT 11787#define RT5665_G_DAC_L3_STO2_L_MASK (0x1 << 10)788#define RT5665_G_DAC_L3_STO2_L_SFT 10789#define RT5665_M_ST_DAC_L1 (0x1 << 9)790#define RT5665_M_ST_DAC_L1_SFT 9791#define RT5665_M_ST_DAC_R1 (0x1 << 8)792#define RT5665_M_ST_DAC_R1_SFT 8793#define RT5665_M_DAC_R1_STO2_R (0x1 << 7)794#define RT5665_M_DAC_R1_STO2_R_SFT 7795#define RT5665_G_DAC_R1_STO2_R_MASK (0x1 << 6)796#define RT5665_G_DAC_R1_STO2_R_SFT 6797#define RT5665_M_DAC_R2_STO2_R (0x1 << 5)798#define RT5665_M_DAC_R2_STO2_R_SFT 5799#define RT5665_G_DAC_R2_STO2_R_MASK (0x1 << 4)800#define RT5665_G_DAC_R2_STO2_R_SFT 4801#define RT5665_M_DAC_R3_STO2_R (0x1 << 3)802#define RT5665_M_DAC_R3_STO2_R_SFT 3803#define RT5665_G_DAC_R3_STO2_R_MASK (0x1 << 2)804#define RT5665_G_DAC_R3_STO2_R_SFT 2805 806/* Analog DAC1 Input Source Control (0x002d) */807#define RT5665_DAC_MIX_L_MASK (0x3 << 12)808#define RT5665_DAC_MIX_L_SFT 12809#define RT5665_DAC_MIX_R_MASK (0x3 << 8)810#define RT5665_DAC_MIX_R_SFT 8811#define RT5665_DAC_L1_SRC_MASK (0x3 << 4)812#define RT5665_A_DACL1_SFT 4813#define RT5665_DAC_R1_SRC_MASK (0x3)814#define RT5665_A_DACR1_SFT 0815 816/* Analog DAC Input Source Control (0x002e) */817#define RT5665_A_DACL2_SEL (0x1 << 4)818#define RT5665_A_DACL2_SFT 4819#define RT5665_A_DACR2_SEL (0x1 << 0)820#define RT5665_A_DACR2_SFT 0821 822/* Digital Interface Data Control (0x002f) */823#define RT5665_IF2_1_ADC_IN_MASK (0x7 << 12)824#define RT5665_IF2_1_ADC_IN_SFT 12825#define RT5665_IF2_1_DAC_SEL_MASK (0x3 << 10)826#define RT5665_IF2_1_DAC_SEL_SFT 10827#define RT5665_IF2_1_ADC_SEL_MASK (0x3 << 8)828#define RT5665_IF2_1_ADC_SEL_SFT 8829#define RT5665_IF2_2_ADC_IN_MASK (0x7 << 4)830#define RT5665_IF2_2_ADC_IN_SFT 4831#define RT5665_IF2_2_DAC_SEL_MASK (0x3 << 2)832#define RT5665_IF2_2_DAC_SEL_SFT 2833#define RT5665_IF2_2_ADC_SEL_MASK (0x3 << 0)834#define RT5665_IF2_2_ADC_SEL_SFT 0835 836/* Digital Interface Data Control (0x0030) */837#define RT5665_IF3_ADC_IN_MASK (0x7 << 4)838#define RT5665_IF3_ADC_IN_SFT 4839#define RT5665_IF3_DAC_SEL_MASK (0x3 << 2)840#define RT5665_IF3_DAC_SEL_SFT 2841#define RT5665_IF3_ADC_SEL_MASK (0x3 << 0)842#define RT5665_IF3_ADC_SEL_SFT 0843 844/* PDM Output Control (0x0031) */845#define RT5665_M_PDM1_L (0x1 << 14)846#define RT5665_M_PDM1_L_SFT 14847#define RT5665_M_PDM1_R (0x1 << 12)848#define RT5665_M_PDM1_R_SFT 12849#define RT5665_PDM1_L_MASK (0x3 << 10)850#define RT5665_PDM1_L_SFT 10851#define RT5665_PDM1_R_MASK (0x3 << 8)852#define RT5665_PDM1_R_SFT 8853#define RT5665_PDM1_BUSY (0x1 << 6)854#define RT5665_PDM_PATTERN (0x1 << 5)855#define RT5665_PDM_GAIN (0x1 << 4)856#define RT5665_LRCK_PDM_PI2C (0x1 << 3)857#define RT5665_PDM_DIV_MASK (0x3)858 859/*S/PDIF Output Control (0x0036) */860#define RT5665_SPDIF_SEL_MASK (0x3 << 0)861#define RT5665_SPDIF_SEL_SFT 0862 863/* REC Left Mixer Control 2 (0x003c) */864#define RT5665_M_CBJ_RM1_L (0x1 << 7)865#define RT5665_M_CBJ_RM1_L_SFT 7866#define RT5665_M_BST1_RM1_L (0x1 << 5)867#define RT5665_M_BST1_RM1_L_SFT 5868#define RT5665_M_BST2_RM1_L (0x1 << 4)869#define RT5665_M_BST2_RM1_L_SFT 4870#define RT5665_M_BST3_RM1_L (0x1 << 3)871#define RT5665_M_BST3_RM1_L_SFT 3872#define RT5665_M_BST4_RM1_L (0x1 << 2)873#define RT5665_M_BST4_RM1_L_SFT 2874#define RT5665_M_INL_RM1_L (0x1 << 1)875#define RT5665_M_INL_RM1_L_SFT 1876#define RT5665_M_INR_RM1_L (0x1)877#define RT5665_M_INR_RM1_L_SFT 0878 879/* REC Right Mixer Control 2 (0x003e) */880#define RT5665_M_AEC_REF_RM1_R (0x1 << 7)881#define RT5665_M_AEC_REF_RM1_R_SFT 7882#define RT5665_M_BST1_RM1_R (0x1 << 5)883#define RT5665_M_BST1_RM1_R_SFT 5884#define RT5665_M_BST2_RM1_R (0x1 << 4)885#define RT5665_M_BST2_RM1_R_SFT 4886#define RT5665_M_BST3_RM1_R (0x1 << 3)887#define RT5665_M_BST3_RM1_R_SFT 3888#define RT5665_M_BST4_RM1_R (0x1 << 2)889#define RT5665_M_BST4_RM1_R_SFT 2890#define RT5665_M_INR_RM1_R (0x1 << 1)891#define RT5665_M_INR_RM1_R_SFT 1892#define RT5665_M_MONOVOL_RM1_R (0x1)893#define RT5665_M_MONOVOL_RM1_R_SFT 0894 895/* REC Mixer 2 Left Control 2 (0x0041) */896#define RT5665_M_CBJ_RM2_L (0x1 << 7)897#define RT5665_M_CBJ_RM2_L_SFT 7898#define RT5665_M_BST1_RM2_L (0x1 << 5)899#define RT5665_M_BST1_RM2_L_SFT 5900#define RT5665_M_BST2_RM2_L (0x1 << 4)901#define RT5665_M_BST2_RM2_L_SFT 4902#define RT5665_M_BST3_RM2_L (0x1 << 3)903#define RT5665_M_BST3_RM2_L_SFT 3904#define RT5665_M_BST4_RM2_L (0x1 << 2)905#define RT5665_M_BST4_RM2_L_SFT 2906#define RT5665_M_INL_RM2_L (0x1 << 1)907#define RT5665_M_INL_RM2_L_SFT 1908#define RT5665_M_INR_RM2_L (0x1)909#define RT5665_M_INR_RM2_L_SFT 0910 911/* REC Mixer 2 Right Control 2 (0x0043) */912#define RT5665_M_MONOVOL_RM2_R (0x1 << 7)913#define RT5665_M_MONOVOL_RM2_R_SFT 7914#define RT5665_M_BST1_RM2_R (0x1 << 5)915#define RT5665_M_BST1_RM2_R_SFT 5916#define RT5665_M_BST2_RM2_R (0x1 << 4)917#define RT5665_M_BST2_RM2_R_SFT 4918#define RT5665_M_BST3_RM2_R (0x1 << 3)919#define RT5665_M_BST3_RM2_R_SFT 3920#define RT5665_M_BST4_RM2_R (0x1 << 2)921#define RT5665_M_BST4_RM2_R_SFT 2922#define RT5665_M_INL_RM2_R (0x1 << 1)923#define RT5665_M_INL_RM2_R_SFT 1924#define RT5665_M_INR_RM2_R (0x1)925#define RT5665_M_INR_RM2_R_SFT 0926 927/* SPK Left Mixer Control (0x0046) */928#define RT5665_M_BST3_SM_L (0x1 << 4)929#define RT5665_M_BST3_SM_L_SFT 4930#define RT5665_M_IN_R_SM_L (0x1 << 3)931#define RT5665_M_IN_R_SM_L_SFT 3932#define RT5665_M_IN_L_SM_L (0x1 << 2)933#define RT5665_M_IN_L_SM_L_SFT 2934#define RT5665_M_BST1_SM_L (0x1 << 1)935#define RT5665_M_BST1_SM_L_SFT 1936#define RT5665_M_DAC_L2_SM_L (0x1)937#define RT5665_M_DAC_L2_SM_L_SFT 0938 939/* SPK Right Mixer Control (0x0047) */940#define RT5665_M_BST3_SM_R (0x1 << 4)941#define RT5665_M_BST3_SM_R_SFT 4942#define RT5665_M_IN_R_SM_R (0x1 << 3)943#define RT5665_M_IN_R_SM_R_SFT 3944#define RT5665_M_IN_L_SM_R (0x1 << 2)945#define RT5665_M_IN_L_SM_R_SFT 2946#define RT5665_M_BST4_SM_R (0x1 << 1)947#define RT5665_M_BST4_SM_R_SFT 1948#define RT5665_M_DAC_R2_SM_R (0x1)949#define RT5665_M_DAC_R2_SM_R_SFT 0950 951/* SPO Amp Input and Gain Control (0x0048) */952#define RT5665_M_DAC_L2_SPKOMIX (0x1 << 13)953#define RT5665_M_DAC_L2_SPKOMIX_SFT 13954#define RT5665_M_SPKVOLL_SPKOMIX (0x1 << 12)955#define RT5665_M_SPKVOLL_SPKOMIX_SFT 12956#define RT5665_M_DAC_R2_SPKOMIX (0x1 << 9)957#define RT5665_M_DAC_R2_SPKOMIX_SFT 9958#define RT5665_M_SPKVOLR_SPKOMIX (0x1 << 8)959#define RT5665_M_SPKVOLR_SPKOMIX_SFT 8960 961/* MONOMIX Input and Gain Control (0x004b) */962#define RT5665_G_MONOVOL_MA (0x1 << 10)963#define RT5665_G_MONOVOL_MA_SFT 10964#define RT5665_M_MONOVOL_MA (0x1 << 9)965#define RT5665_M_MONOVOL_MA_SFT 9966#define RT5665_M_DAC_L2_MA (0x1 << 8)967#define RT5665_M_DAC_L2_MA_SFT 8968#define RT5665_M_BST3_MM (0x1 << 4)969#define RT5665_M_BST3_MM_SFT 4970#define RT5665_M_BST2_MM (0x1 << 3)971#define RT5665_M_BST2_MM_SFT 3972#define RT5665_M_BST1_MM (0x1 << 2)973#define RT5665_M_BST1_MM_SFT 2974#define RT5665_M_RECMIC2L_MM (0x1 << 1)975#define RT5665_M_RECMIC2L_MM_SFT 1976#define RT5665_M_DAC_L2_MM (0x1)977#define RT5665_M_DAC_L2_MM_SFT 0978 979/* Output Left Mixer Control 1 (0x004d) */980#define RT5665_G_BST3_OM_L_MASK (0x7 << 12)981#define RT5665_G_BST3_OM_L_SFT 12982#define RT5665_G_BST2_OM_L_MASK (0x7 << 9)983#define RT5665_G_BST2_OM_L_SFT 9984#define RT5665_G_BST1_OM_L_MASK (0x7 << 6)985#define RT5665_G_BST1_OM_L_SFT 6986#define RT5665_G_IN_L_OM_L_MASK (0x7 << 3)987#define RT5665_G_IN_L_OM_L_SFT 3988#define RT5665_G_DAC_L2_OM_L_MASK (0x7 << 0)989#define RT5665_G_DAC_L2_OM_L_SFT 0990 991/* Output Left Mixer Input Control (0x004e) */992#define RT5665_M_BST3_OM_L (0x1 << 4)993#define RT5665_M_BST3_OM_L_SFT 4994#define RT5665_M_BST2_OM_L (0x1 << 3)995#define RT5665_M_BST2_OM_L_SFT 3996#define RT5665_M_BST1_OM_L (0x1 << 2)997#define RT5665_M_BST1_OM_L_SFT 2998#define RT5665_M_IN_L_OM_L (0x1 << 1)999#define RT5665_M_IN_L_OM_L_SFT 11000#define RT5665_M_DAC_L2_OM_L (0x1)1001#define RT5665_M_DAC_L2_OM_L_SFT 01002 1003/* Output Right Mixer Input Control (0x0050) */1004#define RT5665_M_BST4_OM_R (0x1 << 4)1005#define RT5665_M_BST4_OM_R_SFT 41006#define RT5665_M_BST3_OM_R (0x1 << 3)1007#define RT5665_M_BST3_OM_R_SFT 31008#define RT5665_M_BST2_OM_R (0x1 << 2)1009#define RT5665_M_BST2_OM_R_SFT 21010#define RT5665_M_IN_R_OM_R (0x1 << 1)1011#define RT5665_M_IN_R_OM_R_SFT 11012#define RT5665_M_DAC_R2_OM_R (0x1)1013#define RT5665_M_DAC_R2_OM_R_SFT 01014 1015/* LOUT Mixer Control (0x0052) */1016#define RT5665_M_DAC_L2_LM (0x1 << 15)1017#define RT5665_M_DAC_L2_LM_SFT 151018#define RT5665_M_DAC_R2_LM (0x1 << 14)1019#define RT5665_M_DAC_R2_LM_SFT 141020#define RT5665_M_OV_L_LM (0x1 << 13)1021#define RT5665_M_OV_L_LM_SFT 131022#define RT5665_M_OV_R_LM (0x1 << 12)1023#define RT5665_M_OV_R_LM_SFT 121024#define RT5665_LOUT_BST_SFT 111025#define RT5665_LOUT_DF (0x1 << 11)1026#define RT5665_LOUT_DF_SFT 111027 1028/* Power Management for Digital 1 (0x0061) */1029#define RT5665_PWR_I2S1_1 (0x1 << 15)1030#define RT5665_PWR_I2S1_1_BIT 151031#define RT5665_PWR_I2S1_2 (0x1 << 14)1032#define RT5665_PWR_I2S1_2_BIT 141033#define RT5665_PWR_I2S2_1 (0x1 << 13)1034#define RT5665_PWR_I2S2_1_BIT 131035#define RT5665_PWR_I2S2_2 (0x1 << 12)1036#define RT5665_PWR_I2S2_2_BIT 121037#define RT5665_PWR_DAC_L1 (0x1 << 11)1038#define RT5665_PWR_DAC_L1_BIT 111039#define RT5665_PWR_DAC_R1 (0x1 << 10)1040#define RT5665_PWR_DAC_R1_BIT 101041#define RT5665_PWR_I2S3 (0x1 << 9)1042#define RT5665_PWR_I2S3_BIT 91043#define RT5665_PWR_LDO (0x1 << 8)1044#define RT5665_PWR_LDO_BIT 81045#define RT5665_PWR_DAC_L2 (0x1 << 7)1046#define RT5665_PWR_DAC_L2_BIT 71047#define RT5665_PWR_DAC_R2 (0x1 << 6)1048#define RT5665_PWR_DAC_R2_BIT 61049#define RT5665_PWR_ADC_L1 (0x1 << 4)1050#define RT5665_PWR_ADC_L1_BIT 41051#define RT5665_PWR_ADC_R1 (0x1 << 3)1052#define RT5665_PWR_ADC_R1_BIT 31053#define RT5665_PWR_ADC_L2 (0x1 << 2)1054#define RT5665_PWR_ADC_L2_BIT 21055#define RT5665_PWR_ADC_R2 (0x1 << 1)1056#define RT5665_PWR_ADC_R2_BIT 11057 1058/* Power Management for Digital 2 (0x0062) */1059#define RT5665_PWR_ADC_S1F (0x1 << 15)1060#define RT5665_PWR_ADC_S1F_BIT 151061#define RT5665_PWR_ADC_S2F (0x1 << 14)1062#define RT5665_PWR_ADC_S2F_BIT 141063#define RT5665_PWR_ADC_MF_L (0x1 << 13)1064#define RT5665_PWR_ADC_MF_L_BIT 131065#define RT5665_PWR_ADC_MF_R (0x1 << 12)1066#define RT5665_PWR_ADC_MF_R_BIT 121067#define RT5665_PWR_DAC_S2F (0x1 << 11)1068#define RT5665_PWR_DAC_S2F_BIT 111069#define RT5665_PWR_DAC_S1F (0x1 << 10)1070#define RT5665_PWR_DAC_S1F_BIT 101071#define RT5665_PWR_DAC_MF_L (0x1 << 9)1072#define RT5665_PWR_DAC_MF_L_BIT 91073#define RT5665_PWR_DAC_MF_R (0x1 << 8)1074#define RT5665_PWR_DAC_MF_R_BIT 81075#define RT5665_PWR_PDM1 (0x1 << 7)1076#define RT5665_PWR_PDM1_BIT 71077 1078/* Power Management for Analog 1 (0x0063) */1079#define RT5665_PWR_VREF1 (0x1 << 15)1080#define RT5665_PWR_VREF1_BIT 151081#define RT5665_PWR_FV1 (0x1 << 14)1082#define RT5665_PWR_FV1_BIT 141083#define RT5665_PWR_VREF2 (0x1 << 13)1084#define RT5665_PWR_VREF2_BIT 131085#define RT5665_PWR_FV2 (0x1 << 12)1086#define RT5665_PWR_FV2_BIT 121087#define RT5665_PWR_VREF3 (0x1 << 11)1088#define RT5665_PWR_VREF3_BIT 111089#define RT5665_PWR_FV3 (0x1 << 10)1090#define RT5665_PWR_FV3_BIT 101091#define RT5665_PWR_MB (0x1 << 9)1092#define RT5665_PWR_MB_BIT 91093#define RT5665_PWR_LM (0x1 << 8)1094#define RT5665_PWR_LM_BIT 81095#define RT5665_PWR_BG (0x1 << 7)1096#define RT5665_PWR_BG_BIT 71097#define RT5665_PWR_MA (0x1 << 6)1098#define RT5665_PWR_MA_BIT 61099#define RT5665_PWR_HA_L (0x1 << 5)1100#define RT5665_PWR_HA_L_BIT 51101#define RT5665_PWR_HA_R (0x1 << 4)1102#define RT5665_PWR_HA_R_BIT 41103#define RT5665_HP_DRIVER_MASK (0x3 << 2)1104#define RT5665_HP_DRIVER_1X (0x0 << 2)1105#define RT5665_HP_DRIVER_3X (0x1 << 2)1106#define RT5665_HP_DRIVER_5X (0x3 << 2)1107#define RT5665_LDO1_DVO_MASK (0x3)1108#define RT5665_LDO1_DVO_09 (0x0)1109#define RT5665_LDO1_DVO_10 (0x1)1110#define RT5665_LDO1_DVO_12 (0x2)1111#define RT5665_LDO1_DVO_14 (0x3)1112 1113/* Power Management for Analog 2 (0x0064) */1114#define RT5665_PWR_BST1 (0x1 << 15)1115#define RT5665_PWR_BST1_BIT 151116#define RT5665_PWR_BST2 (0x1 << 14)1117#define RT5665_PWR_BST2_BIT 141118#define RT5665_PWR_BST3 (0x1 << 13)1119#define RT5665_PWR_BST3_BIT 131120#define RT5665_PWR_BST4 (0x1 << 12)1121#define RT5665_PWR_BST4_BIT 121122#define RT5665_PWR_MB1 (0x1 << 11)1123#define RT5665_PWR_MB1_PWR_DOWN (0x0 << 11)1124#define RT5665_PWR_MB1_BIT 111125#define RT5665_PWR_MB2 (0x1 << 10)1126#define RT5665_PWR_MB2_PWR_DOWN (0x0 << 10)1127#define RT5665_PWR_MB2_BIT 101128#define RT5665_PWR_MB3 (0x1 << 9)1129#define RT5665_PWR_MB3_BIT 91130#define RT5665_PWR_BST1_P (0x1 << 7)1131#define RT5665_PWR_BST1_P_BIT 71132#define RT5665_PWR_BST2_P (0x1 << 6)1133#define RT5665_PWR_BST2_P_BIT 61134#define RT5665_PWR_BST3_P (0x1 << 5)1135#define RT5665_PWR_BST3_P_BIT 51136#define RT5665_PWR_BST4_P (0x1 << 4)1137#define RT5665_PWR_BST4_P_BIT 41138#define RT5665_PWR_JD1 (0x1 << 3)1139#define RT5665_PWR_JD1_BIT 31140#define RT5665_PWR_JD2 (0x1 << 2)1141#define RT5665_PWR_JD2_BIT 21142#define RT5665_PWR_RM1_L (0x1 << 1)1143#define RT5665_PWR_RM1_L_BIT 11144#define RT5665_PWR_RM1_R (0x1)1145#define RT5665_PWR_RM1_R_BIT 01146 1147/* Power Management for Analog 3 (0x0065) */1148#define RT5665_PWR_CBJ (0x1 << 9)1149#define RT5665_PWR_CBJ_BIT 91150#define RT5665_PWR_BST_L (0x1 << 8)1151#define RT5665_PWR_BST_L_BIT 81152#define RT5665_PWR_BST_R (0x1 << 7)1153#define RT5665_PWR_BST_R_BIT 71154#define RT5665_PWR_PLL (0x1 << 6)1155#define RT5665_PWR_PLL_BIT 61156#define RT5665_PWR_LDO2 (0x1 << 2)1157#define RT5665_PWR_LDO2_BIT 21158#define RT5665_PWR_SVD (0x1 << 1)1159#define RT5665_PWR_SVD_BIT 11160 1161/* Power Management for Mixer (0x0066) */1162#define RT5665_PWR_RM2_L (0x1 << 15)1163#define RT5665_PWR_RM2_L_BIT 151164#define RT5665_PWR_RM2_R (0x1 << 14)1165#define RT5665_PWR_RM2_R_BIT 141166#define RT5665_PWR_OM_L (0x1 << 13)1167#define RT5665_PWR_OM_L_BIT 131168#define RT5665_PWR_OM_R (0x1 << 12)1169#define RT5665_PWR_OM_R_BIT 121170#define RT5665_PWR_MM (0x1 << 11)1171#define RT5665_PWR_MM_BIT 111172#define RT5665_PWR_AEC_REF (0x1 << 6)1173#define RT5665_PWR_AEC_REF_BIT 61174#define RT5665_PWR_STO1_DAC_L (0x1 << 5)1175#define RT5665_PWR_STO1_DAC_L_BIT 51176#define RT5665_PWR_STO1_DAC_R (0x1 << 4)1177#define RT5665_PWR_STO1_DAC_R_BIT 41178#define RT5665_PWR_MONO_DAC_L (0x1 << 3)1179#define RT5665_PWR_MONO_DAC_L_BIT 31180#define RT5665_PWR_MONO_DAC_R (0x1 << 2)1181#define RT5665_PWR_MONO_DAC_R_BIT 21182#define RT5665_PWR_STO2_DAC_L (0x1 << 1)1183#define RT5665_PWR_STO2_DAC_L_BIT 11184#define RT5665_PWR_STO2_DAC_R (0x1)1185#define RT5665_PWR_STO2_DAC_R_BIT 01186 1187/* Power Management for Volume (0x0067) */1188#define RT5665_PWR_OV_L (0x1 << 13)1189#define RT5665_PWR_OV_L_BIT 131190#define RT5665_PWR_OV_R (0x1 << 12)1191#define RT5665_PWR_OV_R_BIT 121192#define RT5665_PWR_IN_L (0x1 << 9)1193#define RT5665_PWR_IN_L_BIT 91194#define RT5665_PWR_IN_R (0x1 << 8)1195#define RT5665_PWR_IN_R_BIT 81196#define RT5665_PWR_MV (0x1 << 7)1197#define RT5665_PWR_MV_BIT 71198#define RT5665_PWR_MIC_DET (0x1 << 5)1199#define RT5665_PWR_MIC_DET_BIT 51200 1201/* (0x006b) */1202#define RT5665_SYS_CLK_DET 151203#define RT5665_HP_CLK_DET 141204#define RT5665_MONO_CLK_DET 131205#define RT5665_LOUT_CLK_DET 121206#define RT5665_POW_CLK_DET 01207 1208/* Digital Microphone Control 1 (0x006e) */1209#define RT5665_DMIC_1_EN_MASK (0x1 << 15)1210#define RT5665_DMIC_1_EN_SFT 151211#define RT5665_DMIC_1_DIS (0x0 << 15)1212#define RT5665_DMIC_1_EN (0x1 << 15)1213#define RT5665_DMIC_2_EN_MASK (0x1 << 14)1214#define RT5665_DMIC_2_EN_SFT 141215#define RT5665_DMIC_2_DIS (0x0 << 14)1216#define RT5665_DMIC_2_EN (0x1 << 14)1217#define RT5665_DMIC_2_DP_MASK (0x1 << 9)1218#define RT5665_DMIC_2_DP_SFT 91219#define RT5665_DMIC_2_DP_GPIO5 (0x0 << 9)1220#define RT5665_DMIC_2_DP_IN2P (0x1 << 9)1221#define RT5665_DMIC_CLK_MASK (0x7 << 5)1222#define RT5665_DMIC_CLK_SFT 51223#define RT5665_DMIC_1_DP_MASK (0x1 << 1)1224#define RT5665_DMIC_1_DP_SFT 11225#define RT5665_DMIC_1_DP_GPIO4 (0x0 << 1)1226#define RT5665_DMIC_1_DP_IN2N (0x1 << 1)1227 1228 1229/* Digital Microphone Control 1 (0x006f) */1230#define RT5665_DMIC_2L_LH_MASK (0x1 << 3)1231#define RT5665_DMIC_2L_LH_SFT 31232#define RT5665_DMIC_2L_LH_RISING (0x0 << 3)1233#define RT5665_DMIC_2L_LH_FALLING (0x1 << 3)1234#define RT5665_DMIC_2R_LH_MASK (0x1 << 2)1235#define RT5665_DMIC_2R_LH_SFT 21236#define RT5665_DMIC_2R_LH_RISING (0x0 << 2)1237#define RT5665_DMIC_2R_LH_FALLING (0x1 << 2)1238#define RT5665_DMIC_1L_LH_MASK (0x1 << 1)1239#define RT5665_DMIC_1L_LH_SFT 11240#define RT5665_DMIC_1L_LH_RISING (0x0 << 1)1241#define RT5665_DMIC_1L_LH_FALLING (0x1 << 1)1242#define RT5665_DMIC_1R_LH_MASK (0x1 << 0)1243#define RT5665_DMIC_1R_LH_SFT 01244#define RT5665_DMIC_1R_LH_RISING (0x0)1245#define RT5665_DMIC_1R_LH_FALLING (0x1)1246 1247/* I2S1/2/3 Audio Serial Data Port Control (0x0070 0x0071 0x0072) */1248#define RT5665_I2S_MS_MASK (0x1 << 15)1249#define RT5665_I2S_MS_SFT 151250#define RT5665_I2S_MS_M (0x0 << 15)1251#define RT5665_I2S_MS_S (0x1 << 15)1252#define RT5665_I2S_PIN_CFG_MASK (0x1 << 14)1253#define RT5665_I2S_PIN_CFG_SFT 141254#define RT5665_I2S_CLK_SEL_MASK (0x1 << 11)1255#define RT5665_I2S_CLK_SEL_SFT 111256#define RT5665_I2S_BP_MASK (0x1 << 8)1257#define RT5665_I2S_BP_SFT 81258#define RT5665_I2S_BP_NOR (0x0 << 8)1259#define RT5665_I2S_BP_INV (0x1 << 8)1260#define RT5665_I2S_DL_MASK (0x3 << 4)1261#define RT5665_I2S_DL_SFT 41262#define RT5665_I2S_DL_16 (0x0 << 4)1263#define RT5665_I2S_DL_20 (0x1 << 4)1264#define RT5665_I2S_DL_24 (0x2 << 4)1265#define RT5665_I2S_DL_8 (0x3 << 4)1266#define RT5665_I2S_DF_MASK (0x7)1267#define RT5665_I2S_DF_SFT 01268#define RT5665_I2S_DF_I2S (0x0)1269#define RT5665_I2S_DF_LEFT (0x1)1270#define RT5665_I2S_DF_PCM_A (0x2)1271#define RT5665_I2S_DF_PCM_B (0x3)1272#define RT5665_I2S_DF_PCM_A_N (0x6)1273#define RT5665_I2S_DF_PCM_B_N (0x7)1274 1275/* ADC/DAC Clock Control 1 (0x0073) */1276#define RT5665_I2S_PD1_MASK (0x7 << 12)1277#define RT5665_I2S_PD1_SFT 121278#define RT5665_I2S_PD1_1 (0x0 << 12)1279#define RT5665_I2S_PD1_2 (0x1 << 12)1280#define RT5665_I2S_PD1_3 (0x2 << 12)1281#define RT5665_I2S_PD1_4 (0x3 << 12)1282#define RT5665_I2S_PD1_6 (0x4 << 12)1283#define RT5665_I2S_PD1_8 (0x5 << 12)1284#define RT5665_I2S_PD1_12 (0x6 << 12)1285#define RT5665_I2S_PD1_16 (0x7 << 12)1286#define RT5665_I2S_M_PD2_MASK (0x7 << 8)1287#define RT5665_I2S_M_PD2_SFT 81288#define RT5665_I2S_M_PD2_1 (0x0 << 8)1289#define RT5665_I2S_M_PD2_2 (0x1 << 8)1290#define RT5665_I2S_M_PD2_3 (0x2 << 8)1291#define RT5665_I2S_M_PD2_4 (0x3 << 8)1292#define RT5665_I2S_M_PD2_6 (0x4 << 8)1293#define RT5665_I2S_M_PD2_8 (0x5 << 8)1294#define RT5665_I2S_M_PD2_12 (0x6 << 8)1295#define RT5665_I2S_M_PD2_16 (0x7 << 8)1296#define RT5665_I2S_CLK_SRC_MASK (0x3 << 4)1297#define RT5665_I2S_CLK_SRC_SFT 41298#define RT5665_I2S_CLK_SRC_MCLK (0x0 << 4)1299#define RT5665_I2S_CLK_SRC_PLL1 (0x1 << 4)1300#define RT5665_I2S_CLK_SRC_RCCLK (0x2 << 4)1301#define RT5665_DAC_OSR_MASK (0x3 << 2)1302#define RT5665_DAC_OSR_SFT 21303#define RT5665_DAC_OSR_128 (0x0 << 2)1304#define RT5665_DAC_OSR_64 (0x1 << 2)1305#define RT5665_DAC_OSR_32 (0x2 << 2)1306#define RT5665_ADC_OSR_MASK (0x3)1307#define RT5665_ADC_OSR_SFT 01308#define RT5665_ADC_OSR_128 (0x0)1309#define RT5665_ADC_OSR_64 (0x1)1310#define RT5665_ADC_OSR_32 (0x2)1311 1312/* ADC/DAC Clock Control 2 (0x0074) */1313#define RT5665_I2S_BCLK_MS2_MASK (0x1 << 15)1314#define RT5665_I2S_BCLK_MS2_SFT 151315#define RT5665_I2S_BCLK_MS2_32 (0x0 << 15)1316#define RT5665_I2S_BCLK_MS2_64 (0x1 << 15)1317#define RT5665_I2S_PD2_MASK (0x7 << 12)1318#define RT5665_I2S_PD2_SFT 121319#define RT5665_I2S_PD2_1 (0x0 << 12)1320#define RT5665_I2S_PD2_2 (0x1 << 12)1321#define RT5665_I2S_PD2_3 (0x2 << 12)1322#define RT5665_I2S_PD2_4 (0x3 << 12)1323#define RT5665_I2S_PD2_6 (0x4 << 12)1324#define RT5665_I2S_PD2_8 (0x5 << 12)1325#define RT5665_I2S_PD2_12 (0x6 << 12)1326#define RT5665_I2S_PD2_16 (0x7 << 12)1327#define RT5665_I2S_BCLK_MS3_MASK (0x1 << 11)1328#define RT5665_I2S_BCLK_MS3_SFT 111329#define RT5665_I2S_BCLK_MS3_32 (0x0 << 11)1330#define RT5665_I2S_BCLK_MS3_64 (0x1 << 11)1331#define RT5665_I2S_PD3_MASK (0x7 << 8)1332#define RT5665_I2S_PD3_SFT 81333#define RT5665_I2S_PD3_1 (0x0 << 8)1334#define RT5665_I2S_PD3_2 (0x1 << 8)1335#define RT5665_I2S_PD3_3 (0x2 << 8)1336#define RT5665_I2S_PD3_4 (0x3 << 8)1337#define RT5665_I2S_PD3_6 (0x4 << 8)1338#define RT5665_I2S_PD3_8 (0x5 << 8)1339#define RT5665_I2S_PD3_12 (0x6 << 8)1340#define RT5665_I2S_PD3_16 (0x7 << 8)1341#define RT5665_I2S_PD4_MASK (0x7 << 4)1342#define RT5665_I2S_PD4_SFT 41343#define RT5665_I2S_PD4_1 (0x0 << 4)1344#define RT5665_I2S_PD4_2 (0x1 << 4)1345#define RT5665_I2S_PD4_3 (0x2 << 4)1346#define RT5665_I2S_PD4_4 (0x3 << 4)1347#define RT5665_I2S_PD4_6 (0x4 << 4)1348#define RT5665_I2S_PD4_8 (0x5 << 4)1349#define RT5665_I2S_PD4_12 (0x6 << 4)1350#define RT5665_I2S_PD4_16 (0x7 << 4)1351 1352/* TDM control 1 (0x0078) */1353#define RT5665_I2S1_MODE_MASK (0x1 << 15)1354#define RT5665_I2S1_MODE_I2S (0x0 << 15)1355#define RT5665_I2S1_MODE_TDM (0x1 << 15)1356#define RT5665_TDM_IN_CH_MASK (0x3 << 10)1357#define RT5665_TDM_IN_CH_2 (0x0 << 10)1358#define RT5665_TDM_IN_CH_4 (0x1 << 10)1359#define RT5665_TDM_IN_CH_6 (0x2 << 10)1360#define RT5665_TDM_IN_CH_8 (0x3 << 10)1361#define RT5665_TDM_OUT_CH_MASK (0x3 << 8)1362#define RT5665_TDM_OUT_CH_2 (0x0 << 8)1363#define RT5665_TDM_OUT_CH_4 (0x1 << 8)1364#define RT5665_TDM_OUT_CH_6 (0x2 << 8)1365#define RT5665_TDM_OUT_CH_8 (0x3 << 8)1366#define RT5665_TDM_IN_LEN_MASK (0x3 << 6)1367#define RT5665_TDM_IN_LEN_16 (0x0 << 6)1368#define RT5665_TDM_IN_LEN_20 (0x1 << 6)1369#define RT5665_TDM_IN_LEN_24 (0x2 << 6)1370#define RT5665_TDM_IN_LEN_32 (0x3 << 6)1371#define RT5665_TDM_OUT_LEN_MASK (0x3 << 4)1372#define RT5665_TDM_OUT_LEN_16 (0x0 << 4)1373#define RT5665_TDM_OUT_LEN_20 (0x1 << 4)1374#define RT5665_TDM_OUT_LEN_24 (0x2 << 4)1375#define RT5665_TDM_OUT_LEN_32 (0x3 << 4)1376 1377 1378/* TDM control 2 (0x0079) */1379#define RT5665_I2S1_1_DS_ADC_SLOT01_SFT 141380#define RT5665_I2S1_1_DS_ADC_SLOT23_SFT 121381#define RT5665_I2S1_1_DS_ADC_SLOT45_SFT 101382#define RT5665_I2S1_1_DS_ADC_SLOT67_SFT 81383#define RT5665_I2S1_2_DS_ADC_SLOT01_SFT 61384#define RT5665_I2S1_2_DS_ADC_SLOT23_SFT 41385#define RT5665_I2S1_2_DS_ADC_SLOT45_SFT 21386#define RT5665_I2S1_2_DS_ADC_SLOT67_SFT 01387 1388/* TDM control 3/4 (0x007a) (0x007b) */1389#define RT5665_IF1_ADC1_SEL_SFT 101390#define RT5665_IF1_ADC2_SEL_SFT 91391#define RT5665_IF1_ADC3_SEL_SFT 81392#define RT5665_IF1_ADC4_SEL_SFT 71393#define RT5665_TDM_ADC_SEL_SFT 01394#define RT5665_TDM_ADC_CTRL_MASK (0x1f << 0)1395#define RT5665_TDM_ADC_DATA_06 (0x6 << 0)1396 1397/* Global Clock Control (0x0080) */1398#define RT5665_SCLK_SRC_MASK (0x3 << 14)1399#define RT5665_SCLK_SRC_SFT 141400#define RT5665_SCLK_SRC_MCLK (0x0 << 14)1401#define RT5665_SCLK_SRC_PLL1 (0x1 << 14)1402#define RT5665_SCLK_SRC_RCCLK (0x2 << 14)1403#define RT5665_PLL1_SRC_MASK (0x7 << 8)1404#define RT5665_PLL1_SRC_SFT 81405#define RT5665_PLL1_SRC_MCLK (0x0 << 8)1406#define RT5665_PLL1_SRC_BCLK1 (0x1 << 8)1407#define RT5665_PLL1_SRC_BCLK2 (0x2 << 8)1408#define RT5665_PLL1_SRC_BCLK3 (0x3 << 8)1409#define RT5665_PLL1_PD_MASK (0x7 << 4)1410#define RT5665_PLL1_PD_SFT 41411 1412 1413#define RT5665_PLL_INP_MAX 400000001414#define RT5665_PLL_INP_MIN 2560001415/* PLL M/N/K Code Control 1 (0x0081) */1416#define RT5665_PLL_N_MAX 0x001ff1417#define RT5665_PLL_N_MASK (RT5665_PLL_N_MAX << 7)1418#define RT5665_PLL_N_SFT 71419#define RT5665_PLL_K_MAX 0x001f1420#define RT5665_PLL_K_MASK (RT5665_PLL_K_MAX)1421#define RT5665_PLL_K_SFT 01422 1423/* PLL M/N/K Code Control 2 (0x0082) */1424#define RT5665_PLL_M_MAX 0x00f1425#define RT5665_PLL_M_MASK (RT5665_PLL_M_MAX << 12)1426#define RT5665_PLL_M_SFT 121427#define RT5665_PLL_M_BP (0x1 << 11)1428#define RT5665_PLL_M_BP_SFT 111429#define RT5665_PLL_K_BP (0x1 << 10)1430#define RT5665_PLL_K_BP_SFT 101431 1432/* PLL tracking mode 1 (0x0083) */1433#define RT5665_I2S3_ASRC_MASK (0x1 << 15)1434#define RT5665_I2S3_ASRC_SFT 151435#define RT5665_I2S2_ASRC_MASK (0x1 << 14)1436#define RT5665_I2S2_ASRC_SFT 141437#define RT5665_I2S1_ASRC_MASK (0x1 << 13)1438#define RT5665_I2S1_ASRC_SFT 131439#define RT5665_DAC_STO1_ASRC_MASK (0x1 << 12)1440#define RT5665_DAC_STO1_ASRC_SFT 121441#define RT5665_DAC_STO2_ASRC_MASK (0x1 << 11)1442#define RT5665_DAC_STO2_ASRC_SFT 111443#define RT5665_DAC_MONO_L_ASRC_MASK (0x1 << 10)1444#define RT5665_DAC_MONO_L_ASRC_SFT 101445#define RT5665_DAC_MONO_R_ASRC_MASK (0x1 << 9)1446#define RT5665_DAC_MONO_R_ASRC_SFT 91447#define RT5665_DMIC_STO1_ASRC_MASK (0x1 << 8)1448#define RT5665_DMIC_STO1_ASRC_SFT 81449#define RT5665_DMIC_STO2_ASRC_MASK (0x1 << 7)1450#define RT5665_DMIC_STO2_ASRC_SFT 71451#define RT5665_DMIC_MONO_L_ASRC_MASK (0x1 << 6)1452#define RT5665_DMIC_MONO_L_ASRC_SFT 61453#define RT5665_DMIC_MONO_R_ASRC_MASK (0x1 << 5)1454#define RT5665_DMIC_MONO_R_ASRC_SFT 51455#define RT5665_ADC_STO1_ASRC_MASK (0x1 << 4)1456#define RT5665_ADC_STO1_ASRC_SFT 41457#define RT5665_ADC_STO2_ASRC_MASK (0x1 << 3)1458#define RT5665_ADC_STO2_ASRC_SFT 31459#define RT5665_ADC_MONO_L_ASRC_MASK (0x1 << 2)1460#define RT5665_ADC_MONO_L_ASRC_SFT 21461#define RT5665_ADC_MONO_R_ASRC_MASK (0x1 << 1)1462#define RT5665_ADC_MONO_R_ASRC_SFT 11463 1464/* PLL tracking mode 2 (0x0084)*/1465#define RT5665_DA_STO1_CLK_SEL_MASK (0x7 << 12)1466#define RT5665_DA_STO1_CLK_SEL_SFT 121467#define RT5665_DA_STO2_CLK_SEL_MASK (0x7 << 8)1468#define RT5665_DA_STO2_CLK_SEL_SFT 81469#define RT5665_DA_MONOL_CLK_SEL_MASK (0x7 << 4)1470#define RT5665_DA_MONOL_CLK_SEL_SFT 41471#define RT5665_DA_MONOR_CLK_SEL_MASK (0x7)1472#define RT5665_DA_MONOR_CLK_SEL_SFT 01473 1474/* PLL tracking mode 3 (0x0085)*/1475#define RT5665_AD_STO1_CLK_SEL_MASK (0x7 << 12)1476#define RT5665_AD_STO1_CLK_SEL_SFT 121477#define RT5665_AD_STO2_CLK_SEL_MASK (0x7 << 8)1478#define RT5665_AD_STO2_CLK_SEL_SFT 81479#define RT5665_AD_MONOL_CLK_SEL_MASK (0x7 << 4)1480#define RT5665_AD_MONOL_CLK_SEL_SFT 41481#define RT5665_AD_MONOR_CLK_SEL_MASK (0x7)1482#define RT5665_AD_MONOR_CLK_SEL_SFT 01483 1484/* ASRC Control 4 (0x0086) */1485#define RT5665_I2S1_RATE_MASK (0xf << 12)1486#define RT5665_I2S1_RATE_SFT 121487#define RT5665_I2S2_RATE_MASK (0xf << 8)1488#define RT5665_I2S2_RATE_SFT 81489#define RT5665_I2S3_RATE_MASK (0xf << 4)1490#define RT5665_I2S3_RATE_SFT 41491 1492/* Depop Mode Control 1 (0x008e) */1493#define RT5665_PUMP_EN (0x1 << 3)1494 1495/* Depop Mode Control 2 (0x8f) */1496#define RT5665_DEPOP_MASK (0x1 << 13)1497#define RT5665_DEPOP_SFT 131498#define RT5665_DEPOP_AUTO (0x0 << 13)1499#define RT5665_DEPOP_MAN (0x1 << 13)1500#define RT5665_RAMP_MASK (0x1 << 12)1501#define RT5665_RAMP_SFT 121502#define RT5665_RAMP_DIS (0x0 << 12)1503#define RT5665_RAMP_EN (0x1 << 12)1504#define RT5665_BPS_MASK (0x1 << 11)1505#define RT5665_BPS_SFT 111506#define RT5665_BPS_DIS (0x0 << 11)1507#define RT5665_BPS_EN (0x1 << 11)1508#define RT5665_FAST_UPDN_MASK (0x1 << 10)1509#define RT5665_FAST_UPDN_SFT 101510#define RT5665_FAST_UPDN_DIS (0x0 << 10)1511#define RT5665_FAST_UPDN_EN (0x1 << 10)1512#define RT5665_MRES_MASK (0x3 << 8)1513#define RT5665_MRES_SFT 81514#define RT5665_MRES_15MO (0x0 << 8)1515#define RT5665_MRES_25MO (0x1 << 8)1516#define RT5665_MRES_35MO (0x2 << 8)1517#define RT5665_MRES_45MO (0x3 << 8)1518#define RT5665_VLO_MASK (0x1 << 7)1519#define RT5665_VLO_SFT 71520#define RT5665_VLO_3V (0x0 << 7)1521#define RT5665_VLO_32V (0x1 << 7)1522#define RT5665_DIG_DP_MASK (0x1 << 6)1523#define RT5665_DIG_DP_SFT 61524#define RT5665_DIG_DP_DIS (0x0 << 6)1525#define RT5665_DIG_DP_EN (0x1 << 6)1526#define RT5665_DP_TH_MASK (0x3 << 4)1527#define RT5665_DP_TH_SFT 41528 1529/* Depop Mode Control 3 (0x90) */1530#define RT5665_CP_SYS_MASK (0x7 << 12)1531#define RT5665_CP_SYS_SFT 121532#define RT5665_CP_FQ1_MASK (0x7 << 8)1533#define RT5665_CP_FQ1_SFT 81534#define RT5665_CP_FQ2_MASK (0x7 << 4)1535#define RT5665_CP_FQ2_SFT 41536#define RT5665_CP_FQ3_MASK (0x7)1537#define RT5665_CP_FQ3_SFT 01538#define RT5665_CP_FQ_1_5_KHZ 01539#define RT5665_CP_FQ_3_KHZ 11540#define RT5665_CP_FQ_6_KHZ 21541#define RT5665_CP_FQ_12_KHZ 31542#define RT5665_CP_FQ_24_KHZ 41543#define RT5665_CP_FQ_48_KHZ 51544#define RT5665_CP_FQ_96_KHZ 61545#define RT5665_CP_FQ_192_KHZ 71546 1547/* HPOUT charge pump 1 (0x0091) */1548#define RT5665_OSW_L_MASK (0x1 << 11)1549#define RT5665_OSW_L_SFT 111550#define RT5665_OSW_L_DIS (0x0 << 11)1551#define RT5665_OSW_L_EN (0x1 << 11)1552#define RT5665_OSW_R_MASK (0x1 << 10)1553#define RT5665_OSW_R_SFT 101554#define RT5665_OSW_R_DIS (0x0 << 10)1555#define RT5665_OSW_R_EN (0x1 << 10)1556#define RT5665_PM_HP_MASK (0x3 << 8)1557#define RT5665_PM_HP_SFT 81558#define RT5665_PM_HP_LV (0x0 << 8)1559#define RT5665_PM_HP_MV (0x1 << 8)1560#define RT5665_PM_HP_HV (0x2 << 8)1561#define RT5665_IB_HP_MASK (0x3 << 6)1562#define RT5665_IB_HP_SFT 61563#define RT5665_IB_HP_125IL (0x0 << 6)1564#define RT5665_IB_HP_25IL (0x1 << 6)1565#define RT5665_IB_HP_5IL (0x2 << 6)1566#define RT5665_IB_HP_1IL (0x3 << 6)1567 1568/* PV detection and SPK gain control (0x92) */1569#define RT5665_PVDD_DET_MASK (0x1 << 15)1570#define RT5665_PVDD_DET_SFT 151571#define RT5665_PVDD_DET_DIS (0x0 << 15)1572#define RT5665_PVDD_DET_EN (0x1 << 15)1573#define RT5665_SPK_AG_MASK (0x1 << 14)1574#define RT5665_SPK_AG_SFT 141575#define RT5665_SPK_AG_DIS (0x0 << 14)1576#define RT5665_SPK_AG_EN (0x1 << 14)1577 1578/* Micbias Control1 (0x93) */1579#define RT5665_MIC1_BS_MASK (0x1 << 15)1580#define RT5665_MIC1_BS_SFT 151581#define RT5665_MIC1_BS_9AV (0x0 << 15)1582#define RT5665_MIC1_BS_75AV (0x1 << 15)1583#define RT5665_MIC2_BS_MASK (0x1 << 14)1584#define RT5665_MIC2_BS_SFT 141585#define RT5665_MIC2_BS_9AV (0x0 << 14)1586#define RT5665_MIC2_BS_75AV (0x1 << 14)1587#define RT5665_MIC1_CLK_MASK (0x1 << 13)1588#define RT5665_MIC1_CLK_SFT 131589#define RT5665_MIC1_CLK_DIS (0x0 << 13)1590#define RT5665_MIC1_CLK_EN (0x1 << 13)1591#define RT5665_MIC2_CLK_MASK (0x1 << 12)1592#define RT5665_MIC2_CLK_SFT 121593#define RT5665_MIC2_CLK_DIS (0x0 << 12)1594#define RT5665_MIC2_CLK_EN (0x1 << 12)1595#define RT5665_MIC1_OVCD_MASK (0x1 << 11)1596#define RT5665_MIC1_OVCD_SFT 111597#define RT5665_MIC1_OVCD_DIS (0x0 << 11)1598#define RT5665_MIC1_OVCD_EN (0x1 << 11)1599#define RT5665_MIC1_OVTH_MASK (0x3 << 9)1600#define RT5665_MIC1_OVTH_SFT 91601#define RT5665_MIC1_OVTH_600UA (0x0 << 9)1602#define RT5665_MIC1_OVTH_1500UA (0x1 << 9)1603#define RT5665_MIC1_OVTH_2000UA (0x2 << 9)1604#define RT5665_MIC2_OVCD_MASK (0x1 << 8)1605#define RT5665_MIC2_OVCD_SFT 81606#define RT5665_MIC2_OVCD_DIS (0x0 << 8)1607#define RT5665_MIC2_OVCD_EN (0x1 << 8)1608#define RT5665_MIC2_OVTH_MASK (0x3 << 6)1609#define RT5665_MIC2_OVTH_SFT 61610#define RT5665_MIC2_OVTH_600UA (0x0 << 6)1611#define RT5665_MIC2_OVTH_1500UA (0x1 << 6)1612#define RT5665_MIC2_OVTH_2000UA (0x2 << 6)1613#define RT5665_PWR_MB_MASK (0x1 << 5)1614#define RT5665_PWR_MB_SFT 51615#define RT5665_PWR_MB_PD (0x0 << 5)1616#define RT5665_PWR_MB_PU (0x1 << 5)1617 1618/* Micbias Control2 (0x94) */1619#define RT5665_PWR_CLK25M_MASK (0x1 << 9)1620#define RT5665_PWR_CLK25M_SFT 91621#define RT5665_PWR_CLK25M_PD (0x0 << 9)1622#define RT5665_PWR_CLK25M_PU (0x1 << 9)1623#define RT5665_PWR_CLK1M_MASK (0x1 << 8)1624#define RT5665_PWR_CLK1M_SFT 81625#define RT5665_PWR_CLK1M_PD (0x0 << 8)1626#define RT5665_PWR_CLK1M_PU (0x1 << 8)1627 1628/* I2S Master Mode Clock Control 1 (0x00a0) */1629#define RT5665_CLK_SRC_MCLK (0x0)1630#define RT5665_CLK_SRC_PLL1 (0x1)1631#define RT5665_CLK_SRC_RCCLK (0x2)1632#define RT5665_I2S_PD_1 (0x0)1633#define RT5665_I2S_PD_2 (0x1)1634#define RT5665_I2S_PD_3 (0x2)1635#define RT5665_I2S_PD_4 (0x3)1636#define RT5665_I2S_PD_6 (0x4)1637#define RT5665_I2S_PD_8 (0x5)1638#define RT5665_I2S_PD_12 (0x6)1639#define RT5665_I2S_PD_16 (0x7)1640#define RT5665_I2S2_SRC_MASK (0x3 << 12)1641#define RT5665_I2S2_SRC_SFT 121642#define RT5665_I2S2_M_PD_MASK (0x7 << 8)1643#define RT5665_I2S2_M_PD_SFT 81644#define RT5665_I2S3_SRC_MASK (0x3 << 4)1645#define RT5665_I2S3_SRC_SFT 41646#define RT5665_I2S3_M_PD_MASK (0x7 << 0)1647#define RT5665_I2S3_M_PD_SFT 01648 1649 1650/* EQ Control 1 (0x00b0) */1651#define RT5665_EQ_SRC_DAC (0x0 << 15)1652#define RT5665_EQ_SRC_ADC (0x1 << 15)1653#define RT5665_EQ_UPD (0x1 << 14)1654#define RT5665_EQ_UPD_BIT 141655#define RT5665_EQ_CD_MASK (0x1 << 13)1656#define RT5665_EQ_CD_SFT 131657#define RT5665_EQ_CD_DIS (0x0 << 13)1658#define RT5665_EQ_CD_EN (0x1 << 13)1659#define RT5665_EQ_DITH_MASK (0x3 << 8)1660#define RT5665_EQ_DITH_SFT 81661#define RT5665_EQ_DITH_NOR (0x0 << 8)1662#define RT5665_EQ_DITH_LSB (0x1 << 8)1663#define RT5665_EQ_DITH_LSB_1 (0x2 << 8)1664#define RT5665_EQ_DITH_LSB_2 (0x3 << 8)1665 1666/* IRQ Control 1 (0x00b7) */1667#define RT5665_JD1_1_EN_MASK (0x1 << 15)1668#define RT5665_JD1_1_EN_SFT 151669#define RT5665_JD1_1_DIS (0x0 << 15)1670#define RT5665_JD1_1_EN (0x1 << 15)1671#define RT5665_JD1_2_EN_MASK (0x1 << 12)1672#define RT5665_JD1_2_EN_SFT 121673#define RT5665_JD1_2_DIS (0x0 << 12)1674#define RT5665_JD1_2_EN (0x1 << 12)1675 1676/* IRQ Control 2 (0x00b8) */1677#define RT5665_IL_IRQ_MASK (0x1 << 6)1678#define RT5665_IL_IRQ_DIS (0x0 << 6)1679#define RT5665_IL_IRQ_EN (0x1 << 6)1680 1681/* IRQ Control 5 (0x00ba) */1682#define RT5665_IRQ_JD_EN (0x1 << 3)1683#define RT5665_IRQ_JD_EN_SFT 31684 1685/* GPIO Control 1 (0x00c0) */1686#define RT5665_GP1_PIN_MASK (0x1 << 15)1687#define RT5665_GP1_PIN_SFT 151688#define RT5665_GP1_PIN_GPIO1 (0x0 << 15)1689#define RT5665_GP1_PIN_IRQ (0x1 << 15)1690#define RT5665_GP2_PIN_MASK (0x3 << 13)1691#define RT5665_GP2_PIN_SFT 131692#define RT5665_GP2_PIN_GPIO2 (0x0 << 13)1693#define RT5665_GP2_PIN_BCLK2 (0x1 << 13)1694#define RT5665_GP2_PIN_PDM_SCL (0x2 << 13)1695#define RT5665_GP3_PIN_MASK (0x3 << 11)1696#define RT5665_GP3_PIN_SFT 111697#define RT5665_GP3_PIN_GPIO3 (0x0 << 11)1698#define RT5665_GP3_PIN_LRCK2 (0x1 << 11)1699#define RT5665_GP3_PIN_PDM_SDA (0x2 << 11)1700#define RT5665_GP4_PIN_MASK (0x3 << 9)1701#define RT5665_GP4_PIN_SFT 91702#define RT5665_GP4_PIN_GPIO4 (0x0 << 9)1703#define RT5665_GP4_PIN_DACDAT2_1 (0x1 << 9)1704#define RT5665_GP4_PIN_DMIC1_SDA (0x2 << 9)1705#define RT5665_GP5_PIN_MASK (0x3 << 7)1706#define RT5665_GP5_PIN_SFT 71707#define RT5665_GP5_PIN_GPIO5 (0x0 << 7)1708#define RT5665_GP5_PIN_ADCDAT2_1 (0x1 << 7)1709#define RT5665_GP5_PIN_DMIC2_SDA (0x2 << 7)1710#define RT5665_GP6_PIN_MASK (0x3 << 5)1711#define RT5665_GP6_PIN_SFT 51712#define RT5665_GP6_PIN_GPIO6 (0x0 << 5)1713#define RT5665_GP6_PIN_BCLK3 (0x1 << 5)1714#define RT5665_GP6_PIN_PDM_SCL (0x2 << 5)1715#define RT5665_GP7_PIN_MASK (0x3 << 3)1716#define RT5665_GP7_PIN_SFT 31717#define RT5665_GP7_PIN_GPIO7 (0x0 << 3)1718#define RT5665_GP7_PIN_LRCK3 (0x1 << 3)1719#define RT5665_GP7_PIN_PDM_SDA (0x2 << 3)1720#define RT5665_GP8_PIN_MASK (0x3 << 1)1721#define RT5665_GP8_PIN_SFT 11722#define RT5665_GP8_PIN_GPIO8 (0x0 << 1)1723#define RT5665_GP8_PIN_DACDAT3 (0x1 << 1)1724#define RT5665_GP8_PIN_DMIC2_SCL (0x2 << 1)1725#define RT5665_GP8_PIN_DACDAT2_2 (0x3 << 1)1726 1727 1728/* GPIO Control 2 (0x00c1)*/1729#define RT5665_GP9_PIN_MASK (0x3 << 14)1730#define RT5665_GP9_PIN_SFT 141731#define RT5665_GP9_PIN_GPIO9 (0x0 << 14)1732#define RT5665_GP9_PIN_ADCDAT3 (0x1 << 14)1733#define RT5665_GP9_PIN_DMIC1_SCL (0x2 << 14)1734#define RT5665_GP9_PIN_ADCDAT2_2 (0x3 << 14)1735#define RT5665_GP10_PIN_MASK (0x3 << 12)1736#define RT5665_GP10_PIN_SFT 121737#define RT5665_GP10_PIN_GPIO10 (0x0 << 12)1738#define RT5665_GP10_PIN_ADCDAT1_2 (0x1 << 12)1739#define RT5665_GP10_PIN_LPD (0x2 << 12)1740#define RT5665_GP1_PF_MASK (0x1 << 11)1741#define RT5665_GP1_PF_IN (0x0 << 11)1742#define RT5665_GP1_PF_OUT (0x1 << 11)1743#define RT5665_GP1_OUT_MASK (0x1 << 10)1744#define RT5665_GP1_OUT_H (0x0 << 10)1745#define RT5665_GP1_OUT_L (0x1 << 10)1746#define RT5665_GP2_PF_MASK (0x1 << 9)1747#define RT5665_GP2_PF_IN (0x0 << 9)1748#define RT5665_GP2_PF_OUT (0x1 << 9)1749#define RT5665_GP2_OUT_MASK (0x1 << 8)1750#define RT5665_GP2_OUT_H (0x0 << 8)1751#define RT5665_GP2_OUT_L (0x1 << 8)1752#define RT5665_GP3_PF_MASK (0x1 << 7)1753#define RT5665_GP3_PF_IN (0x0 << 7)1754#define RT5665_GP3_PF_OUT (0x1 << 7)1755#define RT5665_GP3_OUT_MASK (0x1 << 6)1756#define RT5665_GP3_OUT_H (0x0 << 6)1757#define RT5665_GP3_OUT_L (0x1 << 6)1758#define RT5665_GP4_PF_MASK (0x1 << 5)1759#define RT5665_GP4_PF_IN (0x0 << 5)1760#define RT5665_GP4_PF_OUT (0x1 << 5)1761#define RT5665_GP4_OUT_MASK (0x1 << 4)1762#define RT5665_GP4_OUT_H (0x0 << 4)1763#define RT5665_GP4_OUT_L (0x1 << 4)1764#define RT5665_GP5_PF_MASK (0x1 << 3)1765#define RT5665_GP5_PF_IN (0x0 << 3)1766#define RT5665_GP5_PF_OUT (0x1 << 3)1767#define RT5665_GP5_OUT_MASK (0x1 << 2)1768#define RT5665_GP5_OUT_H (0x0 << 2)1769#define RT5665_GP5_OUT_L (0x1 << 2)1770#define RT5665_GP6_PF_MASK (0x1 << 1)1771#define RT5665_GP6_PF_IN (0x0 << 1)1772#define RT5665_GP6_PF_OUT (0x1 << 1)1773#define RT5665_GP6_OUT_MASK (0x1)1774#define RT5665_GP6_OUT_H (0x0)1775#define RT5665_GP6_OUT_L (0x1)1776 1777 1778/* GPIO Control 3 (0x00c2) */1779#define RT5665_GP7_PF_MASK (0x1 << 15)1780#define RT5665_GP7_PF_IN (0x0 << 15)1781#define RT5665_GP7_PF_OUT (0x1 << 15)1782#define RT5665_GP7_OUT_MASK (0x1 << 14)1783#define RT5665_GP7_OUT_H (0x0 << 14)1784#define RT5665_GP7_OUT_L (0x1 << 14)1785#define RT5665_GP8_PF_MASK (0x1 << 13)1786#define RT5665_GP8_PF_IN (0x0 << 13)1787#define RT5665_GP8_PF_OUT (0x1 << 13)1788#define RT5665_GP8_OUT_MASK (0x1 << 12)1789#define RT5665_GP8_OUT_H (0x0 << 12)1790#define RT5665_GP8_OUT_L (0x1 << 12)1791#define RT5665_GP9_PF_MASK (0x1 << 11)1792#define RT5665_GP9_PF_IN (0x0 << 11)1793#define RT5665_GP9_PF_OUT (0x1 << 11)1794#define RT5665_GP9_OUT_MASK (0x1 << 10)1795#define RT5665_GP9_OUT_H (0x0 << 10)1796#define RT5665_GP9_OUT_L (0x1 << 10)1797#define RT5665_GP10_PF_MASK (0x1 << 9)1798#define RT5665_GP10_PF_IN (0x0 << 9)1799#define RT5665_GP10_PF_OUT (0x1 << 9)1800#define RT5665_GP10_OUT_MASK (0x1 << 8)1801#define RT5665_GP10_OUT_H (0x0 << 8)1802#define RT5665_GP10_OUT_L (0x1 << 8)1803#define RT5665_GP11_PF_MASK (0x1 << 7)1804#define RT5665_GP11_PF_IN (0x0 << 7)1805#define RT5665_GP11_PF_OUT (0x1 << 7)1806#define RT5665_GP11_OUT_MASK (0x1 << 6)1807#define RT5665_GP11_OUT_H (0x0 << 6)1808#define RT5665_GP11_OUT_L (0x1 << 6)1809 1810/* Soft volume and zero cross control 1 (0x00d9) */1811#define RT5665_SV_MASK (0x1 << 15)1812#define RT5665_SV_SFT 151813#define RT5665_SV_DIS (0x0 << 15)1814#define RT5665_SV_EN (0x1 << 15)1815#define RT5665_OUT_SV_MASK (0x1 << 13)1816#define RT5665_OUT_SV_SFT 131817#define RT5665_OUT_SV_DIS (0x0 << 13)1818#define RT5665_OUT_SV_EN (0x1 << 13)1819#define RT5665_HP_SV_MASK (0x1 << 12)1820#define RT5665_HP_SV_SFT 121821#define RT5665_HP_SV_DIS (0x0 << 12)1822#define RT5665_HP_SV_EN (0x1 << 12)1823#define RT5665_ZCD_DIG_MASK (0x1 << 11)1824#define RT5665_ZCD_DIG_SFT 111825#define RT5665_ZCD_DIG_DIS (0x0 << 11)1826#define RT5665_ZCD_DIG_EN (0x1 << 11)1827#define RT5665_ZCD_MASK (0x1 << 10)1828#define RT5665_ZCD_SFT 101829#define RT5665_ZCD_PD (0x0 << 10)1830#define RT5665_ZCD_PU (0x1 << 10)1831#define RT5665_SV_DLY_MASK (0xf)1832#define RT5665_SV_DLY_SFT 01833 1834/* Soft volume and zero cross control 2 (0x00da) */1835#define RT5665_ZCD_HP_MASK (0x1 << 15)1836#define RT5665_ZCD_HP_SFT 151837#define RT5665_ZCD_HP_DIS (0x0 << 15)1838#define RT5665_ZCD_HP_EN (0x1 << 15)1839 1840/* 4 Button Inline Command Control 2 (0x00e0) */1841#define RT5665_4BTN_IL_MASK (0x1 << 15)1842#define RT5665_4BTN_IL_EN (0x1 << 15)1843#define RT5665_4BTN_IL_DIS (0x0 << 15)1844#define RT5665_4BTN_IL_RST_MASK (0x1 << 14)1845#define RT5665_4BTN_IL_NOR (0x1 << 14)1846#define RT5665_4BTN_IL_RST (0x0 << 14)1847 1848/* Analog JD Control 1 (0x00f0) */1849#define RT5665_JD1_MODE_MASK (0x3 << 0)1850#define RT5665_JD1_MODE_0 (0x0 << 0)1851#define RT5665_JD1_MODE_1 (0x1 << 0)1852#define RT5665_JD1_MODE_2 (0x2 << 0)1853 1854/* Jack Detect Control 3 (0x00f8) */1855#define RT5665_JD_TRI_HPO_SEL_MASK (0x7)1856#define RT5665_JD_TRI_HPO_SEL_SFT (0)1857#define RT5665_JD_HPO_GPIO_JD1 (0x0)1858#define RT5665_JD_HPO_JD1_1 (0x1)1859#define RT5665_JD_HPO_JD1_2 (0x2)1860#define RT5665_JD_HPO_JD2 (0x3)1861#define RT5665_JD_HPO_GPIO_JD2 (0x4)1862#define RT5665_JD_HPO_JD3 (0x5)1863#define RT5665_JD_HPO_JD_D (0x6)1864 1865/* Digital Misc Control (0x00fa) */1866#define RT5665_AM_MASK (0x1 << 7)1867#define RT5665_AM_EN (0x1 << 7)1868#define RT5665_AM_DIS (0x1 << 7)1869#define RT5665_DIG_GATE_CTRL 0x11870#define RT5665_DIG_GATE_CTRL_SFT (0)1871 1872/* Chopper and Clock control for ADC (0x011c)*/1873#define RT5665_M_RF_DIG_MASK (0x1 << 12)1874#define RT5665_M_RF_DIG_SFT 121875#define RT5665_M_RI_DIG (0x1 << 11)1876 1877/* Chopper and Clock control for DAC (0x013a)*/1878#define RT5665_CKXEN_DAC1_MASK (0x1 << 13)1879#define RT5665_CKXEN_DAC1_SFT 131880#define RT5665_CKGEN_DAC1_MASK (0x1 << 12)1881#define RT5665_CKGEN_DAC1_SFT 121882#define RT5665_CKXEN_DAC2_MASK (0x1 << 5)1883#define RT5665_CKXEN_DAC2_SFT 51884#define RT5665_CKGEN_DAC2_MASK (0x1 << 4)1885#define RT5665_CKGEN_DAC2_SFT 41886 1887/* Chopper and Clock control for ADC (0x013b)*/1888#define RT5665_CKXEN_ADC1_MASK (0x1 << 13)1889#define RT5665_CKXEN_ADC1_SFT 131890#define RT5665_CKGEN_ADC1_MASK (0x1 << 12)1891#define RT5665_CKGEN_ADC1_SFT 121892#define RT5665_CKXEN_ADC2_MASK (0x1 << 5)1893#define RT5665_CKXEN_ADC2_SFT 51894#define RT5665_CKGEN_ADC2_MASK (0x1 << 4)1895#define RT5665_CKGEN_ADC2_SFT 41896 1897/* Volume test (0x013f)*/1898#define RT5665_SEL_CLK_VOL_MASK (0x1 << 15)1899#define RT5665_SEL_CLK_VOL_EN (0x1 << 15)1900#define RT5665_SEL_CLK_VOL_DIS (0x0 << 15)1901 1902/* Test Mode Control 1 (0x0145) */1903#define RT5665_AD2DA_LB_MASK (0x1 << 9)1904#define RT5665_AD2DA_LB_SFT 91905 1906/* Stereo Noise Gate Control 1 (0x0160) */1907#define RT5665_NG2_EN_MASK (0x1 << 15)1908#define RT5665_NG2_EN (0x1 << 15)1909#define RT5665_NG2_DIS (0x0 << 15)1910 1911/* Stereo1 DAC Silence Detection Control (0x0190) */1912#define RT5665_DEB_STO_DAC_MASK (0x7 << 4)1913#define RT5665_DEB_80_MS (0x0 << 4)1914 1915/* SAR ADC Inline Command Control 1 (0x0210) */1916#define RT5665_SAR_BUTT_DET_MASK (0x1 << 15)1917#define RT5665_SAR_BUTT_DET_EN (0x1 << 15)1918#define RT5665_SAR_BUTT_DET_DIS (0x0 << 15)1919#define RT5665_SAR_BUTDET_MODE_MASK (0x1 << 14)1920#define RT5665_SAR_BUTDET_POW_SAV (0x1 << 14)1921#define RT5665_SAR_BUTDET_POW_NORM (0x0 << 14)1922#define RT5665_SAR_BUTDET_RST_MASK (0x1 << 13)1923#define RT5665_SAR_BUTDET_RST_NORMAL (0x1 << 13)1924#define RT5665_SAR_BUTDET_RST (0x0 << 13)1925#define RT5665_SAR_POW_MASK (0x1 << 12)1926#define RT5665_SAR_POW_EN (0x1 << 12)1927#define RT5665_SAR_POW_DIS (0x0 << 12)1928#define RT5665_SAR_RST_MASK (0x1 << 11)1929#define RT5665_SAR_RST_NORMAL (0x1 << 11)1930#define RT5665_SAR_RST (0x0 << 11)1931#define RT5665_SAR_BYPASS_MASK (0x1 << 10)1932#define RT5665_SAR_BYPASS_EN (0x1 << 10)1933#define RT5665_SAR_BYPASS_DIS (0x0 << 10)1934#define RT5665_SAR_SEL_MB1_MASK (0x1 << 9)1935#define RT5665_SAR_SEL_MB1_SEL (0x1 << 9)1936#define RT5665_SAR_SEL_MB1_NOSEL (0x0 << 9)1937#define RT5665_SAR_SEL_MB2_MASK (0x1 << 8)1938#define RT5665_SAR_SEL_MB2_SEL (0x1 << 8)1939#define RT5665_SAR_SEL_MB2_NOSEL (0x0 << 8)1940#define RT5665_SAR_SEL_MODE_MASK (0x1 << 7)1941#define RT5665_SAR_SEL_MODE_CMP (0x1 << 7)1942#define RT5665_SAR_SEL_MODE_ADC (0x0 << 7)1943#define RT5665_SAR_SEL_MB1_MB2_MASK (0x1 << 5)1944#define RT5665_SAR_SEL_MB1_MB2_AUTO (0x1 << 5)1945#define RT5665_SAR_SEL_MB1_MB2_MANU (0x0 << 5)1946#define RT5665_SAR_SEL_SIGNAL_MASK (0x1 << 4)1947#define RT5665_SAR_SEL_SIGNAL_AUTO (0x1 << 4)1948#define RT5665_SAR_SEL_SIGNAL_MANU (0x0 << 4)1949 1950/* System Clock Source */1951enum {1952 RT5665_SCLK_S_MCLK,1953 RT5665_SCLK_S_PLL1,1954 RT5665_SCLK_S_RCCLK,1955};1956 1957/* PLL1 Source */1958enum {1959 RT5665_PLL1_S_MCLK,1960 RT5665_PLL1_S_BCLK1,1961 RT5665_PLL1_S_BCLK2,1962 RT5665_PLL1_S_BCLK3,1963 RT5665_PLL1_S_BCLK4,1964};1965 1966enum {1967 RT5665_AIF1_1,1968 RT5665_AIF1_2,1969 RT5665_AIF2_1,1970 RT5665_AIF2_2,1971 RT5665_AIF3,1972 RT5665_AIFS1973};1974 1975enum {1976 CODEC_5665,1977 CODEC_5666,1978};1979 1980/* filter mask */1981enum {1982 RT5665_DA_STEREO1_FILTER = 0x1,1983 RT5665_DA_STEREO2_FILTER = (0x1 << 1),1984 RT5665_DA_MONO_L_FILTER = (0x1 << 2),1985 RT5665_DA_MONO_R_FILTER = (0x1 << 3),1986 RT5665_AD_STEREO1_FILTER = (0x1 << 4),1987 RT5665_AD_STEREO2_FILTER = (0x1 << 5),1988 RT5665_AD_MONO_L_FILTER = (0x1 << 6),1989 RT5665_AD_MONO_R_FILTER = (0x1 << 7),1990};1991 1992enum {1993 RT5665_CLK_SEL_SYS,1994 RT5665_CLK_SEL_I2S1_ASRC,1995 RT5665_CLK_SEL_I2S2_ASRC,1996 RT5665_CLK_SEL_I2S3_ASRC,1997 RT5665_CLK_SEL_SYS2,1998 RT5665_CLK_SEL_SYS3,1999 RT5665_CLK_SEL_SYS4,2000};2001 2002int rt5665_sel_asrc_clk_src(struct snd_soc_component *component,2003 unsigned int filter_mask, unsigned int clk_src);2004 2005#endif /* __RT5665_H__ */2006