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1/* SPDX-License-Identifier: GPL-2.0-only */2/*3 * rt5668.h -- RT5668/RT5658 ALSA SoC audio driver4 *5 * Copyright 2018 Realtek Microelectronics6 * Author: Bard Liao <bardliao@realtek.com>7 */8 9#ifndef __RT5668_H__10#define __RT5668_H__11 12#include <sound/rt5668.h>13 14#define DEVICE_ID 0x653015 16/* Info */17#define RT5668_RESET 0x000018#define RT5668_VERSION_ID 0x00fd19#define RT5668_VENDOR_ID 0x00fe20#define RT5668_DEVICE_ID 0x00ff21/* I/O - Output */22#define RT5668_HP_CTRL_1 0x000223#define RT5668_HP_CTRL_2 0x000324#define RT5668_HPL_GAIN 0x000525#define RT5668_HPR_GAIN 0x000626 27#define RT5668_I2C_CTRL 0x000828 29/* I/O - Input */30#define RT5668_CBJ_BST_CTRL 0x000b31#define RT5668_CBJ_CTRL_1 0x001032#define RT5668_CBJ_CTRL_2 0x001133#define RT5668_CBJ_CTRL_3 0x001234#define RT5668_CBJ_CTRL_4 0x001335#define RT5668_CBJ_CTRL_5 0x001436#define RT5668_CBJ_CTRL_6 0x001537#define RT5668_CBJ_CTRL_7 0x001638/* I/O - ADC/DAC/DMIC */39#define RT5668_DAC1_DIG_VOL 0x001940#define RT5668_STO1_ADC_DIG_VOL 0x001c41#define RT5668_STO1_ADC_BOOST 0x001f42#define RT5668_HP_IMP_GAIN_1 0x002243#define RT5668_HP_IMP_GAIN_2 0x002344/* Mixer - D-D */45#define RT5668_SIDETONE_CTRL 0x002446#define RT5668_STO1_ADC_MIXER 0x002647#define RT5668_AD_DA_MIXER 0x002948#define RT5668_STO1_DAC_MIXER 0x002a49#define RT5668_A_DAC1_MUX 0x002b50#define RT5668_DIG_INF2_DATA 0x003051/* Mixer - ADC */52#define RT5668_REC_MIXER 0x003c53#define RT5668_CAL_REC 0x004454#define RT5668_ALC_BACK_GAIN 0x004955/* Power */56#define RT5668_PWR_DIG_1 0x006157#define RT5668_PWR_DIG_2 0x006258#define RT5668_PWR_ANLG_1 0x006359#define RT5668_PWR_ANLG_2 0x006460#define RT5668_PWR_ANLG_3 0x006561#define RT5668_PWR_MIXER 0x006662#define RT5668_PWR_VOL 0x006763/* Clock Detect */64#define RT5668_CLK_DET 0x006b65/* Filter Auto Reset */66#define RT5668_RESET_LPF_CTRL 0x006c67#define RT5668_RESET_HPF_CTRL 0x006d68/* DMIC */69#define RT5668_DMIC_CTRL_1 0x006e70/* Format - ADC/DAC */71#define RT5668_I2S1_SDP 0x007072#define RT5668_I2S2_SDP 0x007173#define RT5668_ADDA_CLK_1 0x007374#define RT5668_ADDA_CLK_2 0x007475#define RT5668_I2S1_F_DIV_CTRL_1 0x007576#define RT5668_I2S1_F_DIV_CTRL_2 0x007677/* Format - TDM Control */78#define RT5668_TDM_CTRL 0x007979#define RT5668_TDM_ADDA_CTRL_1 0x007a80#define RT5668_TDM_ADDA_CTRL_2 0x007b81#define RT5668_DATA_SEL_CTRL_1 0x007c82#define RT5668_TDM_TCON_CTRL 0x007e83/* Function - Analog */84#define RT5668_GLB_CLK 0x008085#define RT5668_PLL_CTRL_1 0x008186#define RT5668_PLL_CTRL_2 0x008287#define RT5668_PLL_TRACK_1 0x008388#define RT5668_PLL_TRACK_2 0x008489#define RT5668_PLL_TRACK_3 0x008590#define RT5668_PLL_TRACK_4 0x008691#define RT5668_PLL_TRACK_5 0x008792#define RT5668_PLL_TRACK_6 0x008893#define RT5668_PLL_TRACK_11 0x008c94#define RT5668_SDW_REF_CLK 0x008d95#define RT5668_DEPOP_1 0x008e96#define RT5668_DEPOP_2 0x008f97#define RT5668_HP_CHARGE_PUMP_1 0x009198#define RT5668_HP_CHARGE_PUMP_2 0x009299#define RT5668_MICBIAS_1 0x0093100#define RT5668_MICBIAS_2 0x0094101#define RT5668_PLL_TRACK_12 0x0098102#define RT5668_PLL_TRACK_14 0x009a103#define RT5668_PLL2_CTRL_1 0x009b104#define RT5668_PLL2_CTRL_2 0x009c105#define RT5668_PLL2_CTRL_3 0x009d106#define RT5668_PLL2_CTRL_4 0x009e107#define RT5668_RC_CLK_CTRL 0x009f108#define RT5668_I2S_M_CLK_CTRL_1 0x00a0109#define RT5668_I2S2_F_DIV_CTRL_1 0x00a3110#define RT5668_I2S2_F_DIV_CTRL_2 0x00a4111/* Function - Digital */112#define RT5668_EQ_CTRL_1 0x00ae113#define RT5668_EQ_CTRL_2 0x00af114#define RT5668_IRQ_CTRL_1 0x00b6115#define RT5668_IRQ_CTRL_2 0x00b7116#define RT5668_IRQ_CTRL_3 0x00b8117#define RT5668_IRQ_CTRL_4 0x00b9118#define RT5668_INT_ST_1 0x00be119#define RT5668_GPIO_CTRL_1 0x00c0120#define RT5668_GPIO_CTRL_2 0x00c1121#define RT5668_GPIO_CTRL_3 0x00c2122#define RT5668_HP_AMP_DET_CTRL_1 0x00d0123#define RT5668_HP_AMP_DET_CTRL_2 0x00d1124#define RT5668_MID_HP_AMP_DET 0x00d2125#define RT5668_LOW_HP_AMP_DET 0x00d3126#define RT5668_DELAY_BUF_CTRL 0x00d4127#define RT5668_SV_ZCD_1 0x00d9128#define RT5668_SV_ZCD_2 0x00da129#define RT5668_IL_CMD_1 0x00db130#define RT5668_IL_CMD_2 0x00dc131#define RT5668_IL_CMD_3 0x00dd132#define RT5668_IL_CMD_4 0x00de133#define RT5668_IL_CMD_5 0x00df134#define RT5668_IL_CMD_6 0x00e0135#define RT5668_4BTN_IL_CMD_1 0x00e2136#define RT5668_4BTN_IL_CMD_2 0x00e3137#define RT5668_4BTN_IL_CMD_3 0x00e4138#define RT5668_4BTN_IL_CMD_4 0x00e5139#define RT5668_4BTN_IL_CMD_5 0x00e6140#define RT5668_4BTN_IL_CMD_6 0x00e7141#define RT5668_4BTN_IL_CMD_7 0x00e8142 143#define RT5668_ADC_STO1_HP_CTRL_1 0x00ea144#define RT5668_ADC_STO1_HP_CTRL_2 0x00eb145#define RT5668_AJD1_CTRL 0x00f0146#define RT5668_JD1_THD 0x00f1147#define RT5668_JD2_THD 0x00f2148#define RT5668_JD_CTRL_1 0x00f6149/* General Control */150#define RT5668_DUMMY_1 0x00fa151#define RT5668_DUMMY_2 0x00fb152#define RT5668_DUMMY_3 0x00fc153 154#define RT5668_DAC_ADC_DIG_VOL1 0x0100155#define RT5668_BIAS_CUR_CTRL_2 0x010b156#define RT5668_BIAS_CUR_CTRL_3 0x010c157#define RT5668_BIAS_CUR_CTRL_4 0x010d158#define RT5668_BIAS_CUR_CTRL_5 0x010e159#define RT5668_BIAS_CUR_CTRL_6 0x010f160#define RT5668_BIAS_CUR_CTRL_7 0x0110161#define RT5668_BIAS_CUR_CTRL_8 0x0111162#define RT5668_BIAS_CUR_CTRL_9 0x0112163#define RT5668_BIAS_CUR_CTRL_10 0x0113164#define RT5668_VREF_REC_OP_FB_CAP_CTRL 0x0117165#define RT5668_CHARGE_PUMP_1 0x0125166#define RT5668_DIG_IN_CTRL_1 0x0132167#define RT5668_PAD_DRIVING_CTRL 0x0136168#define RT5668_SOFT_RAMP_DEPOP 0x0138169#define RT5668_CHOP_DAC 0x013a170#define RT5668_CHOP_ADC 0x013b171#define RT5668_CALIB_ADC_CTRL 0x013c172#define RT5668_VOL_TEST 0x013f173#define RT5668_SPKVDD_DET_STA 0x0142174#define RT5668_TEST_MODE_CTRL_1 0x0145175#define RT5668_TEST_MODE_CTRL_2 0x0146176#define RT5668_TEST_MODE_CTRL_3 0x0147177#define RT5668_TEST_MODE_CTRL_4 0x0148178#define RT5668_TEST_MODE_CTRL_5 0x0149179#define RT5668_PLL1_INTERNAL 0x0150180#define RT5668_PLL2_INTERNAL 0x0151181#define RT5668_STO_NG2_CTRL_1 0x0160182#define RT5668_STO_NG2_CTRL_2 0x0161183#define RT5668_STO_NG2_CTRL_3 0x0162184#define RT5668_STO_NG2_CTRL_4 0x0163185#define RT5668_STO_NG2_CTRL_5 0x0164186#define RT5668_STO_NG2_CTRL_6 0x0165187#define RT5668_STO_NG2_CTRL_7 0x0166188#define RT5668_STO_NG2_CTRL_8 0x0167189#define RT5668_STO_NG2_CTRL_9 0x0168190#define RT5668_STO_NG2_CTRL_10 0x0169191#define RT5668_STO1_DAC_SIL_DET 0x0190192#define RT5668_SIL_PSV_CTRL1 0x0194193#define RT5668_SIL_PSV_CTRL2 0x0195194#define RT5668_SIL_PSV_CTRL3 0x0197195#define RT5668_SIL_PSV_CTRL4 0x0198196#define RT5668_SIL_PSV_CTRL5 0x0199197#define RT5668_HP_IMP_SENS_CTRL_01 0x01af198#define RT5668_HP_IMP_SENS_CTRL_02 0x01b0199#define RT5668_HP_IMP_SENS_CTRL_03 0x01b1200#define RT5668_HP_IMP_SENS_CTRL_04 0x01b2201#define RT5668_HP_IMP_SENS_CTRL_05 0x01b3202#define RT5668_HP_IMP_SENS_CTRL_06 0x01b4203#define RT5668_HP_IMP_SENS_CTRL_07 0x01b5204#define RT5668_HP_IMP_SENS_CTRL_08 0x01b6205#define RT5668_HP_IMP_SENS_CTRL_09 0x01b7206#define RT5668_HP_IMP_SENS_CTRL_10 0x01b8207#define RT5668_HP_IMP_SENS_CTRL_11 0x01b9208#define RT5668_HP_IMP_SENS_CTRL_12 0x01ba209#define RT5668_HP_IMP_SENS_CTRL_13 0x01bb210#define RT5668_HP_IMP_SENS_CTRL_14 0x01bc211#define RT5668_HP_IMP_SENS_CTRL_15 0x01bd212#define RT5668_HP_IMP_SENS_CTRL_16 0x01be213#define RT5668_HP_IMP_SENS_CTRL_17 0x01bf214#define RT5668_HP_IMP_SENS_CTRL_18 0x01c0215#define RT5668_HP_IMP_SENS_CTRL_19 0x01c1216#define RT5668_HP_IMP_SENS_CTRL_20 0x01c2217#define RT5668_HP_IMP_SENS_CTRL_21 0x01c3218#define RT5668_HP_IMP_SENS_CTRL_22 0x01c4219#define RT5668_HP_IMP_SENS_CTRL_23 0x01c5220#define RT5668_HP_IMP_SENS_CTRL_24 0x01c6221#define RT5668_HP_IMP_SENS_CTRL_25 0x01c7222#define RT5668_HP_IMP_SENS_CTRL_26 0x01c8223#define RT5668_HP_IMP_SENS_CTRL_27 0x01c9224#define RT5668_HP_IMP_SENS_CTRL_28 0x01ca225#define RT5668_HP_IMP_SENS_CTRL_29 0x01cb226#define RT5668_HP_IMP_SENS_CTRL_30 0x01cc227#define RT5668_HP_IMP_SENS_CTRL_31 0x01cd228#define RT5668_HP_IMP_SENS_CTRL_32 0x01ce229#define RT5668_HP_IMP_SENS_CTRL_33 0x01cf230#define RT5668_HP_IMP_SENS_CTRL_34 0x01d0231#define RT5668_HP_IMP_SENS_CTRL_35 0x01d1232#define RT5668_HP_IMP_SENS_CTRL_36 0x01d2233#define RT5668_HP_IMP_SENS_CTRL_37 0x01d3234#define RT5668_HP_IMP_SENS_CTRL_38 0x01d4235#define RT5668_HP_IMP_SENS_CTRL_39 0x01d5236#define RT5668_HP_IMP_SENS_CTRL_40 0x01d6237#define RT5668_HP_IMP_SENS_CTRL_41 0x01d7238#define RT5668_HP_IMP_SENS_CTRL_42 0x01d8239#define RT5668_HP_IMP_SENS_CTRL_43 0x01d9240#define RT5668_HP_LOGIC_CTRL_1 0x01da241#define RT5668_HP_LOGIC_CTRL_2 0x01db242#define RT5668_HP_LOGIC_CTRL_3 0x01dc243#define RT5668_HP_CALIB_CTRL_1 0x01de244#define RT5668_HP_CALIB_CTRL_2 0x01df245#define RT5668_HP_CALIB_CTRL_3 0x01e0246#define RT5668_HP_CALIB_CTRL_4 0x01e1247#define RT5668_HP_CALIB_CTRL_5 0x01e2248#define RT5668_HP_CALIB_CTRL_6 0x01e3249#define RT5668_HP_CALIB_CTRL_7 0x01e4250#define RT5668_HP_CALIB_CTRL_9 0x01e6251#define RT5668_HP_CALIB_CTRL_10 0x01e7252#define RT5668_HP_CALIB_CTRL_11 0x01e8253#define RT5668_HP_CALIB_STA_1 0x01ea254#define RT5668_HP_CALIB_STA_2 0x01eb255#define RT5668_HP_CALIB_STA_3 0x01ec256#define RT5668_HP_CALIB_STA_4 0x01ed257#define RT5668_HP_CALIB_STA_5 0x01ee258#define RT5668_HP_CALIB_STA_6 0x01ef259#define RT5668_HP_CALIB_STA_7 0x01f0260#define RT5668_HP_CALIB_STA_8 0x01f1261#define RT5668_HP_CALIB_STA_9 0x01f2262#define RT5668_HP_CALIB_STA_10 0x01f3263#define RT5668_HP_CALIB_STA_11 0x01f4264#define RT5668_SAR_IL_CMD_1 0x0210265#define RT5668_SAR_IL_CMD_2 0x0211266#define RT5668_SAR_IL_CMD_3 0x0212267#define RT5668_SAR_IL_CMD_4 0x0213268#define RT5668_SAR_IL_CMD_5 0x0214269#define RT5668_SAR_IL_CMD_6 0x0215270#define RT5668_SAR_IL_CMD_7 0x0216271#define RT5668_SAR_IL_CMD_8 0x0217272#define RT5668_SAR_IL_CMD_9 0x0218273#define RT5668_SAR_IL_CMD_10 0x0219274#define RT5668_SAR_IL_CMD_11 0x021a275#define RT5668_SAR_IL_CMD_12 0x021b276#define RT5668_SAR_IL_CMD_13 0x021c277#define RT5668_EFUSE_CTRL_1 0x0250278#define RT5668_EFUSE_CTRL_2 0x0251279#define RT5668_EFUSE_CTRL_3 0x0252280#define RT5668_EFUSE_CTRL_4 0x0253281#define RT5668_EFUSE_CTRL_5 0x0254282#define RT5668_EFUSE_CTRL_6 0x0255283#define RT5668_EFUSE_CTRL_7 0x0256284#define RT5668_EFUSE_CTRL_8 0x0257285#define RT5668_EFUSE_CTRL_9 0x0258286#define RT5668_EFUSE_CTRL_10 0x0259287#define RT5668_EFUSE_CTRL_11 0x025a288#define RT5668_JD_TOP_VC_VTRL 0x0270289#define RT5668_DRC1_CTRL_0 0x02ff290#define RT5668_DRC1_CTRL_1 0x0300291#define RT5668_DRC1_CTRL_2 0x0301292#define RT5668_DRC1_CTRL_3 0x0302293#define RT5668_DRC1_CTRL_4 0x0303294#define RT5668_DRC1_CTRL_5 0x0304295#define RT5668_DRC1_CTRL_6 0x0305296#define RT5668_DRC1_HARD_LMT_CTRL_1 0x0306297#define RT5668_DRC1_HARD_LMT_CTRL_2 0x0307298#define RT5668_DRC1_PRIV_1 0x0310299#define RT5668_DRC1_PRIV_2 0x0311300#define RT5668_DRC1_PRIV_3 0x0312301#define RT5668_DRC1_PRIV_4 0x0313302#define RT5668_DRC1_PRIV_5 0x0314303#define RT5668_DRC1_PRIV_6 0x0315304#define RT5668_DRC1_PRIV_7 0x0316305#define RT5668_DRC1_PRIV_8 0x0317306#define RT5668_EQ_AUTO_RCV_CTRL1 0x03c0307#define RT5668_EQ_AUTO_RCV_CTRL2 0x03c1308#define RT5668_EQ_AUTO_RCV_CTRL3 0x03c2309#define RT5668_EQ_AUTO_RCV_CTRL4 0x03c3310#define RT5668_EQ_AUTO_RCV_CTRL5 0x03c4311#define RT5668_EQ_AUTO_RCV_CTRL6 0x03c5312#define RT5668_EQ_AUTO_RCV_CTRL7 0x03c6313#define RT5668_EQ_AUTO_RCV_CTRL8 0x03c7314#define RT5668_EQ_AUTO_RCV_CTRL9 0x03c8315#define RT5668_EQ_AUTO_RCV_CTRL10 0x03c9316#define RT5668_EQ_AUTO_RCV_CTRL11 0x03ca317#define RT5668_EQ_AUTO_RCV_CTRL12 0x03cb318#define RT5668_EQ_AUTO_RCV_CTRL13 0x03cc319#define RT5668_ADC_L_EQ_LPF1_A1 0x03d0320#define RT5668_R_EQ_LPF1_A1 0x03d1321#define RT5668_L_EQ_LPF1_H0 0x03d2322#define RT5668_R_EQ_LPF1_H0 0x03d3323#define RT5668_L_EQ_BPF1_A1 0x03d4324#define RT5668_R_EQ_BPF1_A1 0x03d5325#define RT5668_L_EQ_BPF1_A2 0x03d6326#define RT5668_R_EQ_BPF1_A2 0x03d7327#define RT5668_L_EQ_BPF1_H0 0x03d8328#define RT5668_R_EQ_BPF1_H0 0x03d9329#define RT5668_L_EQ_BPF2_A1 0x03da330#define RT5668_R_EQ_BPF2_A1 0x03db331#define RT5668_L_EQ_BPF2_A2 0x03dc332#define RT5668_R_EQ_BPF2_A2 0x03dd333#define RT5668_L_EQ_BPF2_H0 0x03de334#define RT5668_R_EQ_BPF2_H0 0x03df335#define RT5668_L_EQ_BPF3_A1 0x03e0336#define RT5668_R_EQ_BPF3_A1 0x03e1337#define RT5668_L_EQ_BPF3_A2 0x03e2338#define RT5668_R_EQ_BPF3_A2 0x03e3339#define RT5668_L_EQ_BPF3_H0 0x03e4340#define RT5668_R_EQ_BPF3_H0 0x03e5341#define RT5668_L_EQ_BPF4_A1 0x03e6342#define RT5668_R_EQ_BPF4_A1 0x03e7343#define RT5668_L_EQ_BPF4_A2 0x03e8344#define RT5668_R_EQ_BPF4_A2 0x03e9345#define RT5668_L_EQ_BPF4_H0 0x03ea346#define RT5668_R_EQ_BPF4_H0 0x03eb347#define RT5668_L_EQ_HPF1_A1 0x03ec348#define RT5668_R_EQ_HPF1_A1 0x03ed349#define RT5668_L_EQ_HPF1_H0 0x03ee350#define RT5668_R_EQ_HPF1_H0 0x03ef351#define RT5668_L_EQ_PRE_VOL 0x03f0352#define RT5668_R_EQ_PRE_VOL 0x03f1353#define RT5668_L_EQ_POST_VOL 0x03f2354#define RT5668_R_EQ_POST_VOL 0x03f3355#define RT5668_I2C_MODE 0xffff356 357 358/* global definition */359#define RT5668_L_MUTE (0x1 << 15)360#define RT5668_L_MUTE_SFT 15361#define RT5668_VOL_L_MUTE (0x1 << 14)362#define RT5668_VOL_L_SFT 14363#define RT5668_R_MUTE (0x1 << 7)364#define RT5668_R_MUTE_SFT 7365#define RT5668_VOL_R_MUTE (0x1 << 6)366#define RT5668_VOL_R_SFT 6367#define RT5668_L_VOL_MASK (0x3f << 8)368#define RT5668_L_VOL_SFT 8369#define RT5668_R_VOL_MASK (0x3f)370#define RT5668_R_VOL_SFT 0371 372/*Headphone Amp L/R Analog Gain and Digital NG2 Gain Control (0x0005 0x0006)*/373#define RT5668_G_HP (0xf << 8)374#define RT5668_G_HP_SFT 8375#define RT5668_G_STO_DA_DMIX (0xf)376#define RT5668_G_STO_DA_SFT 0377 378/* CBJ Control (0x000b) */379#define RT5668_BST_CBJ_MASK (0xf << 8)380#define RT5668_BST_CBJ_SFT 8381 382/* Embeeded Jack and Type Detection Control 1 (0x0010) */383#define RT5668_EMB_JD_EN (0x1 << 15)384#define RT5668_EMB_JD_EN_SFT 15385#define RT5668_EMB_JD_RST (0x1 << 14)386#define RT5668_JD_MODE (0x1 << 13)387#define RT5668_JD_MODE_SFT 13388#define RT5668_DET_TYPE (0x1 << 12)389#define RT5668_DET_TYPE_SFT 12390#define RT5668_POLA_EXT_JD_MASK (0x1 << 11)391#define RT5668_POLA_EXT_JD_LOW (0x1 << 11)392#define RT5668_POLA_EXT_JD_HIGH (0x0 << 11)393#define RT5668_EXT_JD_DIG (0x1 << 9)394#define RT5668_POL_FAST_OFF_MASK (0x1 << 8)395#define RT5668_POL_FAST_OFF_HIGH (0x1 << 8)396#define RT5668_POL_FAST_OFF_LOW (0x0 << 8)397#define RT5668_FAST_OFF_MASK (0x1 << 7)398#define RT5668_FAST_OFF_EN (0x1 << 7)399#define RT5668_FAST_OFF_DIS (0x0 << 7)400#define RT5668_VREF_POW_MASK (0x1 << 6)401#define RT5668_VREF_POW_FSM (0x0 << 6)402#define RT5668_VREF_POW_REG (0x1 << 6)403#define RT5668_MB1_PATH_MASK (0x1 << 5)404#define RT5668_CTRL_MB1_REG (0x1 << 5)405#define RT5668_CTRL_MB1_FSM (0x0 << 5)406#define RT5668_MB2_PATH_MASK (0x1 << 4)407#define RT5668_CTRL_MB2_REG (0x1 << 4)408#define RT5668_CTRL_MB2_FSM (0x0 << 4)409#define RT5668_TRIG_JD_MASK (0x1 << 3)410#define RT5668_TRIG_JD_HIGH (0x1 << 3)411#define RT5668_TRIG_JD_LOW (0x0 << 3)412#define RT5668_MIC_CAP_MASK (0x1 << 1)413#define RT5668_MIC_CAP_HS (0x1 << 1)414#define RT5668_MIC_CAP_HP (0x0 << 1)415#define RT5668_MIC_CAP_SRC_MASK (0x1)416#define RT5668_MIC_CAP_SRC_REG (0x1)417#define RT5668_MIC_CAP_SRC_ANA (0x0)418 419/* Embeeded Jack and Type Detection Control 2 (0x0011) */420#define RT5668_EXT_JD_SRC (0x7 << 4)421#define RT5668_EXT_JD_SRC_SFT 4422#define RT5668_EXT_JD_SRC_GPIO_JD1 (0x0 << 4)423#define RT5668_EXT_JD_SRC_GPIO_JD2 (0x1 << 4)424#define RT5668_EXT_JD_SRC_JDH (0x2 << 4)425#define RT5668_EXT_JD_SRC_JDL (0x3 << 4)426#define RT5668_EXT_JD_SRC_MANUAL (0x4 << 4)427#define RT5668_JACK_TYPE_MASK (0x3)428 429/* Combo Jack and Type Detection Control 3 (0x0012) */430#define RT5668_CBJ_IN_BUF_EN (0x1 << 7)431 432/* Combo Jack and Type Detection Control 4 (0x0013) */433#define RT5668_SEL_SHT_MID_TON_MASK (0x3 << 12)434#define RT5668_SEL_SHT_MID_TON_2 (0x0 << 12)435#define RT5668_SEL_SHT_MID_TON_3 (0x1 << 12)436#define RT5668_CBJ_JD_TEST_MASK (0x1 << 6)437#define RT5668_CBJ_JD_TEST_NORM (0x0 << 6)438#define RT5668_CBJ_JD_TEST_MODE (0x1 << 6)439 440/* DAC1 Digital Volume (0x0019) */441#define RT5668_DAC_L1_VOL_MASK (0xff << 8)442#define RT5668_DAC_L1_VOL_SFT 8443#define RT5668_DAC_R1_VOL_MASK (0xff)444#define RT5668_DAC_R1_VOL_SFT 0445 446/* ADC Digital Volume Control (0x001c) */447#define RT5668_ADC_L_VOL_MASK (0x7f << 8)448#define RT5668_ADC_L_VOL_SFT 8449#define RT5668_ADC_R_VOL_MASK (0x7f)450#define RT5668_ADC_R_VOL_SFT 0451 452/* Stereo1 ADC Boost Gain Control (0x001f) */453#define RT5668_STO1_ADC_L_BST_MASK (0x3 << 14)454#define RT5668_STO1_ADC_L_BST_SFT 14455#define RT5668_STO1_ADC_R_BST_MASK (0x3 << 12)456#define RT5668_STO1_ADC_R_BST_SFT 12457 458/* Sidetone Control (0x0024) */459#define RT5668_ST_SRC_SEL (0x1 << 8)460#define RT5668_ST_SRC_SFT 8461#define RT5668_ST_EN_MASK (0x1 << 6)462#define RT5668_ST_DIS (0x0 << 6)463#define RT5668_ST_EN (0x1 << 6)464#define RT5668_ST_EN_SFT 6465 466/* Stereo1 ADC Mixer Control (0x0026) */467#define RT5668_M_STO1_ADC_L1 (0x1 << 15)468#define RT5668_M_STO1_ADC_L1_SFT 15469#define RT5668_M_STO1_ADC_L2 (0x1 << 14)470#define RT5668_M_STO1_ADC_L2_SFT 14471#define RT5668_STO1_ADC1L_SRC_MASK (0x1 << 13)472#define RT5668_STO1_ADC1L_SRC_SFT 13473#define RT5668_STO1_ADC1_SRC_ADC (0x1 << 13)474#define RT5668_STO1_ADC1_SRC_DACMIX (0x0 << 13)475#define RT5668_STO1_ADC2L_SRC_MASK (0x1 << 12)476#define RT5668_STO1_ADC2L_SRC_SFT 12477#define RT5668_STO1_ADCL_SRC_MASK (0x3 << 10)478#define RT5668_STO1_ADCL_SRC_SFT 10479#define RT5668_STO1_DD_L_SRC_MASK (0x1 << 9)480#define RT5668_STO1_DD_L_SRC_SFT 9481#define RT5668_STO1_DMIC_SRC_MASK (0x1 << 8)482#define RT5668_STO1_DMIC_SRC_SFT 8483#define RT5668_STO1_DMIC_SRC_DMIC2 (0x1 << 8)484#define RT5668_STO1_DMIC_SRC_DMIC1 (0x0 << 8)485#define RT5668_M_STO1_ADC_R1 (0x1 << 7)486#define RT5668_M_STO1_ADC_R1_SFT 7487#define RT5668_M_STO1_ADC_R2 (0x1 << 6)488#define RT5668_M_STO1_ADC_R2_SFT 6489#define RT5668_STO1_ADC1R_SRC_MASK (0x1 << 5)490#define RT5668_STO1_ADC1R_SRC_SFT 5491#define RT5668_STO1_ADC2R_SRC_MASK (0x1 << 4)492#define RT5668_STO1_ADC2R_SRC_SFT 4493#define RT5668_STO1_ADCR_SRC_MASK (0x3 << 2)494#define RT5668_STO1_ADCR_SRC_SFT 2495 496/* ADC Mixer to DAC Mixer Control (0x0029) */497#define RT5668_M_ADCMIX_L (0x1 << 15)498#define RT5668_M_ADCMIX_L_SFT 15499#define RT5668_M_DAC1_L (0x1 << 14)500#define RT5668_M_DAC1_L_SFT 14501#define RT5668_DAC1_R_SEL_MASK (0x1 << 10)502#define RT5668_DAC1_R_SEL_SFT 10503#define RT5668_DAC1_L_SEL_MASK (0x1 << 8)504#define RT5668_DAC1_L_SEL_SFT 8505#define RT5668_M_ADCMIX_R (0x1 << 7)506#define RT5668_M_ADCMIX_R_SFT 7507#define RT5668_M_DAC1_R (0x1 << 6)508#define RT5668_M_DAC1_R_SFT 6509 510/* Stereo1 DAC Mixer Control (0x002a) */511#define RT5668_M_DAC_L1_STO_L (0x1 << 15)512#define RT5668_M_DAC_L1_STO_L_SFT 15513#define RT5668_G_DAC_L1_STO_L_MASK (0x1 << 14)514#define RT5668_G_DAC_L1_STO_L_SFT 14515#define RT5668_M_DAC_R1_STO_L (0x1 << 13)516#define RT5668_M_DAC_R1_STO_L_SFT 13517#define RT5668_G_DAC_R1_STO_L_MASK (0x1 << 12)518#define RT5668_G_DAC_R1_STO_L_SFT 12519#define RT5668_M_DAC_L1_STO_R (0x1 << 7)520#define RT5668_M_DAC_L1_STO_R_SFT 7521#define RT5668_G_DAC_L1_STO_R_MASK (0x1 << 6)522#define RT5668_G_DAC_L1_STO_R_SFT 6523#define RT5668_M_DAC_R1_STO_R (0x1 << 5)524#define RT5668_M_DAC_R1_STO_R_SFT 5525#define RT5668_G_DAC_R1_STO_R_MASK (0x1 << 4)526#define RT5668_G_DAC_R1_STO_R_SFT 4527 528/* Analog DAC1 Input Source Control (0x002b) */529#define RT5668_M_ST_STO_L (0x1 << 9)530#define RT5668_M_ST_STO_L_SFT 9531#define RT5668_M_ST_STO_R (0x1 << 8)532#define RT5668_M_ST_STO_R_SFT 8533#define RT5668_DAC_L1_SRC_MASK (0x3 << 4)534#define RT5668_A_DACL1_SFT 4535#define RT5668_DAC_R1_SRC_MASK (0x3)536#define RT5668_A_DACR1_SFT 0537 538/* Digital Interface Data Control (0x0030) */539#define RT5668_IF2_ADC_SEL_MASK (0x3 << 0)540#define RT5668_IF2_ADC_SEL_SFT 0541 542/* REC Left Mixer Control 2 (0x003c) */543#define RT5668_G_CBJ_RM1_L (0x7 << 10)544#define RT5668_G_CBJ_RM1_L_SFT 10545#define RT5668_M_CBJ_RM1_L (0x1 << 7)546#define RT5668_M_CBJ_RM1_L_SFT 7547 548/* Power Management for Digital 1 (0x0061) */549#define RT5668_PWR_I2S1 (0x1 << 15)550#define RT5668_PWR_I2S1_BIT 15551#define RT5668_PWR_I2S2 (0x1 << 14)552#define RT5668_PWR_I2S2_BIT 14553#define RT5668_PWR_DAC_L1 (0x1 << 11)554#define RT5668_PWR_DAC_L1_BIT 11555#define RT5668_PWR_DAC_R1 (0x1 << 10)556#define RT5668_PWR_DAC_R1_BIT 10557#define RT5668_PWR_LDO (0x1 << 8)558#define RT5668_PWR_LDO_BIT 8559#define RT5668_PWR_ADC_L1 (0x1 << 4)560#define RT5668_PWR_ADC_L1_BIT 4561#define RT5668_PWR_ADC_R1 (0x1 << 3)562#define RT5668_PWR_ADC_R1_BIT 3563#define RT5668_DIG_GATE_CTRL (0x1 << 0)564#define RT5668_DIG_GATE_CTRL_SFT 0565 566 567/* Power Management for Digital 2 (0x0062) */568#define RT5668_PWR_ADC_S1F (0x1 << 15)569#define RT5668_PWR_ADC_S1F_BIT 15570#define RT5668_PWR_DAC_S1F (0x1 << 10)571#define RT5668_PWR_DAC_S1F_BIT 10572 573/* Power Management for Analog 1 (0x0063) */574#define RT5668_PWR_VREF1 (0x1 << 15)575#define RT5668_PWR_VREF1_BIT 15576#define RT5668_PWR_FV1 (0x1 << 14)577#define RT5668_PWR_FV1_BIT 14578#define RT5668_PWR_VREF2 (0x1 << 13)579#define RT5668_PWR_VREF2_BIT 13580#define RT5668_PWR_FV2 (0x1 << 12)581#define RT5668_PWR_FV2_BIT 12582#define RT5668_LDO1_DBG_MASK (0x3 << 10)583#define RT5668_PWR_MB (0x1 << 9)584#define RT5668_PWR_MB_BIT 9585#define RT5668_PWR_BG (0x1 << 7)586#define RT5668_PWR_BG_BIT 7587#define RT5668_LDO1_BYPASS_MASK (0x1 << 6)588#define RT5668_LDO1_BYPASS (0x1 << 6)589#define RT5668_LDO1_NOT_BYPASS (0x0 << 6)590#define RT5668_PWR_MA_BIT 6591#define RT5668_LDO1_DVO_MASK (0x3 << 4)592#define RT5668_LDO1_DVO_09 (0x0 << 4)593#define RT5668_LDO1_DVO_10 (0x1 << 4)594#define RT5668_LDO1_DVO_12 (0x2 << 4)595#define RT5668_LDO1_DVO_14 (0x3 << 4)596#define RT5668_HP_DRIVER_MASK (0x3 << 2)597#define RT5668_HP_DRIVER_1X (0x0 << 2)598#define RT5668_HP_DRIVER_3X (0x1 << 2)599#define RT5668_HP_DRIVER_5X (0x3 << 2)600#define RT5668_PWR_HA_L (0x1 << 1)601#define RT5668_PWR_HA_L_BIT 1602#define RT5668_PWR_HA_R (0x1 << 0)603#define RT5668_PWR_HA_R_BIT 0604 605/* Power Management for Analog 2 (0x0064) */606#define RT5668_PWR_MB1 (0x1 << 11)607#define RT5668_PWR_MB1_PWR_DOWN (0x0 << 11)608#define RT5668_PWR_MB1_BIT 11609#define RT5668_PWR_MB2 (0x1 << 10)610#define RT5668_PWR_MB2_PWR_DOWN (0x0 << 10)611#define RT5668_PWR_MB2_BIT 10612#define RT5668_PWR_JDH (0x1 << 3)613#define RT5668_PWR_JDH_BIT 3614#define RT5668_PWR_JDL (0x1 << 2)615#define RT5668_PWR_JDL_BIT 2616#define RT5668_PWR_RM1_L (0x1 << 1)617#define RT5668_PWR_RM1_L_BIT 1618 619/* Power Management for Analog 3 (0x0065) */620#define RT5668_PWR_CBJ (0x1 << 9)621#define RT5668_PWR_CBJ_BIT 9622#define RT5668_PWR_PLL (0x1 << 6)623#define RT5668_PWR_PLL_BIT 6624#define RT5668_PWR_PLL2B (0x1 << 5)625#define RT5668_PWR_PLL2B_BIT 5626#define RT5668_PWR_PLL2F (0x1 << 4)627#define RT5668_PWR_PLL2F_BIT 4628#define RT5668_PWR_LDO2 (0x1 << 2)629#define RT5668_PWR_LDO2_BIT 2630#define RT5668_PWR_DET_SPKVDD (0x1 << 1)631#define RT5668_PWR_DET_SPKVDD_BIT 1632 633/* Power Management for Mixer (0x0066) */634#define RT5668_PWR_STO1_DAC_L (0x1 << 5)635#define RT5668_PWR_STO1_DAC_L_BIT 5636#define RT5668_PWR_STO1_DAC_R (0x1 << 4)637#define RT5668_PWR_STO1_DAC_R_BIT 4638 639/* MCLK and System Clock Detection Control (0x006b) */640#define RT5668_SYS_CLK_DET (0x1 << 15)641#define RT5668_SYS_CLK_DET_SFT 15642#define RT5668_PLL1_CLK_DET (0x1 << 14)643#define RT5668_PLL1_CLK_DET_SFT 14644#define RT5668_PLL2_CLK_DET (0x1 << 13)645#define RT5668_PLL2_CLK_DET_SFT 13646#define RT5668_POW_CLK_DET2_SFT 8647#define RT5668_POW_CLK_DET_SFT 0648 649/* Digital Microphone Control 1 (0x006e) */650#define RT5668_DMIC_1_EN_MASK (0x1 << 15)651#define RT5668_DMIC_1_EN_SFT 15652#define RT5668_DMIC_1_DIS (0x0 << 15)653#define RT5668_DMIC_1_EN (0x1 << 15)654#define RT5668_DMIC_1_DP_MASK (0x3 << 4)655#define RT5668_DMIC_1_DP_SFT 4656#define RT5668_DMIC_1_DP_GPIO2 (0x0 << 4)657#define RT5668_DMIC_1_DP_GPIO5 (0x1 << 4)658#define RT5668_DMIC_CLK_MASK (0xf << 0)659#define RT5668_DMIC_CLK_SFT 0660 661/* I2S1 Audio Serial Data Port Control (0x0070) */662#define RT5668_SEL_ADCDAT_MASK (0x1 << 15)663#define RT5668_SEL_ADCDAT_OUT (0x0 << 15)664#define RT5668_SEL_ADCDAT_IN (0x1 << 15)665#define RT5668_SEL_ADCDAT_SFT 15666#define RT5668_I2S1_TX_CHL_MASK (0x7 << 12)667#define RT5668_I2S1_TX_CHL_SFT 12668#define RT5668_I2S1_TX_CHL_16 (0x0 << 12)669#define RT5668_I2S1_TX_CHL_20 (0x1 << 12)670#define RT5668_I2S1_TX_CHL_24 (0x2 << 12)671#define RT5668_I2S1_TX_CHL_32 (0x3 << 12)672#define RT5668_I2S1_TX_CHL_8 (0x4 << 12)673#define RT5668_I2S1_RX_CHL_MASK (0x7 << 8)674#define RT5668_I2S1_RX_CHL_SFT 8675#define RT5668_I2S1_RX_CHL_16 (0x0 << 8)676#define RT5668_I2S1_RX_CHL_20 (0x1 << 8)677#define RT5668_I2S1_RX_CHL_24 (0x2 << 8)678#define RT5668_I2S1_RX_CHL_32 (0x3 << 8)679#define RT5668_I2S1_RX_CHL_8 (0x4 << 8)680#define RT5668_I2S1_MONO_MASK (0x1 << 7)681#define RT5668_I2S1_MONO_EN (0x1 << 7)682#define RT5668_I2S1_MONO_DIS (0x0 << 7)683#define RT5668_I2S2_MONO_MASK (0x1 << 6)684#define RT5668_I2S2_MONO_EN (0x1 << 6)685#define RT5668_I2S2_MONO_DIS (0x0 << 6)686#define RT5668_I2S1_DL_MASK (0x7 << 4)687#define RT5668_I2S1_DL_SFT 4688#define RT5668_I2S1_DL_16 (0x0 << 4)689#define RT5668_I2S1_DL_20 (0x1 << 4)690#define RT5668_I2S1_DL_24 (0x2 << 4)691#define RT5668_I2S1_DL_32 (0x3 << 4)692#define RT5668_I2S1_DL_8 (0x4 << 4)693 694/* I2S1/2 Audio Serial Data Port Control (0x0070)(0x0071) */695#define RT5668_I2S2_MS_MASK (0x1 << 15)696#define RT5668_I2S2_MS_SFT 15697#define RT5668_I2S2_MS_M (0x0 << 15)698#define RT5668_I2S2_MS_S (0x1 << 15)699#define RT5668_I2S2_PIN_CFG_MASK (0x1 << 14)700#define RT5668_I2S2_PIN_CFG_SFT 14701#define RT5668_I2S2_CLK_SEL_MASK (0x1 << 11)702#define RT5668_I2S2_CLK_SEL_SFT 11703#define RT5668_I2S2_OUT_MASK (0x1 << 9)704#define RT5668_I2S2_OUT_SFT 9705#define RT5668_I2S2_OUT_UM (0x0 << 9)706#define RT5668_I2S2_OUT_M (0x1 << 9)707#define RT5668_I2S_BP_MASK (0x1 << 8)708#define RT5668_I2S_BP_SFT 8709#define RT5668_I2S_BP_NOR (0x0 << 8)710#define RT5668_I2S_BP_INV (0x1 << 8)711#define RT5668_I2S2_MONO_EN (0x1 << 6)712#define RT5668_I2S2_MONO_DIS (0x0 << 6)713#define RT5668_I2S2_DL_MASK (0x3 << 4)714#define RT5668_I2S2_DL_SFT 4715#define RT5668_I2S2_DL_16 (0x0 << 4)716#define RT5668_I2S2_DL_20 (0x1 << 4)717#define RT5668_I2S2_DL_24 (0x2 << 4)718#define RT5668_I2S2_DL_8 (0x3 << 4)719#define RT5668_I2S_DF_MASK (0x7)720#define RT5668_I2S_DF_SFT 0721#define RT5668_I2S_DF_I2S (0x0)722#define RT5668_I2S_DF_LEFT (0x1)723#define RT5668_I2S_DF_PCM_A (0x2)724#define RT5668_I2S_DF_PCM_B (0x3)725#define RT5668_I2S_DF_PCM_A_N (0x6)726#define RT5668_I2S_DF_PCM_B_N (0x7)727 728/* ADC/DAC Clock Control 1 (0x0073) */729#define RT5668_ADC_OSR_MASK (0xf << 12)730#define RT5668_ADC_OSR_SFT 12731#define RT5668_ADC_OSR_D_1 (0x0 << 12)732#define RT5668_ADC_OSR_D_2 (0x1 << 12)733#define RT5668_ADC_OSR_D_4 (0x2 << 12)734#define RT5668_ADC_OSR_D_6 (0x3 << 12)735#define RT5668_ADC_OSR_D_8 (0x4 << 12)736#define RT5668_ADC_OSR_D_12 (0x5 << 12)737#define RT5668_ADC_OSR_D_16 (0x6 << 12)738#define RT5668_ADC_OSR_D_24 (0x7 << 12)739#define RT5668_ADC_OSR_D_32 (0x8 << 12)740#define RT5668_ADC_OSR_D_48 (0x9 << 12)741#define RT5668_I2S_M_DIV_MASK (0xf << 12)742#define RT5668_I2S_M_DIV_SFT 8743#define RT5668_I2S_M_D_1 (0x0 << 8)744#define RT5668_I2S_M_D_2 (0x1 << 8)745#define RT5668_I2S_M_D_3 (0x2 << 8)746#define RT5668_I2S_M_D_4 (0x3 << 8)747#define RT5668_I2S_M_D_6 (0x4 << 8)748#define RT5668_I2S_M_D_8 (0x5 << 8)749#define RT5668_I2S_M_D_12 (0x6 << 8)750#define RT5668_I2S_M_D_16 (0x7 << 8)751#define RT5668_I2S_M_D_24 (0x8 << 8)752#define RT5668_I2S_M_D_32 (0x9 << 8)753#define RT5668_I2S_M_D_48 (0x10 << 8)754#define RT5668_I2S_CLK_SRC_MASK (0x7 << 4)755#define RT5668_I2S_CLK_SRC_SFT 4756#define RT5668_I2S_CLK_SRC_MCLK (0x0 << 4)757#define RT5668_I2S_CLK_SRC_PLL1 (0x1 << 4)758#define RT5668_I2S_CLK_SRC_PLL2 (0x2 << 4)759#define RT5668_I2S_CLK_SRC_SDW (0x3 << 4)760#define RT5668_I2S_CLK_SRC_RCCLK (0x4 << 4) /* 25M */761#define RT5668_DAC_OSR_MASK (0xf << 0)762#define RT5668_DAC_OSR_SFT 0763#define RT5668_DAC_OSR_D_1 (0x0 << 0)764#define RT5668_DAC_OSR_D_2 (0x1 << 0)765#define RT5668_DAC_OSR_D_4 (0x2 << 0)766#define RT5668_DAC_OSR_D_6 (0x3 << 0)767#define RT5668_DAC_OSR_D_8 (0x4 << 0)768#define RT5668_DAC_OSR_D_12 (0x5 << 0)769#define RT5668_DAC_OSR_D_16 (0x6 << 0)770#define RT5668_DAC_OSR_D_24 (0x7 << 0)771#define RT5668_DAC_OSR_D_32 (0x8 << 0)772#define RT5668_DAC_OSR_D_48 (0x9 << 0)773 774/* ADC/DAC Clock Control 2 (0x0074) */775#define RT5668_I2S2_BCLK_MS2_MASK (0x1 << 11)776#define RT5668_I2S2_BCLK_MS2_SFT 11777#define RT5668_I2S2_BCLK_MS2_32 (0x0 << 11)778#define RT5668_I2S2_BCLK_MS2_64 (0x1 << 11)779 780 781/* TDM control 1 (0x0079) */782#define RT5668_TDM_TX_CH_MASK (0x3 << 12)783#define RT5668_TDM_TX_CH_2 (0x0 << 12)784#define RT5668_TDM_TX_CH_4 (0x1 << 12)785#define RT5668_TDM_TX_CH_6 (0x2 << 12)786#define RT5668_TDM_TX_CH_8 (0x3 << 12)787#define RT5668_TDM_RX_CH_MASK (0x3 << 8)788#define RT5668_TDM_RX_CH_2 (0x0 << 8)789#define RT5668_TDM_RX_CH_4 (0x1 << 8)790#define RT5668_TDM_RX_CH_6 (0x2 << 8)791#define RT5668_TDM_RX_CH_8 (0x3 << 8)792#define RT5668_TDM_ADC_LCA_MASK (0xf << 4)793#define RT5668_TDM_ADC_LCA_SFT 4794#define RT5668_TDM_ADC_DL_SFT 0795 796/* TDM control 3 (0x007a) */797#define RT5668_IF1_ADC1_SEL_SFT 14798#define RT5668_IF1_ADC2_SEL_SFT 12799#define RT5668_IF1_ADC3_SEL_SFT 10800#define RT5668_IF1_ADC4_SEL_SFT 8801#define RT5668_TDM_ADC_SEL_SFT 4802 803/* TDM/I2S control (0x007e) */804#define RT5668_TDM_S_BP_MASK (0x1 << 15)805#define RT5668_TDM_S_BP_SFT 15806#define RT5668_TDM_S_BP_NOR (0x0 << 15)807#define RT5668_TDM_S_BP_INV (0x1 << 15)808#define RT5668_TDM_S_LP_MASK (0x1 << 14)809#define RT5668_TDM_S_LP_SFT 14810#define RT5668_TDM_S_LP_NOR (0x0 << 14)811#define RT5668_TDM_S_LP_INV (0x1 << 14)812#define RT5668_TDM_DF_MASK (0x7 << 11)813#define RT5668_TDM_DF_SFT 11814#define RT5668_TDM_DF_I2S (0x0 << 11)815#define RT5668_TDM_DF_LEFT (0x1 << 11)816#define RT5668_TDM_DF_PCM_A (0x2 << 11)817#define RT5668_TDM_DF_PCM_B (0x3 << 11)818#define RT5668_TDM_DF_PCM_A_N (0x6 << 11)819#define RT5668_TDM_DF_PCM_B_N (0x7 << 11)820#define RT5668_TDM_CL_MASK (0x3 << 4)821#define RT5668_TDM_CL_16 (0x0 << 4)822#define RT5668_TDM_CL_20 (0x1 << 4)823#define RT5668_TDM_CL_24 (0x2 << 4)824#define RT5668_TDM_CL_32 (0x3 << 4)825#define RT5668_TDM_M_BP_MASK (0x1 << 2)826#define RT5668_TDM_M_BP_SFT 2827#define RT5668_TDM_M_BP_NOR (0x0 << 2)828#define RT5668_TDM_M_BP_INV (0x1 << 2)829#define RT5668_TDM_M_LP_MASK (0x1 << 1)830#define RT5668_TDM_M_LP_SFT 1831#define RT5668_TDM_M_LP_NOR (0x0 << 1)832#define RT5668_TDM_M_LP_INV (0x1 << 1)833#define RT5668_TDM_MS_MASK (0x1 << 0)834#define RT5668_TDM_MS_SFT 0835#define RT5668_TDM_MS_M (0x0 << 0)836#define RT5668_TDM_MS_S (0x1 << 0)837 838/* Global Clock Control (0x0080) */839#define RT5668_SCLK_SRC_MASK (0x7 << 13)840#define RT5668_SCLK_SRC_SFT 13841#define RT5668_SCLK_SRC_MCLK (0x0 << 13)842#define RT5668_SCLK_SRC_PLL1 (0x1 << 13)843#define RT5668_SCLK_SRC_PLL2 (0x2 << 13)844#define RT5668_SCLK_SRC_SDW (0x3 << 13)845#define RT5668_SCLK_SRC_RCCLK (0x4 << 13)846#define RT5668_PLL1_SRC_MASK (0x3 << 10)847#define RT5668_PLL1_SRC_SFT 10848#define RT5668_PLL1_SRC_MCLK (0x0 << 10)849#define RT5668_PLL1_SRC_BCLK1 (0x1 << 10)850#define RT5668_PLL1_SRC_SDW (0x2 << 10)851#define RT5668_PLL1_SRC_RC (0x3 << 10)852#define RT5668_PLL2_SRC_MASK (0x3 << 8)853#define RT5668_PLL2_SRC_SFT 8854#define RT5668_PLL2_SRC_MCLK (0x0 << 8)855#define RT5668_PLL2_SRC_BCLK1 (0x1 << 8)856#define RT5668_PLL2_SRC_SDW (0x2 << 8)857#define RT5668_PLL2_SRC_RC (0x3 << 8)858 859 860 861#define RT5668_PLL_INP_MAX 40000000862#define RT5668_PLL_INP_MIN 256000863/* PLL M/N/K Code Control 1 (0x0081) */864#define RT5668_PLL_N_MAX 0x001ff865#define RT5668_PLL_N_MASK (RT5668_PLL_N_MAX << 7)866#define RT5668_PLL_N_SFT 7867#define RT5668_PLL_K_MAX 0x001f868#define RT5668_PLL_K_MASK (RT5668_PLL_K_MAX)869#define RT5668_PLL_K_SFT 0870 871/* PLL M/N/K Code Control 2 (0x0082) */872#define RT5668_PLL_M_MAX 0x00f873#define RT5668_PLL_M_MASK (RT5668_PLL_M_MAX << 12)874#define RT5668_PLL_M_SFT 12875#define RT5668_PLL_M_BP (0x1 << 11)876#define RT5668_PLL_M_BP_SFT 11877#define RT5668_PLL_K_BP (0x1 << 10)878#define RT5668_PLL_K_BP_SFT 10879 880/* PLL tracking mode 1 (0x0083) */881#define RT5668_DA_ASRC_MASK (0x1 << 13)882#define RT5668_DA_ASRC_SFT 13883#define RT5668_DAC_STO1_ASRC_MASK (0x1 << 12)884#define RT5668_DAC_STO1_ASRC_SFT 12885#define RT5668_AD_ASRC_MASK (0x1 << 8)886#define RT5668_AD_ASRC_SFT 8887#define RT5668_AD_ASRC_SEL_MASK (0x1 << 4)888#define RT5668_AD_ASRC_SEL_SFT 4889#define RT5668_DMIC_ASRC_MASK (0x1 << 3)890#define RT5668_DMIC_ASRC_SFT 3891#define RT5668_ADC_STO1_ASRC_MASK (0x1 << 2)892#define RT5668_ADC_STO1_ASRC_SFT 2893#define RT5668_DA_ASRC_SEL_MASK (0x1 << 0)894#define RT5668_DA_ASRC_SEL_SFT 0895 896/* PLL tracking mode 2 3 (0x0084)(0x0085)*/897#define RT5668_FILTER_CLK_SEL_MASK (0x7 << 12)898#define RT5668_FILTER_CLK_SEL_SFT 12899 900/* ASRC Control 4 (0x0086) */901#define RT5668_ASRCIN_FTK_N1_MASK (0x3 << 14)902#define RT5668_ASRCIN_FTK_N1_SFT 14903#define RT5668_ASRCIN_FTK_N2_MASK (0x3 << 12)904#define RT5668_ASRCIN_FTK_N2_SFT 12905#define RT5668_ASRCIN_FTK_M1_MASK (0x7 << 8)906#define RT5668_ASRCIN_FTK_M1_SFT 8907#define RT5668_ASRCIN_FTK_M2_MASK (0x7 << 4)908#define RT5668_ASRCIN_FTK_M2_SFT 4909 910/* SoundWire reference clk (0x008d) */911#define RT5668_PLL2_OUT_MASK (0x1 << 8)912#define RT5668_PLL2_OUT_98M (0x0 << 8)913#define RT5668_PLL2_OUT_49M (0x1 << 8)914#define RT5668_SDW_REF_2_MASK (0xf << 4)915#define RT5668_SDW_REF_2_SFT 4916#define RT5668_SDW_REF_2_48K (0x0 << 4)917#define RT5668_SDW_REF_2_96K (0x1 << 4)918#define RT5668_SDW_REF_2_192K (0x2 << 4)919#define RT5668_SDW_REF_2_32K (0x3 << 4)920#define RT5668_SDW_REF_2_24K (0x4 << 4)921#define RT5668_SDW_REF_2_16K (0x5 << 4)922#define RT5668_SDW_REF_2_12K (0x6 << 4)923#define RT5668_SDW_REF_2_8K (0x7 << 4)924#define RT5668_SDW_REF_2_44K (0x8 << 4)925#define RT5668_SDW_REF_2_88K (0x9 << 4)926#define RT5668_SDW_REF_2_176K (0xa << 4)927#define RT5668_SDW_REF_2_353K (0xb << 4)928#define RT5668_SDW_REF_2_22K (0xc << 4)929#define RT5668_SDW_REF_2_384K (0xd << 4)930#define RT5668_SDW_REF_2_11K (0xe << 4)931#define RT5668_SDW_REF_1_MASK (0xf << 0)932#define RT5668_SDW_REF_1_SFT 0933#define RT5668_SDW_REF_1_48K (0x0 << 0)934#define RT5668_SDW_REF_1_96K (0x1 << 0)935#define RT5668_SDW_REF_1_192K (0x2 << 0)936#define RT5668_SDW_REF_1_32K (0x3 << 0)937#define RT5668_SDW_REF_1_24K (0x4 << 0)938#define RT5668_SDW_REF_1_16K (0x5 << 0)939#define RT5668_SDW_REF_1_12K (0x6 << 0)940#define RT5668_SDW_REF_1_8K (0x7 << 0)941#define RT5668_SDW_REF_1_44K (0x8 << 0)942#define RT5668_SDW_REF_1_88K (0x9 << 0)943#define RT5668_SDW_REF_1_176K (0xa << 0)944#define RT5668_SDW_REF_1_353K (0xb << 0)945#define RT5668_SDW_REF_1_22K (0xc << 0)946#define RT5668_SDW_REF_1_384K (0xd << 0)947#define RT5668_SDW_REF_1_11K (0xe << 0)948 949/* Depop Mode Control 1 (0x008e) */950#define RT5668_PUMP_EN (0x1 << 3)951#define RT5668_PUMP_EN_SFT 3952#define RT5668_CAPLESS_EN (0x1 << 0)953#define RT5668_CAPLESS_EN_SFT 0954 955/* Depop Mode Control 2 (0x8f) */956#define RT5668_RAMP_MASK (0x1 << 12)957#define RT5668_RAMP_SFT 12958#define RT5668_RAMP_DIS (0x0 << 12)959#define RT5668_RAMP_EN (0x1 << 12)960#define RT5668_BPS_MASK (0x1 << 11)961#define RT5668_BPS_SFT 11962#define RT5668_BPS_DIS (0x0 << 11)963#define RT5668_BPS_EN (0x1 << 11)964#define RT5668_FAST_UPDN_MASK (0x1 << 10)965#define RT5668_FAST_UPDN_SFT 10966#define RT5668_FAST_UPDN_DIS (0x0 << 10)967#define RT5668_FAST_UPDN_EN (0x1 << 10)968#define RT5668_VLO_MASK (0x1 << 7)969#define RT5668_VLO_SFT 7970#define RT5668_VLO_3V (0x0 << 7)971#define RT5668_VLO_33V (0x1 << 7)972 973/* HPOUT charge pump 1 (0x0091) */974#define RT5668_OSW_L_MASK (0x1 << 11)975#define RT5668_OSW_L_SFT 11976#define RT5668_OSW_L_DIS (0x0 << 11)977#define RT5668_OSW_L_EN (0x1 << 11)978#define RT5668_OSW_R_MASK (0x1 << 10)979#define RT5668_OSW_R_SFT 10980#define RT5668_OSW_R_DIS (0x0 << 10)981#define RT5668_OSW_R_EN (0x1 << 10)982#define RT5668_PM_HP_MASK (0x3 << 8)983#define RT5668_PM_HP_SFT 8984#define RT5668_PM_HP_LV (0x0 << 8)985#define RT5668_PM_HP_MV (0x1 << 8)986#define RT5668_PM_HP_HV (0x2 << 8)987#define RT5668_IB_HP_MASK (0x3 << 6)988#define RT5668_IB_HP_SFT 6989#define RT5668_IB_HP_125IL (0x0 << 6)990#define RT5668_IB_HP_25IL (0x1 << 6)991#define RT5668_IB_HP_5IL (0x2 << 6)992#define RT5668_IB_HP_1IL (0x3 << 6)993 994/* Micbias Control1 (0x93) */995#define RT5668_MIC1_OV_MASK (0x3 << 14)996#define RT5668_MIC1_OV_SFT 14997#define RT5668_MIC1_OV_2V7 (0x0 << 14)998#define RT5668_MIC1_OV_2V4 (0x1 << 14)999#define RT5668_MIC1_OV_2V25 (0x3 << 14)1000#define RT5668_MIC1_OV_1V8 (0x4 << 14)1001#define RT5668_MIC1_CLK_MASK (0x1 << 13)1002#define RT5668_MIC1_CLK_SFT 131003#define RT5668_MIC1_CLK_DIS (0x0 << 13)1004#define RT5668_MIC1_CLK_EN (0x1 << 13)1005#define RT5668_MIC1_OVCD_MASK (0x1 << 12)1006#define RT5668_MIC1_OVCD_SFT 121007#define RT5668_MIC1_OVCD_DIS (0x0 << 12)1008#define RT5668_MIC1_OVCD_EN (0x1 << 12)1009#define RT5668_MIC1_OVTH_MASK (0x3 << 10)1010#define RT5668_MIC1_OVTH_SFT 101011#define RT5668_MIC1_OVTH_768UA (0x0 << 10)1012#define RT5668_MIC1_OVTH_960UA (0x1 << 10)1013#define RT5668_MIC1_OVTH_1152UA (0x2 << 10)1014#define RT5668_MIC1_OVTH_1960UA (0x3 << 10)1015#define RT5668_MIC2_OV_MASK (0x3 << 8)1016#define RT5668_MIC2_OV_SFT 81017#define RT5668_MIC2_OV_2V7 (0x0 << 8)1018#define RT5668_MIC2_OV_2V4 (0x1 << 8)1019#define RT5668_MIC2_OV_2V25 (0x3 << 8)1020#define RT5668_MIC2_OV_1V8 (0x4 << 8)1021#define RT5668_MIC2_CLK_MASK (0x1 << 7)1022#define RT5668_MIC2_CLK_SFT 71023#define RT5668_MIC2_CLK_DIS (0x0 << 7)1024#define RT5668_MIC2_CLK_EN (0x1 << 7)1025#define RT5668_MIC2_OVTH_MASK (0x3 << 4)1026#define RT5668_MIC2_OVTH_SFT 41027#define RT5668_MIC2_OVTH_768UA (0x0 << 4)1028#define RT5668_MIC2_OVTH_960UA (0x1 << 4)1029#define RT5668_MIC2_OVTH_1152UA (0x2 << 4)1030#define RT5668_MIC2_OVTH_1960UA (0x3 << 4)1031#define RT5668_PWR_MB_MASK (0x1 << 3)1032#define RT5668_PWR_MB_SFT 31033#define RT5668_PWR_MB_PD (0x0 << 3)1034#define RT5668_PWR_MB_PU (0x1 << 3)1035 1036/* Micbias Control2 (0x0094) */1037#define RT5668_PWR_CLK25M_MASK (0x1 << 9)1038#define RT5668_PWR_CLK25M_SFT 91039#define RT5668_PWR_CLK25M_PD (0x0 << 9)1040#define RT5668_PWR_CLK25M_PU (0x1 << 9)1041#define RT5668_PWR_CLK1M_MASK (0x1 << 8)1042#define RT5668_PWR_CLK1M_SFT 81043#define RT5668_PWR_CLK1M_PD (0x0 << 8)1044#define RT5668_PWR_CLK1M_PU (0x1 << 8)1045 1046/* RC Clock Control (0x009f) */1047#define RT5668_POW_IRQ (0x1 << 15)1048#define RT5668_POW_JDH (0x1 << 14)1049#define RT5668_POW_JDL (0x1 << 13)1050#define RT5668_POW_ANA (0x1 << 12)1051 1052/* I2S Master Mode Clock Control 1 (0x00a0) */1053#define RT5668_CLK_SRC_MCLK (0x0)1054#define RT5668_CLK_SRC_PLL1 (0x1)1055#define RT5668_CLK_SRC_PLL2 (0x2)1056#define RT5668_CLK_SRC_SDW (0x3)1057#define RT5668_CLK_SRC_RCCLK (0x4)1058#define RT5668_I2S_PD_1 (0x0)1059#define RT5668_I2S_PD_2 (0x1)1060#define RT5668_I2S_PD_3 (0x2)1061#define RT5668_I2S_PD_4 (0x3)1062#define RT5668_I2S_PD_6 (0x4)1063#define RT5668_I2S_PD_8 (0x5)1064#define RT5668_I2S_PD_12 (0x6)1065#define RT5668_I2S_PD_16 (0x7)1066#define RT5668_I2S_PD_24 (0x8)1067#define RT5668_I2S_PD_32 (0x9)1068#define RT5668_I2S_PD_48 (0xa)1069#define RT5668_I2S2_SRC_MASK (0x3 << 4)1070#define RT5668_I2S2_SRC_SFT 41071#define RT5668_I2S2_M_PD_MASK (0xf << 0)1072#define RT5668_I2S2_M_PD_SFT 01073 1074/* IRQ Control 1 (0x00b6) */1075#define RT5668_JD1_PULSE_EN_MASK (0x1 << 10)1076#define RT5668_JD1_PULSE_EN_SFT 101077#define RT5668_JD1_PULSE_DIS (0x0 << 10)1078#define RT5668_JD1_PULSE_EN (0x1 << 10)1079 1080/* IRQ Control 2 (0x00b7) */1081#define RT5668_JD1_EN_MASK (0x1 << 15)1082#define RT5668_JD1_EN_SFT 151083#define RT5668_JD1_DIS (0x0 << 15)1084#define RT5668_JD1_EN (0x1 << 15)1085#define RT5668_JD1_POL_MASK (0x1 << 13)1086#define RT5668_JD1_POL_NOR (0x0 << 13)1087#define RT5668_JD1_POL_INV (0x1 << 13)1088 1089/* IRQ Control 3 (0x00b8) */1090#define RT5668_IL_IRQ_MASK (0x1 << 7)1091#define RT5668_IL_IRQ_DIS (0x0 << 7)1092#define RT5668_IL_IRQ_EN (0x1 << 7)1093 1094/* GPIO Control 1 (0x00c0) */1095#define RT5668_GP1_PIN_MASK (0x3 << 14)1096#define RT5668_GP1_PIN_SFT 141097#define RT5668_GP1_PIN_GPIO1 (0x0 << 14)1098#define RT5668_GP1_PIN_IRQ (0x1 << 14)1099#define RT5668_GP1_PIN_DMIC_CLK (0x2 << 14)1100#define RT5668_GP2_PIN_MASK (0x3 << 12)1101#define RT5668_GP2_PIN_SFT 121102#define RT5668_GP2_PIN_GPIO2 (0x0 << 12)1103#define RT5668_GP2_PIN_LRCK2 (0x1 << 12)1104#define RT5668_GP2_PIN_DMIC_SDA (0x2 << 12)1105#define RT5668_GP3_PIN_MASK (0x3 << 10)1106#define RT5668_GP3_PIN_SFT 101107#define RT5668_GP3_PIN_GPIO3 (0x0 << 10)1108#define RT5668_GP3_PIN_BCLK2 (0x1 << 10)1109#define RT5668_GP3_PIN_DMIC_CLK (0x2 << 10)1110#define RT5668_GP4_PIN_MASK (0x3 << 8)1111#define RT5668_GP4_PIN_SFT 81112#define RT5668_GP4_PIN_GPIO4 (0x0 << 8)1113#define RT5668_GP4_PIN_ADCDAT1 (0x1 << 8)1114#define RT5668_GP4_PIN_DMIC_CLK (0x2 << 8)1115#define RT5668_GP4_PIN_ADCDAT2 (0x3 << 8)1116#define RT5668_GP5_PIN_MASK (0x3 << 6)1117#define RT5668_GP5_PIN_SFT 61118#define RT5668_GP5_PIN_GPIO5 (0x0 << 6)1119#define RT5668_GP5_PIN_DACDAT1 (0x1 << 6)1120#define RT5668_GP5_PIN_DMIC_SDA (0x2 << 6)1121#define RT5668_GP6_PIN_MASK (0x1 << 5)1122#define RT5668_GP6_PIN_SFT 51123#define RT5668_GP6_PIN_GPIO6 (0x0 << 5)1124#define RT5668_GP6_PIN_LRCK1 (0x1 << 5)1125 1126/* GPIO Control 2 (0x00c1)*/1127#define RT5668_GP1_PF_MASK (0x1 << 15)1128#define RT5668_GP1_PF_IN (0x0 << 15)1129#define RT5668_GP1_PF_OUT (0x1 << 15)1130#define RT5668_GP1_OUT_MASK (0x1 << 14)1131#define RT5668_GP1_OUT_L (0x0 << 14)1132#define RT5668_GP1_OUT_H (0x1 << 14)1133#define RT5668_GP2_PF_MASK (0x1 << 13)1134#define RT5668_GP2_PF_IN (0x0 << 13)1135#define RT5668_GP2_PF_OUT (0x1 << 13)1136#define RT5668_GP2_OUT_MASK (0x1 << 12)1137#define RT5668_GP2_OUT_L (0x0 << 12)1138#define RT5668_GP2_OUT_H (0x1 << 12)1139#define RT5668_GP3_PF_MASK (0x1 << 11)1140#define RT5668_GP3_PF_IN (0x0 << 11)1141#define RT5668_GP3_PF_OUT (0x1 << 11)1142#define RT5668_GP3_OUT_MASK (0x1 << 10)1143#define RT5668_GP3_OUT_L (0x0 << 10)1144#define RT5668_GP3_OUT_H (0x1 << 10)1145#define RT5668_GP4_PF_MASK (0x1 << 9)1146#define RT5668_GP4_PF_IN (0x0 << 9)1147#define RT5668_GP4_PF_OUT (0x1 << 9)1148#define RT5668_GP4_OUT_MASK (0x1 << 8)1149#define RT5668_GP4_OUT_L (0x0 << 8)1150#define RT5668_GP4_OUT_H (0x1 << 8)1151#define RT5668_GP5_PF_MASK (0x1 << 7)1152#define RT5668_GP5_PF_IN (0x0 << 7)1153#define RT5668_GP5_PF_OUT (0x1 << 7)1154#define RT5668_GP5_OUT_MASK (0x1 << 6)1155#define RT5668_GP5_OUT_L (0x0 << 6)1156#define RT5668_GP5_OUT_H (0x1 << 6)1157#define RT5668_GP6_PF_MASK (0x1 << 5)1158#define RT5668_GP6_PF_IN (0x0 << 5)1159#define RT5668_GP6_PF_OUT (0x1 << 5)1160#define RT5668_GP6_OUT_MASK (0x1 << 4)1161#define RT5668_GP6_OUT_L (0x0 << 4)1162#define RT5668_GP6_OUT_H (0x1 << 4)1163 1164 1165/* GPIO Status (0x00c2) */1166#define RT5668_GP6_STA (0x1 << 6)1167#define RT5668_GP5_STA (0x1 << 5)1168#define RT5668_GP4_STA (0x1 << 4)1169#define RT5668_GP3_STA (0x1 << 3)1170#define RT5668_GP2_STA (0x1 << 2)1171#define RT5668_GP1_STA (0x1 << 1)1172 1173/* Soft volume and zero cross control 1 (0x00d9) */1174#define RT5668_SV_MASK (0x1 << 15)1175#define RT5668_SV_SFT 151176#define RT5668_SV_DIS (0x0 << 15)1177#define RT5668_SV_EN (0x1 << 15)1178#define RT5668_ZCD_MASK (0x1 << 10)1179#define RT5668_ZCD_SFT 101180#define RT5668_ZCD_PD (0x0 << 10)1181#define RT5668_ZCD_PU (0x1 << 10)1182#define RT5668_SV_DLY_MASK (0xf)1183#define RT5668_SV_DLY_SFT 01184 1185/* Soft volume and zero cross control 2 (0x00da) */1186#define RT5668_ZCD_BST1_CBJ_MASK (0x1 << 7)1187#define RT5668_ZCD_BST1_CBJ_SFT 71188#define RT5668_ZCD_BST1_CBJ_DIS (0x0 << 7)1189#define RT5668_ZCD_BST1_CBJ_EN (0x1 << 7)1190#define RT5668_ZCD_RECMIX_MASK (0x1)1191#define RT5668_ZCD_RECMIX_SFT 01192#define RT5668_ZCD_RECMIX_DIS (0x0)1193#define RT5668_ZCD_RECMIX_EN (0x1)1194 1195/* 4 Button Inline Command Control 2 (0x00e3) */1196#define RT5668_4BTN_IL_MASK (0x1 << 15)1197#define RT5668_4BTN_IL_EN (0x1 << 15)1198#define RT5668_4BTN_IL_DIS (0x0 << 15)1199#define RT5668_4BTN_IL_RST_MASK (0x1 << 14)1200#define RT5668_4BTN_IL_NOR (0x1 << 14)1201#define RT5668_4BTN_IL_RST (0x0 << 14)1202 1203/* Analog JD Control (0x00f0) */1204#define RT5668_JDH_RS_MASK (0x1 << 4)1205#define RT5668_JDH_NO_PLUG (0x1 << 4)1206#define RT5668_JDH_PLUG (0x0 << 4)1207 1208/* Chopper and Clock control for DAC (0x013a)*/1209#define RT5668_CKXEN_DAC1_MASK (0x1 << 13)1210#define RT5668_CKXEN_DAC1_SFT 131211#define RT5668_CKGEN_DAC1_MASK (0x1 << 12)1212#define RT5668_CKGEN_DAC1_SFT 121213 1214/* Chopper and Clock control for ADC (0x013b)*/1215#define RT5668_CKXEN_ADC1_MASK (0x1 << 13)1216#define RT5668_CKXEN_ADC1_SFT 131217#define RT5668_CKGEN_ADC1_MASK (0x1 << 12)1218#define RT5668_CKGEN_ADC1_SFT 121219 1220/* Volume test (0x013f)*/1221#define RT5668_SEL_CLK_VOL_MASK (0x1 << 15)1222#define RT5668_SEL_CLK_VOL_EN (0x1 << 15)1223#define RT5668_SEL_CLK_VOL_DIS (0x0 << 15)1224 1225/* Test Mode Control 1 (0x0145) */1226#define RT5668_AD2DA_LB_MASK (0x1 << 10)1227#define RT5668_AD2DA_LB_SFT 101228 1229/* Stereo Noise Gate Control 1 (0x0160) */1230#define RT5668_NG2_EN_MASK (0x1 << 15)1231#define RT5668_NG2_EN (0x1 << 15)1232#define RT5668_NG2_DIS (0x0 << 15)1233 1234/* Stereo1 DAC Silence Detection Control (0x0190) */1235#define RT5668_DEB_STO_DAC_MASK (0x7 << 4)1236#define RT5668_DEB_80_MS (0x0 << 4)1237 1238/* SAR ADC Inline Command Control 1 (0x0210) */1239#define RT5668_SAR_BUTT_DET_MASK (0x1 << 15)1240#define RT5668_SAR_BUTT_DET_EN (0x1 << 15)1241#define RT5668_SAR_BUTT_DET_DIS (0x0 << 15)1242#define RT5668_SAR_BUTDET_MODE_MASK (0x1 << 14)1243#define RT5668_SAR_BUTDET_POW_SAV (0x1 << 14)1244#define RT5668_SAR_BUTDET_POW_NORM (0x0 << 14)1245#define RT5668_SAR_BUTDET_RST_MASK (0x1 << 13)1246#define RT5668_SAR_BUTDET_RST_NORMAL (0x1 << 13)1247#define RT5668_SAR_BUTDET_RST (0x0 << 13)1248#define RT5668_SAR_POW_MASK (0x1 << 12)1249#define RT5668_SAR_POW_EN (0x1 << 12)1250#define RT5668_SAR_POW_DIS (0x0 << 12)1251#define RT5668_SAR_RST_MASK (0x1 << 11)1252#define RT5668_SAR_RST_NORMAL (0x1 << 11)1253#define RT5668_SAR_RST (0x0 << 11)1254#define RT5668_SAR_BYPASS_MASK (0x1 << 10)1255#define RT5668_SAR_BYPASS_EN (0x1 << 10)1256#define RT5668_SAR_BYPASS_DIS (0x0 << 10)1257#define RT5668_SAR_SEL_MB1_MASK (0x1 << 9)1258#define RT5668_SAR_SEL_MB1_SEL (0x1 << 9)1259#define RT5668_SAR_SEL_MB1_NOSEL (0x0 << 9)1260#define RT5668_SAR_SEL_MB2_MASK (0x1 << 8)1261#define RT5668_SAR_SEL_MB2_SEL (0x1 << 8)1262#define RT5668_SAR_SEL_MB2_NOSEL (0x0 << 8)1263#define RT5668_SAR_SEL_MODE_MASK (0x1 << 7)1264#define RT5668_SAR_SEL_MODE_CMP (0x1 << 7)1265#define RT5668_SAR_SEL_MODE_ADC (0x0 << 7)1266#define RT5668_SAR_SEL_MB1_MB2_MASK (0x1 << 5)1267#define RT5668_SAR_SEL_MB1_MB2_AUTO (0x1 << 5)1268#define RT5668_SAR_SEL_MB1_MB2_MANU (0x0 << 5)1269#define RT5668_SAR_SEL_SIGNAL_MASK (0x1 << 4)1270#define RT5668_SAR_SEL_SIGNAL_AUTO (0x1 << 4)1271#define RT5668_SAR_SEL_SIGNAL_MANU (0x0 << 4)1272 1273/* SAR ADC Inline Command Control 13 (0x021c) */1274#define RT5668_SAR_SOUR_MASK (0x3f)1275#define RT5668_SAR_SOUR_BTN (0x3f)1276#define RT5668_SAR_SOUR_TYPE (0x0)1277 1278 1279/* System Clock Source */1280enum {1281 RT5668_SCLK_S_MCLK,1282 RT5668_SCLK_S_PLL1,1283 RT5668_SCLK_S_PLL2,1284 RT5668_SCLK_S_RCCLK,1285};1286 1287/* PLL Source */1288enum {1289 RT5668_PLL1_S_MCLK,1290 RT5668_PLL1_S_BCLK1,1291 RT5668_PLL1_S_RCCLK,1292};1293 1294enum {1295 RT5668_AIF1,1296 RT5668_AIF2,1297 RT5668_AIFS1298};1299 1300/* filter mask */1301enum {1302 RT5668_DA_STEREO1_FILTER = 0x1,1303 RT5668_AD_STEREO1_FILTER = (0x1 << 1),1304};1305 1306enum {1307 RT5668_CLK_SEL_SYS,1308 RT5668_CLK_SEL_I2S1_ASRC,1309 RT5668_CLK_SEL_I2S2_ASRC,1310};1311 1312int rt5668_sel_asrc_clk_src(struct snd_soc_component *component,1313 unsigned int filter_mask, unsigned int clk_src);1314 1315#endif /* __RT5668_H__ */1316