1809 lines · c
1/* SPDX-License-Identifier: GPL-2.0-only */2/*3 * rt5677.h -- RT5677 ALSA SoC audio driver4 *5 * Copyright 2013 Realtek Semiconductor Corp.6 * Author: Oder Chiou <oder_chiou@realtek.com>7 */8 9#ifndef __RT5677_H__10#define __RT5677_H__11 12#include <linux/gpio/driver.h>13#include <linux/gpio/consumer.h>14 15/* Info */16#define RT5677_RESET 0x0017#define RT5677_VENDOR_ID 0xfd18#define RT5677_VENDOR_ID1 0xfe19#define RT5677_VENDOR_ID2 0xff20/* I/O - Output */21#define RT5677_LOUT1 0x0122/* I/O - Input */23#define RT5677_IN1 0x0324#define RT5677_MICBIAS 0x0425/* I/O - SLIMBus */26#define RT5677_SLIMBUS_PARAM 0x0727#define RT5677_SLIMBUS_RX 0x0828#define RT5677_SLIMBUS_CTRL 0x0929/* I/O */30#define RT5677_SIDETONE_CTRL 0x1331/* I/O - ADC/DAC */32#define RT5677_ANA_DAC1_2_3_SRC 0x1533#define RT5677_IF_DSP_DAC3_4_MIXER 0x1634#define RT5677_DAC4_DIG_VOL 0x1735#define RT5677_DAC3_DIG_VOL 0x1836#define RT5677_DAC1_DIG_VOL 0x1937#define RT5677_DAC2_DIG_VOL 0x1a38#define RT5677_IF_DSP_DAC2_MIXER 0x1b39#define RT5677_STO1_ADC_DIG_VOL 0x1c40#define RT5677_MONO_ADC_DIG_VOL 0x1d41#define RT5677_STO1_2_ADC_BST 0x1e42#define RT5677_STO2_ADC_DIG_VOL 0x1f43/* Mixer - D-D */44#define RT5677_ADC_BST_CTRL2 0x2045#define RT5677_STO3_4_ADC_BST 0x2146#define RT5677_STO3_ADC_DIG_VOL 0x2247#define RT5677_STO4_ADC_DIG_VOL 0x2348#define RT5677_STO4_ADC_MIXER 0x2449#define RT5677_STO3_ADC_MIXER 0x2550#define RT5677_STO2_ADC_MIXER 0x2651#define RT5677_STO1_ADC_MIXER 0x2752#define RT5677_MONO_ADC_MIXER 0x2853#define RT5677_ADC_IF_DSP_DAC1_MIXER 0x2954#define RT5677_STO1_DAC_MIXER 0x2a55#define RT5677_MONO_DAC_MIXER 0x2b56#define RT5677_DD1_MIXER 0x2c57#define RT5677_DD2_MIXER 0x2d58#define RT5677_IF3_DATA 0x2f59#define RT5677_IF4_DATA 0x3060/* Mixer - PDM */61#define RT5677_PDM_OUT_CTRL 0x3162#define RT5677_PDM_DATA_CTRL1 0x3263#define RT5677_PDM_DATA_CTRL2 0x3364#define RT5677_PDM1_DATA_CTRL2 0x3465#define RT5677_PDM1_DATA_CTRL3 0x3566#define RT5677_PDM1_DATA_CTRL4 0x3667#define RT5677_PDM2_DATA_CTRL2 0x3768#define RT5677_PDM2_DATA_CTRL3 0x3869#define RT5677_PDM2_DATA_CTRL4 0x3970/* TDM */71#define RT5677_TDM1_CTRL1 0x3b72#define RT5677_TDM1_CTRL2 0x3c73#define RT5677_TDM1_CTRL3 0x3d74#define RT5677_TDM1_CTRL4 0x3e75#define RT5677_TDM1_CTRL5 0x3f76#define RT5677_TDM2_CTRL1 0x4077#define RT5677_TDM2_CTRL2 0x4178#define RT5677_TDM2_CTRL3 0x4279#define RT5677_TDM2_CTRL4 0x4380#define RT5677_TDM2_CTRL5 0x4481/* I2C_MASTER_CTRL */82#define RT5677_I2C_MASTER_CTRL1 0x4783#define RT5677_I2C_MASTER_CTRL2 0x4884#define RT5677_I2C_MASTER_CTRL3 0x4985#define RT5677_I2C_MASTER_CTRL4 0x4a86#define RT5677_I2C_MASTER_CTRL5 0x4b87#define RT5677_I2C_MASTER_CTRL6 0x4c88#define RT5677_I2C_MASTER_CTRL7 0x4d89#define RT5677_I2C_MASTER_CTRL8 0x4e90/* DMIC */91#define RT5677_DMIC_CTRL1 0x5092#define RT5677_DMIC_CTRL2 0x5193/* Haptic Generator */94#define RT5677_HAP_GENE_CTRL1 0x5695#define RT5677_HAP_GENE_CTRL2 0x5796#define RT5677_HAP_GENE_CTRL3 0x5897#define RT5677_HAP_GENE_CTRL4 0x5998#define RT5677_HAP_GENE_CTRL5 0x5a99#define RT5677_HAP_GENE_CTRL6 0x5b100#define RT5677_HAP_GENE_CTRL7 0x5c101#define RT5677_HAP_GENE_CTRL8 0x5d102#define RT5677_HAP_GENE_CTRL9 0x5e103#define RT5677_HAP_GENE_CTRL10 0x5f104/* Power */105#define RT5677_PWR_DIG1 0x61106#define RT5677_PWR_DIG2 0x62107#define RT5677_PWR_ANLG1 0x63108#define RT5677_PWR_ANLG2 0x64109#define RT5677_PWR_DSP1 0x65110#define RT5677_PWR_DSP_ST 0x66111#define RT5677_PWR_DSP2 0x67112#define RT5677_ADC_DAC_HPF_CTRL1 0x68113/* Private Register Control */114#define RT5677_PRIV_INDEX 0x6a115#define RT5677_PRIV_DATA 0x6c116/* Format - ADC/DAC */117#define RT5677_I2S4_SDP 0x6f118#define RT5677_I2S1_SDP 0x70119#define RT5677_I2S2_SDP 0x71120#define RT5677_I2S3_SDP 0x72121#define RT5677_CLK_TREE_CTRL1 0x73122#define RT5677_CLK_TREE_CTRL2 0x74123#define RT5677_CLK_TREE_CTRL3 0x75124/* Function - Analog */125#define RT5677_PLL1_CTRL1 0x7a126#define RT5677_PLL1_CTRL2 0x7b127#define RT5677_PLL2_CTRL1 0x7c128#define RT5677_PLL2_CTRL2 0x7d129#define RT5677_GLB_CLK1 0x80130#define RT5677_GLB_CLK2 0x81131#define RT5677_ASRC_1 0x83132#define RT5677_ASRC_2 0x84133#define RT5677_ASRC_3 0x85134#define RT5677_ASRC_4 0x86135#define RT5677_ASRC_5 0x87136#define RT5677_ASRC_6 0x88137#define RT5677_ASRC_7 0x89138#define RT5677_ASRC_8 0x8a139#define RT5677_ASRC_9 0x8b140#define RT5677_ASRC_10 0x8c141#define RT5677_ASRC_11 0x8d142#define RT5677_ASRC_12 0x8e143#define RT5677_ASRC_13 0x8f144#define RT5677_ASRC_14 0x90145#define RT5677_ASRC_15 0x91146#define RT5677_ASRC_16 0x92147#define RT5677_ASRC_17 0x93148#define RT5677_ASRC_18 0x94149#define RT5677_ASRC_19 0x95150#define RT5677_ASRC_20 0x97151#define RT5677_ASRC_21 0x98152#define RT5677_ASRC_22 0x99153#define RT5677_ASRC_23 0x9a154#define RT5677_VAD_CTRL1 0x9c155#define RT5677_VAD_CTRL2 0x9d156#define RT5677_VAD_CTRL3 0x9e157#define RT5677_VAD_CTRL4 0x9f158#define RT5677_VAD_CTRL5 0xa0159/* Function - Digital */160#define RT5677_DSP_INB_CTRL1 0xa3161#define RT5677_DSP_INB_CTRL2 0xa4162#define RT5677_DSP_IN_OUTB_CTRL 0xa5163#define RT5677_DSP_OUTB0_1_DIG_VOL 0xa6164#define RT5677_DSP_OUTB2_3_DIG_VOL 0xa7165#define RT5677_DSP_OUTB4_5_DIG_VOL 0xa8166#define RT5677_DSP_OUTB6_7_DIG_VOL 0xa9167#define RT5677_ADC_EQ_CTRL1 0xae168#define RT5677_ADC_EQ_CTRL2 0xaf169#define RT5677_EQ_CTRL1 0xb0170#define RT5677_EQ_CTRL2 0xb1171#define RT5677_EQ_CTRL3 0xb2172#define RT5677_SOFT_VOL_ZERO_CROSS1 0xb3173#define RT5677_JD_CTRL1 0xb5174#define RT5677_JD_CTRL2 0xb6175#define RT5677_JD_CTRL3 0xb8176#define RT5677_IRQ_CTRL1 0xbd177#define RT5677_IRQ_CTRL2 0xbe178#define RT5677_GPIO_ST 0xbf179#define RT5677_GPIO_CTRL1 0xc0180#define RT5677_GPIO_CTRL2 0xc1181#define RT5677_GPIO_CTRL3 0xc2182#define RT5677_STO1_ADC_HI_FILTER1 0xc5183#define RT5677_STO1_ADC_HI_FILTER2 0xc6184#define RT5677_MONO_ADC_HI_FILTER1 0xc7185#define RT5677_MONO_ADC_HI_FILTER2 0xc8186#define RT5677_STO2_ADC_HI_FILTER1 0xc9187#define RT5677_STO2_ADC_HI_FILTER2 0xca188#define RT5677_STO3_ADC_HI_FILTER1 0xcb189#define RT5677_STO3_ADC_HI_FILTER2 0xcc190#define RT5677_STO4_ADC_HI_FILTER1 0xcd191#define RT5677_STO4_ADC_HI_FILTER2 0xce192#define RT5677_MB_DRC_CTRL1 0xd0193#define RT5677_DRC1_CTRL1 0xd2194#define RT5677_DRC1_CTRL2 0xd3195#define RT5677_DRC1_CTRL3 0xd4196#define RT5677_DRC1_CTRL4 0xd5197#define RT5677_DRC1_CTRL5 0xd6198#define RT5677_DRC1_CTRL6 0xd7199#define RT5677_DRC2_CTRL1 0xd8200#define RT5677_DRC2_CTRL2 0xd9201#define RT5677_DRC2_CTRL3 0xda202#define RT5677_DRC2_CTRL4 0xdb203#define RT5677_DRC2_CTRL5 0xdc204#define RT5677_DRC2_CTRL6 0xdd205#define RT5677_DRC1_HL_CTRL1 0xde206#define RT5677_DRC1_HL_CTRL2 0xdf207#define RT5677_DRC2_HL_CTRL1 0xe0208#define RT5677_DRC2_HL_CTRL2 0xe1209#define RT5677_DSP_INB1_SRC_CTRL1 0xe3210#define RT5677_DSP_INB1_SRC_CTRL2 0xe4211#define RT5677_DSP_INB1_SRC_CTRL3 0xe5212#define RT5677_DSP_INB1_SRC_CTRL4 0xe6213#define RT5677_DSP_INB2_SRC_CTRL1 0xe7214#define RT5677_DSP_INB2_SRC_CTRL2 0xe8215#define RT5677_DSP_INB2_SRC_CTRL3 0xe9216#define RT5677_DSP_INB2_SRC_CTRL4 0xea217#define RT5677_DSP_INB3_SRC_CTRL1 0xeb218#define RT5677_DSP_INB3_SRC_CTRL2 0xec219#define RT5677_DSP_INB3_SRC_CTRL3 0xed220#define RT5677_DSP_INB3_SRC_CTRL4 0xee221#define RT5677_DSP_OUTB1_SRC_CTRL1 0xef222#define RT5677_DSP_OUTB1_SRC_CTRL2 0xf0223#define RT5677_DSP_OUTB1_SRC_CTRL3 0xf1224#define RT5677_DSP_OUTB1_SRC_CTRL4 0xf2225#define RT5677_DSP_OUTB2_SRC_CTRL1 0xf3226#define RT5677_DSP_OUTB2_SRC_CTRL2 0xf4227#define RT5677_DSP_OUTB2_SRC_CTRL3 0xf5228#define RT5677_DSP_OUTB2_SRC_CTRL4 0xf6229 230/* Virtual DSP Mixer Control */231#define RT5677_DSP_OUTB_0123_MIXER_CTRL 0xf7232#define RT5677_DSP_OUTB_45_MIXER_CTRL 0xf8233#define RT5677_DSP_OUTB_67_MIXER_CTRL 0xf9234 235/* General Control */236#define RT5677_DIG_MISC 0xfa237#define RT5677_GEN_CTRL1 0xfb238#define RT5677_GEN_CTRL2 0xfc239 240/* DSP Mode I2C Control*/241#define RT5677_DSP_I2C_OP_CODE 0x00242#define RT5677_DSP_I2C_ADDR_LSB 0x01243#define RT5677_DSP_I2C_ADDR_MSB 0x02244#define RT5677_DSP_I2C_DATA_LSB 0x03245#define RT5677_DSP_I2C_DATA_MSB 0x04246 247/* Index of Codec Private Register definition */248#define RT5677_PR_DRC1_CTRL_1 0x01249#define RT5677_PR_DRC1_CTRL_2 0x02250#define RT5677_PR_DRC1_CTRL_3 0x03251#define RT5677_PR_DRC1_CTRL_4 0x04252#define RT5677_PR_DRC1_CTRL_5 0x05253#define RT5677_PR_DRC1_CTRL_6 0x06254#define RT5677_PR_DRC1_CTRL_7 0x07255#define RT5677_PR_DRC2_CTRL_1 0x08256#define RT5677_PR_DRC2_CTRL_2 0x09257#define RT5677_PR_DRC2_CTRL_3 0x0a258#define RT5677_PR_DRC2_CTRL_4 0x0b259#define RT5677_PR_DRC2_CTRL_5 0x0c260#define RT5677_PR_DRC2_CTRL_6 0x0d261#define RT5677_PR_DRC2_CTRL_7 0x0e262#define RT5677_BIAS_CUR1 0x10263#define RT5677_BIAS_CUR2 0x12264#define RT5677_BIAS_CUR3 0x13265#define RT5677_BIAS_CUR4 0x14266#define RT5677_BIAS_CUR5 0x15267#define RT5677_VREF_LOUT_CTRL 0x17268#define RT5677_DIG_VOL_CTRL1 0x1a269#define RT5677_DIG_VOL_CTRL2 0x1b270#define RT5677_ANA_ADC_GAIN_CTRL 0x1e271#define RT5677_VAD_SRAM_TEST1 0x20272#define RT5677_VAD_SRAM_TEST2 0x21273#define RT5677_VAD_SRAM_TEST3 0x22274#define RT5677_VAD_SRAM_TEST4 0x23275#define RT5677_PAD_DRV_CTRL 0x26276#define RT5677_DIG_IN_PIN_ST_CTRL1 0x29277#define RT5677_DIG_IN_PIN_ST_CTRL2 0x2a278#define RT5677_DIG_IN_PIN_ST_CTRL3 0x2b279#define RT5677_PLL1_INT 0x38280#define RT5677_PLL2_INT 0x39281#define RT5677_TEST_CTRL1 0x3a282#define RT5677_TEST_CTRL2 0x3b283#define RT5677_TEST_CTRL3 0x3c284#define RT5677_CHOP_DAC_ADC 0x3d285#define RT5677_SOFT_DEPOP_DAC_CLK_CTRL 0x3e286#define RT5677_CROSS_OVER_FILTER1 0x90287#define RT5677_CROSS_OVER_FILTER2 0x91288#define RT5677_CROSS_OVER_FILTER3 0x92289#define RT5677_CROSS_OVER_FILTER4 0x93290#define RT5677_CROSS_OVER_FILTER5 0x94291#define RT5677_CROSS_OVER_FILTER6 0x95292#define RT5677_CROSS_OVER_FILTER7 0x96293#define RT5677_CROSS_OVER_FILTER8 0x97294#define RT5677_CROSS_OVER_FILTER9 0x98295#define RT5677_CROSS_OVER_FILTER10 0x99296 297/* global definition */298#define RT5677_L_MUTE (0x1 << 15)299#define RT5677_L_MUTE_SFT 15300#define RT5677_VOL_L_MUTE (0x1 << 14)301#define RT5677_VOL_L_SFT 14302#define RT5677_R_MUTE (0x1 << 7)303#define RT5677_R_MUTE_SFT 7304#define RT5677_VOL_R_MUTE (0x1 << 6)305#define RT5677_VOL_R_SFT 6306#define RT5677_L_VOL_MASK (0x7f << 9)307#define RT5677_L_VOL_SFT 9308#define RT5677_R_VOL_MASK (0x7f << 1)309#define RT5677_R_VOL_SFT 1310 311/* LOUT1 Control (0x01) */312#define RT5677_LOUT1_L_MUTE (0x1 << 15)313#define RT5677_LOUT1_L_MUTE_SFT (15)314#define RT5677_LOUT1_L_DF (0x1 << 14)315#define RT5677_LOUT1_L_DF_SFT (14)316#define RT5677_LOUT2_L_MUTE (0x1 << 13)317#define RT5677_LOUT2_L_MUTE_SFT (13)318#define RT5677_LOUT2_L_DF (0x1 << 12)319#define RT5677_LOUT2_L_DF_SFT (12)320#define RT5677_LOUT3_L_MUTE (0x1 << 11)321#define RT5677_LOUT3_L_MUTE_SFT (11)322#define RT5677_LOUT3_L_DF (0x1 << 10)323#define RT5677_LOUT3_L_DF_SFT (10)324#define RT5677_LOUT1_ENH_DRV (0x1 << 9)325#define RT5677_LOUT1_ENH_DRV_SFT (9)326#define RT5677_LOUT2_ENH_DRV (0x1 << 8)327#define RT5677_LOUT2_ENH_DRV_SFT (8)328#define RT5677_LOUT3_ENH_DRV (0x1 << 7)329#define RT5677_LOUT3_ENH_DRV_SFT (7)330 331/* IN1 Control (0x03) */332#define RT5677_BST_MASK1 (0xf << 12)333#define RT5677_BST_SFT1 12334#define RT5677_BST_MASK2 (0xf << 8)335#define RT5677_BST_SFT2 8336#define RT5677_IN_DF1 (0x1 << 7)337#define RT5677_IN_DF1_SFT 7338#define RT5677_IN_DF2 (0x1 << 6)339#define RT5677_IN_DF2_SFT 6340 341/* Micbias Control (0x04) */342#define RT5677_MICBIAS1_OUTVOLT_MASK (0x1 << 15)343#define RT5677_MICBIAS1_OUTVOLT_SFT (15)344#define RT5677_MICBIAS1_OUTVOLT_2_7V (0x0 << 15)345#define RT5677_MICBIAS1_OUTVOLT_2_25V (0x1 << 15)346#define RT5677_MICBIAS1_CTRL_VDD_MASK (0x1 << 14)347#define RT5677_MICBIAS1_CTRL_VDD_SFT (14)348#define RT5677_MICBIAS1_CTRL_VDD_1_8V (0x0 << 14)349#define RT5677_MICBIAS1_CTRL_VDD_3_3V (0x1 << 14)350#define RT5677_MICBIAS1_OVCD_MASK (0x1 << 11)351#define RT5677_MICBIAS1_OVCD_SHIFT (11)352#define RT5677_MICBIAS1_OVCD_DIS (0x0 << 11)353#define RT5677_MICBIAS1_OVCD_EN (0x1 << 11)354#define RT5677_MICBIAS1_OVTH_MASK (0x3 << 9)355#define RT5677_MICBIAS1_OVTH_SFT 9356#define RT5677_MICBIAS1_OVTH_640UA (0x0 << 9)357#define RT5677_MICBIAS1_OVTH_1280UA (0x1 << 9)358#define RT5677_MICBIAS1_OVTH_1920UA (0x2 << 9)359 360/* SLIMbus Parameter (0x07) */361 362/* SLIMbus Rx (0x08) */363#define RT5677_SLB_ADC4_MASK (0x3 << 6)364#define RT5677_SLB_ADC4_SFT 6365#define RT5677_SLB_ADC3_MASK (0x3 << 4)366#define RT5677_SLB_ADC3_SFT 4367#define RT5677_SLB_ADC2_MASK (0x3 << 2)368#define RT5677_SLB_ADC2_SFT 2369#define RT5677_SLB_ADC1_MASK (0x3 << 0)370#define RT5677_SLB_ADC1_SFT 0371 372/* SLIMBus control (0x09) */373 374/* Sidetone Control (0x13) */375#define RT5677_ST_HPF_SEL_MASK (0x7 << 13)376#define RT5677_ST_HPF_SEL_SFT 13377#define RT5677_ST_HPF_PATH (0x1 << 12)378#define RT5677_ST_HPF_PATH_SFT 12379#define RT5677_ST_SEL_MASK (0x7 << 9)380#define RT5677_ST_SEL_SFT 9381#define RT5677_ST_EN (0x1 << 6)382#define RT5677_ST_EN_SFT 6383#define RT5677_ST_GAIN (0x1 << 5)384#define RT5677_ST_GAIN_SFT 5385#define RT5677_ST_VOL_MASK (0x1f << 0)386#define RT5677_ST_VOL_SFT 0387 388/* Analog DAC1/2/3 Source Control (0x15) */389#define RT5677_ANA_DAC3_SRC_SEL_MASK (0x3 << 4)390#define RT5677_ANA_DAC3_SRC_SEL_SFT 4391#define RT5677_ANA_DAC1_2_SRC_SEL_MASK (0x3 << 0)392#define RT5677_ANA_DAC1_2_SRC_SEL_SFT 0393 394/* IF/DSP to DAC3/4 Mixer Control (0x16) */395#define RT5677_M_DAC4_L_VOL (0x1 << 15)396#define RT5677_M_DAC4_L_VOL_SFT 15397#define RT5677_SEL_DAC4_L_SRC_MASK (0x7 << 12)398#define RT5677_SEL_DAC4_L_SRC_SFT 12399#define RT5677_M_DAC4_R_VOL (0x1 << 11)400#define RT5677_M_DAC4_R_VOL_SFT 11401#define RT5677_SEL_DAC4_R_SRC_MASK (0x7 << 8)402#define RT5677_SEL_DAC4_R_SRC_SFT 8403#define RT5677_M_DAC3_L_VOL (0x1 << 7)404#define RT5677_M_DAC3_L_VOL_SFT 7405#define RT5677_SEL_DAC3_L_SRC_MASK (0x7 << 4)406#define RT5677_SEL_DAC3_L_SRC_SFT 4407#define RT5677_M_DAC3_R_VOL (0x1 << 3)408#define RT5677_M_DAC3_R_VOL_SFT 3409#define RT5677_SEL_DAC3_R_SRC_MASK (0x7 << 0)410#define RT5677_SEL_DAC3_R_SRC_SFT 0411 412/* DAC4 Digital Volume (0x17) */413#define RT5677_DAC4_L_VOL_MASK (0xff << 8)414#define RT5677_DAC4_L_VOL_SFT 8415#define RT5677_DAC4_R_VOL_MASK (0xff)416#define RT5677_DAC4_R_VOL_SFT 0417 418/* DAC3 Digital Volume (0x18) */419#define RT5677_DAC3_L_VOL_MASK (0xff << 8)420#define RT5677_DAC3_L_VOL_SFT 8421#define RT5677_DAC3_R_VOL_MASK (0xff)422#define RT5677_DAC3_R_VOL_SFT 0423 424/* DAC3 Digital Volume (0x19) */425#define RT5677_DAC1_L_VOL_MASK (0xff << 8)426#define RT5677_DAC1_L_VOL_SFT 8427#define RT5677_DAC1_R_VOL_MASK (0xff)428#define RT5677_DAC1_R_VOL_SFT 0429 430/* DAC2 Digital Volume (0x1a) */431#define RT5677_DAC2_L_VOL_MASK (0xff << 8)432#define RT5677_DAC2_L_VOL_SFT 8433#define RT5677_DAC2_R_VOL_MASK (0xff)434#define RT5677_DAC2_R_VOL_SFT 0435 436/* IF/DSP to DAC2 Mixer Control (0x1b) */437#define RT5677_M_DAC2_L_VOL (0x1 << 7)438#define RT5677_M_DAC2_L_VOL_SFT 7439#define RT5677_SEL_DAC2_L_SRC_MASK (0x7 << 4)440#define RT5677_SEL_DAC2_L_SRC_SFT 4441#define RT5677_M_DAC2_R_VOL (0x1 << 3)442#define RT5677_M_DAC2_R_VOL_SFT 3443#define RT5677_SEL_DAC2_R_SRC_MASK (0x7 << 0)444#define RT5677_SEL_DAC2_R_SRC_SFT 0445 446/* Stereo1 ADC Digital Volume Control (0x1c) */447#define RT5677_STO1_ADC_L_VOL_MASK (0x3f << 9)448#define RT5677_STO1_ADC_L_VOL_SFT 9449#define RT5677_STO1_ADC_R_VOL_MASK (0x3f << 1)450#define RT5677_STO1_ADC_R_VOL_SFT 1451 452/* Mono ADC Digital Volume Control (0x1d) */453#define RT5677_MONO_ADC_L_VOL_MASK (0x3f << 9)454#define RT5677_MONO_ADC_L_VOL_SFT 9455#define RT5677_MONO_ADC_R_VOL_MASK (0x3f << 1)456#define RT5677_MONO_ADC_R_VOL_SFT 1457 458/* Stereo 1/2 ADC Boost Gain Control (0x1e) */459#define RT5677_STO1_ADC_L_BST_MASK (0x3 << 14)460#define RT5677_STO1_ADC_L_BST_SFT 14461#define RT5677_STO1_ADC_R_BST_MASK (0x3 << 12)462#define RT5677_STO1_ADC_R_BST_SFT 12463#define RT5677_STO1_ADC_COMP_MASK (0x3 << 10)464#define RT5677_STO1_ADC_COMP_SFT 10465#define RT5677_STO2_ADC_L_BST_MASK (0x3 << 8)466#define RT5677_STO2_ADC_L_BST_SFT 8467#define RT5677_STO2_ADC_R_BST_MASK (0x3 << 6)468#define RT5677_STO2_ADC_R_BST_SFT 6469#define RT5677_STO2_ADC_COMP_MASK (0x3 << 4)470#define RT5677_STO2_ADC_COMP_SFT 4471 472/* Stereo2 ADC Digital Volume Control (0x1f) */473#define RT5677_STO2_ADC_L_VOL_MASK (0x7f << 8)474#define RT5677_STO2_ADC_L_VOL_SFT 8475#define RT5677_STO2_ADC_R_VOL_MASK (0x7f)476#define RT5677_STO2_ADC_R_VOL_SFT 0477 478/* ADC Boost Gain Control 2 (0x20) */479#define RT5677_MONO_ADC_L_BST_MASK (0x3 << 14)480#define RT5677_MONO_ADC_L_BST_SFT 14481#define RT5677_MONO_ADC_R_BST_MASK (0x3 << 12)482#define RT5677_MONO_ADC_R_BST_SFT 12483#define RT5677_MONO_ADC_COMP_MASK (0x3 << 10)484#define RT5677_MONO_ADC_COMP_SFT 10485 486/* Stereo 3/4 ADC Boost Gain Control (0x21) */487#define RT5677_STO3_ADC_L_BST_MASK (0x3 << 14)488#define RT5677_STO3_ADC_L_BST_SFT 14489#define RT5677_STO3_ADC_R_BST_MASK (0x3 << 12)490#define RT5677_STO3_ADC_R_BST_SFT 12491#define RT5677_STO3_ADC_COMP_MASK (0x3 << 10)492#define RT5677_STO3_ADC_COMP_SFT 10493#define RT5677_STO4_ADC_L_BST_MASK (0x3 << 8)494#define RT5677_STO4_ADC_L_BST_SFT 8495#define RT5677_STO4_ADC_R_BST_MASK (0x3 << 6)496#define RT5677_STO4_ADC_R_BST_SFT 6497#define RT5677_STO4_ADC_COMP_MASK (0x3 << 4)498#define RT5677_STO4_ADC_COMP_SFT 4499 500/* Stereo3 ADC Digital Volume Control (0x22) */501#define RT5677_STO3_ADC_L_VOL_MASK (0x7f << 8)502#define RT5677_STO3_ADC_L_VOL_SFT 8503#define RT5677_STO3_ADC_R_VOL_MASK (0x7f)504#define RT5677_STO3_ADC_R_VOL_SFT 0505 506/* Stereo4 ADC Digital Volume Control (0x23) */507#define RT5677_STO4_ADC_L_VOL_MASK (0x7f << 8)508#define RT5677_STO4_ADC_L_VOL_SFT 8509#define RT5677_STO4_ADC_R_VOL_MASK (0x7f)510#define RT5677_STO4_ADC_R_VOL_SFT 0511 512/* Stereo4 ADC Mixer control (0x24) */513#define RT5677_M_STO4_ADC_L2 (0x1 << 15)514#define RT5677_M_STO4_ADC_L2_SFT 15515#define RT5677_M_STO4_ADC_L1 (0x1 << 14)516#define RT5677_M_STO4_ADC_L1_SFT 14517#define RT5677_SEL_STO4_ADC1_MASK (0x3 << 12)518#define RT5677_SEL_STO4_ADC1_SFT 12519#define RT5677_SEL_STO4_ADC2_MASK (0x3 << 10)520#define RT5677_SEL_STO4_ADC2_SFT 10521#define RT5677_SEL_STO4_DMIC_MASK (0x3 << 8)522#define RT5677_SEL_STO4_DMIC_SFT 8523#define RT5677_M_STO4_ADC_R1 (0x1 << 7)524#define RT5677_M_STO4_ADC_R1_SFT 7525#define RT5677_M_STO4_ADC_R2 (0x1 << 6)526#define RT5677_M_STO4_ADC_R2_SFT 6527 528/* Stereo3 ADC Mixer control (0x25) */529#define RT5677_M_STO3_ADC_L2 (0x1 << 15)530#define RT5677_M_STO3_ADC_L2_SFT 15531#define RT5677_M_STO3_ADC_L1 (0x1 << 14)532#define RT5677_M_STO3_ADC_L1_SFT 14533#define RT5677_SEL_STO3_ADC1_MASK (0x3 << 12)534#define RT5677_SEL_STO3_ADC1_SFT 12535#define RT5677_SEL_STO3_ADC2_MASK (0x3 << 10)536#define RT5677_SEL_STO3_ADC2_SFT 10537#define RT5677_SEL_STO3_DMIC_MASK (0x3 << 8)538#define RT5677_SEL_STO3_DMIC_SFT 8539#define RT5677_M_STO3_ADC_R1 (0x1 << 7)540#define RT5677_M_STO3_ADC_R1_SFT 7541#define RT5677_M_STO3_ADC_R2 (0x1 << 6)542#define RT5677_M_STO3_ADC_R2_SFT 6543 544/* Stereo2 ADC Mixer Control (0x26) */545#define RT5677_M_STO2_ADC_L2 (0x1 << 15)546#define RT5677_M_STO2_ADC_L2_SFT 15547#define RT5677_M_STO2_ADC_L1 (0x1 << 14)548#define RT5677_M_STO2_ADC_L1_SFT 14549#define RT5677_SEL_STO2_ADC1_MASK (0x3 << 12)550#define RT5677_SEL_STO2_ADC1_SFT 12551#define RT5677_SEL_STO2_ADC2_MASK (0x3 << 10)552#define RT5677_SEL_STO2_ADC2_SFT 10553#define RT5677_SEL_STO2_DMIC_MASK (0x3 << 8)554#define RT5677_SEL_STO2_DMIC_SFT 8555#define RT5677_M_STO2_ADC_R1 (0x1 << 7)556#define RT5677_M_STO2_ADC_R1_SFT 7557#define RT5677_M_STO2_ADC_R2 (0x1 << 6)558#define RT5677_M_STO2_ADC_R2_SFT 6559#define RT5677_SEL_STO2_LR_MIX_MASK (0x1 << 0)560#define RT5677_SEL_STO2_LR_MIX_SFT 0561#define RT5677_SEL_STO2_LR_MIX_L (0x0 << 0)562#define RT5677_SEL_STO2_LR_MIX_LR (0x1 << 0)563 564/* Stereo1 ADC Mixer control (0x27) */565#define RT5677_M_STO1_ADC_L2 (0x1 << 15)566#define RT5677_M_STO1_ADC_L2_SFT 15567#define RT5677_M_STO1_ADC_L1 (0x1 << 14)568#define RT5677_M_STO1_ADC_L1_SFT 14569#define RT5677_SEL_STO1_ADC1_MASK (0x3 << 12)570#define RT5677_SEL_STO1_ADC1_SFT 12571#define RT5677_SEL_STO1_ADC2_MASK (0x3 << 10)572#define RT5677_SEL_STO1_ADC2_SFT 10573#define RT5677_SEL_STO1_DMIC_MASK (0x3 << 8)574#define RT5677_SEL_STO1_DMIC_SFT 8575#define RT5677_M_STO1_ADC_R1 (0x1 << 7)576#define RT5677_M_STO1_ADC_R1_SFT 7577#define RT5677_M_STO1_ADC_R2 (0x1 << 6)578#define RT5677_M_STO1_ADC_R2_SFT 6579 580/* Mono ADC Mixer control (0x28) */581#define RT5677_M_MONO_ADC_L2 (0x1 << 15)582#define RT5677_M_MONO_ADC_L2_SFT 15583#define RT5677_M_MONO_ADC_L1 (0x1 << 14)584#define RT5677_M_MONO_ADC_L1_SFT 14585#define RT5677_SEL_MONO_ADC_L1_MASK (0x3 << 12)586#define RT5677_SEL_MONO_ADC_L1_SFT 12587#define RT5677_SEL_MONO_ADC_L2_MASK (0x3 << 10)588#define RT5677_SEL_MONO_ADC_L2_SFT 10589#define RT5677_SEL_MONO_DMIC_L_MASK (0x3 << 8)590#define RT5677_SEL_MONO_DMIC_L_SFT 8591#define RT5677_M_MONO_ADC_R1 (0x1 << 7)592#define RT5677_M_MONO_ADC_R1_SFT 7593#define RT5677_M_MONO_ADC_R2 (0x1 << 6)594#define RT5677_M_MONO_ADC_R2_SFT 6595#define RT5677_SEL_MONO_ADC_R1_MASK (0x3 << 4)596#define RT5677_SEL_MONO_ADC_R1_SFT 4597#define RT5677_SEL_MONO_ADC_R2_MASK (0x3 << 2)598#define RT5677_SEL_MONO_ADC_R2_SFT 2599#define RT5677_SEL_MONO_DMIC_R_MASK (0x3 << 0)600#define RT5677_SEL_MONO_DMIC_R_SFT 0601 602/* ADC/IF/DSP to DAC1 Mixer control (0x29) */603#define RT5677_M_ADDA_MIXER1_L (0x1 << 15)604#define RT5677_M_ADDA_MIXER1_L_SFT 15605#define RT5677_M_DAC1_L (0x1 << 14)606#define RT5677_M_DAC1_L_SFT 14607#define RT5677_DAC1_L_SEL_MASK (0x7 << 8)608#define RT5677_DAC1_L_SEL_SFT 8609#define RT5677_M_ADDA_MIXER1_R (0x1 << 7)610#define RT5677_M_ADDA_MIXER1_R_SFT 7611#define RT5677_M_DAC1_R (0x1 << 6)612#define RT5677_M_DAC1_R_SFT 6613#define RT5677_ADDA1_SEL_MASK (0x3 << 0)614#define RT5677_ADDA1_SEL_SFT 0615 616/* Stereo1 DAC Mixer L/R Control (0x2a) */617#define RT5677_M_ST_DAC1_L (0x1 << 15)618#define RT5677_M_ST_DAC1_L_SFT 15619#define RT5677_M_DAC1_L_STO_L (0x1 << 13)620#define RT5677_M_DAC1_L_STO_L_SFT 13621#define RT5677_DAC1_L_STO_L_VOL_MASK (0x1 << 12)622#define RT5677_DAC1_L_STO_L_VOL_SFT 12623#define RT5677_M_DAC2_L_STO_L (0x1 << 11)624#define RT5677_M_DAC2_L_STO_L_SFT 11625#define RT5677_DAC2_L_STO_L_VOL_MASK (0x1 << 10)626#define RT5677_DAC2_L_STO_L_VOL_SFT 10627#define RT5677_M_DAC1_R_STO_L (0x1 << 9)628#define RT5677_M_DAC1_R_STO_L_SFT 9629#define RT5677_DAC1_R_STO_L_VOL_MASK (0x1 << 8)630#define RT5677_DAC1_R_STO_L_VOL_SFT 8631#define RT5677_M_ST_DAC1_R (0x1 << 7)632#define RT5677_M_ST_DAC1_R_SFT 7633#define RT5677_M_DAC1_R_STO_R (0x1 << 5)634#define RT5677_M_DAC1_R_STO_R_SFT 5635#define RT5677_DAC1_R_STO_R_VOL_MASK (0x1 << 4)636#define RT5677_DAC1_R_STO_R_VOL_SFT 4637#define RT5677_M_DAC2_R_STO_R (0x1 << 3)638#define RT5677_M_DAC2_R_STO_R_SFT 3639#define RT5677_DAC2_R_STO_R_VOL_MASK (0x1 << 2)640#define RT5677_DAC2_R_STO_R_VOL_SFT 2641#define RT5677_M_DAC1_L_STO_R (0x1 << 1)642#define RT5677_M_DAC1_L_STO_R_SFT 1643#define RT5677_DAC1_L_STO_R_VOL_MASK (0x1 << 0)644#define RT5677_DAC1_L_STO_R_VOL_SFT 0645 646/* Mono DAC Mixer L/R Control (0x2b) */647#define RT5677_M_ST_DAC2_L (0x1 << 15)648#define RT5677_M_ST_DAC2_L_SFT 15649#define RT5677_M_DAC2_L_MONO_L (0x1 << 13)650#define RT5677_M_DAC2_L_MONO_L_SFT 13651#define RT5677_DAC2_L_MONO_L_VOL_MASK (0x1 << 12)652#define RT5677_DAC2_L_MONO_L_VOL_SFT 12653#define RT5677_M_DAC2_R_MONO_L (0x1 << 11)654#define RT5677_M_DAC2_R_MONO_L_SFT 11655#define RT5677_DAC2_R_MONO_L_VOL_MASK (0x1 << 10)656#define RT5677_DAC2_R_MONO_L_VOL_SFT 10657#define RT5677_M_DAC1_L_MONO_L (0x1 << 9)658#define RT5677_M_DAC1_L_MONO_L_SFT 9659#define RT5677_DAC1_L_MONO_L_VOL_MASK (0x1 << 8)660#define RT5677_DAC1_L_MONO_L_VOL_SFT 8661#define RT5677_M_ST_DAC2_R (0x1 << 7)662#define RT5677_M_ST_DAC2_R_SFT 7663#define RT5677_M_DAC2_R_MONO_R (0x1 << 5)664#define RT5677_M_DAC2_R_MONO_R_SFT 5665#define RT5677_DAC2_R_MONO_R_VOL_MASK (0x1 << 4)666#define RT5677_DAC2_R_MONO_R_VOL_SFT 4667#define RT5677_M_DAC1_R_MONO_R (0x1 << 3)668#define RT5677_M_DAC1_R_MONO_R_SFT 3669#define RT5677_DAC1_R_MONO_R_VOL_MASK (0x1 << 2)670#define RT5677_DAC1_R_MONO_R_VOL_SFT 2671#define RT5677_M_DAC2_L_MONO_R (0x1 << 1)672#define RT5677_M_DAC2_L_MONO_R_SFT 1673#define RT5677_DAC2_L_MONO_R_VOL_MASK (0x1 << 0)674#define RT5677_DAC2_L_MONO_R_VOL_SFT 0675 676/* DD Mixer 1 Control (0x2c) */677#define RT5677_M_STO_L_DD1_L (0x1 << 15)678#define RT5677_M_STO_L_DD1_L_SFT 15679#define RT5677_STO_L_DD1_L_VOL_MASK (0x1 << 14)680#define RT5677_STO_L_DD1_L_VOL_SFT 14681#define RT5677_M_MONO_L_DD1_L (0x1 << 13)682#define RT5677_M_MONO_L_DD1_L_SFT 13683#define RT5677_MONO_L_DD1_L_VOL_MASK (0x1 << 12)684#define RT5677_MONO_L_DD1_L_VOL_SFT 12685#define RT5677_M_DAC3_L_DD1_L (0x1 << 11)686#define RT5677_M_DAC3_L_DD1_L_SFT 11687#define RT5677_DAC3_L_DD1_L_VOL_MASK (0x1 << 10)688#define RT5677_DAC3_L_DD1_L_VOL_SFT 10689#define RT5677_M_DAC3_R_DD1_L (0x1 << 9)690#define RT5677_M_DAC3_R_DD1_L_SFT 9691#define RT5677_DAC3_R_DD1_L_VOL_MASK (0x1 << 8)692#define RT5677_DAC3_R_DD1_L_VOL_SFT 8693#define RT5677_M_STO_R_DD1_R (0x1 << 7)694#define RT5677_M_STO_R_DD1_R_SFT 7695#define RT5677_STO_R_DD1_R_VOL_MASK (0x1 << 6)696#define RT5677_STO_R_DD1_R_VOL_SFT 6697#define RT5677_M_MONO_R_DD1_R (0x1 << 5)698#define RT5677_M_MONO_R_DD1_R_SFT 5699#define RT5677_MONO_R_DD1_R_VOL_MASK (0x1 << 4)700#define RT5677_MONO_R_DD1_R_VOL_SFT 4701#define RT5677_M_DAC3_R_DD1_R (0x1 << 3)702#define RT5677_M_DAC3_R_DD1_R_SFT 3703#define RT5677_DAC3_R_DD1_R_VOL_MASK (0x1 << 2)704#define RT5677_DAC3_R_DD1_R_VOL_SFT 2705#define RT5677_M_DAC3_L_DD1_R (0x1 << 1)706#define RT5677_M_DAC3_L_DD1_R_SFT 1707#define RT5677_DAC3_L_DD1_R_VOL_MASK (0x1 << 0)708#define RT5677_DAC3_L_DD1_R_VOL_SFT 0709 710/* DD Mixer 2 Control (0x2d) */711#define RT5677_M_STO_L_DD2_L (0x1 << 15)712#define RT5677_M_STO_L_DD2_L_SFT 15713#define RT5677_STO_L_DD2_L_VOL_MASK (0x1 << 14)714#define RT5677_STO_L_DD2_L_VOL_SFT 14715#define RT5677_M_MONO_L_DD2_L (0x1 << 13)716#define RT5677_M_MONO_L_DD2_L_SFT 13717#define RT5677_MONO_L_DD2_L_VOL_MASK (0x1 << 12)718#define RT5677_MONO_L_DD2_L_VOL_SFT 12719#define RT5677_M_DAC4_L_DD2_L (0x1 << 11)720#define RT5677_M_DAC4_L_DD2_L_SFT 11721#define RT5677_DAC4_L_DD2_L_VOL_MASK (0x1 << 10)722#define RT5677_DAC4_L_DD2_L_VOL_SFT 10723#define RT5677_M_DAC4_R_DD2_L (0x1 << 9)724#define RT5677_M_DAC4_R_DD2_L_SFT 9725#define RT5677_DAC4_R_DD2_L_VOL_MASK (0x1 << 8)726#define RT5677_DAC4_R_DD2_L_VOL_SFT 8727#define RT5677_M_STO_R_DD2_R (0x1 << 7)728#define RT5677_M_STO_R_DD2_R_SFT 7729#define RT5677_STO_R_DD2_R_VOL_MASK (0x1 << 6)730#define RT5677_STO_R_DD2_R_VOL_SFT 6731#define RT5677_M_MONO_R_DD2_R (0x1 << 5)732#define RT5677_M_MONO_R_DD2_R_SFT 5733#define RT5677_MONO_R_DD2_R_VOL_MASK (0x1 << 4)734#define RT5677_MONO_R_DD2_R_VOL_SFT 4735#define RT5677_M_DAC4_R_DD2_R (0x1 << 3)736#define RT5677_M_DAC4_R_DD2_R_SFT 3737#define RT5677_DAC4_R_DD2_R_VOL_MASK (0x1 << 2)738#define RT5677_DAC4_R_DD2_R_VOL_SFT 2739#define RT5677_M_DAC4_L_DD2_R (0x1 << 1)740#define RT5677_M_DAC4_L_DD2_R_SFT 1741#define RT5677_DAC4_L_DD2_R_VOL_MASK (0x1 << 0)742#define RT5677_DAC4_L_DD2_R_VOL_SFT 0743 744/* IF3 data control (0x2f) */745#define RT5677_IF3_DAC_SEL_MASK (0x3 << 6)746#define RT5677_IF3_DAC_SEL_SFT 6747#define RT5677_IF3_ADC_SEL_MASK (0x3 << 4)748#define RT5677_IF3_ADC_SEL_SFT 4749#define RT5677_IF3_ADC_IN_MASK (0xf << 0)750#define RT5677_IF3_ADC_IN_SFT 0751 752/* IF4 data control (0x30) */753#define RT5677_IF4_ADC_IN_MASK (0xf << 4)754#define RT5677_IF4_ADC_IN_SFT 4755#define RT5677_IF4_DAC_SEL_MASK (0x3 << 2)756#define RT5677_IF4_DAC_SEL_SFT 2757#define RT5677_IF4_ADC_SEL_MASK (0x3 << 0)758#define RT5677_IF4_ADC_SEL_SFT 0759 760/* PDM Output Control (0x31) */761#define RT5677_M_PDM1_L (0x1 << 15)762#define RT5677_M_PDM1_L_SFT 15763#define RT5677_SEL_PDM1_L_MASK (0x3 << 12)764#define RT5677_SEL_PDM1_L_SFT 12765#define RT5677_M_PDM1_R (0x1 << 11)766#define RT5677_M_PDM1_R_SFT 11767#define RT5677_SEL_PDM1_R_MASK (0x3 << 8)768#define RT5677_SEL_PDM1_R_SFT 8769#define RT5677_M_PDM2_L (0x1 << 7)770#define RT5677_M_PDM2_L_SFT 7771#define RT5677_SEL_PDM2_L_MASK (0x3 << 4)772#define RT5677_SEL_PDM2_L_SFT 4773#define RT5677_M_PDM2_R (0x1 << 3)774#define RT5677_M_PDM2_R_SFT 3775#define RT5677_SEL_PDM2_R_MASK (0x3 << 0)776#define RT5677_SEL_PDM2_R_SFT 0777 778/* PDM I2C / Data Control 1 (0x32) */779#define RT5677_PDM2_PW_DOWN (0x1 << 7)780#define RT5677_PDM1_PW_DOWN (0x1 << 6)781#define RT5677_PDM2_BUSY (0x1 << 5)782#define RT5677_PDM1_BUSY (0x1 << 4)783#define RT5677_PDM_PATTERN (0x1 << 3)784#define RT5677_PDM_GAIN (0x1 << 2)785#define RT5677_PDM_DIV_MASK (0x3 << 0)786 787/* PDM I2C / Data Control 2 (0x33) */788#define RT5677_PDM1_I2C_ID (0xf << 12)789#define RT5677_PDM1_EXE (0x1 << 11)790#define RT5677_PDM1_I2C_CMD (0x1 << 10)791#define RT5677_PDM1_I2C_EXE (0x1 << 9)792#define RT5677_PDM1_I2C_BUSY (0x1 << 8)793#define RT5677_PDM2_I2C_ID (0xf << 4)794#define RT5677_PDM2_EXE (0x1 << 3)795#define RT5677_PDM2_I2C_CMD (0x1 << 2)796#define RT5677_PDM2_I2C_EXE (0x1 << 1)797#define RT5677_PDM2_I2C_BUSY (0x1 << 0)798 799/* TDM1 control 1 (0x3b) */800#define RT5677_IF1_ADC_MODE_MASK (0x1 << 12)801#define RT5677_IF1_ADC_MODE_SFT 12802#define RT5677_IF1_ADC_MODE_I2S (0x0 << 12)803#define RT5677_IF1_ADC_MODE_TDM (0x1 << 12)804#define RT5677_IF1_ADC1_SWAP_MASK (0x3 << 6)805#define RT5677_IF1_ADC1_SWAP_SFT 6806#define RT5677_IF1_ADC2_SWAP_MASK (0x3 << 4)807#define RT5677_IF1_ADC2_SWAP_SFT 4808#define RT5677_IF1_ADC3_SWAP_MASK (0x3 << 2)809#define RT5677_IF1_ADC3_SWAP_SFT 2810#define RT5677_IF1_ADC4_SWAP_MASK (0x3 << 0)811#define RT5677_IF1_ADC4_SWAP_SFT 0812 813/* TDM1 control 2 (0x3c) */814#define RT5677_IF1_ADC4_MASK (0x3 << 10)815#define RT5677_IF1_ADC4_SFT 10816#define RT5677_IF1_ADC3_MASK (0x3 << 8)817#define RT5677_IF1_ADC3_SFT 8818#define RT5677_IF1_ADC2_MASK (0x3 << 6)819#define RT5677_IF1_ADC2_SFT 6820#define RT5677_IF1_ADC1_MASK (0x3 << 4)821#define RT5677_IF1_ADC1_SFT 4822#define RT5677_IF1_ADC_CTRL_MASK (0x7 << 0)823#define RT5677_IF1_ADC_CTRL_SFT 0824 825/* TDM1 control 4 (0x3e) */826#define RT5677_IF1_DAC0_MASK (0x7 << 12)827#define RT5677_IF1_DAC0_SFT 12828#define RT5677_IF1_DAC1_MASK (0x7 << 8)829#define RT5677_IF1_DAC1_SFT 8830#define RT5677_IF1_DAC2_MASK (0x7 << 4)831#define RT5677_IF1_DAC2_SFT 4832#define RT5677_IF1_DAC3_MASK (0x7 << 0)833#define RT5677_IF1_DAC3_SFT 0834 835/* TDM1 control 5 (0x3f) */836#define RT5677_IF1_DAC4_MASK (0x7 << 12)837#define RT5677_IF1_DAC4_SFT 12838#define RT5677_IF1_DAC5_MASK (0x7 << 8)839#define RT5677_IF1_DAC5_SFT 8840#define RT5677_IF1_DAC6_MASK (0x7 << 4)841#define RT5677_IF1_DAC6_SFT 4842#define RT5677_IF1_DAC7_MASK (0x7 << 0)843#define RT5677_IF1_DAC7_SFT 0844 845/* TDM2 control 1 (0x40) */846#define RT5677_IF2_ADC_MODE_MASK (0x1 << 12)847#define RT5677_IF2_ADC_MODE_SFT 12848#define RT5677_IF2_ADC_MODE_I2S (0x0 << 12)849#define RT5677_IF2_ADC_MODE_TDM (0x1 << 12)850#define RT5677_IF2_ADC1_SWAP_MASK (0x3 << 6)851#define RT5677_IF2_ADC1_SWAP_SFT 6852#define RT5677_IF2_ADC2_SWAP_MASK (0x3 << 4)853#define RT5677_IF2_ADC2_SWAP_SFT 4854#define RT5677_IF2_ADC3_SWAP_MASK (0x3 << 2)855#define RT5677_IF2_ADC3_SWAP_SFT 2856#define RT5677_IF2_ADC4_SWAP_MASK (0x3 << 0)857#define RT5677_IF2_ADC4_SWAP_SFT 0858 859/* TDM2 control 2 (0x41) */860#define RT5677_IF2_ADC4_MASK (0x3 << 10)861#define RT5677_IF2_ADC4_SFT 10862#define RT5677_IF2_ADC3_MASK (0x3 << 8)863#define RT5677_IF2_ADC3_SFT 8864#define RT5677_IF2_ADC2_MASK (0x3 << 6)865#define RT5677_IF2_ADC2_SFT 6866#define RT5677_IF2_ADC1_MASK (0x3 << 4)867#define RT5677_IF2_ADC1_SFT 4868#define RT5677_IF2_ADC_CTRL_MASK (0x7 << 0)869#define RT5677_IF2_ADC_CTRL_SFT 0870 871/* TDM2 control 4 (0x43) */872#define RT5677_IF2_DAC0_MASK (0x7 << 12)873#define RT5677_IF2_DAC0_SFT 12874#define RT5677_IF2_DAC1_MASK (0x7 << 8)875#define RT5677_IF2_DAC1_SFT 8876#define RT5677_IF2_DAC2_MASK (0x7 << 4)877#define RT5677_IF2_DAC2_SFT 4878#define RT5677_IF2_DAC3_MASK (0x7 << 0)879#define RT5677_IF2_DAC3_SFT 0880 881/* TDM2 control 5 (0x44) */882#define RT5677_IF2_DAC4_MASK (0x7 << 12)883#define RT5677_IF2_DAC4_SFT 12884#define RT5677_IF2_DAC5_MASK (0x7 << 8)885#define RT5677_IF2_DAC5_SFT 8886#define RT5677_IF2_DAC6_MASK (0x7 << 4)887#define RT5677_IF2_DAC6_SFT 4888#define RT5677_IF2_DAC7_MASK (0x7 << 0)889#define RT5677_IF2_DAC7_SFT 0890 891/* Digital Microphone Control 1 (0x50) */892#define RT5677_DMIC_1_EN_MASK (0x1 << 15)893#define RT5677_DMIC_1_EN_SFT 15894#define RT5677_DMIC_1_DIS (0x0 << 15)895#define RT5677_DMIC_1_EN (0x1 << 15)896#define RT5677_DMIC_2_EN_MASK (0x1 << 14)897#define RT5677_DMIC_2_EN_SFT 14898#define RT5677_DMIC_2_DIS (0x0 << 14)899#define RT5677_DMIC_2_EN (0x1 << 14)900#define RT5677_DMIC_L_STO1_LH_MASK (0x1 << 13)901#define RT5677_DMIC_L_STO1_LH_SFT 13902#define RT5677_DMIC_L_STO1_LH_FALLING (0x0 << 13)903#define RT5677_DMIC_L_STO1_LH_RISING (0x1 << 13)904#define RT5677_DMIC_R_STO1_LH_MASK (0x1 << 12)905#define RT5677_DMIC_R_STO1_LH_SFT 12906#define RT5677_DMIC_R_STO1_LH_FALLING (0x0 << 12)907#define RT5677_DMIC_R_STO1_LH_RISING (0x1 << 12)908#define RT5677_DMIC_L_STO3_LH_MASK (0x1 << 11)909#define RT5677_DMIC_L_STO3_LH_SFT 11910#define RT5677_DMIC_L_STO3_LH_FALLING (0x0 << 11)911#define RT5677_DMIC_L_STO3_LH_RISING (0x1 << 11)912#define RT5677_DMIC_R_STO3_LH_MASK (0x1 << 10)913#define RT5677_DMIC_R_STO3_LH_SFT 10914#define RT5677_DMIC_R_STO3_LH_FALLING (0x0 << 10)915#define RT5677_DMIC_R_STO3_LH_RISING (0x1 << 10)916#define RT5677_DMIC_L_STO2_LH_MASK (0x1 << 9)917#define RT5677_DMIC_L_STO2_LH_SFT 9918#define RT5677_DMIC_L_STO2_LH_FALLING (0x0 << 9)919#define RT5677_DMIC_L_STO2_LH_RISING (0x1 << 9)920#define RT5677_DMIC_R_STO2_LH_MASK (0x1 << 8)921#define RT5677_DMIC_R_STO2_LH_SFT 8922#define RT5677_DMIC_R_STO2_LH_FALLING (0x0 << 8)923#define RT5677_DMIC_R_STO2_LH_RISING (0x1 << 8)924#define RT5677_DMIC_CLK_MASK (0x7 << 5)925#define RT5677_DMIC_CLK_SFT 5926#define RT5677_DMIC_3_EN_MASK (0x1 << 4)927#define RT5677_DMIC_3_EN_SFT 4928#define RT5677_DMIC_3_DIS (0x0 << 4)929#define RT5677_DMIC_3_EN (0x1 << 4)930#define RT5677_DMIC_R_MONO_LH_MASK (0x1 << 2)931#define RT5677_DMIC_R_MONO_LH_SFT 2932#define RT5677_DMIC_R_MONO_LH_FALLING (0x0 << 2)933#define RT5677_DMIC_R_MONO_LH_RISING (0x1 << 2)934#define RT5677_DMIC_L_STO4_LH_MASK (0x1 << 1)935#define RT5677_DMIC_L_STO4_LH_SFT 1936#define RT5677_DMIC_L_STO4_LH_FALLING (0x0 << 1)937#define RT5677_DMIC_L_STO4_LH_RISING (0x1 << 1)938#define RT5677_DMIC_R_STO4_LH_MASK (0x1 << 0)939#define RT5677_DMIC_R_STO4_LH_SFT 0940#define RT5677_DMIC_R_STO4_LH_FALLING (0x0 << 0)941#define RT5677_DMIC_R_STO4_LH_RISING (0x1 << 0)942 943/* Digital Microphone Control 2 (0x51) */944#define RT5677_DMIC_4_EN_MASK (0x1 << 15)945#define RT5677_DMIC_4_EN_SFT 15946#define RT5677_DMIC_4_DIS (0x0 << 15)947#define RT5677_DMIC_4_EN (0x1 << 15)948#define RT5677_DMIC_4L_LH_MASK (0x1 << 7)949#define RT5677_DMIC_4L_LH_SFT 7950#define RT5677_DMIC_4L_LH_FALLING (0x0 << 7)951#define RT5677_DMIC_4L_LH_RISING (0x1 << 7)952#define RT5677_DMIC_4R_LH_MASK (0x1 << 6)953#define RT5677_DMIC_4R_LH_SFT 6954#define RT5677_DMIC_4R_LH_FALLING (0x0 << 6)955#define RT5677_DMIC_4R_LH_RISING (0x1 << 6)956#define RT5677_DMIC_3L_LH_MASK (0x1 << 5)957#define RT5677_DMIC_3L_LH_SFT 5958#define RT5677_DMIC_3L_LH_FALLING (0x0 << 5)959#define RT5677_DMIC_3L_LH_RISING (0x1 << 5)960#define RT5677_DMIC_3R_LH_MASK (0x1 << 4)961#define RT5677_DMIC_3R_LH_SFT 4962#define RT5677_DMIC_3R_LH_FALLING (0x0 << 4)963#define RT5677_DMIC_3R_LH_RISING (0x1 << 4)964#define RT5677_DMIC_2L_LH_MASK (0x1 << 3)965#define RT5677_DMIC_2L_LH_SFT 3966#define RT5677_DMIC_2L_LH_FALLING (0x0 << 3)967#define RT5677_DMIC_2L_LH_RISING (0x1 << 3)968#define RT5677_DMIC_2R_LH_MASK (0x1 << 2)969#define RT5677_DMIC_2R_LH_SFT 2970#define RT5677_DMIC_2R_LH_FALLING (0x0 << 2)971#define RT5677_DMIC_2R_LH_RISING (0x1 << 2)972#define RT5677_DMIC_1L_LH_MASK (0x1 << 1)973#define RT5677_DMIC_1L_LH_SFT 1974#define RT5677_DMIC_1L_LH_FALLING (0x0 << 1)975#define RT5677_DMIC_1L_LH_RISING (0x1 << 1)976#define RT5677_DMIC_1R_LH_MASK (0x1 << 0)977#define RT5677_DMIC_1R_LH_SFT 0978#define RT5677_DMIC_1R_LH_FALLING (0x0 << 0)979#define RT5677_DMIC_1R_LH_RISING (0x1 << 0)980 981/* Power Management for Digital 1 (0x61) */982#define RT5677_PWR_I2S1 (0x1 << 15)983#define RT5677_PWR_I2S1_BIT 15984#define RT5677_PWR_I2S2 (0x1 << 14)985#define RT5677_PWR_I2S2_BIT 14986#define RT5677_PWR_I2S3 (0x1 << 13)987#define RT5677_PWR_I2S3_BIT 13988#define RT5677_PWR_DAC1 (0x1 << 12)989#define RT5677_PWR_DAC1_BIT 12990#define RT5677_PWR_DAC2 (0x1 << 11)991#define RT5677_PWR_DAC2_BIT 11992#define RT5677_PWR_I2S4 (0x1 << 10)993#define RT5677_PWR_I2S4_BIT 10994#define RT5677_PWR_SLB (0x1 << 9)995#define RT5677_PWR_SLB_BIT 9996#define RT5677_PWR_DAC3 (0x1 << 7)997#define RT5677_PWR_DAC3_BIT 7998#define RT5677_PWR_ADCFED2 (0x1 << 4)999#define RT5677_PWR_ADCFED2_BIT 41000#define RT5677_PWR_ADCFED1 (0x1 << 3)1001#define RT5677_PWR_ADCFED1_BIT 31002#define RT5677_PWR_ADC_L (0x1 << 2)1003#define RT5677_PWR_ADC_L_BIT 21004#define RT5677_PWR_ADC_R (0x1 << 1)1005#define RT5677_PWR_ADC_R_BIT 11006#define RT5677_PWR_I2C_MASTER (0x1 << 0)1007#define RT5677_PWR_I2C_MASTER_BIT 01008 1009/* Power Management for Digital 2 (0x62) */1010#define RT5677_PWR_ADC_S1F (0x1 << 15)1011#define RT5677_PWR_ADC_S1F_BIT 151012#define RT5677_PWR_ADC_MF_L (0x1 << 14)1013#define RT5677_PWR_ADC_MF_L_BIT 141014#define RT5677_PWR_ADC_MF_R (0x1 << 13)1015#define RT5677_PWR_ADC_MF_R_BIT 131016#define RT5677_PWR_DAC_S1F (0x1 << 12)1017#define RT5677_PWR_DAC_S1F_BIT 121018#define RT5677_PWR_DAC_M2F_L (0x1 << 11)1019#define RT5677_PWR_DAC_M2F_L_BIT 111020#define RT5677_PWR_DAC_M2F_R (0x1 << 10)1021#define RT5677_PWR_DAC_M2F_R_BIT 101022#define RT5677_PWR_DAC_M3F_L (0x1 << 9)1023#define RT5677_PWR_DAC_M3F_L_BIT 91024#define RT5677_PWR_DAC_M3F_R (0x1 << 8)1025#define RT5677_PWR_DAC_M3F_R_BIT 81026#define RT5677_PWR_DAC_M4F_L (0x1 << 7)1027#define RT5677_PWR_DAC_M4F_L_BIT 71028#define RT5677_PWR_DAC_M4F_R (0x1 << 6)1029#define RT5677_PWR_DAC_M4F_R_BIT 61030#define RT5677_PWR_ADC_S2F (0x1 << 5)1031#define RT5677_PWR_ADC_S2F_BIT 51032#define RT5677_PWR_ADC_S3F (0x1 << 4)1033#define RT5677_PWR_ADC_S3F_BIT 41034#define RT5677_PWR_ADC_S4F (0x1 << 3)1035#define RT5677_PWR_ADC_S4F_BIT 31036#define RT5677_PWR_PDM1 (0x1 << 2)1037#define RT5677_PWR_PDM1_BIT 21038#define RT5677_PWR_PDM2 (0x1 << 1)1039#define RT5677_PWR_PDM2_BIT 11040 1041/* Power Management for Analog 1 (0x63) */1042#define RT5677_PWR_VREF1 (0x1 << 15)1043#define RT5677_PWR_VREF1_BIT 151044#define RT5677_PWR_FV1 (0x1 << 14)1045#define RT5677_PWR_FV1_BIT 141046#define RT5677_PWR_MB (0x1 << 13)1047#define RT5677_PWR_MB_BIT 131048#define RT5677_PWR_LO1 (0x1 << 12)1049#define RT5677_PWR_LO1_BIT 121050#define RT5677_PWR_BG (0x1 << 11)1051#define RT5677_PWR_BG_BIT 111052#define RT5677_PWR_LO2 (0x1 << 10)1053#define RT5677_PWR_LO2_BIT 101054#define RT5677_PWR_LO3 (0x1 << 9)1055#define RT5677_PWR_LO3_BIT 91056#define RT5677_PWR_VREF2 (0x1 << 8)1057#define RT5677_PWR_VREF2_BIT 81058#define RT5677_PWR_FV2 (0x1 << 7)1059#define RT5677_PWR_FV2_BIT 71060#define RT5677_LDO2_SEL_MASK (0x7 << 4)1061#define RT5677_LDO2_SEL_SFT 41062#define RT5677_LDO1_SEL_MASK (0x7 << 0)1063#define RT5677_LDO1_SEL_SFT 01064 1065/* Power Management for Analog 2 (0x64) */1066#define RT5677_PWR_BST1 (0x1 << 15)1067#define RT5677_PWR_BST1_BIT 151068#define RT5677_PWR_BST2 (0x1 << 14)1069#define RT5677_PWR_BST2_BIT 141070#define RT5677_PWR_CLK_MB1 (0x1 << 13)1071#define RT5677_PWR_CLK_MB1_BIT 131072#define RT5677_PWR_SLIM (0x1 << 12)1073#define RT5677_PWR_SLIM_BIT 121074#define RT5677_PWR_MB1 (0x1 << 11)1075#define RT5677_PWR_MB1_BIT 111076#define RT5677_PWR_PP_MB1 (0x1 << 10)1077#define RT5677_PWR_PP_MB1_BIT 101078#define RT5677_PWR_PLL1 (0x1 << 9)1079#define RT5677_PWR_PLL1_BIT 91080#define RT5677_PWR_PLL2 (0x1 << 8)1081#define RT5677_PWR_PLL2_BIT 81082#define RT5677_PWR_CORE (0x1 << 7)1083#define RT5677_PWR_CORE_BIT 71084#define RT5677_PWR_CLK_MB (0x1 << 6)1085#define RT5677_PWR_CLK_MB_BIT 61086#define RT5677_PWR_BST1_P (0x1 << 5)1087#define RT5677_PWR_BST1_P_BIT 51088#define RT5677_PWR_BST2_P (0x1 << 4)1089#define RT5677_PWR_BST2_P_BIT 41090#define RT5677_PWR_IPTV (0x1 << 3)1091#define RT5677_PWR_IPTV_BIT 31092#define RT5677_PWR_25M_CLK (0x1 << 1)1093#define RT5677_PWR_25M_CLK_BIT 11094#define RT5677_PWR_LDO1 (0x1 << 0)1095#define RT5677_PWR_LDO1_BIT 01096 1097/* Power Management for DSP (0x65) */1098#define RT5677_PWR_SR7 (0x1 << 10)1099#define RT5677_PWR_SR7_BIT 101100#define RT5677_PWR_SR6 (0x1 << 9)1101#define RT5677_PWR_SR6_BIT 91102#define RT5677_PWR_SR5 (0x1 << 8)1103#define RT5677_PWR_SR5_BIT 81104#define RT5677_PWR_SR4 (0x1 << 7)1105#define RT5677_PWR_SR4_BIT 71106#define RT5677_PWR_SR3 (0x1 << 6)1107#define RT5677_PWR_SR3_BIT 61108#define RT5677_PWR_SR2 (0x1 << 5)1109#define RT5677_PWR_SR2_BIT 51110#define RT5677_PWR_SR1 (0x1 << 4)1111#define RT5677_PWR_SR1_BIT 41112#define RT5677_PWR_SR0 (0x1 << 3)1113#define RT5677_PWR_SR0_BIT 31114#define RT5677_PWR_MLT (0x1 << 2)1115#define RT5677_PWR_MLT_BIT 21116#define RT5677_PWR_DSP (0x1 << 1)1117#define RT5677_PWR_DSP_BIT 11118#define RT5677_PWR_DSP_CPU (0x1 << 0)1119#define RT5677_PWR_DSP_CPU_BIT 01120 1121/* Power Status for DSP (0x66) */1122#define RT5677_PWR_SR7_RDY (0x1 << 9)1123#define RT5677_PWR_SR7_RDY_BIT 91124#define RT5677_PWR_SR6_RDY (0x1 << 8)1125#define RT5677_PWR_SR6_RDY_BIT 81126#define RT5677_PWR_SR5_RDY (0x1 << 7)1127#define RT5677_PWR_SR5_RDY_BIT 71128#define RT5677_PWR_SR4_RDY (0x1 << 6)1129#define RT5677_PWR_SR4_RDY_BIT 61130#define RT5677_PWR_SR3_RDY (0x1 << 5)1131#define RT5677_PWR_SR3_RDY_BIT 51132#define RT5677_PWR_SR2_RDY (0x1 << 4)1133#define RT5677_PWR_SR2_RDY_BIT 41134#define RT5677_PWR_SR1_RDY (0x1 << 3)1135#define RT5677_PWR_SR1_RDY_BIT 31136#define RT5677_PWR_SR0_RDY (0x1 << 2)1137#define RT5677_PWR_SR0_RDY_BIT 21138#define RT5677_PWR_MLT_RDY (0x1 << 1)1139#define RT5677_PWR_MLT_RDY_BIT 11140#define RT5677_PWR_DSP_RDY (0x1 << 0)1141#define RT5677_PWR_DSP_RDY_BIT 01142 1143/* Power Management for DSP (0x67) */1144#define RT5677_PWR_SLIM_ISO (0x1 << 11)1145#define RT5677_PWR_SLIM_ISO_BIT 111146#define RT5677_PWR_CORE_ISO (0x1 << 10)1147#define RT5677_PWR_CORE_ISO_BIT 101148#define RT5677_PWR_DSP_ISO (0x1 << 9)1149#define RT5677_PWR_DSP_ISO_BIT 91150#define RT5677_PWR_SR7_ISO (0x1 << 8)1151#define RT5677_PWR_SR7_ISO_BIT 81152#define RT5677_PWR_SR6_ISO (0x1 << 7)1153#define RT5677_PWR_SR6_ISO_BIT 71154#define RT5677_PWR_SR5_ISO (0x1 << 6)1155#define RT5677_PWR_SR5_ISO_BIT 61156#define RT5677_PWR_SR4_ISO (0x1 << 5)1157#define RT5677_PWR_SR4_ISO_BIT 51158#define RT5677_PWR_SR3_ISO (0x1 << 4)1159#define RT5677_PWR_SR3_ISO_BIT 41160#define RT5677_PWR_SR2_ISO (0x1 << 3)1161#define RT5677_PWR_SR2_ISO_BIT 31162#define RT5677_PWR_SR1_ISO (0x1 << 2)1163#define RT5677_PWR_SR1_ISO_BIT 21164#define RT5677_PWR_SR0_ISO (0x1 << 1)1165#define RT5677_PWR_SR0_ISO_BIT 11166#define RT5677_PWR_MLT_ISO (0x1 << 0)1167#define RT5677_PWR_MLT_ISO_BIT 01168 1169/* I2S1/2/3/4 Audio Serial Data Port Control (0x6f 0x70 0x71 0x72) */1170#define RT5677_I2S_MS_MASK (0x1 << 15)1171#define RT5677_I2S_MS_SFT 151172#define RT5677_I2S_MS_M (0x0 << 15)1173#define RT5677_I2S_MS_S (0x1 << 15)1174#define RT5677_I2S_O_CP_MASK (0x3 << 10)1175#define RT5677_I2S_O_CP_SFT 101176#define RT5677_I2S_O_CP_OFF (0x0 << 10)1177#define RT5677_I2S_O_CP_U_LAW (0x1 << 10)1178#define RT5677_I2S_O_CP_A_LAW (0x2 << 10)1179#define RT5677_I2S_I_CP_MASK (0x3 << 8)1180#define RT5677_I2S_I_CP_SFT 81181#define RT5677_I2S_I_CP_OFF (0x0 << 8)1182#define RT5677_I2S_I_CP_U_LAW (0x1 << 8)1183#define RT5677_I2S_I_CP_A_LAW (0x2 << 8)1184#define RT5677_I2S_BP_MASK (0x1 << 7)1185#define RT5677_I2S_BP_SFT 71186#define RT5677_I2S_BP_NOR (0x0 << 7)1187#define RT5677_I2S_BP_INV (0x1 << 7)1188#define RT5677_I2S_DL_MASK (0x3 << 2)1189#define RT5677_I2S_DL_SFT 21190#define RT5677_I2S_DL_16 (0x0 << 2)1191#define RT5677_I2S_DL_20 (0x1 << 2)1192#define RT5677_I2S_DL_24 (0x2 << 2)1193#define RT5677_I2S_DL_8 (0x3 << 2)1194#define RT5677_I2S_DF_MASK (0x3 << 0)1195#define RT5677_I2S_DF_SFT 01196#define RT5677_I2S_DF_I2S (0x0 << 0)1197#define RT5677_I2S_DF_LEFT (0x1 << 0)1198#define RT5677_I2S_DF_PCM_A (0x2 << 0)1199#define RT5677_I2S_DF_PCM_B (0x3 << 0)1200 1201/* Clock Tree Control 1 (0x73) */1202#define RT5677_I2S_PD1_MASK (0x7 << 12)1203#define RT5677_I2S_PD1_SFT 121204#define RT5677_I2S_PD1_1 (0x0 << 12)1205#define RT5677_I2S_PD1_2 (0x1 << 12)1206#define RT5677_I2S_PD1_3 (0x2 << 12)1207#define RT5677_I2S_PD1_4 (0x3 << 12)1208#define RT5677_I2S_PD1_6 (0x4 << 12)1209#define RT5677_I2S_PD1_8 (0x5 << 12)1210#define RT5677_I2S_PD1_12 (0x6 << 12)1211#define RT5677_I2S_PD1_16 (0x7 << 12)1212#define RT5677_I2S_BCLK_MS2_MASK (0x1 << 11)1213#define RT5677_I2S_BCLK_MS2_SFT 111214#define RT5677_I2S_BCLK_MS2_32 (0x0 << 11)1215#define RT5677_I2S_BCLK_MS2_64 (0x1 << 11)1216#define RT5677_I2S_PD2_MASK (0x7 << 8)1217#define RT5677_I2S_PD2_SFT 81218#define RT5677_I2S_PD2_1 (0x0 << 8)1219#define RT5677_I2S_PD2_2 (0x1 << 8)1220#define RT5677_I2S_PD2_3 (0x2 << 8)1221#define RT5677_I2S_PD2_4 (0x3 << 8)1222#define RT5677_I2S_PD2_6 (0x4 << 8)1223#define RT5677_I2S_PD2_8 (0x5 << 8)1224#define RT5677_I2S_PD2_12 (0x6 << 8)1225#define RT5677_I2S_PD2_16 (0x7 << 8)1226#define RT5677_I2S_BCLK_MS3_MASK (0x1 << 7)1227#define RT5677_I2S_BCLK_MS3_SFT 71228#define RT5677_I2S_BCLK_MS3_32 (0x0 << 7)1229#define RT5677_I2S_BCLK_MS3_64 (0x1 << 7)1230#define RT5677_I2S_PD3_MASK (0x7 << 4)1231#define RT5677_I2S_PD3_SFT 41232#define RT5677_I2S_PD3_1 (0x0 << 4)1233#define RT5677_I2S_PD3_2 (0x1 << 4)1234#define RT5677_I2S_PD3_3 (0x2 << 4)1235#define RT5677_I2S_PD3_4 (0x3 << 4)1236#define RT5677_I2S_PD3_6 (0x4 << 4)1237#define RT5677_I2S_PD3_8 (0x5 << 4)1238#define RT5677_I2S_PD3_12 (0x6 << 4)1239#define RT5677_I2S_PD3_16 (0x7 << 4)1240#define RT5677_I2S_BCLK_MS4_MASK (0x1 << 3)1241#define RT5677_I2S_BCLK_MS4_SFT 31242#define RT5677_I2S_BCLK_MS4_32 (0x0 << 3)1243#define RT5677_I2S_BCLK_MS4_64 (0x1 << 3)1244#define RT5677_I2S_PD4_MASK (0x7 << 0)1245#define RT5677_I2S_PD4_SFT 01246#define RT5677_I2S_PD4_1 (0x0 << 0)1247#define RT5677_I2S_PD4_2 (0x1 << 0)1248#define RT5677_I2S_PD4_3 (0x2 << 0)1249#define RT5677_I2S_PD4_4 (0x3 << 0)1250#define RT5677_I2S_PD4_6 (0x4 << 0)1251#define RT5677_I2S_PD4_8 (0x5 << 0)1252#define RT5677_I2S_PD4_12 (0x6 << 0)1253#define RT5677_I2S_PD4_16 (0x7 << 0)1254 1255/* Clock Tree Control 2 (0x74) */1256#define RT5677_I2S_PD5_MASK (0x7 << 12)1257#define RT5677_I2S_PD5_SFT 121258#define RT5677_I2S_PD5_1 (0x0 << 12)1259#define RT5677_I2S_PD5_2 (0x1 << 12)1260#define RT5677_I2S_PD5_3 (0x2 << 12)1261#define RT5677_I2S_PD5_4 (0x3 << 12)1262#define RT5677_I2S_PD5_6 (0x4 << 12)1263#define RT5677_I2S_PD5_8 (0x5 << 12)1264#define RT5677_I2S_PD5_12 (0x6 << 12)1265#define RT5677_I2S_PD5_16 (0x7 << 12)1266#define RT5677_I2S_PD6_MASK (0x7 << 8)1267#define RT5677_I2S_PD6_SFT 81268#define RT5677_I2S_PD6_1 (0x0 << 8)1269#define RT5677_I2S_PD6_2 (0x1 << 8)1270#define RT5677_I2S_PD6_3 (0x2 << 8)1271#define RT5677_I2S_PD6_4 (0x3 << 8)1272#define RT5677_I2S_PD6_6 (0x4 << 8)1273#define RT5677_I2S_PD6_8 (0x5 << 8)1274#define RT5677_I2S_PD6_12 (0x6 << 8)1275#define RT5677_I2S_PD6_16 (0x7 << 8)1276#define RT5677_I2S_PD7_MASK (0x7 << 4)1277#define RT5677_I2S_PD7_SFT 41278#define RT5677_I2S_PD7_1 (0x0 << 4)1279#define RT5677_I2S_PD7_2 (0x1 << 4)1280#define RT5677_I2S_PD7_3 (0x2 << 4)1281#define RT5677_I2S_PD7_4 (0x3 << 4)1282#define RT5677_I2S_PD7_6 (0x4 << 4)1283#define RT5677_I2S_PD7_8 (0x5 << 4)1284#define RT5677_I2S_PD7_12 (0x6 << 4)1285#define RT5677_I2S_PD7_16 (0x7 << 4)1286#define RT5677_I2S_PD8_MASK (0x7 << 0)1287#define RT5677_I2S_PD8_SFT 01288#define RT5677_I2S_PD8_1 (0x0 << 0)1289#define RT5677_I2S_PD8_2 (0x1 << 0)1290#define RT5677_I2S_PD8_3 (0x2 << 0)1291#define RT5677_I2S_PD8_4 (0x3 << 0)1292#define RT5677_I2S_PD8_6 (0x4 << 0)1293#define RT5677_I2S_PD8_8 (0x5 << 0)1294#define RT5677_I2S_PD8_12 (0x6 << 0)1295#define RT5677_I2S_PD8_16 (0x7 << 0)1296 1297/* Clock Tree Control 3 (0x75) */1298#define RT5677_DSP_ASRC_O_MASK (0x3 << 6)1299#define RT5677_DSP_ASRC_O_SFT 61300#define RT5677_DSP_ASRC_O_1_0 (0x0 << 6)1301#define RT5677_DSP_ASRC_O_1_5 (0x1 << 6)1302#define RT5677_DSP_ASRC_O_2_0 (0x2 << 6)1303#define RT5677_DSP_ASRC_O_3_0 (0x3 << 6)1304#define RT5677_DSP_ASRC_I_MASK (0x3 << 4)1305#define RT5677_DSP_ASRC_I_SFT 41306#define RT5677_DSP_ASRC_I_1_0 (0x0 << 4)1307#define RT5677_DSP_ASRC_I_1_5 (0x1 << 4)1308#define RT5677_DSP_ASRC_I_2_0 (0x2 << 4)1309#define RT5677_DSP_ASRC_I_3_0 (0x3 << 4)1310#define RT5677_DSP_BUS_PD_MASK (0x7 << 0)1311#define RT5677_DSP_BUS_PD_SFT 01312#define RT5677_DSP_BUS_PD_1 (0x0 << 0)1313#define RT5677_DSP_BUS_PD_2 (0x1 << 0)1314#define RT5677_DSP_BUS_PD_3 (0x2 << 0)1315#define RT5677_DSP_BUS_PD_4 (0x3 << 0)1316#define RT5677_DSP_BUS_PD_6 (0x4 << 0)1317#define RT5677_DSP_BUS_PD_8 (0x5 << 0)1318#define RT5677_DSP_BUS_PD_12 (0x6 << 0)1319#define RT5677_DSP_BUS_PD_16 (0x7 << 0)1320 1321#define RT5677_PLL_INP_MAX 400000001322#define RT5677_PLL_INP_MIN 20480001323/* PLL M/N/K Code Control 1 (0x7a 0x7c) */1324#define RT5677_PLL_N_MAX 0x1ff1325#define RT5677_PLL_N_MASK (RT5677_PLL_N_MAX << 7)1326#define RT5677_PLL_N_SFT 71327#define RT5677_PLL_K_BP (0x1 << 5)1328#define RT5677_PLL_K_BP_SFT 51329#define RT5677_PLL_K_MAX 0x1f1330#define RT5677_PLL_K_MASK (RT5677_PLL_K_MAX)1331#define RT5677_PLL_K_SFT 01332 1333/* PLL M/N/K Code Control 2 (0x7b 0x7d) */1334#define RT5677_PLL_M_MAX 0xf1335#define RT5677_PLL_M_MASK (RT5677_PLL_M_MAX << 12)1336#define RT5677_PLL_M_SFT 121337#define RT5677_PLL_M_BP (0x1 << 11)1338#define RT5677_PLL_M_BP_SFT 111339#define RT5677_PLL_UPDATE_PLL1 (0x1 << 1)1340#define RT5677_PLL_UPDATE_PLL1_SFT 11341 1342/* Global Clock Control 1 (0x80) */1343#define RT5677_SCLK_SRC_MASK (0x3 << 14)1344#define RT5677_SCLK_SRC_SFT 141345#define RT5677_SCLK_SRC_MCLK (0x0 << 14)1346#define RT5677_SCLK_SRC_PLL1 (0x1 << 14)1347#define RT5677_SCLK_SRC_RCCLK (0x2 << 14) /* 25MHz */1348#define RT5677_SCLK_SRC_SLIM (0x3 << 14)1349#define RT5677_PLL1_SRC_MASK (0x7 << 11)1350#define RT5677_PLL1_SRC_SFT 111351#define RT5677_PLL1_SRC_MCLK (0x0 << 11)1352#define RT5677_PLL1_SRC_BCLK1 (0x1 << 11)1353#define RT5677_PLL1_SRC_BCLK2 (0x2 << 11)1354#define RT5677_PLL1_SRC_BCLK3 (0x3 << 11)1355#define RT5677_PLL1_SRC_BCLK4 (0x4 << 11)1356#define RT5677_PLL1_SRC_RCCLK (0x5 << 11)1357#define RT5677_PLL1_SRC_SLIM (0x6 << 11)1358#define RT5677_MCLK_SRC_MASK (0x1 << 10)1359#define RT5677_MCLK_SRC_SFT 101360#define RT5677_MCLK1_SRC (0x0 << 10)1361#define RT5677_MCLK2_SRC (0x1 << 10)1362#define RT5677_PLL1_PD_MASK (0x1 << 8)1363#define RT5677_PLL1_PD_SFT 81364#define RT5677_PLL1_PD_1 (0x0 << 8)1365#define RT5677_PLL1_PD_2 (0x1 << 8)1366#define RT5677_DAC_OSR_MASK (0x3 << 6)1367#define RT5677_DAC_OSR_SFT 61368#define RT5677_DAC_OSR_128 (0x0 << 6)1369#define RT5677_DAC_OSR_64 (0x1 << 6)1370#define RT5677_DAC_OSR_32 (0x2 << 6)1371#define RT5677_ADC_OSR_MASK (0x3 << 4)1372#define RT5677_ADC_OSR_SFT 41373#define RT5677_ADC_OSR_128 (0x0 << 4)1374#define RT5677_ADC_OSR_64 (0x1 << 4)1375#define RT5677_ADC_OSR_32 (0x2 << 4)1376 1377/* Global Clock Control 2 (0x81) */1378#define RT5677_PLL2_PR_SRC_MASK (0x1 << 15)1379#define RT5677_PLL2_PR_SRC_SFT 151380#define RT5677_PLL2_PR_SRC_MCLK1 (0x0 << 15)1381#define RT5677_PLL2_PR_SRC_MCLK2 (0x1 << 15)1382#define RT5677_PLL2_SRC_MASK (0x7 << 12)1383#define RT5677_PLL2_SRC_SFT 121384#define RT5677_PLL2_SRC_MCLK (0x0 << 12)1385#define RT5677_PLL2_SRC_BCLK1 (0x1 << 12)1386#define RT5677_PLL2_SRC_BCLK2 (0x2 << 12)1387#define RT5677_PLL2_SRC_BCLK3 (0x3 << 12)1388#define RT5677_PLL2_SRC_BCLK4 (0x4 << 12)1389#define RT5677_PLL2_SRC_RCCLK (0x5 << 12)1390#define RT5677_PLL2_SRC_SLIM (0x6 << 12)1391#define RT5677_DSP_ASRC_O_SRC (0x3 << 10)1392#define RT5677_DSP_ASRC_O_SRC_SFT 101393#define RT5677_DSP_ASRC_O_MCLK (0x0 << 10)1394#define RT5677_DSP_ASRC_O_PLL1 (0x1 << 10)1395#define RT5677_DSP_ASRC_O_SLIM (0x2 << 10)1396#define RT5677_DSP_ASRC_O_RCCLK (0x3 << 10)1397#define RT5677_DSP_ASRC_I_SRC (0x3 << 8)1398#define RT5677_DSP_ASRC_I_SRC_SFT 81399#define RT5677_DSP_ASRC_I_MCLK (0x0 << 8)1400#define RT5677_DSP_ASRC_I_PLL1 (0x1 << 8)1401#define RT5677_DSP_ASRC_I_SLIM (0x2 << 8)1402#define RT5677_DSP_ASRC_I_RCCLK (0x3 << 8)1403#define RT5677_DSP_CLK_SRC_MASK (0x1 << 7)1404#define RT5677_DSP_CLK_SRC_SFT 71405#define RT5677_DSP_CLK_SRC_PLL2 (0x0 << 7)1406#define RT5677_DSP_CLK_SRC_BYPASS (0x1 << 7)1407 1408/* ASRC Control 3 (0x85) */1409#define RT5677_DA_STO_CLK_SEL_MASK (0xf << 12)1410#define RT5677_DA_STO_CLK_SEL_SFT 121411#define RT5677_DA_MONO2L_CLK_SEL_MASK (0xf << 4)1412#define RT5677_DA_MONO2L_CLK_SEL_SFT 41413#define RT5677_DA_MONO2R_CLK_SEL_MASK (0xf << 0)1414#define RT5677_DA_MONO2R_CLK_SEL_SFT 01415 1416/* ASRC Control 4 (0x86) */1417#define RT5677_DA_MONO3L_CLK_SEL_MASK (0xf << 12)1418#define RT5677_DA_MONO3L_CLK_SEL_SFT 121419#define RT5677_DA_MONO3R_CLK_SEL_MASK (0xf << 8)1420#define RT5677_DA_MONO3R_CLK_SEL_SFT 81421#define RT5677_DA_MONO4L_CLK_SEL_MASK (0xf << 4)1422#define RT5677_DA_MONO4L_CLK_SEL_SFT 41423#define RT5677_DA_MONO4R_CLK_SEL_MASK (0xf << 0)1424#define RT5677_DA_MONO4R_CLK_SEL_SFT 01425 1426/* ASRC Control 5 (0x87) */1427#define RT5677_AD_STO1_CLK_SEL_MASK (0xf << 12)1428#define RT5677_AD_STO1_CLK_SEL_SFT 121429#define RT5677_AD_STO2_CLK_SEL_MASK (0xf << 8)1430#define RT5677_AD_STO2_CLK_SEL_SFT 81431#define RT5677_AD_STO3_CLK_SEL_MASK (0xf << 4)1432#define RT5677_AD_STO3_CLK_SEL_SFT 41433#define RT5677_AD_STO4_CLK_SEL_MASK (0xf << 0)1434#define RT5677_AD_STO4_CLK_SEL_SFT 01435 1436/* ASRC Control 6 (0x88) */1437#define RT5677_AD_MONOL_CLK_SEL_MASK (0xf << 12)1438#define RT5677_AD_MONOL_CLK_SEL_SFT 121439#define RT5677_AD_MONOR_CLK_SEL_MASK (0xf << 8)1440#define RT5677_AD_MONOR_CLK_SEL_SFT 81441 1442/* ASRC Control 7 (0x89) */1443#define RT5677_DSP_OB_0_3_CLK_SEL_MASK (0xf << 12)1444#define RT5677_DSP_OB_0_3_CLK_SEL_SFT 121445#define RT5677_DSP_OB_4_7_CLK_SEL_MASK (0xf << 8)1446#define RT5677_DSP_OB_4_7_CLK_SEL_SFT 81447 1448/* ASRC Control 8 (0x8a) */1449#define RT5677_I2S1_CLK_SEL_MASK (0xf << 12)1450#define RT5677_I2S1_CLK_SEL_SFT 121451#define RT5677_I2S2_CLK_SEL_MASK (0xf << 8)1452#define RT5677_I2S2_CLK_SEL_SFT 81453#define RT5677_I2S3_CLK_SEL_MASK (0xf << 4)1454#define RT5677_I2S3_CLK_SEL_SFT 41455#define RT5677_I2S4_CLK_SEL_MASK (0xf)1456#define RT5677_I2S4_CLK_SEL_SFT 01457 1458/* VAD Function Control 1 (0x9c) */1459#define RT5677_VAD_MIN_DUR_MASK (0x3 << 13)1460#define RT5677_VAD_MIN_DUR_SFT 131461#define RT5677_VAD_ADPCM_BYPASS (1 << 10)1462#define RT5677_VAD_ADPCM_BYPASS_BIT 101463#define RT5677_VAD_FG2ENC (1 << 9)1464#define RT5677_VAD_FG2ENC_BIT 91465#define RT5677_VAD_BUF_OW (1 << 8)1466#define RT5677_VAD_BUF_OW_BIT 81467#define RT5677_VAD_CLR_FLAG (1 << 7)1468#define RT5677_VAD_CLR_FLAG_BIT 71469#define RT5677_VAD_BUF_POP (1 << 6)1470#define RT5677_VAD_BUF_POP_BIT 61471#define RT5677_VAD_BUF_PUSH (1 << 5)1472#define RT5677_VAD_BUF_PUSH_BIT 51473#define RT5677_VAD_DET_ENABLE (1 << 4)1474#define RT5677_VAD_DET_ENABLE_BIT 41475#define RT5677_VAD_FUNC_ENABLE (1 << 3)1476#define RT5677_VAD_FUNC_ENABLE_BIT 31477#define RT5677_VAD_FUNC_RESET (1 << 2)1478#define RT5677_VAD_FUNC_RESET_BIT 21479 1480/* VAD Function Control 4 (0x9f) */1481#define RT5677_VAD_OUT_SRC_RATE_MASK (0x1 << 11)1482#define RT5677_VAD_OUT_SRC_RATE_SFT 111483#define RT5677_VAD_OUT_SRC_MASK (0x1 << 10)1484#define RT5677_VAD_OUT_SRC_SFT 101485#define RT5677_VAD_SRC_MASK (0x3 << 8)1486#define RT5677_VAD_SRC_SFT 81487#define RT5677_VAD_LV_DIFF_MASK (0xff << 0)1488#define RT5677_VAD_LV_DIFF_SFT 01489 1490/* DSP InBound Control (0xa3) */1491#define RT5677_IB01_SRC_MASK (0x7 << 12)1492#define RT5677_IB01_SRC_SFT 121493#define RT5677_IB23_SRC_MASK (0x7 << 8)1494#define RT5677_IB23_SRC_SFT 81495#define RT5677_IB45_SRC_MASK (0x7 << 4)1496#define RT5677_IB45_SRC_SFT 41497#define RT5677_IB6_SRC_MASK (0x7 << 0)1498#define RT5677_IB6_SRC_SFT 01499 1500/* DSP InBound Control (0xa4) */1501#define RT5677_IB7_SRC_MASK (0x7 << 12)1502#define RT5677_IB7_SRC_SFT 121503#define RT5677_IB8_SRC_MASK (0x7 << 8)1504#define RT5677_IB8_SRC_SFT 81505#define RT5677_IB9_SRC_MASK (0x7 << 4)1506#define RT5677_IB9_SRC_SFT 41507 1508/* DSP In/OutBound Control (0xa5) */1509#define RT5677_SEL_SRC_OB23 (0x1 << 4)1510#define RT5677_SEL_SRC_OB23_SFT 41511#define RT5677_SEL_SRC_OB01 (0x1 << 3)1512#define RT5677_SEL_SRC_OB01_SFT 31513#define RT5677_SEL_SRC_IB45 (0x1 << 2)1514#define RT5677_SEL_SRC_IB45_SFT 21515#define RT5677_SEL_SRC_IB23 (0x1 << 1)1516#define RT5677_SEL_SRC_IB23_SFT 11517#define RT5677_SEL_SRC_IB01 (0x1 << 0)1518#define RT5677_SEL_SRC_IB01_SFT 01519 1520/* Jack Detect Control 1 (0xb5) */1521#define RT5677_SEL_GPIO_JD1_MASK (0x3 << 14)1522#define RT5677_SEL_GPIO_JD1_SFT 141523#define RT5677_SEL_GPIO_JD2_MASK (0x3 << 12)1524#define RT5677_SEL_GPIO_JD2_SFT 121525#define RT5677_SEL_GPIO_JD3_MASK (0x3 << 10)1526#define RT5677_SEL_GPIO_JD3_SFT 101527 1528/* IRQ Control 1 (0xbd) */1529#define RT5677_STA_GPIO_JD1 (0x1 << 15)1530#define RT5677_STA_GPIO_JD1_SFT 151531#define RT5677_EN_IRQ_GPIO_JD1 (0x1 << 14)1532#define RT5677_EN_IRQ_GPIO_JD1_SFT 141533#define RT5677_EN_GPIO_JD1_STICKY (0x1 << 13)1534#define RT5677_EN_GPIO_JD1_STICKY_SFT 131535#define RT5677_INV_GPIO_JD1 (0x1 << 12)1536#define RT5677_INV_GPIO_JD1_SFT 121537#define RT5677_STA_GPIO_JD2 (0x1 << 11)1538#define RT5677_STA_GPIO_JD2_SFT 111539#define RT5677_EN_IRQ_GPIO_JD2 (0x1 << 10)1540#define RT5677_EN_IRQ_GPIO_JD2_SFT 101541#define RT5677_EN_GPIO_JD2_STICKY (0x1 << 9)1542#define RT5677_EN_GPIO_JD2_STICKY_SFT 91543#define RT5677_INV_GPIO_JD2 (0x1 << 8)1544#define RT5677_INV_GPIO_JD2_SFT 81545#define RT5677_STA_MICBIAS1_OVCD (0x1 << 7)1546#define RT5677_STA_MICBIAS1_OVCD_SFT 71547#define RT5677_EN_IRQ_MICBIAS1_OVCD (0x1 << 6)1548#define RT5677_EN_IRQ_MICBIAS1_OVCD_SFT 61549#define RT5677_EN_MICBIAS1_OVCD_STICKY (0x1 << 5)1550#define RT5677_EN_MICBIAS1_OVCD_STICKY_SFT 51551#define RT5677_INV_MICBIAS1_OVCD (0x1 << 4)1552#define RT5677_INV_MICBIAS1_OVCD_SFT 41553#define RT5677_STA_GPIO_JD3 (0x1 << 3)1554#define RT5677_STA_GPIO_JD3_SFT 31555#define RT5677_EN_IRQ_GPIO_JD3 (0x1 << 2)1556#define RT5677_EN_IRQ_GPIO_JD3_SFT 21557#define RT5677_EN_GPIO_JD3_STICKY (0x1 << 1)1558#define RT5677_EN_GPIO_JD3_STICKY_SFT 11559#define RT5677_INV_GPIO_JD3 (0x1 << 0)1560#define RT5677_INV_GPIO_JD3_SFT 01561 1562/* GPIO status (0xbf) */1563#define RT5677_GPIO6_STATUS_MASK (0x1 << 5)1564#define RT5677_GPIO6_STATUS_SFT 51565#define RT5677_GPIO5_STATUS_MASK (0x1 << 4)1566#define RT5677_GPIO5_STATUS_SFT 41567#define RT5677_GPIO4_STATUS_MASK (0x1 << 3)1568#define RT5677_GPIO4_STATUS_SFT 31569#define RT5677_GPIO3_STATUS_MASK (0x1 << 2)1570#define RT5677_GPIO3_STATUS_SFT 21571#define RT5677_GPIO2_STATUS_MASK (0x1 << 1)1572#define RT5677_GPIO2_STATUS_SFT 11573#define RT5677_GPIO1_STATUS_MASK (0x1 << 0)1574#define RT5677_GPIO1_STATUS_SFT 01575 1576/* GPIO Control 1 (0xc0) */1577#define RT5677_GPIO1_PIN_MASK (0x1 << 15)1578#define RT5677_GPIO1_PIN_SFT 151579#define RT5677_GPIO1_PIN_GPIO1 (0x0 << 15)1580#define RT5677_GPIO1_PIN_IRQ (0x1 << 15)1581#define RT5677_IPTV_MODE_MASK (0x1 << 14)1582#define RT5677_IPTV_MODE_SFT 141583#define RT5677_IPTV_MODE_GPIO (0x0 << 14)1584#define RT5677_IPTV_MODE_IPTV (0x1 << 14)1585#define RT5677_FUNC_MODE_MASK (0x1 << 13)1586#define RT5677_FUNC_MODE_SFT 131587#define RT5677_FUNC_MODE_DMIC_GPIO (0x0 << 13)1588#define RT5677_FUNC_MODE_JTAG (0x1 << 13)1589 1590/* GPIO Control 2 (0xc1) & 3 (0xc2) common bits */1591#define RT5677_GPIOx_DIR_MASK (0x1 << 2)1592#define RT5677_GPIOx_DIR_SFT 21593#define RT5677_GPIOx_DIR_IN (0x0 << 2)1594#define RT5677_GPIOx_DIR_OUT (0x1 << 2)1595#define RT5677_GPIOx_OUT_MASK (0x1 << 1)1596#define RT5677_GPIOx_OUT_SFT 11597#define RT5677_GPIOx_OUT_LO (0x0 << 1)1598#define RT5677_GPIOx_OUT_HI (0x1 << 1)1599#define RT5677_GPIOx_P_MASK (0x1 << 0)1600#define RT5677_GPIOx_P_SFT 01601#define RT5677_GPIOx_P_NOR (0x0 << 0)1602#define RT5677_GPIOx_P_INV (0x1 << 0)1603 1604/* General Control (0xfa) */1605#define RT5677_IRQ_DEBOUNCE_SEL_MASK (0x3 << 3)1606#define RT5677_IRQ_DEBOUNCE_SEL_MCLK (0x0 << 3)1607#define RT5677_IRQ_DEBOUNCE_SEL_RC (0x1 << 3)1608#define RT5677_IRQ_DEBOUNCE_SEL_SLIM (0x2 << 3)1609 1610/* Virtual DSP Mixer Control (0xf7 0xf8 0xf9) */1611#define RT5677_DSP_IB_01_H (0x1 << 15)1612#define RT5677_DSP_IB_01_H_SFT 151613#define RT5677_DSP_IB_23_H (0x1 << 14)1614#define RT5677_DSP_IB_23_H_SFT 141615#define RT5677_DSP_IB_45_H (0x1 << 13)1616#define RT5677_DSP_IB_45_H_SFT 131617#define RT5677_DSP_IB_6_H (0x1 << 12)1618#define RT5677_DSP_IB_6_H_SFT 121619#define RT5677_DSP_IB_7_H (0x1 << 11)1620#define RT5677_DSP_IB_7_H_SFT 111621#define RT5677_DSP_IB_8_H (0x1 << 10)1622#define RT5677_DSP_IB_8_H_SFT 101623#define RT5677_DSP_IB_9_H (0x1 << 9)1624#define RT5677_DSP_IB_9_H_SFT 91625#define RT5677_DSP_IB_01_L (0x1 << 7)1626#define RT5677_DSP_IB_01_L_SFT 71627#define RT5677_DSP_IB_23_L (0x1 << 6)1628#define RT5677_DSP_IB_23_L_SFT 61629#define RT5677_DSP_IB_45_L (0x1 << 5)1630#define RT5677_DSP_IB_45_L_SFT 51631#define RT5677_DSP_IB_6_L (0x1 << 4)1632#define RT5677_DSP_IB_6_L_SFT 41633#define RT5677_DSP_IB_7_L (0x1 << 3)1634#define RT5677_DSP_IB_7_L_SFT 31635#define RT5677_DSP_IB_8_L (0x1 << 2)1636#define RT5677_DSP_IB_8_L_SFT 21637#define RT5677_DSP_IB_9_L (0x1 << 1)1638#define RT5677_DSP_IB_9_L_SFT 11639 1640/* General Control2 (0xfc)*/1641#define RT5677_GPIO5_FUNC_MASK (0x1 << 9)1642#define RT5677_GPIO5_FUNC_GPIO (0x0 << 9)1643#define RT5677_GPIO5_FUNC_DMIC (0x1 << 9)1644 1645#define RT5677_FIRMWARE1 "rt5677_dsp_fw1.bin"1646#define RT5677_FIRMWARE2 "rt5677_dsp_fw2.bin"1647 1648#define RT5677_DRV_NAME "rt5677"1649 1650/* System Clock Source */1651enum {1652 RT5677_SCLK_S_MCLK,1653 RT5677_SCLK_S_PLL1,1654 RT5677_SCLK_S_RCCLK,1655};1656 1657/* PLL1 Source */1658enum {1659 RT5677_PLL1_S_MCLK,1660 RT5677_PLL1_S_BCLK1,1661 RT5677_PLL1_S_BCLK2,1662 RT5677_PLL1_S_BCLK3,1663 RT5677_PLL1_S_BCLK4,1664};1665 1666enum {1667 RT5677_AIF1,1668 RT5677_AIF2,1669 RT5677_AIF3,1670 RT5677_AIF4,1671 RT5677_AIF5,1672 RT5677_AIFS,1673 RT5677_DSPBUFF,1674};1675 1676enum {1677 RT5677_GPIO1,1678 RT5677_GPIO2,1679 RT5677_GPIO3,1680 RT5677_GPIO4,1681 RT5677_GPIO5,1682 RT5677_GPIO6,1683 RT5677_GPIO_NUM,1684};1685 1686enum {1687 RT5677_IRQ_JD1,1688 RT5677_IRQ_JD2,1689 RT5677_IRQ_JD3,1690 RT5677_IRQ_NUM,1691};1692 1693enum rt5677_type {1694 RT5677 = 1,1695 RT5676 = 2,1696};1697 1698/* ASRC clock source selection */1699enum {1700 RT5677_CLK_SEL_SYS,1701 RT5677_CLK_SEL_I2S1_ASRC,1702 RT5677_CLK_SEL_I2S2_ASRC,1703 RT5677_CLK_SEL_I2S3_ASRC,1704 RT5677_CLK_SEL_I2S4_ASRC,1705 RT5677_CLK_SEL_I2S5_ASRC,1706 RT5677_CLK_SEL_I2S6_ASRC,1707 RT5677_CLK_SEL_SYS2,1708 RT5677_CLK_SEL_SYS3,1709 RT5677_CLK_SEL_SYS4,1710 RT5677_CLK_SEL_SYS5,1711 RT5677_CLK_SEL_SYS6,1712 RT5677_CLK_SEL_SYS7,1713};1714 1715/* filter mask */1716enum {1717 RT5677_DA_STEREO_FILTER = 0x1,1718 RT5677_DA_MONO2_L_FILTER = (0x1 << 1),1719 RT5677_DA_MONO2_R_FILTER = (0x1 << 2),1720 RT5677_DA_MONO3_L_FILTER = (0x1 << 3),1721 RT5677_DA_MONO3_R_FILTER = (0x1 << 4),1722 RT5677_DA_MONO4_L_FILTER = (0x1 << 5),1723 RT5677_DA_MONO4_R_FILTER = (0x1 << 6),1724 RT5677_AD_STEREO1_FILTER = (0x1 << 7),1725 RT5677_AD_STEREO2_FILTER = (0x1 << 8),1726 RT5677_AD_STEREO3_FILTER = (0x1 << 9),1727 RT5677_AD_STEREO4_FILTER = (0x1 << 10),1728 RT5677_AD_MONO_L_FILTER = (0x1 << 11),1729 RT5677_AD_MONO_R_FILTER = (0x1 << 12),1730 RT5677_DSP_OB_0_3_FILTER = (0x1 << 13),1731 RT5677_DSP_OB_4_7_FILTER = (0x1 << 14),1732 RT5677_I2S1_SOURCE = (0x1 << 15),1733 RT5677_I2S2_SOURCE = (0x1 << 16),1734 RT5677_I2S3_SOURCE = (0x1 << 17),1735 RT5677_I2S4_SOURCE = (0x1 << 18),1736};1737 1738enum rt5677_dmic2_clk {1739 RT5677_DMIC_CLK1 = 0,1740 RT5677_DMIC_CLK2 = 1,1741};1742 1743struct rt5677_platform_data {1744 /* IN1/IN2/LOUT1/LOUT2/LOUT3 can optionally be differential */1745 bool in1_diff;1746 bool in2_diff;1747 bool lout1_diff;1748 bool lout2_diff;1749 bool lout3_diff;1750 /* DMIC2 clock source selection */1751 enum rt5677_dmic2_clk dmic2_clk_pin;1752 1753 /* configures GPIO, 0 - floating, 1 - pulldown, 2 - pullup */1754 u8 gpio_config[6];1755 1756 /* jd1 can select 0 ~ 3 as OFF, GPIO1, GPIO2 and GPIO3 respectively */1757 unsigned int jd1_gpio;1758 /* jd2 and jd3 can select 0 ~ 3 as1759 OFF, GPIO4, GPIO5 and GPIO6 respectively */1760 unsigned int jd2_gpio;1761 unsigned int jd3_gpio;1762 1763 /* Set MICBIAS1 VDD 1v8 or 3v3 */1764 bool micbias1_vdd_3v3;1765};1766 1767struct rt5677_priv {1768 struct snd_soc_component *component;1769 struct device *dev;1770 struct rt5677_platform_data pdata;1771 struct regmap *regmap, *regmap_physical;1772 const struct firmware *fw1, *fw2;1773 struct mutex dsp_cmd_lock, dsp_pri_lock;1774 1775 int sysclk;1776 int sysclk_src;1777 int lrck[RT5677_AIFS];1778 int bclk[RT5677_AIFS];1779 int master[RT5677_AIFS];1780 int pll_src;1781 int pll_in;1782 int pll_out;1783 struct gpio_desc *pow_ldo2; /* POW_LDO2 pin */1784 struct gpio_desc *reset_pin; /* RESET pin */1785 enum rt5677_type type;1786#ifdef CONFIG_GPIOLIB1787 struct gpio_chip gpio_chip;1788#endif1789 bool dsp_vad_en_request; /* DSP VAD enable/disable request */1790 bool dsp_vad_en; /* dsp_work parameter */1791 bool is_dsp_mode;1792 bool is_vref_slow;1793 struct delayed_work dsp_work;1794 1795 /* Interrupt handling */1796 struct irq_domain *domain;1797 struct mutex irq_lock;1798 unsigned int irq_en;1799 struct delayed_work resume_irq_check;1800 int irq;1801 1802 int (*set_dsp_vad)(struct snd_soc_component *component, bool on);1803};1804 1805int rt5677_sel_asrc_clk_src(struct snd_soc_component *component,1806 unsigned int filter_mask, unsigned int clk_src);1807 1808#endif /* __RT5677_H__ */1809