brintos / linux-shallow public Read only

1// SPDX-License-Identifier: GPL-2.0-only2//3// rt5682.c  --  RT5682 ALSA SoC audio component driver4//5// Copyright 2018 Realtek Semiconductor Corp.6// Author: Bard Liao <bardliao@realtek.com>7//8 9#include <linux/module.h>10#include <linux/moduleparam.h>11#include <linux/init.h>12#include <linux/delay.h>13#include <linux/pm.h>14#include <linux/pm_runtime.h>15#include <linux/platform_device.h>16#include <linux/spi/spi.h>17#include <linux/acpi.h>18#include <linux/gpio/consumer.h>19#include <linux/mutex.h>20#include <sound/core.h>21#include <sound/pcm.h>22#include <sound/pcm_params.h>23#include <sound/jack.h>24#include <sound/soc.h>25#include <sound/soc-dapm.h>26#include <sound/initval.h>27#include <sound/tlv.h>28#include <sound/rt5682.h>29 30#include "rl6231.h"31#include "rt5682.h"32 33const char *rt5682_supply_names[RT5682_NUM_SUPPLIES] = {34	"AVDD",35	"MICVDD",36	"VBAT",37	"DBVDD",38	"LDO1-IN",39};40EXPORT_SYMBOL_GPL(rt5682_supply_names);41 42static const struct reg_sequence patch_list[] = {43	{RT5682_HP_IMP_SENS_CTRL_19, 0x1000},44	{RT5682_DAC_ADC_DIG_VOL1, 0xa020},45	{RT5682_I2C_CTRL, 0x000f},46	{RT5682_PLL2_INTERNAL, 0x8266},47	{RT5682_SAR_IL_CMD_1, 0x22b7},48	{RT5682_SAR_IL_CMD_3, 0x0365},49	{RT5682_SAR_IL_CMD_6, 0x0110},50	{RT5682_CHARGE_PUMP_1, 0x0210},51	{RT5682_HP_LOGIC_CTRL_2, 0x0007},52	{RT5682_SAR_IL_CMD_2, 0xac00},53	{RT5682_CBJ_CTRL_7, 0x0104},54};55 56void rt5682_apply_patch_list(struct rt5682_priv *rt5682, struct device *dev)57{58	int ret;59 60	ret = regmap_multi_reg_write(rt5682->regmap, patch_list,61				     ARRAY_SIZE(patch_list));62	if (ret)63		dev_warn(dev, "Failed to apply regmap patch: %d\n", ret);64}65EXPORT_SYMBOL_GPL(rt5682_apply_patch_list);66 67const struct reg_default rt5682_reg[RT5682_REG_NUM] = {68	{0x0002, 0x8080},69	{0x0003, 0x8000},70	{0x0005, 0x0000},71	{0x0006, 0x0000},72	{0x0008, 0x800f},73	{0x000b, 0x0000},74	{0x0010, 0x4040},75	{0x0011, 0x0000},76	{0x0012, 0x1404},77	{0x0013, 0x1000},78	{0x0014, 0xa00a},79	{0x0015, 0x0404},80	{0x0016, 0x0404},81	{0x0019, 0xafaf},82	{0x001c, 0x2f2f},83	{0x001f, 0x0000},84	{0x0022, 0x5757},85	{0x0023, 0x0039},86	{0x0024, 0x000b},87	{0x0026, 0xc0c4},88	{0x0029, 0x8080},89	{0x002a, 0xa0a0},90	{0x002b, 0x0300},91	{0x0030, 0x0000},92	{0x003c, 0x0080},93	{0x0044, 0x0c0c},94	{0x0049, 0x0000},95	{0x0061, 0x0000},96	{0x0062, 0x0000},97	{0x0063, 0x003f},98	{0x0064, 0x0000},99	{0x0065, 0x0000},100	{0x0066, 0x0030},101	{0x0067, 0x0000},102	{0x006b, 0x0000},103	{0x006c, 0x0000},104	{0x006d, 0x2200},105	{0x006e, 0x0a10},106	{0x0070, 0x8000},107	{0x0071, 0x8000},108	{0x0073, 0x0000},109	{0x0074, 0x0000},110	{0x0075, 0x0002},111	{0x0076, 0x0001},112	{0x0079, 0x0000},113	{0x007a, 0x0000},114	{0x007b, 0x0000},115	{0x007c, 0x0100},116	{0x007e, 0x0000},117	{0x0080, 0x0000},118	{0x0081, 0x0000},119	{0x0082, 0x0000},120	{0x0083, 0x0000},121	{0x0084, 0x0000},122	{0x0085, 0x0000},123	{0x0086, 0x0005},124	{0x0087, 0x0000},125	{0x0088, 0x0000},126	{0x008c, 0x0003},127	{0x008d, 0x0000},128	{0x008e, 0x0060},129	{0x008f, 0x1000},130	{0x0091, 0x0c26},131	{0x0092, 0x0073},132	{0x0093, 0x0000},133	{0x0094, 0x0080},134	{0x0098, 0x0000},135	{0x009a, 0x0000},136	{0x009b, 0x0000},137	{0x009c, 0x0000},138	{0x009d, 0x0000},139	{0x009e, 0x100c},140	{0x009f, 0x0000},141	{0x00a0, 0x0000},142	{0x00a3, 0x0002},143	{0x00a4, 0x0001},144	{0x00ae, 0x2040},145	{0x00af, 0x0000},146	{0x00b6, 0x0000},147	{0x00b7, 0x0000},148	{0x00b8, 0x0000},149	{0x00b9, 0x0002},150	{0x00be, 0x0000},151	{0x00c0, 0x0160},152	{0x00c1, 0x82a0},153	{0x00c2, 0x0000},154	{0x00d0, 0x0000},155	{0x00d1, 0x2244},156	{0x00d2, 0x3300},157	{0x00d3, 0x2200},158	{0x00d4, 0x0000},159	{0x00d9, 0x0009},160	{0x00da, 0x0000},161	{0x00db, 0x0000},162	{0x00dc, 0x00c0},163	{0x00dd, 0x2220},164	{0x00de, 0x3131},165	{0x00df, 0x3131},166	{0x00e0, 0x3131},167	{0x00e2, 0x0000},168	{0x00e3, 0x4000},169	{0x00e4, 0x0aa0},170	{0x00e5, 0x3131},171	{0x00e6, 0x3131},172	{0x00e7, 0x3131},173	{0x00e8, 0x3131},174	{0x00ea, 0xb320},175	{0x00eb, 0x0000},176	{0x00f0, 0x0000},177	{0x00f1, 0x00d0},178	{0x00f2, 0x00d0},179	{0x00f6, 0x0000},180	{0x00fa, 0x0000},181	{0x00fb, 0x0000},182	{0x00fc, 0x0000},183	{0x00fd, 0x0000},184	{0x00fe, 0x10ec},185	{0x00ff, 0x6530},186	{0x0100, 0xa0a0},187	{0x010b, 0x0000},188	{0x010c, 0xae00},189	{0x010d, 0xaaa0},190	{0x010e, 0x8aa2},191	{0x010f, 0x02a2},192	{0x0110, 0xc000},193	{0x0111, 0x04a2},194	{0x0112, 0x2800},195	{0x0113, 0x0000},196	{0x0117, 0x0100},197	{0x0125, 0x0410},198	{0x0132, 0x6026},199	{0x0136, 0x5555},200	{0x0138, 0x3700},201	{0x013a, 0x2000},202	{0x013b, 0x2000},203	{0x013c, 0x2005},204	{0x013f, 0x0000},205	{0x0142, 0x0000},206	{0x0145, 0x0002},207	{0x0146, 0x0000},208	{0x0147, 0x0000},209	{0x0148, 0x0000},210	{0x0149, 0x0000},211	{0x0150, 0x79a1},212	{0x0156, 0xaaaa},213	{0x0160, 0x4ec0},214	{0x0161, 0x0080},215	{0x0162, 0x0200},216	{0x0163, 0x0800},217	{0x0164, 0x0000},218	{0x0165, 0x0000},219	{0x0166, 0x0000},220	{0x0167, 0x000f},221	{0x0168, 0x000f},222	{0x0169, 0x0021},223	{0x0190, 0x413d},224	{0x0194, 0x0000},225	{0x0195, 0x0000},226	{0x0197, 0x0022},227	{0x0198, 0x0000},228	{0x0199, 0x0000},229	{0x01af, 0x0000},230	{0x01b0, 0x0400},231	{0x01b1, 0x0000},232	{0x01b2, 0x0000},233	{0x01b3, 0x0000},234	{0x01b4, 0x0000},235	{0x01b5, 0x0000},236	{0x01b6, 0x01c3},237	{0x01b7, 0x02a0},238	{0x01b8, 0x03e9},239	{0x01b9, 0x1389},240	{0x01ba, 0xc351},241	{0x01bb, 0x0009},242	{0x01bc, 0x0018},243	{0x01bd, 0x002a},244	{0x01be, 0x004c},245	{0x01bf, 0x0097},246	{0x01c0, 0x433d},247	{0x01c2, 0x0000},248	{0x01c3, 0x0000},249	{0x01c4, 0x0000},250	{0x01c5, 0x0000},251	{0x01c6, 0x0000},252	{0x01c7, 0x0000},253	{0x01c8, 0x40af},254	{0x01c9, 0x0702},255	{0x01ca, 0x0000},256	{0x01cb, 0x0000},257	{0x01cc, 0x5757},258	{0x01cd, 0x5757},259	{0x01ce, 0x5757},260	{0x01cf, 0x5757},261	{0x01d0, 0x5757},262	{0x01d1, 0x5757},263	{0x01d2, 0x5757},264	{0x01d3, 0x5757},265	{0x01d4, 0x5757},266	{0x01d5, 0x5757},267	{0x01d6, 0x0000},268	{0x01d7, 0x0008},269	{0x01d8, 0x0029},270	{0x01d9, 0x3333},271	{0x01da, 0x0000},272	{0x01db, 0x0004},273	{0x01dc, 0x0000},274	{0x01de, 0x7c00},275	{0x01df, 0x0320},276	{0x01e0, 0x06a1},277	{0x01e1, 0x0000},278	{0x01e2, 0x0000},279	{0x01e3, 0x0000},280	{0x01e4, 0x0000},281	{0x01e6, 0x0001},282	{0x01e7, 0x0000},283	{0x01e8, 0x0000},284	{0x01ea, 0x0000},285	{0x01eb, 0x0000},286	{0x01ec, 0x0000},287	{0x01ed, 0x0000},288	{0x01ee, 0x0000},289	{0x01ef, 0x0000},290	{0x01f0, 0x0000},291	{0x01f1, 0x0000},292	{0x01f2, 0x0000},293	{0x01f3, 0x0000},294	{0x01f4, 0x0000},295	{0x0210, 0x6297},296	{0x0211, 0xa005},297	{0x0212, 0x824c},298	{0x0213, 0xf7ff},299	{0x0214, 0xf24c},300	{0x0215, 0x0102},301	{0x0216, 0x00a3},302	{0x0217, 0x0048},303	{0x0218, 0xa2c0},304	{0x0219, 0x0400},305	{0x021a, 0x00c8},306	{0x021b, 0x00c0},307	{0x021c, 0x0000},308	{0x0250, 0x4500},309	{0x0251, 0x40b3},310	{0x0252, 0x0000},311	{0x0253, 0x0000},312	{0x0254, 0x0000},313	{0x0255, 0x0000},314	{0x0256, 0x0000},315	{0x0257, 0x0000},316	{0x0258, 0x0000},317	{0x0259, 0x0000},318	{0x025a, 0x0005},319	{0x0270, 0x0000},320	{0x02ff, 0x0110},321	{0x0300, 0x001f},322	{0x0301, 0x032c},323	{0x0302, 0x5f21},324	{0x0303, 0x4000},325	{0x0304, 0x4000},326	{0x0305, 0x06d5},327	{0x0306, 0x8000},328	{0x0307, 0x0700},329	{0x0310, 0x4560},330	{0x0311, 0xa4a8},331	{0x0312, 0x7418},332	{0x0313, 0x0000},333	{0x0314, 0x0006},334	{0x0315, 0xffff},335	{0x0316, 0xc400},336	{0x0317, 0x0000},337	{0x03c0, 0x7e00},338	{0x03c1, 0x8000},339	{0x03c2, 0x8000},340	{0x03c3, 0x8000},341	{0x03c4, 0x8000},342	{0x03c5, 0x8000},343	{0x03c6, 0x8000},344	{0x03c7, 0x8000},345	{0x03c8, 0x8000},346	{0x03c9, 0x8000},347	{0x03ca, 0x8000},348	{0x03cb, 0x8000},349	{0x03cc, 0x8000},350	{0x03d0, 0x0000},351	{0x03d1, 0x0000},352	{0x03d2, 0x0000},353	{0x03d3, 0x0000},354	{0x03d4, 0x2000},355	{0x03d5, 0x2000},356	{0x03d6, 0x0000},357	{0x03d7, 0x0000},358	{0x03d8, 0x2000},359	{0x03d9, 0x2000},360	{0x03da, 0x2000},361	{0x03db, 0x2000},362	{0x03dc, 0x0000},363	{0x03dd, 0x0000},364	{0x03de, 0x0000},365	{0x03df, 0x2000},366	{0x03e0, 0x0000},367	{0x03e1, 0x0000},368	{0x03e2, 0x0000},369	{0x03e3, 0x0000},370	{0x03e4, 0x0000},371	{0x03e5, 0x0000},372	{0x03e6, 0x0000},373	{0x03e7, 0x0000},374	{0x03e8, 0x0000},375	{0x03e9, 0x0000},376	{0x03ea, 0x0000},377	{0x03eb, 0x0000},378	{0x03ec, 0x0000},379	{0x03ed, 0x0000},380	{0x03ee, 0x0000},381	{0x03ef, 0x0000},382	{0x03f0, 0x0800},383	{0x03f1, 0x0800},384	{0x03f2, 0x0800},385	{0x03f3, 0x0800},386};387EXPORT_SYMBOL_GPL(rt5682_reg);388 389bool rt5682_volatile_register(struct device *dev, unsigned int reg)390{391	switch (reg) {392	case RT5682_RESET:393	case RT5682_CBJ_CTRL_2:394	case RT5682_INT_ST_1:395	case RT5682_4BTN_IL_CMD_1:396	case RT5682_AJD1_CTRL:397	case RT5682_HP_CALIB_CTRL_1:398	case RT5682_DEVICE_ID:399	case RT5682_I2C_MODE:400	case RT5682_HP_CALIB_CTRL_10:401	case RT5682_EFUSE_CTRL_2:402	case RT5682_JD_TOP_VC_VTRL:403	case RT5682_HP_IMP_SENS_CTRL_19:404	case RT5682_IL_CMD_1:405	case RT5682_SAR_IL_CMD_2:406	case RT5682_SAR_IL_CMD_4:407	case RT5682_SAR_IL_CMD_10:408	case RT5682_SAR_IL_CMD_11:409	case RT5682_EFUSE_CTRL_6...RT5682_EFUSE_CTRL_11:410	case RT5682_HP_CALIB_STA_1...RT5682_HP_CALIB_STA_11:411		return true;412	default:413		return false;414	}415}416EXPORT_SYMBOL_GPL(rt5682_volatile_register);417 418bool rt5682_readable_register(struct device *dev, unsigned int reg)419{420	switch (reg) {421	case RT5682_RESET:422	case RT5682_VERSION_ID:423	case RT5682_VENDOR_ID:424	case RT5682_DEVICE_ID:425	case RT5682_HP_CTRL_1:426	case RT5682_HP_CTRL_2:427	case RT5682_HPL_GAIN:428	case RT5682_HPR_GAIN:429	case RT5682_I2C_CTRL:430	case RT5682_CBJ_BST_CTRL:431	case RT5682_CBJ_CTRL_1:432	case RT5682_CBJ_CTRL_2:433	case RT5682_CBJ_CTRL_3:434	case RT5682_CBJ_CTRL_4:435	case RT5682_CBJ_CTRL_5:436	case RT5682_CBJ_CTRL_6:437	case RT5682_CBJ_CTRL_7:438	case RT5682_DAC1_DIG_VOL:439	case RT5682_STO1_ADC_DIG_VOL:440	case RT5682_STO1_ADC_BOOST:441	case RT5682_HP_IMP_GAIN_1:442	case RT5682_HP_IMP_GAIN_2:443	case RT5682_SIDETONE_CTRL:444	case RT5682_STO1_ADC_MIXER:445	case RT5682_AD_DA_MIXER:446	case RT5682_STO1_DAC_MIXER:447	case RT5682_A_DAC1_MUX:448	case RT5682_DIG_INF2_DATA:449	case RT5682_REC_MIXER:450	case RT5682_CAL_REC:451	case RT5682_ALC_BACK_GAIN:452	case RT5682_PWR_DIG_1:453	case RT5682_PWR_DIG_2:454	case RT5682_PWR_ANLG_1:455	case RT5682_PWR_ANLG_2:456	case RT5682_PWR_ANLG_3:457	case RT5682_PWR_MIXER:458	case RT5682_PWR_VOL:459	case RT5682_CLK_DET:460	case RT5682_RESET_LPF_CTRL:461	case RT5682_RESET_HPF_CTRL:462	case RT5682_DMIC_CTRL_1:463	case RT5682_I2S1_SDP:464	case RT5682_I2S2_SDP:465	case RT5682_ADDA_CLK_1:466	case RT5682_ADDA_CLK_2:467	case RT5682_I2S1_F_DIV_CTRL_1:468	case RT5682_I2S1_F_DIV_CTRL_2:469	case RT5682_TDM_CTRL:470	case RT5682_TDM_ADDA_CTRL_1:471	case RT5682_TDM_ADDA_CTRL_2:472	case RT5682_DATA_SEL_CTRL_1:473	case RT5682_TDM_TCON_CTRL:474	case RT5682_GLB_CLK:475	case RT5682_PLL_CTRL_1:476	case RT5682_PLL_CTRL_2:477	case RT5682_PLL_TRACK_1:478	case RT5682_PLL_TRACK_2:479	case RT5682_PLL_TRACK_3:480	case RT5682_PLL_TRACK_4:481	case RT5682_PLL_TRACK_5:482	case RT5682_PLL_TRACK_6:483	case RT5682_PLL_TRACK_11:484	case RT5682_SDW_REF_CLK:485	case RT5682_DEPOP_1:486	case RT5682_DEPOP_2:487	case RT5682_HP_CHARGE_PUMP_1:488	case RT5682_HP_CHARGE_PUMP_2:489	case RT5682_MICBIAS_1:490	case RT5682_MICBIAS_2:491	case RT5682_PLL_TRACK_12:492	case RT5682_PLL_TRACK_14:493	case RT5682_PLL2_CTRL_1:494	case RT5682_PLL2_CTRL_2:495	case RT5682_PLL2_CTRL_3:496	case RT5682_PLL2_CTRL_4:497	case RT5682_RC_CLK_CTRL:498	case RT5682_I2S_M_CLK_CTRL_1:499	case RT5682_I2S2_F_DIV_CTRL_1:500	case RT5682_I2S2_F_DIV_CTRL_2:501	case RT5682_EQ_CTRL_1:502	case RT5682_EQ_CTRL_2:503	case RT5682_IRQ_CTRL_1:504	case RT5682_IRQ_CTRL_2:505	case RT5682_IRQ_CTRL_3:506	case RT5682_IRQ_CTRL_4:507	case RT5682_INT_ST_1:508	case RT5682_GPIO_CTRL_1:509	case RT5682_GPIO_CTRL_2:510	case RT5682_GPIO_CTRL_3:511	case RT5682_HP_AMP_DET_CTRL_1:512	case RT5682_HP_AMP_DET_CTRL_2:513	case RT5682_MID_HP_AMP_DET:514	case RT5682_LOW_HP_AMP_DET:515	case RT5682_DELAY_BUF_CTRL:516	case RT5682_SV_ZCD_1:517	case RT5682_SV_ZCD_2:518	case RT5682_IL_CMD_1:519	case RT5682_IL_CMD_2:520	case RT5682_IL_CMD_3:521	case RT5682_IL_CMD_4:522	case RT5682_IL_CMD_5:523	case RT5682_IL_CMD_6:524	case RT5682_4BTN_IL_CMD_1:525	case RT5682_4BTN_IL_CMD_2:526	case RT5682_4BTN_IL_CMD_3:527	case RT5682_4BTN_IL_CMD_4:528	case RT5682_4BTN_IL_CMD_5:529	case RT5682_4BTN_IL_CMD_6:530	case RT5682_4BTN_IL_CMD_7:531	case RT5682_ADC_STO1_HP_CTRL_1:532	case RT5682_ADC_STO1_HP_CTRL_2:533	case RT5682_AJD1_CTRL:534	case RT5682_JD1_THD:535	case RT5682_JD2_THD:536	case RT5682_JD_CTRL_1:537	case RT5682_DUMMY_1:538	case RT5682_DUMMY_2:539	case RT5682_DUMMY_3:540	case RT5682_DAC_ADC_DIG_VOL1:541	case RT5682_BIAS_CUR_CTRL_2:542	case RT5682_BIAS_CUR_CTRL_3:543	case RT5682_BIAS_CUR_CTRL_4:544	case RT5682_BIAS_CUR_CTRL_5:545	case RT5682_BIAS_CUR_CTRL_6:546	case RT5682_BIAS_CUR_CTRL_7:547	case RT5682_BIAS_CUR_CTRL_8:548	case RT5682_BIAS_CUR_CTRL_9:549	case RT5682_BIAS_CUR_CTRL_10:550	case RT5682_VREF_REC_OP_FB_CAP_CTRL:551	case RT5682_CHARGE_PUMP_1:552	case RT5682_DIG_IN_CTRL_1:553	case RT5682_PAD_DRIVING_CTRL:554	case RT5682_SOFT_RAMP_DEPOP:555	case RT5682_CHOP_DAC:556	case RT5682_CHOP_ADC:557	case RT5682_CALIB_ADC_CTRL:558	case RT5682_VOL_TEST:559	case RT5682_SPKVDD_DET_STA:560	case RT5682_TEST_MODE_CTRL_1:561	case RT5682_TEST_MODE_CTRL_2:562	case RT5682_TEST_MODE_CTRL_3:563	case RT5682_TEST_MODE_CTRL_4:564	case RT5682_TEST_MODE_CTRL_5:565	case RT5682_PLL1_INTERNAL:566	case RT5682_PLL2_INTERNAL:567	case RT5682_STO_NG2_CTRL_1:568	case RT5682_STO_NG2_CTRL_2:569	case RT5682_STO_NG2_CTRL_3:570	case RT5682_STO_NG2_CTRL_4:571	case RT5682_STO_NG2_CTRL_5:572	case RT5682_STO_NG2_CTRL_6:573	case RT5682_STO_NG2_CTRL_7:574	case RT5682_STO_NG2_CTRL_8:575	case RT5682_STO_NG2_CTRL_9:576	case RT5682_STO_NG2_CTRL_10:577	case RT5682_STO1_DAC_SIL_DET:578	case RT5682_SIL_PSV_CTRL1:579	case RT5682_SIL_PSV_CTRL2:580	case RT5682_SIL_PSV_CTRL3:581	case RT5682_SIL_PSV_CTRL4:582	case RT5682_SIL_PSV_CTRL5:583	case RT5682_HP_IMP_SENS_CTRL_01:584	case RT5682_HP_IMP_SENS_CTRL_02:585	case RT5682_HP_IMP_SENS_CTRL_03:586	case RT5682_HP_IMP_SENS_CTRL_04:587	case RT5682_HP_IMP_SENS_CTRL_05:588	case RT5682_HP_IMP_SENS_CTRL_06:589	case RT5682_HP_IMP_SENS_CTRL_07:590	case RT5682_HP_IMP_SENS_CTRL_08:591	case RT5682_HP_IMP_SENS_CTRL_09:592	case RT5682_HP_IMP_SENS_CTRL_10:593	case RT5682_HP_IMP_SENS_CTRL_11:594	case RT5682_HP_IMP_SENS_CTRL_12:595	case RT5682_HP_IMP_SENS_CTRL_13:596	case RT5682_HP_IMP_SENS_CTRL_14:597	case RT5682_HP_IMP_SENS_CTRL_15:598	case RT5682_HP_IMP_SENS_CTRL_16:599	case RT5682_HP_IMP_SENS_CTRL_17:600	case RT5682_HP_IMP_SENS_CTRL_18:601	case RT5682_HP_IMP_SENS_CTRL_19:602	case RT5682_HP_IMP_SENS_CTRL_20:603	case RT5682_HP_IMP_SENS_CTRL_21:604	case RT5682_HP_IMP_SENS_CTRL_22:605	case RT5682_HP_IMP_SENS_CTRL_23:606	case RT5682_HP_IMP_SENS_CTRL_24:607	case RT5682_HP_IMP_SENS_CTRL_25:608	case RT5682_HP_IMP_SENS_CTRL_26:609	case RT5682_HP_IMP_SENS_CTRL_27:610	case RT5682_HP_IMP_SENS_CTRL_28:611	case RT5682_HP_IMP_SENS_CTRL_29:612	case RT5682_HP_IMP_SENS_CTRL_30:613	case RT5682_HP_IMP_SENS_CTRL_31:614	case RT5682_HP_IMP_SENS_CTRL_32:615	case RT5682_HP_IMP_SENS_CTRL_33:616	case RT5682_HP_IMP_SENS_CTRL_34:617	case RT5682_HP_IMP_SENS_CTRL_35:618	case RT5682_HP_IMP_SENS_CTRL_36:619	case RT5682_HP_IMP_SENS_CTRL_37:620	case RT5682_HP_IMP_SENS_CTRL_38:621	case RT5682_HP_IMP_SENS_CTRL_39:622	case RT5682_HP_IMP_SENS_CTRL_40:623	case RT5682_HP_IMP_SENS_CTRL_41:624	case RT5682_HP_IMP_SENS_CTRL_42:625	case RT5682_HP_IMP_SENS_CTRL_43:626	case RT5682_HP_LOGIC_CTRL_1:627	case RT5682_HP_LOGIC_CTRL_2:628	case RT5682_HP_LOGIC_CTRL_3:629	case RT5682_HP_CALIB_CTRL_1:630	case RT5682_HP_CALIB_CTRL_2:631	case RT5682_HP_CALIB_CTRL_3:632	case RT5682_HP_CALIB_CTRL_4:633	case RT5682_HP_CALIB_CTRL_5:634	case RT5682_HP_CALIB_CTRL_6:635	case RT5682_HP_CALIB_CTRL_7:636	case RT5682_HP_CALIB_CTRL_9:637	case RT5682_HP_CALIB_CTRL_10:638	case RT5682_HP_CALIB_CTRL_11:639	case RT5682_HP_CALIB_STA_1:640	case RT5682_HP_CALIB_STA_2:641	case RT5682_HP_CALIB_STA_3:642	case RT5682_HP_CALIB_STA_4:643	case RT5682_HP_CALIB_STA_5:644	case RT5682_HP_CALIB_STA_6:645	case RT5682_HP_CALIB_STA_7:646	case RT5682_HP_CALIB_STA_8:647	case RT5682_HP_CALIB_STA_9:648	case RT5682_HP_CALIB_STA_10:649	case RT5682_HP_CALIB_STA_11:650	case RT5682_SAR_IL_CMD_1:651	case RT5682_SAR_IL_CMD_2:652	case RT5682_SAR_IL_CMD_3:653	case RT5682_SAR_IL_CMD_4:654	case RT5682_SAR_IL_CMD_5:655	case RT5682_SAR_IL_CMD_6:656	case RT5682_SAR_IL_CMD_7:657	case RT5682_SAR_IL_CMD_8:658	case RT5682_SAR_IL_CMD_9:659	case RT5682_SAR_IL_CMD_10:660	case RT5682_SAR_IL_CMD_11:661	case RT5682_SAR_IL_CMD_12:662	case RT5682_SAR_IL_CMD_13:663	case RT5682_EFUSE_CTRL_1:664	case RT5682_EFUSE_CTRL_2:665	case RT5682_EFUSE_CTRL_3:666	case RT5682_EFUSE_CTRL_4:667	case RT5682_EFUSE_CTRL_5:668	case RT5682_EFUSE_CTRL_6:669	case RT5682_EFUSE_CTRL_7:670	case RT5682_EFUSE_CTRL_8:671	case RT5682_EFUSE_CTRL_9:672	case RT5682_EFUSE_CTRL_10:673	case RT5682_EFUSE_CTRL_11:674	case RT5682_JD_TOP_VC_VTRL:675	case RT5682_DRC1_CTRL_0:676	case RT5682_DRC1_CTRL_1:677	case RT5682_DRC1_CTRL_2:678	case RT5682_DRC1_CTRL_3:679	case RT5682_DRC1_CTRL_4:680	case RT5682_DRC1_CTRL_5:681	case RT5682_DRC1_CTRL_6:682	case RT5682_DRC1_HARD_LMT_CTRL_1:683	case RT5682_DRC1_HARD_LMT_CTRL_2:684	case RT5682_DRC1_PRIV_1:685	case RT5682_DRC1_PRIV_2:686	case RT5682_DRC1_PRIV_3:687	case RT5682_DRC1_PRIV_4:688	case RT5682_DRC1_PRIV_5:689	case RT5682_DRC1_PRIV_6:690	case RT5682_DRC1_PRIV_7:691	case RT5682_DRC1_PRIV_8:692	case RT5682_EQ_AUTO_RCV_CTRL1:693	case RT5682_EQ_AUTO_RCV_CTRL2:694	case RT5682_EQ_AUTO_RCV_CTRL3:695	case RT5682_EQ_AUTO_RCV_CTRL4:696	case RT5682_EQ_AUTO_RCV_CTRL5:697	case RT5682_EQ_AUTO_RCV_CTRL6:698	case RT5682_EQ_AUTO_RCV_CTRL7:699	case RT5682_EQ_AUTO_RCV_CTRL8:700	case RT5682_EQ_AUTO_RCV_CTRL9:701	case RT5682_EQ_AUTO_RCV_CTRL10:702	case RT5682_EQ_AUTO_RCV_CTRL11:703	case RT5682_EQ_AUTO_RCV_CTRL12:704	case RT5682_EQ_AUTO_RCV_CTRL13:705	case RT5682_ADC_L_EQ_LPF1_A1:706	case RT5682_R_EQ_LPF1_A1:707	case RT5682_L_EQ_LPF1_H0:708	case RT5682_R_EQ_LPF1_H0:709	case RT5682_L_EQ_BPF1_A1:710	case RT5682_R_EQ_BPF1_A1:711	case RT5682_L_EQ_BPF1_A2:712	case RT5682_R_EQ_BPF1_A2:713	case RT5682_L_EQ_BPF1_H0:714	case RT5682_R_EQ_BPF1_H0:715	case RT5682_L_EQ_BPF2_A1:716	case RT5682_R_EQ_BPF2_A1:717	case RT5682_L_EQ_BPF2_A2:718	case RT5682_R_EQ_BPF2_A2:719	case RT5682_L_EQ_BPF2_H0:720	case RT5682_R_EQ_BPF2_H0:721	case RT5682_L_EQ_BPF3_A1:722	case RT5682_R_EQ_BPF3_A1:723	case RT5682_L_EQ_BPF3_A2:724	case RT5682_R_EQ_BPF3_A2:725	case RT5682_L_EQ_BPF3_H0:726	case RT5682_R_EQ_BPF3_H0:727	case RT5682_L_EQ_BPF4_A1:728	case RT5682_R_EQ_BPF4_A1:729	case RT5682_L_EQ_BPF4_A2:730	case RT5682_R_EQ_BPF4_A2:731	case RT5682_L_EQ_BPF4_H0:732	case RT5682_R_EQ_BPF4_H0:733	case RT5682_L_EQ_HPF1_A1:734	case RT5682_R_EQ_HPF1_A1:735	case RT5682_L_EQ_HPF1_H0:736	case RT5682_R_EQ_HPF1_H0:737	case RT5682_L_EQ_PRE_VOL:738	case RT5682_R_EQ_PRE_VOL:739	case RT5682_L_EQ_POST_VOL:740	case RT5682_R_EQ_POST_VOL:741	case RT5682_I2C_MODE:742		return true;743	default:744		return false;745	}746}747EXPORT_SYMBOL_GPL(rt5682_readable_register);748 749static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -6525, 75, 0);750static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -1725, 75, 0);751static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0);752 753/* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */754static const DECLARE_TLV_DB_RANGE(bst_tlv,755	0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),756	1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0),757	2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),758	3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0),759	6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0),760	7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0),761	8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0)762);763 764/* Interface data select */765static const char * const rt5682_data_select[] = {766	"L/R", "R/L", "L/L", "R/R"767};768 769static SOC_ENUM_SINGLE_DECL(rt5682_if2_adc_enum,770	RT5682_DIG_INF2_DATA, RT5682_IF2_ADC_SEL_SFT, rt5682_data_select);771 772static SOC_ENUM_SINGLE_DECL(rt5682_if1_01_adc_enum,773	RT5682_TDM_ADDA_CTRL_1, RT5682_IF1_ADC1_SEL_SFT, rt5682_data_select);774 775static SOC_ENUM_SINGLE_DECL(rt5682_if1_23_adc_enum,776	RT5682_TDM_ADDA_CTRL_1, RT5682_IF1_ADC2_SEL_SFT, rt5682_data_select);777 778static SOC_ENUM_SINGLE_DECL(rt5682_if1_45_adc_enum,779	RT5682_TDM_ADDA_CTRL_1, RT5682_IF1_ADC3_SEL_SFT, rt5682_data_select);780 781static SOC_ENUM_SINGLE_DECL(rt5682_if1_67_adc_enum,782	RT5682_TDM_ADDA_CTRL_1, RT5682_IF1_ADC4_SEL_SFT, rt5682_data_select);783 784static const struct snd_kcontrol_new rt5682_if2_adc_swap_mux =785	SOC_DAPM_ENUM("IF2 ADC Swap Mux", rt5682_if2_adc_enum);786 787static const struct snd_kcontrol_new rt5682_if1_01_adc_swap_mux =788	SOC_DAPM_ENUM("IF1 01 ADC Swap Mux", rt5682_if1_01_adc_enum);789 790static const struct snd_kcontrol_new rt5682_if1_23_adc_swap_mux =791	SOC_DAPM_ENUM("IF1 23 ADC Swap Mux", rt5682_if1_23_adc_enum);792 793static const struct snd_kcontrol_new rt5682_if1_45_adc_swap_mux =794	SOC_DAPM_ENUM("IF1 45 ADC Swap Mux", rt5682_if1_45_adc_enum);795 796static const struct snd_kcontrol_new rt5682_if1_67_adc_swap_mux =797	SOC_DAPM_ENUM("IF1 67 ADC Swap Mux", rt5682_if1_67_adc_enum);798 799static const char * const rt5682_dac_select[] = {800	"IF1", "SOUND"801};802 803static SOC_ENUM_SINGLE_DECL(rt5682_dacl_enum,804	RT5682_AD_DA_MIXER, RT5682_DAC1_L_SEL_SFT, rt5682_dac_select);805 806static const struct snd_kcontrol_new rt5682_dac_l_mux =807	SOC_DAPM_ENUM("DAC L Mux", rt5682_dacl_enum);808 809static SOC_ENUM_SINGLE_DECL(rt5682_dacr_enum,810	RT5682_AD_DA_MIXER, RT5682_DAC1_R_SEL_SFT, rt5682_dac_select);811 812static const struct snd_kcontrol_new rt5682_dac_r_mux =813	SOC_DAPM_ENUM("DAC R Mux", rt5682_dacr_enum);814 815void rt5682_reset(struct rt5682_priv *rt5682)816{817	regmap_write(rt5682->regmap, RT5682_RESET, 0);818	if (!rt5682->is_sdw)819		regmap_write(rt5682->regmap, RT5682_I2C_MODE, 1);820}821EXPORT_SYMBOL_GPL(rt5682_reset);822 823/**824 * rt5682_sel_asrc_clk_src - select ASRC clock source for a set of filters825 * @component: SoC audio component device.826 * @filter_mask: mask of filters.827 * @clk_src: clock source828 *829 * The ASRC function is for asynchronous MCLK and LRCK. Also, since RT5682 can830 * only support standard 32fs or 64fs i2s format, ASRC should be enabled to831 * support special i2s clock format such as Intel's 100fs(100 * sampling rate).832 * ASRC function will track i2s clock and generate a corresponding system clock833 * for codec. This function provides an API to select the clock source for a834 * set of filters specified by the mask. And the component driver will turn on835 * ASRC for these filters if ASRC is selected as their clock source.836 */837int rt5682_sel_asrc_clk_src(struct snd_soc_component *component,838		unsigned int filter_mask, unsigned int clk_src)839{840	switch (clk_src) {841	case RT5682_CLK_SEL_SYS:842	case RT5682_CLK_SEL_I2S1_ASRC:843	case RT5682_CLK_SEL_I2S2_ASRC:844		break;845 846	default:847		return -EINVAL;848	}849 850	if (filter_mask & RT5682_DA_STEREO1_FILTER) {851		snd_soc_component_update_bits(component, RT5682_PLL_TRACK_2,852			RT5682_FILTER_CLK_SEL_MASK,853			clk_src << RT5682_FILTER_CLK_SEL_SFT);854	}855 856	if (filter_mask & RT5682_AD_STEREO1_FILTER) {857		snd_soc_component_update_bits(component, RT5682_PLL_TRACK_3,858			RT5682_FILTER_CLK_SEL_MASK,859			clk_src << RT5682_FILTER_CLK_SEL_SFT);860	}861 862	return 0;863}864EXPORT_SYMBOL_GPL(rt5682_sel_asrc_clk_src);865 866static int rt5682_button_detect(struct snd_soc_component *component)867{868	int btn_type, val;869 870	val = snd_soc_component_read(component, RT5682_4BTN_IL_CMD_1);871	btn_type = val & 0xfff0;872	snd_soc_component_write(component, RT5682_4BTN_IL_CMD_1, val);873	dev_dbg(component->dev, "%s btn_type=%x\n", __func__, btn_type);874	snd_soc_component_update_bits(component,875		RT5682_SAR_IL_CMD_2, 0x10, 0x10);876 877	return btn_type;878}879 880static void rt5682_enable_push_button_irq(struct snd_soc_component *component,881		bool enable)882{883	struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);884 885	if (enable) {886		snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_1,887			RT5682_SAR_BUTT_DET_MASK, RT5682_SAR_BUTT_DET_EN);888		snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_13,889			RT5682_SAR_SOUR_MASK, RT5682_SAR_SOUR_BTN);890		snd_soc_component_write(component, RT5682_IL_CMD_1, 0x0040);891		snd_soc_component_update_bits(component, RT5682_4BTN_IL_CMD_2,892			RT5682_4BTN_IL_MASK | RT5682_4BTN_IL_RST_MASK,893			RT5682_4BTN_IL_EN | RT5682_4BTN_IL_NOR);894		if (rt5682->is_sdw)895			snd_soc_component_update_bits(component,896				RT5682_IRQ_CTRL_3,897				RT5682_IL_IRQ_MASK | RT5682_IL_IRQ_TYPE_MASK,898				RT5682_IL_IRQ_EN | RT5682_IL_IRQ_PUL);899		else900			snd_soc_component_update_bits(component,901				RT5682_IRQ_CTRL_3, RT5682_IL_IRQ_MASK,902				RT5682_IL_IRQ_EN);903	} else {904		snd_soc_component_update_bits(component, RT5682_IRQ_CTRL_3,905			RT5682_IL_IRQ_MASK, RT5682_IL_IRQ_DIS);906		snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_1,907			RT5682_SAR_BUTT_DET_MASK, RT5682_SAR_BUTT_DET_DIS);908		snd_soc_component_update_bits(component, RT5682_4BTN_IL_CMD_2,909			RT5682_4BTN_IL_MASK, RT5682_4BTN_IL_DIS);910		snd_soc_component_update_bits(component, RT5682_4BTN_IL_CMD_2,911			RT5682_4BTN_IL_RST_MASK, RT5682_4BTN_IL_RST);912		snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_13,913			RT5682_SAR_SOUR_MASK, RT5682_SAR_SOUR_TYPE);914	}915}916 917/**918 * rt5682_headset_detect - Detect headset.919 * @component: SoC audio component device.920 * @jack_insert: Jack insert or not.921 *922 * Detect whether is headset or not when jack inserted.923 *924 * Returns detect status.925 */926static int rt5682_headset_detect(struct snd_soc_component *component, int jack_insert)927{928	struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);929	struct snd_soc_dapm_context *dapm = &component->dapm;930	unsigned int val, count;931 932	if (jack_insert) {933		snd_soc_component_update_bits(component, RT5682_PWR_ANLG_1,934			RT5682_PWR_VREF2 | RT5682_PWR_MB,935			RT5682_PWR_VREF2 | RT5682_PWR_MB);936		snd_soc_component_update_bits(component,937			RT5682_PWR_ANLG_1, RT5682_PWR_FV2, 0);938		usleep_range(15000, 20000);939		snd_soc_component_update_bits(component,940			RT5682_PWR_ANLG_1, RT5682_PWR_FV2, RT5682_PWR_FV2);941		snd_soc_component_update_bits(component, RT5682_PWR_ANLG_3,942			RT5682_PWR_CBJ, RT5682_PWR_CBJ);943		snd_soc_component_update_bits(component,944			RT5682_HP_CHARGE_PUMP_1,945			RT5682_OSW_L_MASK | RT5682_OSW_R_MASK, 0);946		rt5682_enable_push_button_irq(component, false);947		snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_1,948			RT5682_TRIG_JD_MASK, RT5682_TRIG_JD_LOW);949		usleep_range(55000, 60000);950		snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_1,951			RT5682_TRIG_JD_MASK, RT5682_TRIG_JD_HIGH);952 953		count = 0;954		val = snd_soc_component_read(component, RT5682_CBJ_CTRL_2)955			& RT5682_JACK_TYPE_MASK;956		while (val == 0 && count < 50) {957			usleep_range(10000, 15000);958			val = snd_soc_component_read(component,959				RT5682_CBJ_CTRL_2) & RT5682_JACK_TYPE_MASK;960			count++;961		}962 963		switch (val) {964		case 0x1:965		case 0x2:966			rt5682->jack_type = SND_JACK_HEADSET;967			snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_1,968				RT5682_FAST_OFF_MASK, RT5682_FAST_OFF_EN);969			rt5682_enable_push_button_irq(component, true);970			break;971		default:972			rt5682->jack_type = SND_JACK_HEADPHONE;973			break;974		}975 976		snd_soc_component_update_bits(component,977			RT5682_HP_CHARGE_PUMP_1,978			RT5682_OSW_L_MASK | RT5682_OSW_R_MASK,979			RT5682_OSW_L_EN | RT5682_OSW_R_EN);980		snd_soc_component_update_bits(component, RT5682_MICBIAS_2,981			RT5682_PWR_CLK25M_MASK | RT5682_PWR_CLK1M_MASK,982			RT5682_PWR_CLK25M_PU | RT5682_PWR_CLK1M_PU);983	} else {984		rt5682_enable_push_button_irq(component, false);985		snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_1,986			RT5682_TRIG_JD_MASK, RT5682_TRIG_JD_LOW);987		if (!snd_soc_dapm_get_pin_status(dapm, "MICBIAS") &&988			!snd_soc_dapm_get_pin_status(dapm, "PLL1") &&989			!snd_soc_dapm_get_pin_status(dapm, "PLL2B"))990			snd_soc_component_update_bits(component,991				RT5682_PWR_ANLG_1, RT5682_PWR_MB, 0);992		if (!snd_soc_dapm_get_pin_status(dapm, "Vref2") &&993			!snd_soc_dapm_get_pin_status(dapm, "PLL1") &&994			!snd_soc_dapm_get_pin_status(dapm, "PLL2B"))995			snd_soc_component_update_bits(component,996				RT5682_PWR_ANLG_1, RT5682_PWR_VREF2, 0);997		snd_soc_component_update_bits(component, RT5682_PWR_ANLG_3,998			RT5682_PWR_CBJ, 0);999		snd_soc_component_update_bits(component, RT5682_MICBIAS_2,1000			RT5682_PWR_CLK25M_MASK | RT5682_PWR_CLK1M_MASK,1001			RT5682_PWR_CLK25M_PD | RT5682_PWR_CLK1M_PD);1002		snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_1,1003			RT5682_FAST_OFF_MASK, RT5682_FAST_OFF_DIS);1004 1005		rt5682->jack_type = 0;1006	}1007 1008	dev_dbg(component->dev, "jack_type = %d\n", rt5682->jack_type);1009	return rt5682->jack_type;1010}1011 1012static int rt5682_set_jack_detect(struct snd_soc_component *component,1013		struct snd_soc_jack *hs_jack, void *data)1014{1015	struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);1016 1017	rt5682->hs_jack = hs_jack;1018 1019	if (rt5682->is_sdw && !rt5682->first_hw_init)1020		return 0;1021 1022	if (!hs_jack) {1023		regmap_update_bits(rt5682->regmap, RT5682_IRQ_CTRL_2,1024			RT5682_JD1_EN_MASK, RT5682_JD1_DIS);1025		regmap_update_bits(rt5682->regmap, RT5682_RC_CLK_CTRL,1026			RT5682_POW_JDH | RT5682_POW_JDL, 0);1027		cancel_delayed_work_sync(&rt5682->jack_detect_work);1028 1029		return 0;1030	}1031 1032	if (!rt5682->is_sdw) {1033		switch (rt5682->pdata.jd_src) {1034		case RT5682_JD1:1035			snd_soc_component_update_bits(component,1036				RT5682_CBJ_CTRL_5, 0x0700, 0x0600);1037			snd_soc_component_update_bits(component,1038				RT5682_CBJ_CTRL_2, RT5682_EXT_JD_SRC,1039				RT5682_EXT_JD_SRC_MANUAL);1040			snd_soc_component_write(component, RT5682_CBJ_CTRL_1,1041				0xd142);1042			snd_soc_component_update_bits(component,1043				RT5682_CBJ_CTRL_3, RT5682_CBJ_IN_BUF_EN,1044				RT5682_CBJ_IN_BUF_EN);1045			snd_soc_component_update_bits(component,1046				RT5682_SAR_IL_CMD_1, RT5682_SAR_POW_MASK,1047				RT5682_SAR_POW_EN);1048			regmap_update_bits(rt5682->regmap, RT5682_GPIO_CTRL_1,1049				RT5682_GP1_PIN_MASK, RT5682_GP1_PIN_IRQ);1050			regmap_update_bits(rt5682->regmap, RT5682_RC_CLK_CTRL,1051				RT5682_POW_IRQ | RT5682_POW_JDH |1052				RT5682_POW_ANA, RT5682_POW_IRQ |1053				RT5682_POW_JDH | RT5682_POW_ANA);1054			regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_2,1055				RT5682_PWR_JDH, RT5682_PWR_JDH);1056			regmap_update_bits(rt5682->regmap, RT5682_IRQ_CTRL_2,1057				RT5682_JD1_EN_MASK | RT5682_JD1_POL_MASK,1058				RT5682_JD1_EN | RT5682_JD1_POL_NOR);1059			regmap_update_bits(rt5682->regmap, RT5682_4BTN_IL_CMD_4,1060				0x7f7f, (rt5682->pdata.btndet_delay << 8 |1061				rt5682->pdata.btndet_delay));1062			regmap_update_bits(rt5682->regmap, RT5682_4BTN_IL_CMD_5,1063				0x7f7f, (rt5682->pdata.btndet_delay << 8 |1064				rt5682->pdata.btndet_delay));1065			regmap_update_bits(rt5682->regmap, RT5682_4BTN_IL_CMD_6,1066				0x7f7f, (rt5682->pdata.btndet_delay << 8 |1067				rt5682->pdata.btndet_delay));1068			regmap_update_bits(rt5682->regmap, RT5682_4BTN_IL_CMD_7,1069				0x7f7f, (rt5682->pdata.btndet_delay << 8 |1070				rt5682->pdata.btndet_delay));1071			mod_delayed_work(system_power_efficient_wq,1072				&rt5682->jack_detect_work,1073				msecs_to_jiffies(250));1074			break;1075 1076		case RT5682_JD_NULL:1077			regmap_update_bits(rt5682->regmap, RT5682_IRQ_CTRL_2,1078				RT5682_JD1_EN_MASK, RT5682_JD1_DIS);1079			regmap_update_bits(rt5682->regmap, RT5682_RC_CLK_CTRL,1080				RT5682_POW_JDH | RT5682_POW_JDL, 0);1081			break;1082 1083		default:1084			dev_warn(component->dev, "Wrong JD source\n");1085			break;1086		}1087	}1088 1089	return 0;1090}1091 1092void rt5682_jack_detect_handler(struct work_struct *work)1093{1094	struct rt5682_priv *rt5682 =1095		container_of(work, struct rt5682_priv, jack_detect_work.work);1096	struct snd_soc_dapm_context *dapm;1097	int val, btn_type;1098 1099	if (!rt5682->component ||1100	    !snd_soc_card_is_instantiated(rt5682->component->card)) {1101		/* card not yet ready, try later */1102		mod_delayed_work(system_power_efficient_wq,1103				 &rt5682->jack_detect_work, msecs_to_jiffies(15));1104		return;1105	}1106 1107	if (rt5682->is_sdw) {1108		if (pm_runtime_status_suspended(rt5682->slave->dev.parent)) {1109			dev_dbg(&rt5682->slave->dev,1110				"%s: parent device is pm_runtime_status_suspended, skipping jack detection\n",1111				__func__);1112			return;1113		}1114	}1115 1116	dapm = snd_soc_component_get_dapm(rt5682->component);1117 1118	snd_soc_dapm_mutex_lock(dapm);1119	mutex_lock(&rt5682->calibrate_mutex);1120 1121	val = snd_soc_component_read(rt5682->component, RT5682_AJD1_CTRL)1122		& RT5682_JDH_RS_MASK;1123	if (!val) {1124		/* jack in */1125		if (rt5682->jack_type == 0) {1126			/* jack was out, report jack type */1127			rt5682->jack_type =1128				rt5682_headset_detect(rt5682->component, 1);1129			rt5682->irq_work_delay_time = 0;1130		} else if ((rt5682->jack_type & SND_JACK_HEADSET) ==1131			SND_JACK_HEADSET) {1132			/* jack is already in, report button event */1133			rt5682->jack_type = SND_JACK_HEADSET;1134			btn_type = rt5682_button_detect(rt5682->component);1135			/**1136			 * rt5682 can report three kinds of button behavior,1137			 * one click, double click and hold. However,1138			 * currently we will report button pressed/released1139			 * event. So all the three button behaviors are1140			 * treated as button pressed.1141			 */1142			switch (btn_type) {1143			case 0x8000:1144			case 0x4000:1145			case 0x2000:1146				rt5682->jack_type |= SND_JACK_BTN_0;1147				break;1148			case 0x1000:1149			case 0x0800:1150			case 0x0400:1151				rt5682->jack_type |= SND_JACK_BTN_1;1152				break;1153			case 0x0200:1154			case 0x0100:1155			case 0x0080:1156				rt5682->jack_type |= SND_JACK_BTN_2;1157				break;1158			case 0x0040:1159			case 0x0020:1160			case 0x0010:1161				rt5682->jack_type |= SND_JACK_BTN_3;1162				break;1163			case 0x0000: /* unpressed */1164				break;1165			default:1166				dev_err(rt5682->component->dev,1167					"Unexpected button code 0x%04x\n",1168					btn_type);1169				break;1170			}1171		}1172	} else {1173		/* jack out */1174		rt5682->jack_type = rt5682_headset_detect(rt5682->component, 0);1175		rt5682->irq_work_delay_time = 50;1176	}1177 1178	mutex_unlock(&rt5682->calibrate_mutex);1179	snd_soc_dapm_mutex_unlock(dapm);1180 1181	snd_soc_jack_report(rt5682->hs_jack, rt5682->jack_type,1182		SND_JACK_HEADSET |1183		SND_JACK_BTN_0 | SND_JACK_BTN_1 |1184		SND_JACK_BTN_2 | SND_JACK_BTN_3);1185 1186	if (!rt5682->is_sdw) {1187		if (rt5682->jack_type & (SND_JACK_BTN_0 | SND_JACK_BTN_1 |1188			SND_JACK_BTN_2 | SND_JACK_BTN_3))1189			schedule_delayed_work(&rt5682->jd_check_work, 0);1190		else1191			cancel_delayed_work_sync(&rt5682->jd_check_work);1192	}1193}1194EXPORT_SYMBOL_GPL(rt5682_jack_detect_handler);1195 1196static const struct snd_kcontrol_new rt5682_snd_controls[] = {1197	/* DAC Digital Volume */1198	SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5682_DAC1_DIG_VOL,1199		RT5682_L_VOL_SFT + 1, RT5682_R_VOL_SFT + 1, 87, 0, dac_vol_tlv),1200 1201	/* IN Boost Volume */1202	SOC_SINGLE_TLV("CBJ Boost Volume", RT5682_CBJ_BST_CTRL,1203		RT5682_BST_CBJ_SFT, 8, 0, bst_tlv),1204 1205	/* ADC Digital Volume Control */1206	SOC_DOUBLE("STO1 ADC Capture Switch", RT5682_STO1_ADC_DIG_VOL,1207		RT5682_L_MUTE_SFT, RT5682_R_MUTE_SFT, 1, 1),1208	SOC_DOUBLE_TLV("STO1 ADC Capture Volume", RT5682_STO1_ADC_DIG_VOL,1209		RT5682_L_VOL_SFT + 1, RT5682_R_VOL_SFT + 1, 63, 0, adc_vol_tlv),1210 1211	/* ADC Boost Volume Control */1212	SOC_DOUBLE_TLV("STO1 ADC Boost Gain Volume", RT5682_STO1_ADC_BOOST,1213		RT5682_STO1_ADC_L_BST_SFT, RT5682_STO1_ADC_R_BST_SFT,1214		3, 0, adc_bst_tlv),1215};1216 1217static int rt5682_div_sel(struct rt5682_priv *rt5682,1218		int target, const int div[], int size)1219{1220	int i;1221 1222	if (rt5682->sysclk < target) {1223		dev_err(rt5682->component->dev,1224			"sysclk rate %d is too low\n", rt5682->sysclk);1225		return 0;1226	}1227 1228	for (i = 0; i < size - 1; i++) {1229		dev_dbg(rt5682->component->dev, "div[%d]=%d\n", i, div[i]);1230		if (target * div[i] == rt5682->sysclk)1231			return i;1232		if (target * div[i + 1] > rt5682->sysclk) {1233			dev_dbg(rt5682->component->dev,1234				"can't find div for sysclk %d\n",1235				rt5682->sysclk);1236			return i;1237		}1238	}1239 1240	if (target * div[i] < rt5682->sysclk)1241		dev_err(rt5682->component->dev,1242			"sysclk rate %d is too high\n", rt5682->sysclk);1243 1244	return size - 1;1245}1246 1247/**1248 * set_dmic_clk - Set parameter of dmic.1249 *1250 * @w: DAPM widget.1251 * @kcontrol: The kcontrol of this widget.1252 * @event: Event id.1253 *1254 * Choose dmic clock between 1MHz and 3MHz.1255 * It is better for clock to approximate 3MHz.1256 */1257static int set_dmic_clk(struct snd_soc_dapm_widget *w,1258		struct snd_kcontrol *kcontrol, int event)1259{1260	struct snd_soc_component *component =1261		snd_soc_dapm_to_component(w->dapm);1262	struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);1263	int idx, dmic_clk_rate = 3072000;1264	static const int div[] = {2, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96, 128};1265 1266	if (rt5682->pdata.dmic_clk_rate)1267		dmic_clk_rate = rt5682->pdata.dmic_clk_rate;1268 1269	idx = rt5682_div_sel(rt5682, dmic_clk_rate, div, ARRAY_SIZE(div));1270 1271	snd_soc_component_update_bits(component, RT5682_DMIC_CTRL_1,1272		RT5682_DMIC_CLK_MASK, idx << RT5682_DMIC_CLK_SFT);1273 1274	return 0;1275}1276 1277static int set_filter_clk(struct snd_soc_dapm_widget *w,1278		struct snd_kcontrol *kcontrol, int event)1279{1280	struct snd_soc_component *component =1281		snd_soc_dapm_to_component(w->dapm);1282	struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);1283	int ref, val, reg, idx;1284	static const int div_f[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32, 48};1285	static const int div_o[] = {1, 2, 4, 6, 8, 12, 16, 24, 32, 48};1286 1287	if (rt5682->is_sdw)1288		return 0;1289 1290	val = snd_soc_component_read(component, RT5682_GPIO_CTRL_1) &1291		RT5682_GP4_PIN_MASK;1292	if (w->shift == RT5682_PWR_ADC_S1F_BIT &&1293		val == RT5682_GP4_PIN_ADCDAT2)1294		ref = 256 * rt5682->lrck[RT5682_AIF2];1295	else1296		ref = 256 * rt5682->lrck[RT5682_AIF1];1297 1298	idx = rt5682_div_sel(rt5682, ref, div_f, ARRAY_SIZE(div_f));1299 1300	if (w->shift == RT5682_PWR_ADC_S1F_BIT)1301		reg = RT5682_PLL_TRACK_3;1302	else1303		reg = RT5682_PLL_TRACK_2;1304 1305	snd_soc_component_update_bits(component, reg,1306		RT5682_FILTER_CLK_DIV_MASK, idx << RT5682_FILTER_CLK_DIV_SFT);1307 1308	/* select over sample rate */1309	for (idx = 0; idx < ARRAY_SIZE(div_o); idx++) {1310		if (rt5682->sysclk <= 12288000 * div_o[idx])1311			break;1312	}1313 1314	snd_soc_component_update_bits(component, RT5682_ADDA_CLK_1,1315		RT5682_ADC_OSR_MASK | RT5682_DAC_OSR_MASK,1316		(idx << RT5682_ADC_OSR_SFT) | (idx << RT5682_DAC_OSR_SFT));1317 1318	return 0;1319}1320 1321static int is_sys_clk_from_pll1(struct snd_soc_dapm_widget *w,1322		struct snd_soc_dapm_widget *sink)1323{1324	unsigned int val;1325	struct snd_soc_component *component =1326		snd_soc_dapm_to_component(w->dapm);1327 1328	val = snd_soc_component_read(component, RT5682_GLB_CLK);1329	val &= RT5682_SCLK_SRC_MASK;1330	if (val == RT5682_SCLK_SRC_PLL1)1331		return 1;1332	else1333		return 0;1334}1335 1336static int is_sys_clk_from_pll2(struct snd_soc_dapm_widget *w,1337		struct snd_soc_dapm_widget *sink)1338{1339	unsigned int val;1340	struct snd_soc_component *component =1341		snd_soc_dapm_to_component(w->dapm);1342 1343	val = snd_soc_component_read(component, RT5682_GLB_CLK);1344	val &= RT5682_SCLK_SRC_MASK;1345	if (val == RT5682_SCLK_SRC_PLL2)1346		return 1;1347	else1348		return 0;1349}1350 1351static int is_using_asrc(struct snd_soc_dapm_widget *w,1352		struct snd_soc_dapm_widget *sink)1353{1354	unsigned int reg, shift, val;1355	struct snd_soc_component *component =1356		snd_soc_dapm_to_component(w->dapm);1357 1358	switch (w->shift) {1359	case RT5682_ADC_STO1_ASRC_SFT:1360		reg = RT5682_PLL_TRACK_3;1361		shift = RT5682_FILTER_CLK_SEL_SFT;1362		break;1363	case RT5682_DAC_STO1_ASRC_SFT:1364		reg = RT5682_PLL_TRACK_2;1365		shift = RT5682_FILTER_CLK_SEL_SFT;1366		break;1367	default:1368		return 0;1369	}1370 1371	val = (snd_soc_component_read(component, reg) >> shift) & 0xf;1372	switch (val) {1373	case RT5682_CLK_SEL_I2S1_ASRC:1374	case RT5682_CLK_SEL_I2S2_ASRC:1375		return 1;1376	default:1377		return 0;1378	}1379}1380 1381/* Digital Mixer */1382static const struct snd_kcontrol_new rt5682_sto1_adc_l_mix[] = {1383	SOC_DAPM_SINGLE("ADC1 Switch", RT5682_STO1_ADC_MIXER,1384			RT5682_M_STO1_ADC_L1_SFT, 1, 1),1385	SOC_DAPM_SINGLE("ADC2 Switch", RT5682_STO1_ADC_MIXER,1386			RT5682_M_STO1_ADC_L2_SFT, 1, 1),1387};1388 1389static const struct snd_kcontrol_new rt5682_sto1_adc_r_mix[] = {1390	SOC_DAPM_SINGLE("ADC1 Switch", RT5682_STO1_ADC_MIXER,1391			RT5682_M_STO1_ADC_R1_SFT, 1, 1),1392	SOC_DAPM_SINGLE("ADC2 Switch", RT5682_STO1_ADC_MIXER,1393			RT5682_M_STO1_ADC_R2_SFT, 1, 1),1394};1395 1396static const struct snd_kcontrol_new rt5682_dac_l_mix[] = {1397	SOC_DAPM_SINGLE("Stereo ADC Switch", RT5682_AD_DA_MIXER,1398			RT5682_M_ADCMIX_L_SFT, 1, 1),1399	SOC_DAPM_SINGLE("DAC1 Switch", RT5682_AD_DA_MIXER,1400			RT5682_M_DAC1_L_SFT, 1, 1),1401};1402 1403static const struct snd_kcontrol_new rt5682_dac_r_mix[] = {1404	SOC_DAPM_SINGLE("Stereo ADC Switch", RT5682_AD_DA_MIXER,1405			RT5682_M_ADCMIX_R_SFT, 1, 1),1406	SOC_DAPM_SINGLE("DAC1 Switch", RT5682_AD_DA_MIXER,1407			RT5682_M_DAC1_R_SFT, 1, 1),1408};1409 1410static const struct snd_kcontrol_new rt5682_sto1_dac_l_mix[] = {1411	SOC_DAPM_SINGLE("DAC L1 Switch", RT5682_STO1_DAC_MIXER,1412			RT5682_M_DAC_L1_STO_L_SFT, 1, 1),1413	SOC_DAPM_SINGLE("DAC R1 Switch", RT5682_STO1_DAC_MIXER,1414			RT5682_M_DAC_R1_STO_L_SFT, 1, 1),1415};1416 1417static const struct snd_kcontrol_new rt5682_sto1_dac_r_mix[] = {1418	SOC_DAPM_SINGLE("DAC L1 Switch", RT5682_STO1_DAC_MIXER,1419			RT5682_M_DAC_L1_STO_R_SFT, 1, 1),1420	SOC_DAPM_SINGLE("DAC R1 Switch", RT5682_STO1_DAC_MIXER,1421			RT5682_M_DAC_R1_STO_R_SFT, 1, 1),1422};1423 1424/* Analog Input Mixer */1425static const struct snd_kcontrol_new rt5682_rec1_l_mix[] = {1426	SOC_DAPM_SINGLE("CBJ Switch", RT5682_REC_MIXER,1427			RT5682_M_CBJ_RM1_L_SFT, 1, 1),1428};1429 1430/* STO1 ADC1 Source */1431/* MX-26 [13] [5] */1432static const char * const rt5682_sto1_adc1_src[] = {1433	"DAC MIX", "ADC"1434};1435 1436static SOC_ENUM_SINGLE_DECL(1437	rt5682_sto1_adc1l_enum, RT5682_STO1_ADC_MIXER,1438	RT5682_STO1_ADC1L_SRC_SFT, rt5682_sto1_adc1_src);1439 1440static const struct snd_kcontrol_new rt5682_sto1_adc1l_mux =1441	SOC_DAPM_ENUM("Stereo1 ADC1L Source", rt5682_sto1_adc1l_enum);1442 1443static SOC_ENUM_SINGLE_DECL(1444	rt5682_sto1_adc1r_enum, RT5682_STO1_ADC_MIXER,1445	RT5682_STO1_ADC1R_SRC_SFT, rt5682_sto1_adc1_src);1446 1447static const struct snd_kcontrol_new rt5682_sto1_adc1r_mux =1448	SOC_DAPM_ENUM("Stereo1 ADC1L Source", rt5682_sto1_adc1r_enum);1449 1450/* STO1 ADC Source */1451/* MX-26 [11:10] [3:2] */1452static const char * const rt5682_sto1_adc_src[] = {1453	"ADC1 L", "ADC1 R"1454};1455 1456static SOC_ENUM_SINGLE_DECL(1457	rt5682_sto1_adcl_enum, RT5682_STO1_ADC_MIXER,1458	RT5682_STO1_ADCL_SRC_SFT, rt5682_sto1_adc_src);1459 1460static const struct snd_kcontrol_new rt5682_sto1_adcl_mux =1461	SOC_DAPM_ENUM("Stereo1 ADCL Source", rt5682_sto1_adcl_enum);1462 1463static SOC_ENUM_SINGLE_DECL(1464	rt5682_sto1_adcr_enum, RT5682_STO1_ADC_MIXER,1465	RT5682_STO1_ADCR_SRC_SFT, rt5682_sto1_adc_src);1466 1467static const struct snd_kcontrol_new rt5682_sto1_adcr_mux =1468	SOC_DAPM_ENUM("Stereo1 ADCR Source", rt5682_sto1_adcr_enum);1469 1470/* STO1 ADC2 Source */1471/* MX-26 [12] [4] */1472static const char * const rt5682_sto1_adc2_src[] = {1473	"DAC MIX", "DMIC"1474};1475 1476static SOC_ENUM_SINGLE_DECL(1477	rt5682_sto1_adc2l_enum, RT5682_STO1_ADC_MIXER,1478	RT5682_STO1_ADC2L_SRC_SFT, rt5682_sto1_adc2_src);1479 1480static const struct snd_kcontrol_new rt5682_sto1_adc2l_mux =1481	SOC_DAPM_ENUM("Stereo1 ADC2L Source", rt5682_sto1_adc2l_enum);1482 1483static SOC_ENUM_SINGLE_DECL(1484	rt5682_sto1_adc2r_enum, RT5682_STO1_ADC_MIXER,1485	RT5682_STO1_ADC2R_SRC_SFT, rt5682_sto1_adc2_src);1486 1487static const struct snd_kcontrol_new rt5682_sto1_adc2r_mux =1488	SOC_DAPM_ENUM("Stereo1 ADC2R Source", rt5682_sto1_adc2r_enum);1489 1490/* MX-79 [6:4] I2S1 ADC data location */1491static const unsigned int rt5682_if1_adc_slot_values[] = {1492	0,1493	2,1494	4,1495	6,1496};1497 1498static const char * const rt5682_if1_adc_slot_src[] = {1499	"Slot 0", "Slot 2", "Slot 4", "Slot 6"1500};1501 1502static SOC_VALUE_ENUM_SINGLE_DECL(rt5682_if1_adc_slot_enum,1503	RT5682_TDM_CTRL, RT5682_TDM_ADC_LCA_SFT, RT5682_TDM_ADC_LCA_MASK,1504	rt5682_if1_adc_slot_src, rt5682_if1_adc_slot_values);1505 1506static const struct snd_kcontrol_new rt5682_if1_adc_slot_mux =1507	SOC_DAPM_ENUM("IF1 ADC Slot location", rt5682_if1_adc_slot_enum);1508 1509/* Analog DAC L1 Source, Analog DAC R1 Source*/1510/* MX-2B [4], MX-2B [0]*/1511static const char * const rt5682_alg_dac1_src[] = {1512	"Stereo1 DAC Mixer", "DAC1"1513};1514 1515static SOC_ENUM_SINGLE_DECL(1516	rt5682_alg_dac_l1_enum, RT5682_A_DAC1_MUX,1517	RT5682_A_DACL1_SFT, rt5682_alg_dac1_src);1518 1519static const struct snd_kcontrol_new rt5682_alg_dac_l1_mux =1520	SOC_DAPM_ENUM("Analog DAC L1 Source", rt5682_alg_dac_l1_enum);1521 1522static SOC_ENUM_SINGLE_DECL(1523	rt5682_alg_dac_r1_enum, RT5682_A_DAC1_MUX,1524	RT5682_A_DACR1_SFT, rt5682_alg_dac1_src);1525 1526static const struct snd_kcontrol_new rt5682_alg_dac_r1_mux =1527	SOC_DAPM_ENUM("Analog DAC R1 Source", rt5682_alg_dac_r1_enum);1528 1529/* Out Switch */1530static const struct snd_kcontrol_new hpol_switch =1531	SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5682_HP_CTRL_1,1532		RT5682_L_MUTE_SFT, 1, 1);1533static const struct snd_kcontrol_new hpor_switch =1534	SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5682_HP_CTRL_1,1535		RT5682_R_MUTE_SFT, 1, 1);1536 1537static int rt5682_hp_event(struct snd_soc_dapm_widget *w,1538		struct snd_kcontrol *kcontrol, int event)1539{1540	struct snd_soc_component *component =1541		snd_soc_dapm_to_component(w->dapm);1542 1543	switch (event) {1544	case SND_SOC_DAPM_PRE_PMU:1545		snd_soc_component_update_bits(component, RT5682_HP_CTRL_2,1546			RT5682_HP_C2_DAC_AMP_MUTE, 0);1547		snd_soc_component_update_bits(component, RT5682_HP_LOGIC_CTRL_2,1548			RT5682_HP_LC2_SIG_SOUR2_MASK, RT5682_HP_LC2_SIG_SOUR2_REG);1549		snd_soc_component_update_bits(component,1550			RT5682_DEPOP_1, 0x60, 0x60);1551		snd_soc_component_update_bits(component,1552			RT5682_DAC_ADC_DIG_VOL1, 0x00c0, 0x0080);1553		snd_soc_component_update_bits(component, RT5682_HP_CTRL_2,1554			RT5682_HP_C2_DAC_L_EN | RT5682_HP_C2_DAC_R_EN,1555			RT5682_HP_C2_DAC_L_EN | RT5682_HP_C2_DAC_R_EN);1556		usleep_range(5000, 10000);1557		snd_soc_component_update_bits(component, RT5682_CHARGE_PUMP_1,1558			RT5682_CP_SW_SIZE_MASK, RT5682_CP_SW_SIZE_L);1559		break;1560 1561	case SND_SOC_DAPM_POST_PMD:1562		snd_soc_component_update_bits(component, RT5682_HP_CTRL_2,1563			RT5682_HP_C2_DAC_L_EN | RT5682_HP_C2_DAC_R_EN, 0);1564		snd_soc_component_update_bits(component, RT5682_CHARGE_PUMP_1,1565			RT5682_CP_SW_SIZE_MASK, RT5682_CP_SW_SIZE_M);1566		snd_soc_component_update_bits(component,1567			RT5682_DEPOP_1, 0x60, 0x0);1568		snd_soc_component_update_bits(component,1569			RT5682_DAC_ADC_DIG_VOL1, 0x00c0, 0x0000);1570		break;1571	}1572 1573	return 0;1574}1575 1576static int set_dmic_power(struct snd_soc_dapm_widget *w,1577		struct snd_kcontrol *kcontrol, int event)1578{1579	struct snd_soc_component *component =1580		snd_soc_dapm_to_component(w->dapm);1581	struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);1582	unsigned int delay = 50, val;1583 1584	if (rt5682->pdata.dmic_delay)1585		delay = rt5682->pdata.dmic_delay;1586 1587	switch (event) {1588	case SND_SOC_DAPM_POST_PMU:1589		val = snd_soc_component_read(component, RT5682_GLB_CLK);1590		val &= RT5682_SCLK_SRC_MASK;1591		if (val == RT5682_SCLK_SRC_PLL1 || val == RT5682_SCLK_SRC_PLL2)1592			snd_soc_component_update_bits(component,1593				RT5682_PWR_ANLG_1,1594				RT5682_PWR_VREF2 | RT5682_PWR_MB,1595				RT5682_PWR_VREF2 | RT5682_PWR_MB);1596 1597		/*Add delay to avoid pop noise*/1598		msleep(delay);1599		break;1600 1601	case SND_SOC_DAPM_POST_PMD:1602		if (!rt5682->jack_type) {1603			if (!snd_soc_dapm_get_pin_status(w->dapm, "MICBIAS"))1604				snd_soc_component_update_bits(component,1605					RT5682_PWR_ANLG_1, RT5682_PWR_MB, 0);1606			if (!snd_soc_dapm_get_pin_status(w->dapm, "Vref2"))1607				snd_soc_component_update_bits(component,1608					RT5682_PWR_ANLG_1, RT5682_PWR_VREF2, 0);1609		}1610		break;1611	}1612 1613	return 0;1614}1615 1616static int rt5682_set_verf(struct snd_soc_dapm_widget *w,1617		struct snd_kcontrol *kcontrol, int event)1618{1619	struct snd_soc_component *component =1620		snd_soc_dapm_to_component(w->dapm);1621 1622	switch (event) {1623	case SND_SOC_DAPM_PRE_PMU:1624		switch (w->shift) {1625		case RT5682_PWR_VREF1_BIT:1626			snd_soc_component_update_bits(component,1627				RT5682_PWR_ANLG_1, RT5682_PWR_FV1, 0);1628			break;1629 1630		case RT5682_PWR_VREF2_BIT:1631			snd_soc_component_update_bits(component,1632				RT5682_PWR_ANLG_1, RT5682_PWR_FV2, 0);1633			break;1634		}1635		break;1636 1637	case SND_SOC_DAPM_POST_PMU:1638		usleep_range(15000, 20000);1639		switch (w->shift) {1640		case RT5682_PWR_VREF1_BIT:1641			snd_soc_component_update_bits(component,1642				RT5682_PWR_ANLG_1, RT5682_PWR_FV1,1643				RT5682_PWR_FV1);1644			break;1645 1646		case RT5682_PWR_VREF2_BIT:1647			snd_soc_component_update_bits(component,1648				RT5682_PWR_ANLG_1, RT5682_PWR_FV2,1649				RT5682_PWR_FV2);1650			break;1651		}1652		break;1653	}1654 1655	return 0;1656}1657 1658static const unsigned int rt5682_adcdat_pin_values[] = {1659	1,1660	3,1661};1662 1663static const char * const rt5682_adcdat_pin_select[] = {1664	"ADCDAT1",1665	"ADCDAT2",1666};1667 1668static SOC_VALUE_ENUM_SINGLE_DECL(rt5682_adcdat_pin_enum,1669	RT5682_GPIO_CTRL_1, RT5682_GP4_PIN_SFT, RT5682_GP4_PIN_MASK,1670	rt5682_adcdat_pin_select, rt5682_adcdat_pin_values);1671 1672static const struct snd_kcontrol_new rt5682_adcdat_pin_ctrl =1673	SOC_DAPM_ENUM("ADCDAT", rt5682_adcdat_pin_enum);1674 1675static const unsigned int rt5682_hpo_sig_out_values[] = {1676	2,1677	7,1678};1679 1680static const char * const rt5682_hpo_sig_out_mode[] = {1681	"Legacy",1682	"OneBit",1683};1684 1685static SOC_VALUE_ENUM_SINGLE_DECL(rt5682_hpo_sig_out_enum,1686	RT5682_HP_LOGIC_CTRL_2, 0, RT5682_HP_LC2_SIG_SOUR1_MASK,1687	rt5682_hpo_sig_out_mode, rt5682_hpo_sig_out_values);1688 1689static const struct snd_kcontrol_new rt5682_hpo_sig_demux =1690	SOC_DAPM_ENUM("HPO Signal Demux", rt5682_hpo_sig_out_enum);1691 1692static const struct snd_soc_dapm_widget rt5682_dapm_widgets[] = {1693	SND_SOC_DAPM_SUPPLY("LDO2", RT5682_PWR_ANLG_3, RT5682_PWR_LDO2_BIT,1694		0, NULL, 0),1695	SND_SOC_DAPM_SUPPLY("PLL1", RT5682_PWR_ANLG_3, RT5682_PWR_PLL_BIT,1696		0, NULL, 0),1697	SND_SOC_DAPM_SUPPLY("PLL2B", RT5682_PWR_ANLG_3, RT5682_PWR_PLL2B_BIT,1698		0, NULL, 0),1699	SND_SOC_DAPM_SUPPLY("PLL2F", RT5682_PWR_ANLG_3, RT5682_PWR_PLL2F_BIT,1700		0, set_filter_clk, SND_SOC_DAPM_PRE_PMU),1701	SND_SOC_DAPM_SUPPLY("Vref1", RT5682_PWR_ANLG_1, RT5682_PWR_VREF1_BIT, 0,1702		rt5682_set_verf, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),1703	SND_SOC_DAPM_SUPPLY("Vref2", SND_SOC_NOPM, 0, 0, NULL, 0),1704	SND_SOC_DAPM_SUPPLY("MICBIAS", SND_SOC_NOPM, 0, 0, NULL, 0),1705 1706	/* ASRC */1707	SND_SOC_DAPM_SUPPLY_S("DAC STO1 ASRC", 1, RT5682_PLL_TRACK_1,1708		RT5682_DAC_STO1_ASRC_SFT, 0, NULL, 0),1709	SND_SOC_DAPM_SUPPLY_S("ADC STO1 ASRC", 1, RT5682_PLL_TRACK_1,1710		RT5682_ADC_STO1_ASRC_SFT, 0, NULL, 0),1711	SND_SOC_DAPM_SUPPLY_S("AD ASRC", 1, RT5682_PLL_TRACK_1,1712		RT5682_AD_ASRC_SFT, 0, NULL, 0),1713	SND_SOC_DAPM_SUPPLY_S("DA ASRC", 1, RT5682_PLL_TRACK_1,1714		RT5682_DA_ASRC_SFT, 0, NULL, 0),1715	SND_SOC_DAPM_SUPPLY_S("DMIC ASRC", 1, RT5682_PLL_TRACK_1,1716		RT5682_DMIC_ASRC_SFT, 0, NULL, 0),1717 1718	/* Input Side */1719	SND_SOC_DAPM_SUPPLY("MICBIAS1", RT5682_PWR_ANLG_2, RT5682_PWR_MB1_BIT,1720		0, NULL, 0),1721	SND_SOC_DAPM_SUPPLY("MICBIAS2", RT5682_PWR_ANLG_2, RT5682_PWR_MB2_BIT,1722		0, NULL, 0),1723 1724	/* Input Lines */1725	SND_SOC_DAPM_INPUT("DMIC L1"),1726	SND_SOC_DAPM_INPUT("DMIC R1"),1727 1728	SND_SOC_DAPM_INPUT("IN1P"),1729 1730	SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0,1731		set_dmic_clk, SND_SOC_DAPM_PRE_PMU),1732	SND_SOC_DAPM_SUPPLY("DMIC1 Power", RT5682_DMIC_CTRL_1,1733		RT5682_DMIC_1_EN_SFT, 0, set_dmic_power,1734		SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),1735 1736	/* Boost */1737	SND_SOC_DAPM_PGA("BST1 CBJ", SND_SOC_NOPM,1738		0, 0, NULL, 0),1739 1740	/* REC Mixer */1741	SND_SOC_DAPM_MIXER("RECMIX1L", SND_SOC_NOPM, 0, 0, rt5682_rec1_l_mix,1742		ARRAY_SIZE(rt5682_rec1_l_mix)),1743	SND_SOC_DAPM_SUPPLY("RECMIX1L Power", RT5682_PWR_ANLG_2,1744		RT5682_PWR_RM1_L_BIT, 0, NULL, 0),1745 1746	/* ADCs */1747	SND_SOC_DAPM_ADC("ADC1 L", NULL, SND_SOC_NOPM, 0, 0),1748	SND_SOC_DAPM_ADC("ADC1 R", NULL, SND_SOC_NOPM, 0, 0),1749 1750	SND_SOC_DAPM_SUPPLY("ADC1 L Power", RT5682_PWR_DIG_1,1751		RT5682_PWR_ADC_L1_BIT, 0, NULL, 0),1752	SND_SOC_DAPM_SUPPLY("ADC1 R Power", RT5682_PWR_DIG_1,1753		RT5682_PWR_ADC_R1_BIT, 0, NULL, 0),1754	SND_SOC_DAPM_SUPPLY("ADC1 clock", RT5682_CHOP_ADC,1755		RT5682_CKGEN_ADC1_SFT, 0, NULL, 0),1756 1757	/* ADC Mux */1758	SND_SOC_DAPM_MUX("Stereo1 ADC L1 Mux", SND_SOC_NOPM, 0, 0,1759		&rt5682_sto1_adc1l_mux),1760	SND_SOC_DAPM_MUX("Stereo1 ADC R1 Mux", SND_SOC_NOPM, 0, 0,1761		&rt5682_sto1_adc1r_mux),1762	SND_SOC_DAPM_MUX("Stereo1 ADC L2 Mux", SND_SOC_NOPM, 0, 0,1763		&rt5682_sto1_adc2l_mux),1764	SND_SOC_DAPM_MUX("Stereo1 ADC R2 Mux", SND_SOC_NOPM, 0, 0,1765		&rt5682_sto1_adc2r_mux),1766	SND_SOC_DAPM_MUX("Stereo1 ADC L Mux", SND_SOC_NOPM, 0, 0,1767		&rt5682_sto1_adcl_mux),1768	SND_SOC_DAPM_MUX("Stereo1 ADC R Mux", SND_SOC_NOPM, 0, 0,1769		&rt5682_sto1_adcr_mux),1770	SND_SOC_DAPM_MUX("IF1_ADC Mux", SND_SOC_NOPM, 0, 0,1771		&rt5682_if1_adc_slot_mux),1772 1773	/* ADC Mixer */1774	SND_SOC_DAPM_SUPPLY("ADC Stereo1 Filter", RT5682_PWR_DIG_2,1775		RT5682_PWR_ADC_S1F_BIT, 0, set_filter_clk,1776		SND_SOC_DAPM_PRE_PMU),1777	SND_SOC_DAPM_MIXER("Stereo1 ADC MIXL", RT5682_STO1_ADC_DIG_VOL,1778		RT5682_L_MUTE_SFT, 1, rt5682_sto1_adc_l_mix,1779		ARRAY_SIZE(rt5682_sto1_adc_l_mix)),1780	SND_SOC_DAPM_MIXER("Stereo1 ADC MIXR", RT5682_STO1_ADC_DIG_VOL,1781		RT5682_R_MUTE_SFT, 1, rt5682_sto1_adc_r_mix,1782		ARRAY_SIZE(rt5682_sto1_adc_r_mix)),1783 1784	/* ADC PGA */1785	SND_SOC_DAPM_PGA("Stereo1 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),1786 1787	/* Digital Interface */1788	SND_SOC_DAPM_SUPPLY("I2S1", RT5682_PWR_DIG_1, RT5682_PWR_I2S1_BIT,1789		0, NULL, 0),1790	SND_SOC_DAPM_SUPPLY("I2S2", RT5682_PWR_DIG_1, RT5682_PWR_I2S2_BIT,1791		0, NULL, 0),1792	SND_SOC_DAPM_PGA("IF1 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),1793	SND_SOC_DAPM_PGA("IF1 DAC1 L", SND_SOC_NOPM, 0, 0, NULL, 0),1794	SND_SOC_DAPM_PGA("IF1 DAC1 R", SND_SOC_NOPM, 0, 0, NULL, 0),1795	SND_SOC_DAPM_PGA("SOUND DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),1796	SND_SOC_DAPM_PGA("SOUND DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),1797 1798	/* Digital Interface Select */1799	SND_SOC_DAPM_MUX("IF1 01 ADC Swap Mux", SND_SOC_NOPM, 0, 0,1800		&rt5682_if1_01_adc_swap_mux),1801	SND_SOC_DAPM_MUX("IF1 23 ADC Swap Mux", SND_SOC_NOPM, 0, 0,1802		&rt5682_if1_23_adc_swap_mux),1803	SND_SOC_DAPM_MUX("IF1 45 ADC Swap Mux", SND_SOC_NOPM, 0, 0,1804		&rt5682_if1_45_adc_swap_mux),1805	SND_SOC_DAPM_MUX("IF1 67 ADC Swap Mux", SND_SOC_NOPM, 0, 0,1806		&rt5682_if1_67_adc_swap_mux),1807	SND_SOC_DAPM_MUX("IF2 ADC Swap Mux", SND_SOC_NOPM, 0, 0,1808		&rt5682_if2_adc_swap_mux),1809 1810	SND_SOC_DAPM_MUX("ADCDAT Mux", SND_SOC_NOPM, 0, 0,1811		&rt5682_adcdat_pin_ctrl),1812 1813	SND_SOC_DAPM_MUX("DAC L Mux", SND_SOC_NOPM, 0, 0,1814		&rt5682_dac_l_mux),1815	SND_SOC_DAPM_MUX("DAC R Mux", SND_SOC_NOPM, 0, 0,1816		&rt5682_dac_r_mux),1817 1818	/* Audio Interface */1819	SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0,1820		RT5682_I2S1_SDP, RT5682_SEL_ADCDAT_SFT, 1),1821	SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0,1822		RT5682_I2S2_SDP, RT5682_I2S2_PIN_CFG_SFT, 1),1823	SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),1824	SND_SOC_DAPM_AIF_IN("SDWRX", "SDW Playback", 0, SND_SOC_NOPM, 0, 0),1825	SND_SOC_DAPM_AIF_OUT("SDWTX", "SDW Capture", 0, SND_SOC_NOPM, 0, 0),1826 1827	/* Output Side */1828	/* DAC mixer before sound effect  */1829	SND_SOC_DAPM_MIXER("DAC1 MIXL", SND_SOC_NOPM, 0, 0,1830		rt5682_dac_l_mix, ARRAY_SIZE(rt5682_dac_l_mix)),1831	SND_SOC_DAPM_MIXER("DAC1 MIXR", SND_SOC_NOPM, 0, 0,1832		rt5682_dac_r_mix, ARRAY_SIZE(rt5682_dac_r_mix)),1833 1834	/* DAC channel Mux */1835	SND_SOC_DAPM_MUX("DAC L1 Source", SND_SOC_NOPM, 0, 0,1836		&rt5682_alg_dac_l1_mux),1837	SND_SOC_DAPM_MUX("DAC R1 Source", SND_SOC_NOPM, 0, 0,1838		&rt5682_alg_dac_r1_mux),1839 1840	/* DAC Mixer */1841	SND_SOC_DAPM_SUPPLY("DAC Stereo1 Filter", RT5682_PWR_DIG_2,1842		RT5682_PWR_DAC_S1F_BIT, 0, set_filter_clk,1843		SND_SOC_DAPM_PRE_PMU),1844	SND_SOC_DAPM_MIXER("Stereo1 DAC MIXL", SND_SOC_NOPM, 0, 0,1845		rt5682_sto1_dac_l_mix, ARRAY_SIZE(rt5682_sto1_dac_l_mix)),1846	SND_SOC_DAPM_MIXER("Stereo1 DAC MIXR", SND_SOC_NOPM, 0, 0,1847		rt5682_sto1_dac_r_mix, ARRAY_SIZE(rt5682_sto1_dac_r_mix)),1848 1849	/* DACs */1850	SND_SOC_DAPM_DAC("DAC L1", NULL, RT5682_PWR_DIG_1,1851		RT5682_PWR_DAC_L1_BIT, 0),1852	SND_SOC_DAPM_DAC("DAC R1", NULL, RT5682_PWR_DIG_1,1853		RT5682_PWR_DAC_R1_BIT, 0),1854	SND_SOC_DAPM_SUPPLY_S("DAC 1 Clock", 3, RT5682_CHOP_DAC,1855		RT5682_CKGEN_DAC1_SFT, 0, NULL, 0),1856 1857	/* HPO */1858	SND_SOC_DAPM_PGA_S("HP Amp", 1, SND_SOC_NOPM, 0, 0, rt5682_hp_event,1859		SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_PRE_PMU),1860 1861	SND_SOC_DAPM_SUPPLY("HP Amp L", RT5682_PWR_ANLG_1,1862		RT5682_PWR_HA_L_BIT, 0, NULL, 0),1863	SND_SOC_DAPM_SUPPLY("HP Amp R", RT5682_PWR_ANLG_1,1864		RT5682_PWR_HA_R_BIT, 0, NULL, 0),1865	SND_SOC_DAPM_SUPPLY_S("Charge Pump", 1, RT5682_DEPOP_1,1866		RT5682_PUMP_EN_SFT, 0, NULL, 0),1867	SND_SOC_DAPM_SUPPLY_S("Capless", 2, RT5682_DEPOP_1,1868		RT5682_CAPLESS_EN_SFT, 0, NULL, 0),1869 1870	SND_SOC_DAPM_SWITCH("HPOL Playback", SND_SOC_NOPM, 0, 0,1871		&hpol_switch),1872	SND_SOC_DAPM_SWITCH("HPOR Playback", SND_SOC_NOPM, 0, 0,1873		&hpor_switch),1874 1875	SND_SOC_DAPM_OUT_DRV("HPO Legacy", SND_SOC_NOPM, 0, 0, NULL, 0),1876	SND_SOC_DAPM_OUT_DRV("HPO OneBit", SND_SOC_NOPM, 0, 0, NULL, 0),1877	SND_SOC_DAPM_DEMUX("HPO Signal Demux", SND_SOC_NOPM, 0, 0, &rt5682_hpo_sig_demux),1878 1879	/* CLK DET */1880	SND_SOC_DAPM_SUPPLY("CLKDET SYS", RT5682_CLK_DET,1881		RT5682_SYS_CLK_DET_SFT,	0, NULL, 0),1882	SND_SOC_DAPM_SUPPLY("CLKDET PLL1", RT5682_CLK_DET,1883		RT5682_PLL1_CLK_DET_SFT, 0, NULL, 0),1884	SND_SOC_DAPM_SUPPLY("CLKDET PLL2", RT5682_CLK_DET,1885		RT5682_PLL2_CLK_DET_SFT, 0, NULL, 0),1886	SND_SOC_DAPM_SUPPLY("CLKDET", RT5682_CLK_DET,1887		RT5682_POW_CLK_DET_SFT, 0, NULL, 0),1888 1889	/* Output Lines */1890	SND_SOC_DAPM_OUTPUT("HPOL"),1891	SND_SOC_DAPM_OUTPUT("HPOR"),1892};1893 1894static const struct snd_soc_dapm_route rt5682_dapm_routes[] = {1895	/*PLL*/1896	{"ADC Stereo1 Filter", NULL, "PLL1", is_sys_clk_from_pll1},1897	{"ADC Stereo1 Filter", NULL, "PLL2B", is_sys_clk_from_pll2},1898	{"ADC Stereo1 Filter", NULL, "PLL2F", is_sys_clk_from_pll2},1899	{"DAC Stereo1 Filter", NULL, "PLL1", is_sys_clk_from_pll1},1900	{"DAC Stereo1 Filter", NULL, "PLL2B", is_sys_clk_from_pll2},1901	{"DAC Stereo1 Filter", NULL, "PLL2F", is_sys_clk_from_pll2},1902 1903	/*ASRC*/1904	{"ADC Stereo1 Filter", NULL, "ADC STO1 ASRC", is_using_asrc},1905	{"DAC Stereo1 Filter", NULL, "DAC STO1 ASRC", is_using_asrc},1906	{"ADC STO1 ASRC", NULL, "AD ASRC"},1907	{"ADC STO1 ASRC", NULL, "DA ASRC"},1908	{"ADC STO1 ASRC", NULL, "CLKDET"},1909	{"DAC STO1 ASRC", NULL, "AD ASRC"},1910	{"DAC STO1 ASRC", NULL, "DA ASRC"},1911	{"DAC STO1 ASRC", NULL, "CLKDET"},1912 1913	/*Vref*/1914	{"MICBIAS1", NULL, "Vref1"},1915	{"MICBIAS2", NULL, "Vref1"},1916 1917	{"CLKDET SYS", NULL, "CLKDET"},1918 1919	{"BST1 CBJ", NULL, "IN1P"},1920 1921	{"RECMIX1L", "CBJ Switch", "BST1 CBJ"},1922	{"RECMIX1L", NULL, "RECMIX1L Power"},1923 1924	{"ADC1 L", NULL, "RECMIX1L"},1925	{"ADC1 L", NULL, "ADC1 L Power"},1926	{"ADC1 L", NULL, "ADC1 clock"},1927 1928	{"DMIC L1", NULL, "DMIC CLK"},1929	{"DMIC L1", NULL, "DMIC1 Power"},1930	{"DMIC R1", NULL, "DMIC CLK"},1931	{"DMIC R1", NULL, "DMIC1 Power"},1932	{"DMIC CLK", NULL, "DMIC ASRC"},1933 1934	{"Stereo1 ADC L Mux", "ADC1 L", "ADC1 L"},1935	{"Stereo1 ADC L Mux", "ADC1 R", "ADC1 R"},1936	{"Stereo1 ADC R Mux", "ADC1 L", "ADC1 L"},1937	{"Stereo1 ADC R Mux", "ADC1 R", "ADC1 R"},1938 1939	{"Stereo1 ADC L1 Mux", "ADC", "Stereo1 ADC L Mux"},1940	{"Stereo1 ADC L1 Mux", "DAC MIX", "Stereo1 DAC MIXL"},1941	{"Stereo1 ADC L2 Mux", "DMIC", "DMIC L1"},1942	{"Stereo1 ADC L2 Mux", "DAC MIX", "Stereo1 DAC MIXL"},1943 1944	{"Stereo1 ADC R1 Mux", "ADC", "Stereo1 ADC R Mux"},1945	{"Stereo1 ADC R1 Mux", "DAC MIX", "Stereo1 DAC MIXR"},1946	{"Stereo1 ADC R2 Mux", "DMIC", "DMIC R1"},1947	{"Stereo1 ADC R2 Mux", "DAC MIX", "Stereo1 DAC MIXR"},1948 1949	{"Stereo1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC L1 Mux"},1950	{"Stereo1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC L2 Mux"},1951	{"Stereo1 ADC MIXL", NULL, "ADC Stereo1 Filter"},1952 1953	{"Stereo1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC R1 Mux"},1954	{"Stereo1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC R2 Mux"},1955	{"Stereo1 ADC MIXR", NULL, "ADC Stereo1 Filter"},1956 1957	{"Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXL"},1958	{"Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXR"},1959 1960	{"IF1 01 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},1961	{"IF1 01 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},1962	{"IF1 01 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},1963	{"IF1 01 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},1964	{"IF1 23 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},1965	{"IF1 23 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},1966	{"IF1 23 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},1967	{"IF1 23 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},1968	{"IF1 45 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},1969	{"IF1 45 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},1970	{"IF1 45 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},1971	{"IF1 45 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},1972	{"IF1 67 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},1973	{"IF1 67 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},1974	{"IF1 67 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},1975	{"IF1 67 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},1976 1977	{"IF1_ADC Mux", "Slot 0", "IF1 01 ADC Swap Mux"},1978	{"IF1_ADC Mux", "Slot 2", "IF1 23 ADC Swap Mux"},1979	{"IF1_ADC Mux", "Slot 4", "IF1 45 ADC Swap Mux"},1980	{"IF1_ADC Mux", "Slot 6", "IF1 67 ADC Swap Mux"},1981	{"ADCDAT Mux", "ADCDAT1", "IF1_ADC Mux"},1982	{"AIF1TX", NULL, "I2S1"},1983	{"AIF1TX", NULL, "ADCDAT Mux"},1984	{"IF2 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},1985	{"IF2 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},1986	{"IF2 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},1987	{"IF2 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},1988	{"ADCDAT Mux", "ADCDAT2", "IF2 ADC Swap Mux"},1989	{"AIF2TX", NULL, "ADCDAT Mux"},1990 1991	{"SDWTX", NULL, "PLL2B"},1992	{"SDWTX", NULL, "PLL2F"},1993	{"SDWTX", NULL, "ADCDAT Mux"},1994 1995	{"IF1 DAC1 L", NULL, "AIF1RX"},1996	{"IF1 DAC1 L", NULL, "I2S1"},1997	{"IF1 DAC1 L", NULL, "DAC Stereo1 Filter"},1998	{"IF1 DAC1 R", NULL, "AIF1RX"},1999	{"IF1 DAC1 R", NULL, "I2S1"},2000	{"IF1 DAC1 R", NULL, "DAC Stereo1 Filter"},2001 2002	{"SOUND DAC L", NULL, "SDWRX"},2003	{"SOUND DAC L", NULL, "DAC Stereo1 Filter"},2004	{"SOUND DAC L", NULL, "PLL2B"},2005	{"SOUND DAC L", NULL, "PLL2F"},2006	{"SOUND DAC R", NULL, "SDWRX"},2007	{"SOUND DAC R", NULL, "DAC Stereo1 Filter"},2008	{"SOUND DAC R", NULL, "PLL2B"},2009	{"SOUND DAC R", NULL, "PLL2F"},2010 2011	{"DAC L Mux", "IF1", "IF1 DAC1 L"},2012	{"DAC L Mux", "SOUND", "SOUND DAC L"},2013	{"DAC R Mux", "IF1", "IF1 DAC1 R"},2014	{"DAC R Mux", "SOUND", "SOUND DAC R"},2015 2016	{"DAC1 MIXL", "Stereo ADC Switch", "Stereo1 ADC MIXL"},2017	{"DAC1 MIXL", "DAC1 Switch", "DAC L Mux"},2018	{"DAC1 MIXR", "Stereo ADC Switch", "Stereo1 ADC MIXR"},2019	{"DAC1 MIXR", "DAC1 Switch", "DAC R Mux"},2020 2021	{"Stereo1 DAC MIXL", "DAC L1 Switch", "DAC1 MIXL"},2022	{"Stereo1 DAC MIXL", "DAC R1 Switch", "DAC1 MIXR"},2023 2024	{"Stereo1 DAC MIXR", "DAC R1 Switch", "DAC1 MIXR"},2025	{"Stereo1 DAC MIXR", "DAC L1 Switch", "DAC1 MIXL"},2026 2027	{"DAC L1 Source", "DAC1", "DAC1 MIXL"},2028	{"DAC L1 Source", "Stereo1 DAC Mixer", "Stereo1 DAC MIXL"},2029	{"DAC R1 Source", "DAC1", "DAC1 MIXR"},2030	{"DAC R1 Source", "Stereo1 DAC Mixer", "Stereo1 DAC MIXR"},2031 2032	{"DAC L1", NULL, "DAC L1 Source"},2033	{"DAC R1", NULL, "DAC R1 Source"},2034 2035	{"DAC L1", NULL, "DAC 1 Clock"},2036	{"DAC R1", NULL, "DAC 1 Clock"},2037 2038	{"HP Amp", NULL, "DAC L1"},2039	{"HP Amp", NULL, "DAC R1"},2040	{"HP Amp", NULL, "HP Amp L"},2041	{"HP Amp", NULL, "HP Amp R"},2042	{"HP Amp", NULL, "Capless"},2043	{"HP Amp", NULL, "Charge Pump"},2044	{"HP Amp", NULL, "CLKDET SYS"},2045	{"HP Amp", NULL, "Vref1"},2046 2047	{"HPO Signal Demux", NULL, "HP Amp"},2048 2049	{"HPO Legacy", "Legacy", "HPO Signal Demux"},2050	{"HPO OneBit", "OneBit", "HPO Signal Demux"},2051 2052	{"HPOL Playback", "Switch", "HPO Legacy"},2053	{"HPOR Playback", "Switch", "HPO Legacy"},2054 2055	{"HPOL", NULL, "HPOL Playback"},2056	{"HPOR", NULL, "HPOR Playback"},2057	{"HPOL", NULL, "HPO OneBit"},2058	{"HPOR", NULL, "HPO OneBit"},2059};2060 2061static int rt5682_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,2062		unsigned int rx_mask, int slots, int slot_width)2063{2064	struct snd_soc_component *component = dai->component;2065	unsigned int cl, val = 0;2066 2067	if (tx_mask || rx_mask)2068		snd_soc_component_update_bits(component, RT5682_TDM_ADDA_CTRL_2,2069			RT5682_TDM_EN, RT5682_TDM_EN);2070	else2071		snd_soc_component_update_bits(component, RT5682_TDM_ADDA_CTRL_2,2072			RT5682_TDM_EN, 0);2073 2074	switch (slots) {2075	case 4:2076		val |= RT5682_TDM_TX_CH_4;2077		val |= RT5682_TDM_RX_CH_4;2078		break;2079	case 6:2080		val |= RT5682_TDM_TX_CH_6;2081		val |= RT5682_TDM_RX_CH_6;2082		break;2083	case 8:2084		val |= RT5682_TDM_TX_CH_8;2085		val |= RT5682_TDM_RX_CH_8;2086		break;2087	case 2:2088		break;2089	default:2090		return -EINVAL;2091	}2092 2093	snd_soc_component_update_bits(component, RT5682_TDM_CTRL,2094		RT5682_TDM_TX_CH_MASK | RT5682_TDM_RX_CH_MASK, val);2095 2096	switch (slot_width) {2097	case 8:2098		if (tx_mask || rx_mask)2099			return -EINVAL;2100		cl = RT5682_I2S1_TX_CHL_8 | RT5682_I2S1_RX_CHL_8;2101		break;2102	case 16:2103		val = RT5682_TDM_CL_16;2104		cl = RT5682_I2S1_TX_CHL_16 | RT5682_I2S1_RX_CHL_16;2105		break;2106	case 20:2107		val = RT5682_TDM_CL_20;2108		cl = RT5682_I2S1_TX_CHL_20 | RT5682_I2S1_RX_CHL_20;2109		break;2110	case 24:2111		val = RT5682_TDM_CL_24;2112		cl = RT5682_I2S1_TX_CHL_24 | RT5682_I2S1_RX_CHL_24;2113		break;2114	case 32:2115		val = RT5682_TDM_CL_32;2116		cl = RT5682_I2S1_TX_CHL_32 | RT5682_I2S1_RX_CHL_32;2117		break;2118	default:2119		return -EINVAL;2120	}2121 2122	snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL,2123		RT5682_TDM_CL_MASK, val);2124	snd_soc_component_update_bits(component, RT5682_I2S1_SDP,2125		RT5682_I2S1_TX_CHL_MASK | RT5682_I2S1_RX_CHL_MASK, cl);2126 2127	return 0;2128}2129 2130static int rt5682_hw_params(struct snd_pcm_substream *substream,2131		struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)2132{2133	struct snd_soc_component *component = dai->component;2134	struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);2135	unsigned int len_1 = 0, len_2 = 0;2136	int pre_div, frame_size;2137 2138	rt5682->lrck[dai->id] = params_rate(params);2139	pre_div = rl6231_get_clk_info(rt5682->sysclk, rt5682->lrck[dai->id]);2140 2141	frame_size = snd_soc_params_to_frame_size(params);2142	if (frame_size < 0) {2143		dev_err(component->dev, "Unsupported frame size: %d\n",2144			frame_size);2145		return -EINVAL;2146	}2147 2148	dev_dbg(dai->dev, "lrck is %dHz and pre_div is %d for iis %d\n",2149		rt5682->lrck[dai->id], pre_div, dai->id);2150 2151	switch (params_width(params)) {2152	case 16:2153		break;2154	case 20:2155		len_1 |= RT5682_I2S1_DL_20;2156		len_2 |= RT5682_I2S2_DL_20;2157		break;2158	case 24:2159		len_1 |= RT5682_I2S1_DL_24;2160		len_2 |= RT5682_I2S2_DL_24;2161		break;2162	case 32:2163		len_1 |= RT5682_I2S1_DL_32;2164		len_2 |= RT5682_I2S2_DL_24;2165		break;2166	case 8:2167		len_1 |= RT5682_I2S2_DL_8;2168		len_2 |= RT5682_I2S2_DL_8;2169		break;2170	default:2171		return -EINVAL;2172	}2173 2174	switch (dai->id) {2175	case RT5682_AIF1:2176		snd_soc_component_update_bits(component, RT5682_I2S1_SDP,2177			RT5682_I2S1_DL_MASK, len_1);2178		if (rt5682->master[RT5682_AIF1]) {2179			snd_soc_component_update_bits(component,2180				RT5682_ADDA_CLK_1, RT5682_I2S_M_DIV_MASK |2181				RT5682_I2S_CLK_SRC_MASK,2182				pre_div << RT5682_I2S_M_DIV_SFT |2183				(rt5682->sysclk_src) << RT5682_I2S_CLK_SRC_SFT);2184		}2185		if (params_channels(params) == 1) /* mono mode */2186			snd_soc_component_update_bits(component,2187				RT5682_I2S1_SDP, RT5682_I2S1_MONO_MASK,2188				RT5682_I2S1_MONO_EN);2189		else2190			snd_soc_component_update_bits(component,2191				RT5682_I2S1_SDP, RT5682_I2S1_MONO_MASK,2192				RT5682_I2S1_MONO_DIS);2193		break;2194	case RT5682_AIF2:2195		snd_soc_component_update_bits(component, RT5682_I2S2_SDP,2196			RT5682_I2S2_DL_MASK, len_2);2197		if (rt5682->master[RT5682_AIF2]) {2198			snd_soc_component_update_bits(component,2199				RT5682_I2S_M_CLK_CTRL_1, RT5682_I2S2_M_PD_MASK,2200				pre_div << RT5682_I2S2_M_PD_SFT);2201		}2202		if (params_channels(params) == 1) /* mono mode */2203			snd_soc_component_update_bits(component,2204				RT5682_I2S2_SDP, RT5682_I2S2_MONO_MASK,2205				RT5682_I2S2_MONO_EN);2206		else2207			snd_soc_component_update_bits(component,2208				RT5682_I2S2_SDP, RT5682_I2S2_MONO_MASK,2209				RT5682_I2S2_MONO_DIS);2210		break;2211	default:2212		dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);2213		return -EINVAL;2214	}2215 2216	return 0;2217}2218 2219static int rt5682_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)2220{2221	struct snd_soc_component *component = dai->component;2222	struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);2223	unsigned int reg_val = 0, tdm_ctrl = 0;2224 2225	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {2226	case SND_SOC_DAIFMT_CBM_CFM:2227		rt5682->master[dai->id] = 1;2228		break;2229	case SND_SOC_DAIFMT_CBS_CFS:2230		rt5682->master[dai->id] = 0;2231		break;2232	default:2233		return -EINVAL;2234	}2235 2236	switch (fmt & SND_SOC_DAIFMT_INV_MASK) {2237	case SND_SOC_DAIFMT_NB_NF:2238		break;2239	case SND_SOC_DAIFMT_IB_NF:2240		reg_val |= RT5682_I2S_BP_INV;2241		tdm_ctrl |= RT5682_TDM_S_BP_INV;2242		break;2243	case SND_SOC_DAIFMT_NB_IF:2244		if (dai->id == RT5682_AIF1)2245			tdm_ctrl |= RT5682_TDM_S_LP_INV | RT5682_TDM_M_BP_INV;2246		else2247			return -EINVAL;2248		break;2249	case SND_SOC_DAIFMT_IB_IF:2250		if (dai->id == RT5682_AIF1)2251			tdm_ctrl |= RT5682_TDM_S_BP_INV | RT5682_TDM_S_LP_INV |2252				    RT5682_TDM_M_BP_INV | RT5682_TDM_M_LP_INV;2253		else2254			return -EINVAL;2255		break;2256	default:2257		return -EINVAL;2258	}2259 2260	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {2261	case SND_SOC_DAIFMT_I2S:2262		break;2263	case SND_SOC_DAIFMT_LEFT_J:2264		reg_val |= RT5682_I2S_DF_LEFT;2265		tdm_ctrl |= RT5682_TDM_DF_LEFT;2266		break;2267	case SND_SOC_DAIFMT_DSP_A:2268		reg_val |= RT5682_I2S_DF_PCM_A;2269		tdm_ctrl |= RT5682_TDM_DF_PCM_A;2270		break;2271	case SND_SOC_DAIFMT_DSP_B:2272		reg_val |= RT5682_I2S_DF_PCM_B;2273		tdm_ctrl |= RT5682_TDM_DF_PCM_B;2274		break;2275	default:2276		return -EINVAL;2277	}2278 2279	switch (dai->id) {2280	case RT5682_AIF1:2281		snd_soc_component_update_bits(component, RT5682_I2S1_SDP,2282			RT5682_I2S_DF_MASK, reg_val);2283		snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL,2284			RT5682_TDM_MS_MASK | RT5682_TDM_S_BP_MASK |2285			RT5682_TDM_DF_MASK | RT5682_TDM_M_BP_MASK |2286			RT5682_TDM_M_LP_MASK | RT5682_TDM_S_LP_MASK,2287			tdm_ctrl | rt5682->master[dai->id]);2288		break;2289	case RT5682_AIF2:2290		if (rt5682->master[dai->id] == 0)2291			reg_val |= RT5682_I2S2_MS_S;2292		snd_soc_component_update_bits(component, RT5682_I2S2_SDP,2293			RT5682_I2S2_MS_MASK | RT5682_I2S_BP_MASK |2294			RT5682_I2S_DF_MASK, reg_val);2295		break;2296	default:2297		dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);2298		return -EINVAL;2299	}2300	return 0;2301}2302 2303static int rt5682_set_component_sysclk(struct snd_soc_component *component,2304		int clk_id, int source, unsigned int freq, int dir)2305{2306	struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);2307	unsigned int reg_val = 0, src = 0;2308 2309	if (freq == rt5682->sysclk && clk_id == rt5682->sysclk_src)2310		return 0;2311 2312	switch (clk_id) {2313	case RT5682_SCLK_S_MCLK:2314		reg_val |= RT5682_SCLK_SRC_MCLK;2315		src = RT5682_CLK_SRC_MCLK;2316		break;2317	case RT5682_SCLK_S_PLL1:2318		reg_val |= RT5682_SCLK_SRC_PLL1;2319		src = RT5682_CLK_SRC_PLL1;2320		break;2321	case RT5682_SCLK_S_PLL2:2322		reg_val |= RT5682_SCLK_SRC_PLL2;2323		src = RT5682_CLK_SRC_PLL2;2324		break;2325	case RT5682_SCLK_S_RCCLK:2326		reg_val |= RT5682_SCLK_SRC_RCCLK;2327		src = RT5682_CLK_SRC_RCCLK;2328		break;2329	default:2330		dev_err(component->dev, "Invalid clock id (%d)\n", clk_id);2331		return -EINVAL;2332	}2333	snd_soc_component_update_bits(component, RT5682_GLB_CLK,2334		RT5682_SCLK_SRC_MASK, reg_val);2335 2336	if (rt5682->master[RT5682_AIF2]) {2337		snd_soc_component_update_bits(component,2338			RT5682_I2S_M_CLK_CTRL_1, RT5682_I2S2_SRC_MASK,2339			src << RT5682_I2S2_SRC_SFT);2340	}2341 2342	rt5682->sysclk = freq;2343	rt5682->sysclk_src = clk_id;2344 2345	dev_dbg(component->dev, "Sysclk is %dHz and clock id is %d\n",2346		freq, clk_id);2347 2348	return 0;2349}2350 2351static int rt5682_set_component_pll(struct snd_soc_component *component,2352		int pll_id, int source, unsigned int freq_in,2353		unsigned int freq_out)2354{2355	struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);2356	struct rl6231_pll_code pll_code, pll2f_code, pll2b_code;2357	unsigned int pll2_fout1, pll2_ps_val;2358	int ret;2359 2360	if (source == rt5682->pll_src[pll_id] &&2361	    freq_in == rt5682->pll_in[pll_id] &&2362	    freq_out == rt5682->pll_out[pll_id])2363		return 0;2364 2365	if (!freq_in || !freq_out) {2366		dev_dbg(component->dev, "PLL disabled\n");2367 2368		rt5682->pll_in[pll_id] = 0;2369		rt5682->pll_out[pll_id] = 0;2370		snd_soc_component_update_bits(component, RT5682_GLB_CLK,2371			RT5682_SCLK_SRC_MASK, RT5682_SCLK_SRC_MCLK);2372		return 0;2373	}2374 2375	if (pll_id == RT5682_PLL2) {2376		switch (source) {2377		case RT5682_PLL2_S_MCLK:2378			snd_soc_component_update_bits(component,2379				RT5682_GLB_CLK, RT5682_PLL2_SRC_MASK,2380				RT5682_PLL2_SRC_MCLK);2381			break;2382		default:2383			dev_err(component->dev, "Unknown PLL2 Source %d\n",2384				source);2385			return -EINVAL;2386		}2387 2388		/**2389		 * PLL2 concatenates 2 PLL units.2390		 * We suggest the Fout of the front PLL is 3.84MHz.2391		 */2392		pll2_fout1 = 3840000;2393		ret = rl6231_pll_calc(freq_in, pll2_fout1, &pll2f_code);2394		if (ret < 0) {2395			dev_err(component->dev, "Unsupported input clock %d\n",2396				freq_in);2397			return ret;2398		}2399		dev_dbg(component->dev, "PLL2F: fin=%d fout=%d bypass=%d m=%d n=%d k=%d\n",2400			freq_in, pll2_fout1,2401			pll2f_code.m_bp,2402			(pll2f_code.m_bp ? 0 : pll2f_code.m_code),2403			pll2f_code.n_code, pll2f_code.k_code);2404 2405		ret = rl6231_pll_calc(pll2_fout1, freq_out, &pll2b_code);2406		if (ret < 0) {2407			dev_err(component->dev, "Unsupported input clock %d\n",2408				pll2_fout1);2409			return ret;2410		}2411		dev_dbg(component->dev, "PLL2B: fin=%d fout=%d bypass=%d m=%d n=%d k=%d\n",2412			pll2_fout1, freq_out,2413			pll2b_code.m_bp,2414			(pll2b_code.m_bp ? 0 : pll2b_code.m_code),2415			pll2b_code.n_code, pll2b_code.k_code);2416 2417		snd_soc_component_write(component, RT5682_PLL2_CTRL_1,2418			pll2f_code.k_code << RT5682_PLL2F_K_SFT |2419			pll2b_code.k_code << RT5682_PLL2B_K_SFT |2420			pll2b_code.m_code);2421		snd_soc_component_write(component, RT5682_PLL2_CTRL_2,2422			pll2f_code.m_code << RT5682_PLL2F_M_SFT |2423			pll2b_code.n_code);2424		snd_soc_component_write(component, RT5682_PLL2_CTRL_3,2425			pll2f_code.n_code << RT5682_PLL2F_N_SFT);2426 2427		if (freq_out == 22579200)2428			pll2_ps_val = 1 << RT5682_PLL2B_SEL_PS_SFT;2429		else2430			pll2_ps_val = 1 << RT5682_PLL2B_PS_BYP_SFT;2431		snd_soc_component_update_bits(component, RT5682_PLL2_CTRL_4,2432			RT5682_PLL2B_SEL_PS_MASK | RT5682_PLL2B_PS_BYP_MASK |2433			RT5682_PLL2B_M_BP_MASK | RT5682_PLL2F_M_BP_MASK | 0xf,2434			pll2_ps_val |2435			(pll2b_code.m_bp ? 1 : 0) << RT5682_PLL2B_M_BP_SFT |2436			(pll2f_code.m_bp ? 1 : 0) << RT5682_PLL2F_M_BP_SFT |2437			0xf);2438	} else {2439		switch (source) {2440		case RT5682_PLL1_S_MCLK:2441			snd_soc_component_update_bits(component,2442				RT5682_GLB_CLK, RT5682_PLL1_SRC_MASK,2443				RT5682_PLL1_SRC_MCLK);2444			break;2445		case RT5682_PLL1_S_BCLK1:2446			snd_soc_component_update_bits(component,2447				RT5682_GLB_CLK, RT5682_PLL1_SRC_MASK,2448				RT5682_PLL1_SRC_BCLK1);2449			break;2450		default:2451			dev_err(component->dev, "Unknown PLL1 Source %d\n",2452				source);2453			return -EINVAL;2454		}2455 2456		ret = rl6231_pll_calc(freq_in, freq_out, &pll_code);2457		if (ret < 0) {2458			dev_err(component->dev, "Unsupported input clock %d\n",2459				freq_in);2460			return ret;2461		}2462 2463		dev_dbg(component->dev, "bypass=%d m=%d n=%d k=%d\n",2464			pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),2465			pll_code.n_code, pll_code.k_code);2466 2467		snd_soc_component_write(component, RT5682_PLL_CTRL_1,2468			(pll_code.n_code << RT5682_PLL_N_SFT) | pll_code.k_code);2469		snd_soc_component_write(component, RT5682_PLL_CTRL_2,2470			((pll_code.m_bp ? 0 : pll_code.m_code) << RT5682_PLL_M_SFT) |2471			((pll_code.m_bp << RT5682_PLL_M_BP_SFT) | RT5682_PLL_RST));2472	}2473 2474	rt5682->pll_in[pll_id] = freq_in;2475	rt5682->pll_out[pll_id] = freq_out;2476	rt5682->pll_src[pll_id] = source;2477 2478	return 0;2479}2480 2481static int rt5682_set_bclk1_ratio(struct snd_soc_dai *dai, unsigned int ratio)2482{2483	struct snd_soc_component *component = dai->component;2484	struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);2485 2486	rt5682->bclk[dai->id] = ratio;2487 2488	switch (ratio) {2489	case 256:2490		snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL,2491			RT5682_TDM_BCLK_MS1_MASK, RT5682_TDM_BCLK_MS1_256);2492		break;2493	case 128:2494		snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL,2495			RT5682_TDM_BCLK_MS1_MASK, RT5682_TDM_BCLK_MS1_128);2496		break;2497	case 64:2498		snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL,2499			RT5682_TDM_BCLK_MS1_MASK, RT5682_TDM_BCLK_MS1_64);2500		break;2501	case 32:2502		snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL,2503			RT5682_TDM_BCLK_MS1_MASK, RT5682_TDM_BCLK_MS1_32);2504		break;2505	default:2506		dev_err(dai->dev, "Invalid bclk1 ratio %d\n", ratio);2507		return -EINVAL;2508	}2509 2510	return 0;2511}2512 2513static int rt5682_set_bclk2_ratio(struct snd_soc_dai *dai, unsigned int ratio)2514{2515	struct snd_soc_component *component = dai->component;2516	struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);2517 2518	rt5682->bclk[dai->id] = ratio;2519 2520	switch (ratio) {2521	case 64:2522		snd_soc_component_update_bits(component, RT5682_ADDA_CLK_2,2523			RT5682_I2S2_BCLK_MS2_MASK,2524			RT5682_I2S2_BCLK_MS2_64);2525		break;2526	case 32:2527		snd_soc_component_update_bits(component, RT5682_ADDA_CLK_2,2528			RT5682_I2S2_BCLK_MS2_MASK,2529			RT5682_I2S2_BCLK_MS2_32);2530		break;2531	default:2532		dev_err(dai->dev, "Invalid bclk2 ratio %d\n", ratio);2533		return -EINVAL;2534	}2535 2536	return 0;2537}2538 2539static int rt5682_set_bias_level(struct snd_soc_component *component,2540		enum snd_soc_bias_level level)2541{2542	struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);2543 2544	switch (level) {2545	case SND_SOC_BIAS_PREPARE:2546		regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_1,2547			RT5682_PWR_BG, RT5682_PWR_BG);2548		regmap_update_bits(rt5682->regmap, RT5682_PWR_DIG_1,2549			RT5682_DIG_GATE_CTRL | RT5682_PWR_LDO,2550			RT5682_DIG_GATE_CTRL | RT5682_PWR_LDO);2551		break;2552 2553	case SND_SOC_BIAS_STANDBY:2554		regmap_update_bits(rt5682->regmap, RT5682_PWR_DIG_1,2555			RT5682_DIG_GATE_CTRL, RT5682_DIG_GATE_CTRL);2556		break;2557	case SND_SOC_BIAS_OFF:2558		regmap_update_bits(rt5682->regmap, RT5682_PWR_DIG_1,2559			RT5682_DIG_GATE_CTRL | RT5682_PWR_LDO, 0);2560		regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_1,2561			RT5682_PWR_BG, 0);2562		break;2563	case SND_SOC_BIAS_ON:2564		break;2565	}2566 2567	return 0;2568}2569 2570#ifdef CONFIG_COMMON_CLK2571#define CLK_PLL2_FIN 480000002572#define CLK_48 480002573#define CLK_44 441002574 2575static bool rt5682_clk_check(struct rt5682_priv *rt5682)2576{2577	if (!rt5682->master[RT5682_AIF1]) {2578		dev_dbg(rt5682->i2c_dev, "sysclk/dai not set correctly\n");2579		return false;2580	}2581	return true;2582}2583 2584static int rt5682_wclk_prepare(struct clk_hw *hw)2585{2586	struct rt5682_priv *rt5682 =2587		container_of(hw, struct rt5682_priv,2588			     dai_clks_hw[RT5682_DAI_WCLK_IDX]);2589	struct snd_soc_component *component;2590	struct snd_soc_dapm_context *dapm;2591 2592	if (!rt5682_clk_check(rt5682))2593		return -EINVAL;2594 2595	component = rt5682->component;2596	dapm = snd_soc_component_get_dapm(component);2597 2598	snd_soc_dapm_mutex_lock(dapm);2599 2600	snd_soc_dapm_force_enable_pin_unlocked(dapm, "MICBIAS");2601	snd_soc_component_update_bits(component, RT5682_PWR_ANLG_1,2602				RT5682_PWR_MB, RT5682_PWR_MB);2603 2604	snd_soc_dapm_force_enable_pin_unlocked(dapm, "Vref2");2605	snd_soc_component_update_bits(component, RT5682_PWR_ANLG_1,2606			RT5682_PWR_VREF2 | RT5682_PWR_FV2,2607			RT5682_PWR_VREF2);2608	usleep_range(55000, 60000);2609	snd_soc_component_update_bits(component, RT5682_PWR_ANLG_1,2610			RT5682_PWR_FV2, RT5682_PWR_FV2);2611 2612	snd_soc_dapm_force_enable_pin_unlocked(dapm, "I2S1");2613	snd_soc_dapm_force_enable_pin_unlocked(dapm, "PLL2F");2614	snd_soc_dapm_force_enable_pin_unlocked(dapm, "PLL2B");2615	snd_soc_dapm_sync_unlocked(dapm);2616 2617	snd_soc_dapm_mutex_unlock(dapm);2618 2619	return 0;2620}2621 2622static void rt5682_wclk_unprepare(struct clk_hw *hw)2623{2624	struct rt5682_priv *rt5682 =2625		container_of(hw, struct rt5682_priv,2626			     dai_clks_hw[RT5682_DAI_WCLK_IDX]);2627	struct snd_soc_component *component;2628	struct snd_soc_dapm_context *dapm;2629 2630	if (!rt5682_clk_check(rt5682))2631		return;2632 2633	component = rt5682->component;2634	dapm = snd_soc_component_get_dapm(component);2635 2636	snd_soc_dapm_mutex_lock(dapm);2637 2638	snd_soc_dapm_disable_pin_unlocked(dapm, "MICBIAS");2639	snd_soc_dapm_disable_pin_unlocked(dapm, "Vref2");2640	if (!rt5682->jack_type)2641		snd_soc_component_update_bits(component, RT5682_PWR_ANLG_1,2642				RT5682_PWR_VREF2 | RT5682_PWR_FV2 |2643				RT5682_PWR_MB, 0);2644 2645	snd_soc_dapm_disable_pin_unlocked(dapm, "I2S1");2646	snd_soc_dapm_disable_pin_unlocked(dapm, "PLL2F");2647	snd_soc_dapm_disable_pin_unlocked(dapm, "PLL2B");2648	snd_soc_dapm_sync_unlocked(dapm);2649 2650	snd_soc_dapm_mutex_unlock(dapm);2651}2652 2653static unsigned long rt5682_wclk_recalc_rate(struct clk_hw *hw,2654					     unsigned long parent_rate)2655{2656	struct rt5682_priv *rt5682 =2657		container_of(hw, struct rt5682_priv,2658			     dai_clks_hw[RT5682_DAI_WCLK_IDX]);2659	const char * const clk_name = clk_hw_get_name(hw);2660 2661	if (!rt5682_clk_check(rt5682))2662		return 0;2663	/*2664	 * Only accept to set wclk rate to 44.1k or 48kHz.2665	 */2666	if (rt5682->lrck[RT5682_AIF1] != CLK_48 &&2667	    rt5682->lrck[RT5682_AIF1] != CLK_44) {2668		dev_warn(rt5682->i2c_dev, "%s: clk %s only support %d or %d Hz output\n",2669			__func__, clk_name, CLK_44, CLK_48);2670		return 0;2671	}2672 2673	return rt5682->lrck[RT5682_AIF1];2674}2675 2676static long rt5682_wclk_round_rate(struct clk_hw *hw, unsigned long rate,2677				   unsigned long *parent_rate)2678{2679	struct rt5682_priv *rt5682 =2680		container_of(hw, struct rt5682_priv,2681			     dai_clks_hw[RT5682_DAI_WCLK_IDX]);2682	const char * const clk_name = clk_hw_get_name(hw);2683 2684	if (!rt5682_clk_check(rt5682))2685		return -EINVAL;2686	/*2687	 * Only accept to set wclk rate to 44.1k or 48kHz.2688	 * It will force to 48kHz if not both.2689	 */2690	if (rate != CLK_48 && rate != CLK_44) {2691		dev_warn(rt5682->i2c_dev, "%s: clk %s only support %d or %d Hz output\n",2692			__func__, clk_name, CLK_44, CLK_48);2693		rate = CLK_48;2694	}2695 2696	return rate;2697}2698 2699static int rt5682_wclk_set_rate(struct clk_hw *hw, unsigned long rate,2700				unsigned long parent_rate)2701{2702	struct rt5682_priv *rt5682 =2703		container_of(hw, struct rt5682_priv,2704			     dai_clks_hw[RT5682_DAI_WCLK_IDX]);2705	struct snd_soc_component *component;2706	struct clk_hw *parent_hw;2707	const char * const clk_name = clk_hw_get_name(hw);2708	int pre_div;2709	unsigned int clk_pll2_out;2710 2711	if (!rt5682_clk_check(rt5682))2712		return -EINVAL;2713 2714	component = rt5682->component;2715 2716	/*2717	 * Whether the wclk's parent clk (mclk) exists or not, please ensure2718	 * it is fixed or set to 48MHz before setting wclk rate. It's a2719	 * temporary limitation. Only accept 48MHz clk as the clk provider.2720	 *2721	 * It will set the codec anyway by assuming mclk is 48MHz.2722	 */2723	parent_hw = clk_hw_get_parent(hw);2724	if (!parent_hw)2725		dev_warn(rt5682->i2c_dev,2726			"Parent mclk of wclk not acquired in driver. Please ensure mclk was provided as %d Hz.\n",2727			CLK_PLL2_FIN);2728 2729	if (parent_rate != CLK_PLL2_FIN)2730		dev_warn(rt5682->i2c_dev, "clk %s only support %d Hz input\n",2731			clk_name, CLK_PLL2_FIN);2732 2733	/*2734	 * To achieve the rate conversion from 48MHz to 44.1k or 48kHz,2735	 * PLL2 is needed.2736	 */2737	clk_pll2_out = rate * 512;2738	rt5682_set_component_pll(component, RT5682_PLL2, RT5682_PLL2_S_MCLK,2739		CLK_PLL2_FIN, clk_pll2_out);2740 2741	rt5682_set_component_sysclk(component, RT5682_SCLK_S_PLL2, 0,2742		clk_pll2_out, SND_SOC_CLOCK_IN);2743 2744	rt5682->lrck[RT5682_AIF1] = rate;2745 2746	pre_div = rl6231_get_clk_info(rt5682->sysclk, rate);2747 2748	snd_soc_component_update_bits(component, RT5682_ADDA_CLK_1,2749		RT5682_I2S_M_DIV_MASK | RT5682_I2S_CLK_SRC_MASK,2750		pre_div << RT5682_I2S_M_DIV_SFT |2751		(rt5682->sysclk_src) << RT5682_I2S_CLK_SRC_SFT);2752 2753	return 0;2754}2755 2756static unsigned long rt5682_bclk_recalc_rate(struct clk_hw *hw,2757					     unsigned long parent_rate)2758{2759	struct rt5682_priv *rt5682 =2760		container_of(hw, struct rt5682_priv,2761			     dai_clks_hw[RT5682_DAI_BCLK_IDX]);2762	unsigned int bclks_per_wclk;2763 2764	regmap_read(rt5682->regmap, RT5682_TDM_TCON_CTRL, &bclks_per_wclk);2765 2766	switch (bclks_per_wclk & RT5682_TDM_BCLK_MS1_MASK) {2767	case RT5682_TDM_BCLK_MS1_256:2768		return parent_rate * 256;2769	case RT5682_TDM_BCLK_MS1_128:2770		return parent_rate * 128;2771	case RT5682_TDM_BCLK_MS1_64:2772		return parent_rate * 64;2773	case RT5682_TDM_BCLK_MS1_32:2774		return parent_rate * 32;2775	default:2776		return 0;2777	}2778}2779 2780static unsigned long rt5682_bclk_get_factor(unsigned long rate,2781					    unsigned long parent_rate)2782{2783	unsigned long factor;2784 2785	factor = rate / parent_rate;2786	if (factor < 64)2787		return 32;2788	else if (factor < 128)2789		return 64;2790	else if (factor < 256)2791		return 128;2792	else2793		return 256;2794}2795 2796static long rt5682_bclk_round_rate(struct clk_hw *hw, unsigned long rate,2797				   unsigned long *parent_rate)2798{2799	struct rt5682_priv *rt5682 =2800		container_of(hw, struct rt5682_priv,2801			     dai_clks_hw[RT5682_DAI_BCLK_IDX]);2802	unsigned long factor;2803 2804	if (!*parent_rate || !rt5682_clk_check(rt5682))2805		return -EINVAL;2806 2807	/*2808	 * BCLK rates are set as a multiplier of WCLK in HW.2809	 * We don't allow changing the parent WCLK. We just do2810	 * some rounding down based on the parent WCLK rate2811	 * and find the appropriate multiplier of BCLK to2812	 * get the rounded down BCLK value.2813	 */2814	factor = rt5682_bclk_get_factor(rate, *parent_rate);2815 2816	return *parent_rate * factor;2817}2818 2819static int rt5682_bclk_set_rate(struct clk_hw *hw, unsigned long rate,2820				unsigned long parent_rate)2821{2822	struct rt5682_priv *rt5682 =2823		container_of(hw, struct rt5682_priv,2824			     dai_clks_hw[RT5682_DAI_BCLK_IDX]);2825	struct snd_soc_component *component;2826	struct snd_soc_dai *dai;2827	unsigned long factor;2828 2829	if (!rt5682_clk_check(rt5682))2830		return -EINVAL;2831 2832	component = rt5682->component;2833 2834	factor = rt5682_bclk_get_factor(rate, parent_rate);2835 2836	for_each_component_dais(component, dai)2837		if (dai->id == RT5682_AIF1)2838			return rt5682_set_bclk1_ratio(dai, factor);2839 2840	dev_err(rt5682->i2c_dev, "dai %d not found in component\n",2841		RT5682_AIF1);2842	return -ENODEV;2843}2844 2845static const struct clk_ops rt5682_dai_clk_ops[RT5682_DAI_NUM_CLKS] = {2846	[RT5682_DAI_WCLK_IDX] = {2847		.prepare = rt5682_wclk_prepare,2848		.unprepare = rt5682_wclk_unprepare,2849		.recalc_rate = rt5682_wclk_recalc_rate,2850		.round_rate = rt5682_wclk_round_rate,2851		.set_rate = rt5682_wclk_set_rate,2852	},2853	[RT5682_DAI_BCLK_IDX] = {2854		.recalc_rate = rt5682_bclk_recalc_rate,2855		.round_rate = rt5682_bclk_round_rate,2856		.set_rate = rt5682_bclk_set_rate,2857	},2858};2859 2860int rt5682_register_dai_clks(struct rt5682_priv *rt5682)2861{2862	struct device *dev = rt5682->i2c_dev;2863	struct rt5682_platform_data *pdata = &rt5682->pdata;2864	struct clk_hw *dai_clk_hw;2865	int i, ret;2866 2867	for (i = 0; i < RT5682_DAI_NUM_CLKS; ++i) {2868		struct clk_init_data init = { };2869		const struct clk_hw *parent;2870 2871		dai_clk_hw = &rt5682->dai_clks_hw[i];2872 2873		switch (i) {2874		case RT5682_DAI_WCLK_IDX:2875			/* Make MCLK the parent of WCLK */2876			if (rt5682->mclk) {2877				parent = __clk_get_hw(rt5682->mclk);2878				init.parent_hws = &parent;2879				init.num_parents = 1;2880			}2881			break;2882		case RT5682_DAI_BCLK_IDX:2883			/* Make WCLK the parent of BCLK */2884			parent = &rt5682->dai_clks_hw[RT5682_DAI_WCLK_IDX];2885			init.parent_hws = &parent;2886			init.num_parents = 1;2887			break;2888		default:2889			dev_err(dev, "Invalid clock index\n");2890			return -EINVAL;2891		}2892 2893		init.name = pdata->dai_clk_names[i];2894		init.ops = &rt5682_dai_clk_ops[i];2895		init.flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_GATE;2896		dai_clk_hw->init = &init;2897 2898		ret = devm_clk_hw_register(dev, dai_clk_hw);2899		if (ret) {2900			dev_warn(dev, "Failed to register %s: %d\n",2901				 init.name, ret);2902			return ret;2903		}2904 2905		if (dev->of_node) {2906			ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get,2907						    dai_clk_hw);2908			if (ret)2909				return ret;2910		} else {2911			ret = devm_clk_hw_register_clkdev(dev, dai_clk_hw,2912							  init.name,2913							  dev_name(dev));2914			if (ret)2915				return ret;2916		}2917	}2918 2919	return 0;2920}2921EXPORT_SYMBOL_GPL(rt5682_register_dai_clks);2922#endif /* CONFIG_COMMON_CLK */2923 2924static int rt5682_probe(struct snd_soc_component *component)2925{2926	struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);2927	struct sdw_slave *slave;2928	unsigned long time;2929	struct snd_soc_dapm_context *dapm = &component->dapm;2930 2931	rt5682->component = component;2932 2933	if (rt5682->is_sdw) {2934		slave = rt5682->slave;2935		time = wait_for_completion_timeout(2936			&slave->initialization_complete,2937			msecs_to_jiffies(RT5682_PROBE_TIMEOUT));2938		if (!time) {2939			dev_err(&slave->dev, "Initialization not complete, timed out\n");2940			return -ETIMEDOUT;2941		}2942	}2943 2944	snd_soc_dapm_disable_pin(dapm, "MICBIAS");2945	snd_soc_dapm_disable_pin(dapm, "Vref2");2946	snd_soc_dapm_sync(dapm);2947	return 0;2948}2949 2950static void rt5682_remove(struct snd_soc_component *component)2951{2952	struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);2953 2954	rt5682_reset(rt5682);2955}2956 2957#ifdef CONFIG_PM2958static int rt5682_suspend(struct snd_soc_component *component)2959{2960	struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);2961	unsigned int val;2962 2963	if (rt5682->is_sdw)2964		return 0;2965 2966	if (rt5682->irq)2967		disable_irq(rt5682->irq);2968 2969	cancel_delayed_work_sync(&rt5682->jack_detect_work);2970	cancel_delayed_work_sync(&rt5682->jd_check_work);2971	if (rt5682->hs_jack && (rt5682->jack_type & SND_JACK_HEADSET) == SND_JACK_HEADSET) {2972		val = snd_soc_component_read(component,2973				RT5682_CBJ_CTRL_2) & RT5682_JACK_TYPE_MASK;2974 2975		switch (val) {2976		case 0x1:2977			snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_1,2978				RT5682_SAR_SEL_MB1_MASK | RT5682_SAR_SEL_MB2_MASK,2979				RT5682_SAR_SEL_MB1_NOSEL | RT5682_SAR_SEL_MB2_SEL);2980			break;2981		case 0x2:2982			snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_1,2983				RT5682_SAR_SEL_MB1_MASK | RT5682_SAR_SEL_MB2_MASK,2984				RT5682_SAR_SEL_MB1_SEL | RT5682_SAR_SEL_MB2_NOSEL);2985			break;2986		default:2987			break;2988		}2989 2990		/* enter SAR ADC power saving mode */2991		snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_1,2992			RT5682_SAR_BUTT_DET_MASK | RT5682_SAR_BUTDET_MODE_MASK |2993			RT5682_SAR_SEL_MB1_MB2_MASK, 0);2994		usleep_range(5000, 6000);2995		snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_1,2996			RT5682_MB1_PATH_MASK | RT5682_MB2_PATH_MASK,2997			RT5682_CTRL_MB1_REG | RT5682_CTRL_MB2_REG);2998		usleep_range(10000, 12000);2999		snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_1,3000			RT5682_SAR_BUTT_DET_MASK | RT5682_SAR_BUTDET_MODE_MASK,3001			RT5682_SAR_BUTT_DET_EN | RT5682_SAR_BUTDET_POW_SAV);3002		snd_soc_component_update_bits(component, RT5682_HP_CHARGE_PUMP_1,3003			RT5682_OSW_L_MASK | RT5682_OSW_R_MASK, 0);3004	}3005 3006	regcache_cache_only(rt5682->regmap, true);3007	regcache_mark_dirty(rt5682->regmap);3008	return 0;3009}3010 3011static int rt5682_resume(struct snd_soc_component *component)3012{3013	struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);3014 3015	if (rt5682->is_sdw)3016		return 0;3017 3018	regcache_cache_only(rt5682->regmap, false);3019	regcache_sync(rt5682->regmap);3020 3021	if (rt5682->hs_jack && (rt5682->jack_type & SND_JACK_HEADSET) == SND_JACK_HEADSET) {3022		snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_1,3023			RT5682_SAR_BUTDET_MODE_MASK | RT5682_SAR_SEL_MB1_MB2_MASK,3024			RT5682_SAR_BUTDET_POW_NORM | RT5682_SAR_SEL_MB1_MB2_AUTO);3025		usleep_range(5000, 6000);3026		snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_1,3027			RT5682_MB1_PATH_MASK | RT5682_MB2_PATH_MASK,3028			RT5682_CTRL_MB1_FSM | RT5682_CTRL_MB2_FSM);3029		snd_soc_component_update_bits(component, RT5682_PWR_ANLG_3,3030			RT5682_PWR_CBJ, RT5682_PWR_CBJ);3031	}3032 3033	rt5682->jack_type = 0;3034	mod_delayed_work(system_power_efficient_wq,3035		&rt5682->jack_detect_work, msecs_to_jiffies(0));3036 3037	if (rt5682->irq)3038		enable_irq(rt5682->irq);3039 3040	return 0;3041}3042#else3043#define rt5682_suspend NULL3044#define rt5682_resume NULL3045#endif3046 3047const struct snd_soc_dai_ops rt5682_aif1_dai_ops = {3048	.hw_params = rt5682_hw_params,3049	.set_fmt = rt5682_set_dai_fmt,3050	.set_tdm_slot = rt5682_set_tdm_slot,3051	.set_bclk_ratio = rt5682_set_bclk1_ratio,3052};3053EXPORT_SYMBOL_GPL(rt5682_aif1_dai_ops);3054 3055const struct snd_soc_dai_ops rt5682_aif2_dai_ops = {3056	.hw_params = rt5682_hw_params,3057	.set_fmt = rt5682_set_dai_fmt,3058	.set_bclk_ratio = rt5682_set_bclk2_ratio,3059};3060EXPORT_SYMBOL_GPL(rt5682_aif2_dai_ops);3061 3062const struct snd_soc_component_driver rt5682_soc_component_dev = {3063	.probe = rt5682_probe,3064	.remove = rt5682_remove,3065	.suspend = rt5682_suspend,3066	.resume = rt5682_resume,3067	.set_bias_level = rt5682_set_bias_level,3068	.controls = rt5682_snd_controls,3069	.num_controls = ARRAY_SIZE(rt5682_snd_controls),3070	.dapm_widgets = rt5682_dapm_widgets,3071	.num_dapm_widgets = ARRAY_SIZE(rt5682_dapm_widgets),3072	.dapm_routes = rt5682_dapm_routes,3073	.num_dapm_routes = ARRAY_SIZE(rt5682_dapm_routes),3074	.set_sysclk = rt5682_set_component_sysclk,3075	.set_pll = rt5682_set_component_pll,3076	.set_jack = rt5682_set_jack_detect,3077	.use_pmdown_time	= 1,3078	.endianness		= 1,3079};3080EXPORT_SYMBOL_GPL(rt5682_soc_component_dev);3081 3082int rt5682_parse_dt(struct rt5682_priv *rt5682, struct device *dev)3083{3084 3085	device_property_read_u32(dev, "realtek,dmic1-data-pin",3086		&rt5682->pdata.dmic1_data_pin);3087	device_property_read_u32(dev, "realtek,dmic1-clk-pin",3088		&rt5682->pdata.dmic1_clk_pin);3089	device_property_read_u32(dev, "realtek,jd-src",3090		&rt5682->pdata.jd_src);3091	device_property_read_u32(dev, "realtek,btndet-delay",3092		&rt5682->pdata.btndet_delay);3093	device_property_read_u32(dev, "realtek,dmic-clk-rate-hz",3094		&rt5682->pdata.dmic_clk_rate);3095	device_property_read_u32(dev, "realtek,dmic-delay-ms",3096		&rt5682->pdata.dmic_delay);3097 3098	if (device_property_read_string_array(dev, "clock-output-names",3099					      rt5682->pdata.dai_clk_names,3100					      RT5682_DAI_NUM_CLKS) < 0)3101		dev_warn(dev, "Using default DAI clk names: %s, %s\n",3102			 rt5682->pdata.dai_clk_names[RT5682_DAI_WCLK_IDX],3103			 rt5682->pdata.dai_clk_names[RT5682_DAI_BCLK_IDX]);3104 3105	rt5682->pdata.dmic_clk_driving_high = device_property_read_bool(dev,3106		"realtek,dmic-clk-driving-high");3107 3108	return 0;3109}3110EXPORT_SYMBOL_GPL(rt5682_parse_dt);3111 3112int rt5682_get_ldo1(struct rt5682_priv *rt5682, struct device *dev)3113{3114	rt5682->ldo1_en = devm_gpiod_get_optional(dev,3115						  "realtek,ldo1-en",3116						  GPIOD_OUT_HIGH);3117	if (IS_ERR(rt5682->ldo1_en)) {3118		dev_err(dev, "Fail gpio request ldo1_en\n");3119		return PTR_ERR(rt5682->ldo1_en);3120	}3121 3122	return 0;3123}3124EXPORT_SYMBOL_GPL(rt5682_get_ldo1);3125 3126void rt5682_calibrate(struct rt5682_priv *rt5682)3127{3128	int value, count;3129 3130	mutex_lock(&rt5682->calibrate_mutex);3131 3132	rt5682_reset(rt5682);3133	regmap_write(rt5682->regmap, RT5682_I2C_CTRL, 0x000f);3134	regmap_write(rt5682->regmap, RT5682_PWR_ANLG_1, 0xa2af);3135	usleep_range(15000, 20000);3136	regmap_write(rt5682->regmap, RT5682_PWR_ANLG_1, 0xf2af);3137	regmap_write(rt5682->regmap, RT5682_MICBIAS_2, 0x0300);3138	regmap_write(rt5682->regmap, RT5682_GLB_CLK, 0x8000);3139	regmap_write(rt5682->regmap, RT5682_PWR_DIG_1, 0x0100);3140	regmap_write(rt5682->regmap, RT5682_HP_IMP_SENS_CTRL_19, 0x3800);3141	regmap_write(rt5682->regmap, RT5682_CHOP_DAC, 0x3000);3142	regmap_write(rt5682->regmap, RT5682_CALIB_ADC_CTRL, 0x7005);3143	regmap_write(rt5682->regmap, RT5682_STO1_ADC_MIXER, 0x686c);3144	regmap_write(rt5682->regmap, RT5682_CAL_REC, 0x0d0d);3145	regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_2, 0x0321);3146	regmap_write(rt5682->regmap, RT5682_HP_LOGIC_CTRL_2, 0x0004);3147	regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_1, 0x7c00);3148	regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_3, 0x06a1);3149	regmap_write(rt5682->regmap, RT5682_A_DAC1_MUX, 0x0311);3150	regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_1, 0x7c00);3151 3152	regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_1, 0xfc00);3153 3154	for (count = 0; count < 60; count++) {3155		regmap_read(rt5682->regmap, RT5682_HP_CALIB_STA_1, &value);3156		if (!(value & 0x8000))3157			break;3158 3159		usleep_range(10000, 10005);3160	}3161 3162	if (count >= 60)3163		dev_err(rt5682->component->dev, "HP Calibration Failure\n");3164 3165	/* restore settings */3166	regmap_write(rt5682->regmap, RT5682_PWR_ANLG_1, 0x002f);3167	regmap_write(rt5682->regmap, RT5682_MICBIAS_2, 0x0080);3168	regmap_write(rt5682->regmap, RT5682_GLB_CLK, 0x0000);3169	regmap_write(rt5682->regmap, RT5682_PWR_DIG_1, 0x0000);3170	regmap_write(rt5682->regmap, RT5682_CHOP_DAC, 0x2000);3171	regmap_write(rt5682->regmap, RT5682_CALIB_ADC_CTRL, 0x2005);3172	regmap_write(rt5682->regmap, RT5682_STO1_ADC_MIXER, 0xc0c4);3173	regmap_write(rt5682->regmap, RT5682_CAL_REC, 0x0c0c);3174 3175	mutex_unlock(&rt5682->calibrate_mutex);3176}3177EXPORT_SYMBOL_GPL(rt5682_calibrate);3178 3179MODULE_DESCRIPTION("ASoC RT5682 driver");3180MODULE_AUTHOR("Bard Liao <bardliao@realtek.com>");3181MODULE_LICENSE("GPL v2");3182