409 lines · c
1/* SPDX-License-Identifier: GPL-2.0 */2/*3 * sgtl5000.h - SGTL5000 audio codec interface4 *5 * Copyright 2010-2011 Freescale Semiconductor, Inc.6 */7 8#ifndef _SGTL5000_H9#define _SGTL5000_H10 11/*12 * Registers addresses13 */14#define SGTL5000_CHIP_ID 0x000015#define SGTL5000_CHIP_DIG_POWER 0x000216#define SGTL5000_CHIP_CLK_CTRL 0x000417#define SGTL5000_CHIP_I2S_CTRL 0x000618#define SGTL5000_CHIP_SSS_CTRL 0x000a19#define SGTL5000_CHIP_ADCDAC_CTRL 0x000e20#define SGTL5000_CHIP_DAC_VOL 0x001021#define SGTL5000_CHIP_PAD_STRENGTH 0x001422#define SGTL5000_CHIP_ANA_ADC_CTRL 0x002023#define SGTL5000_CHIP_ANA_HP_CTRL 0x002224#define SGTL5000_CHIP_ANA_CTRL 0x002425#define SGTL5000_CHIP_LINREG_CTRL 0x002626#define SGTL5000_CHIP_REF_CTRL 0x002827#define SGTL5000_CHIP_MIC_CTRL 0x002a28#define SGTL5000_CHIP_LINE_OUT_CTRL 0x002c29#define SGTL5000_CHIP_LINE_OUT_VOL 0x002e30#define SGTL5000_CHIP_ANA_POWER 0x003031#define SGTL5000_CHIP_PLL_CTRL 0x003232#define SGTL5000_CHIP_CLK_TOP_CTRL 0x003433#define SGTL5000_CHIP_ANA_STATUS 0x003634#define SGTL5000_CHIP_SHORT_CTRL 0x003c35#define SGTL5000_CHIP_ANA_TEST2 0x003a36#define SGTL5000_DAP_CTRL 0x010037#define SGTL5000_DAP_PEQ 0x010238#define SGTL5000_DAP_BASS_ENHANCE 0x010439#define SGTL5000_DAP_BASS_ENHANCE_CTRL 0x010640#define SGTL5000_DAP_AUDIO_EQ 0x010841#define SGTL5000_DAP_SURROUND 0x010a42#define SGTL5000_DAP_FLT_COEF_ACCESS 0x010c43#define SGTL5000_DAP_COEF_WR_B0_MSB 0x010e44#define SGTL5000_DAP_COEF_WR_B0_LSB 0x011045#define SGTL5000_DAP_EQ_BASS_BAND0 0x011646#define SGTL5000_DAP_EQ_BASS_BAND1 0x011847#define SGTL5000_DAP_EQ_BASS_BAND2 0x011a48#define SGTL5000_DAP_EQ_BASS_BAND3 0x011c49#define SGTL5000_DAP_EQ_BASS_BAND4 0x011e50#define SGTL5000_DAP_MAIN_CHAN 0x012051#define SGTL5000_DAP_MIX_CHAN 0x012252#define SGTL5000_DAP_AVC_CTRL 0x012453#define SGTL5000_DAP_AVC_THRESHOLD 0x012654#define SGTL5000_DAP_AVC_ATTACK 0x012855#define SGTL5000_DAP_AVC_DECAY 0x012a56#define SGTL5000_DAP_COEF_WR_B1_MSB 0x012c57#define SGTL5000_DAP_COEF_WR_B1_LSB 0x012e58#define SGTL5000_DAP_COEF_WR_B2_MSB 0x013059#define SGTL5000_DAP_COEF_WR_B2_LSB 0x013260#define SGTL5000_DAP_COEF_WR_A1_MSB 0x013461#define SGTL5000_DAP_COEF_WR_A1_LSB 0x013662#define SGTL5000_DAP_COEF_WR_A2_MSB 0x013863#define SGTL5000_DAP_COEF_WR_A2_LSB 0x013a64 65/*66 * Field Definitions.67 */68 69/*70 * SGTL5000_CHIP_ID71 */72#define SGTL5000_PARTID_MASK 0xff0073#define SGTL5000_PARTID_SHIFT 874#define SGTL5000_PARTID_WIDTH 875#define SGTL5000_PARTID_PART_ID 0xa076#define SGTL5000_REVID_MASK 0x00ff77#define SGTL5000_REVID_SHIFT 078#define SGTL5000_REVID_WIDTH 879 80/*81 * SGTL5000_CHIP_DIG_POWER82 */83#define SGTL5000_DIG_POWER_DEFAULT 0x000084#define SGTL5000_ADC_EN 0x004085#define SGTL5000_DAC_EN 0x002086#define SGTL5000_DAP_POWERUP 0x001087#define SGTL5000_I2S_OUT_POWERUP 0x000288#define SGTL5000_I2S_IN_POWERUP 0x000189 90/*91 * SGTL5000_CHIP_CLK_CTRL92 */93#define SGTL5000_CHIP_CLK_CTRL_DEFAULT 0x000894#define SGTL5000_RATE_MODE_MASK 0x003095#define SGTL5000_RATE_MODE_SHIFT 496#define SGTL5000_RATE_MODE_WIDTH 297#define SGTL5000_RATE_MODE_DIV_1 098#define SGTL5000_RATE_MODE_DIV_2 199#define SGTL5000_RATE_MODE_DIV_4 2100#define SGTL5000_RATE_MODE_DIV_6 3101#define SGTL5000_SYS_FS_MASK 0x000c102#define SGTL5000_SYS_FS_SHIFT 2103#define SGTL5000_SYS_FS_WIDTH 2104#define SGTL5000_SYS_FS_32k 0x0105#define SGTL5000_SYS_FS_44_1k 0x1106#define SGTL5000_SYS_FS_48k 0x2107#define SGTL5000_SYS_FS_96k 0x3108#define SGTL5000_MCLK_FREQ_MASK 0x0003109#define SGTL5000_MCLK_FREQ_SHIFT 0110#define SGTL5000_MCLK_FREQ_WIDTH 2111#define SGTL5000_MCLK_FREQ_256FS 0x0112#define SGTL5000_MCLK_FREQ_384FS 0x1113#define SGTL5000_MCLK_FREQ_512FS 0x2114#define SGTL5000_MCLK_FREQ_PLL 0x3115 116/*117 * SGTL5000_CHIP_I2S_CTRL118 */119#define SGTL5000_I2S_SCLKFREQ_MASK 0x0100120#define SGTL5000_I2S_SCLKFREQ_SHIFT 8121#define SGTL5000_I2S_SCLKFREQ_WIDTH 1122#define SGTL5000_I2S_SCLKFREQ_64FS 0x0123#define SGTL5000_I2S_SCLKFREQ_32FS 0x1 /* Not for RJ mode */124#define SGTL5000_I2S_MASTER 0x0080125#define SGTL5000_I2S_SCLK_INV 0x0040126#define SGTL5000_I2S_DLEN_MASK 0x0030127#define SGTL5000_I2S_DLEN_SHIFT 4128#define SGTL5000_I2S_DLEN_WIDTH 2129#define SGTL5000_I2S_DLEN_32 0x0130#define SGTL5000_I2S_DLEN_24 0x1131#define SGTL5000_I2S_DLEN_20 0x2132#define SGTL5000_I2S_DLEN_16 0x3133#define SGTL5000_I2S_MODE_MASK 0x000c134#define SGTL5000_I2S_MODE_SHIFT 2135#define SGTL5000_I2S_MODE_WIDTH 2136#define SGTL5000_I2S_MODE_I2S_LJ 0x0137#define SGTL5000_I2S_MODE_RJ 0x1138#define SGTL5000_I2S_MODE_PCM 0x2139#define SGTL5000_I2S_LRALIGN 0x0002140#define SGTL5000_I2S_LRPOL 0x0001 /* set for which mode */141 142/*143 * SGTL5000_CHIP_SSS_CTRL144 */145#define SGTL5000_DAP_MIX_LRSWAP 0x4000146#define SGTL5000_DAP_LRSWAP 0x2000147#define SGTL5000_DAC_LRSWAP 0x1000148#define SGTL5000_I2S_OUT_LRSWAP 0x0400149#define SGTL5000_DAP_MIX_SEL_MASK 0x0300150#define SGTL5000_DAP_MIX_SEL_SHIFT 8151#define SGTL5000_DAP_MIX_SEL_WIDTH 2152#define SGTL5000_DAP_MIX_SEL_ADC 0x0153#define SGTL5000_DAP_MIX_SEL_I2S_IN 0x1154#define SGTL5000_DAP_SEL_MASK 0x00c0155#define SGTL5000_DAP_SEL_SHIFT 6156#define SGTL5000_DAP_SEL_WIDTH 2157#define SGTL5000_DAP_SEL_ADC 0x0158#define SGTL5000_DAP_SEL_I2S_IN 0x1159#define SGTL5000_DAC_SEL_MASK 0x0030160#define SGTL5000_DAC_SEL_SHIFT 4161#define SGTL5000_DAC_SEL_WIDTH 2162#define SGTL5000_DAC_SEL_ADC 0x0163#define SGTL5000_DAC_SEL_I2S_IN 0x1164#define SGTL5000_DAC_SEL_DAP 0x3165#define SGTL5000_I2S_OUT_SEL_MASK 0x0003166#define SGTL5000_I2S_OUT_SEL_SHIFT 0167#define SGTL5000_I2S_OUT_SEL_WIDTH 2168#define SGTL5000_I2S_OUT_SEL_ADC 0x0169#define SGTL5000_I2S_OUT_SEL_I2S_IN 0x1170#define SGTL5000_I2S_OUT_SEL_DAP 0x3171 172/*173 * SGTL5000_CHIP_ADCDAC_CTRL174 */175#define SGTL5000_VOL_BUSY_DAC_RIGHT 0x2000176#define SGTL5000_VOL_BUSY_DAC_LEFT 0x1000177#define SGTL5000_DAC_VOL_RAMP_EN 0x0200178#define SGTL5000_DAC_VOL_RAMP_EXPO 0x0100179#define SGTL5000_DAC_MUTE_RIGHT 0x0008180#define SGTL5000_DAC_MUTE_LEFT 0x0004181#define SGTL5000_ADC_HPF_FREEZE 0x0002182#define SGTL5000_ADC_HPF_BYPASS 0x0001183 184/*185 * SGTL5000_CHIP_DAC_VOL186 */187#define SGTL5000_DAC_VOL_RIGHT_MASK 0xff00188#define SGTL5000_DAC_VOL_RIGHT_SHIFT 8189#define SGTL5000_DAC_VOL_RIGHT_WIDTH 8190#define SGTL5000_DAC_VOL_LEFT_MASK 0x00ff191#define SGTL5000_DAC_VOL_LEFT_SHIFT 0192#define SGTL5000_DAC_VOL_LEFT_WIDTH 8193 194/*195 * SGTL5000_CHIP_PAD_STRENGTH196 */197#define SGTL5000_PAD_I2S_LRCLK_MASK 0x0300198#define SGTL5000_PAD_I2S_LRCLK_SHIFT 8199#define SGTL5000_PAD_I2S_LRCLK_WIDTH 2200#define SGTL5000_PAD_I2S_SCLK_MASK 0x00c0201#define SGTL5000_PAD_I2S_SCLK_SHIFT 6202#define SGTL5000_PAD_I2S_SCLK_WIDTH 2203#define SGTL5000_PAD_I2S_DOUT_MASK 0x0030204#define SGTL5000_PAD_I2S_DOUT_SHIFT 4205#define SGTL5000_PAD_I2S_DOUT_WIDTH 2206#define SGTL5000_PAD_I2C_SDA_MASK 0x000c207#define SGTL5000_PAD_I2C_SDA_SHIFT 2208#define SGTL5000_PAD_I2C_SDA_WIDTH 2209#define SGTL5000_PAD_I2C_SCL_MASK 0x0003210#define SGTL5000_PAD_I2C_SCL_SHIFT 0211#define SGTL5000_PAD_I2C_SCL_WIDTH 2212 213/*214 * SGTL5000_CHIP_ANA_ADC_CTRL215 */216#define SGTL5000_ADC_VOL_M6DB 0x0100217#define SGTL5000_ADC_VOL_RIGHT_MASK 0x00f0218#define SGTL5000_ADC_VOL_RIGHT_SHIFT 4219#define SGTL5000_ADC_VOL_RIGHT_WIDTH 4220#define SGTL5000_ADC_VOL_LEFT_MASK 0x000f221#define SGTL5000_ADC_VOL_LEFT_SHIFT 0222#define SGTL5000_ADC_VOL_LEFT_WIDTH 4223 224/*225 * SGTL5000_CHIP_ANA_HP_CTRL226 */227#define SGTL5000_HP_VOL_RIGHT_MASK 0x7f00228#define SGTL5000_HP_VOL_RIGHT_SHIFT 8229#define SGTL5000_HP_VOL_RIGHT_WIDTH 7230#define SGTL5000_HP_VOL_LEFT_MASK 0x007f231#define SGTL5000_HP_VOL_LEFT_SHIFT 0232#define SGTL5000_HP_VOL_LEFT_WIDTH 7233 234/*235 * SGTL5000_CHIP_ANA_CTRL236 */237#define SGTL5000_CHIP_ANA_CTRL_DEFAULT 0x0133238#define SGTL5000_LINE_OUT_MUTE 0x0100239#define SGTL5000_HP_SEL_MASK 0x0040240#define SGTL5000_HP_SEL_SHIFT 6241#define SGTL5000_HP_SEL_WIDTH 1242#define SGTL5000_HP_SEL_DAC 0x0243#define SGTL5000_HP_SEL_LINE_IN 0x1244#define SGTL5000_HP_ZCD_EN 0x0020245#define SGTL5000_HP_MUTE 0x0010246#define SGTL5000_ADC_SEL_MASK 0x0004247#define SGTL5000_ADC_SEL_SHIFT 2248#define SGTL5000_ADC_SEL_WIDTH 1249#define SGTL5000_ADC_SEL_MIC 0x0250#define SGTL5000_ADC_SEL_LINE_IN 0x1251#define SGTL5000_ADC_ZCD_EN 0x0002252#define SGTL5000_ADC_MUTE 0x0001253 254/*255 * SGTL5000_CHIP_LINREG_CTRL256 */257#define SGTL5000_VDDC_MAN_ASSN_MASK 0x0040258#define SGTL5000_VDDC_MAN_ASSN_SHIFT 6259#define SGTL5000_VDDC_MAN_ASSN_WIDTH 1260#define SGTL5000_VDDC_MAN_ASSN_VDDA 0x0261#define SGTL5000_VDDC_MAN_ASSN_VDDIO 0x1262#define SGTL5000_VDDC_ASSN_OVRD 0x0020263#define SGTL5000_LINREG_VDDD_MASK 0x000f264#define SGTL5000_LINREG_VDDD_SHIFT 0265#define SGTL5000_LINREG_VDDD_WIDTH 4266 267/*268 * SGTL5000_CHIP_REF_CTRL269 */270#define SGTL5000_ANA_GND_MASK 0x01f0271#define SGTL5000_ANA_GND_SHIFT 4272#define SGTL5000_ANA_GND_WIDTH 5273#define SGTL5000_ANA_GND_BASE 800 /* mv */274#define SGTL5000_ANA_GND_STP 25 /*mv */275#define SGTL5000_BIAS_CTRL_MASK 0x000e276#define SGTL5000_BIAS_CTRL_SHIFT 1277#define SGTL5000_BIAS_CTRL_WIDTH 3278#define SGTL5000_SMALL_POP 0x0001279 280/*281 * SGTL5000_CHIP_MIC_CTRL282 */283#define SGTL5000_BIAS_R_MASK 0x0300284#define SGTL5000_BIAS_R_SHIFT 8285#define SGTL5000_BIAS_R_WIDTH 2286#define SGTL5000_BIAS_R_off 0x0287#define SGTL5000_BIAS_R_2K 0x1288#define SGTL5000_BIAS_R_4k 0x2289#define SGTL5000_BIAS_R_8k 0x3290#define SGTL5000_BIAS_VOLT_MASK 0x0070291#define SGTL5000_BIAS_VOLT_SHIFT 4292#define SGTL5000_BIAS_VOLT_WIDTH 3293#define SGTL5000_MIC_GAIN_MASK 0x0003294#define SGTL5000_MIC_GAIN_SHIFT 0295#define SGTL5000_MIC_GAIN_WIDTH 2296 297/*298 * SGTL5000_CHIP_LINE_OUT_CTRL299 */300#define SGTL5000_LINE_OUT_CURRENT_MASK 0x0f00301#define SGTL5000_LINE_OUT_CURRENT_SHIFT 8302#define SGTL5000_LINE_OUT_CURRENT_WIDTH 4303#define SGTL5000_LINE_OUT_CURRENT_180u 0x0304#define SGTL5000_LINE_OUT_CURRENT_270u 0x1305#define SGTL5000_LINE_OUT_CURRENT_360u 0x3306#define SGTL5000_LINE_OUT_CURRENT_450u 0x7307#define SGTL5000_LINE_OUT_CURRENT_540u 0xf308#define SGTL5000_LINE_OUT_GND_MASK 0x003f309#define SGTL5000_LINE_OUT_GND_SHIFT 0310#define SGTL5000_LINE_OUT_GND_WIDTH 6311#define SGTL5000_LINE_OUT_GND_BASE 800 /* mv */312#define SGTL5000_LINE_OUT_GND_STP 25313#define SGTL5000_LINE_OUT_GND_MAX 0x23314 315/*316 * SGTL5000_CHIP_LINE_OUT_VOL317 */318#define SGTL5000_LINE_OUT_VOL_RIGHT_MASK 0x1f00319#define SGTL5000_LINE_OUT_VOL_RIGHT_SHIFT 8320#define SGTL5000_LINE_OUT_VOL_RIGHT_WIDTH 5321#define SGTL5000_LINE_OUT_VOL_LEFT_MASK 0x001f322#define SGTL5000_LINE_OUT_VOL_LEFT_SHIFT 0323#define SGTL5000_LINE_OUT_VOL_LEFT_WIDTH 5324 325/*326 * SGTL5000_CHIP_ANA_POWER327 */328#define SGTL5000_ANA_POWER_DEFAULT 0x7060329#define SGTL5000_DAC_STEREO 0x4000330#define SGTL5000_LINREG_SIMPLE_POWERUP 0x2000331#define SGTL5000_STARTUP_POWERUP 0x1000332#define SGTL5000_VDDC_CHRGPMP_POWERUP 0x0800333#define SGTL5000_PLL_POWERUP 0x0400334#define SGTL5000_LINEREG_D_POWERUP 0x0200335#define SGTL5000_VCOAMP_POWERUP 0x0100336#define SGTL5000_VAG_POWERUP 0x0080337#define SGTL5000_ADC_STEREO 0x0040338#define SGTL5000_REFTOP_POWERUP 0x0020339#define SGTL5000_HP_POWERUP 0x0010340#define SGTL5000_DAC_POWERUP 0x0008341#define SGTL5000_CAPLESS_HP_POWERUP 0x0004342#define SGTL5000_ADC_POWERUP 0x0002343#define SGTL5000_LINE_OUT_POWERUP 0x0001344 345/*346 * SGTL5000_CHIP_PLL_CTRL347 */348#define SGTL5000_PLL_INT_DIV_MASK 0xf800349#define SGTL5000_PLL_INT_DIV_SHIFT 11350#define SGTL5000_PLL_INT_DIV_WIDTH 5351#define SGTL5000_PLL_FRAC_DIV_MASK 0x07ff352#define SGTL5000_PLL_FRAC_DIV_SHIFT 0353#define SGTL5000_PLL_FRAC_DIV_WIDTH 11354 355/*356 * SGTL5000_CHIP_CLK_TOP_CTRL357 */358#define SGTL5000_INT_OSC_EN 0x0800359#define SGTL5000_INPUT_FREQ_DIV2 0x0008360 361/*362 * SGTL5000_CHIP_ANA_STATUS363 */364#define SGTL5000_HP_LRSHORT 0x0200365#define SGTL5000_CAPLESS_SHORT 0x0100366#define SGTL5000_PLL_LOCKED 0x0010367 368/*369 * SGTL5000_CHIP_SHORT_CTRL370 */371#define SGTL5000_LVLADJR_MASK 0x7000372#define SGTL5000_LVLADJR_SHIFT 12373#define SGTL5000_LVLADJR_WIDTH 3374#define SGTL5000_LVLADJL_MASK 0x0700375#define SGTL5000_LVLADJL_SHIFT 8376#define SGTL5000_LVLADJL_WIDTH 3377#define SGTL5000_LVLADJC_MASK 0x0070378#define SGTL5000_LVLADJC_SHIFT 4379#define SGTL5000_LVLADJC_WIDTH 3380#define SGTL5000_LR_SHORT_MOD_MASK 0x000c381#define SGTL5000_LR_SHORT_MOD_SHIFT 2382#define SGTL5000_LR_SHORT_MOD_WIDTH 2383#define SGTL5000_CM_SHORT_MOD_MASK 0x0003384#define SGTL5000_CM_SHORT_MOD_SHIFT 0385#define SGTL5000_CM_SHORT_MOD_WIDTH 2386 387/*388 *SGTL5000_CHIP_ANA_TEST2389 */390#define SGTL5000_MONO_DAC 0x1000391 392/*393 * SGTL5000_DAP_CTRL394 */395#define SGTL5000_DAP_MIX_EN 0x0010396#define SGTL5000_DAP_EN 0x0001397 398#define SGTL5000_SYSCLK 0x00399#define SGTL5000_LRCLK 0x01400 401/*402 * SGTL5000_DAP_AUDIO_EQ403 */404#define SGTL5000_DAP_SEL_PEQ 1405#define SGTL5000_DAP_SEL_TONE_CTRL 2406#define SGTL5000_DAP_SEL_GEQ 3407 408#endif409