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1// SPDX-License-Identifier: GPL-2.02//3// src4xxx.h -- SRC4XXX ALSA SoC audio driver4//5// Copyright 2021-2022 Deqx Pty Ltd6// Author: Matt R Flax <flatmax@flatmax.com>7 8#ifndef __SRC4XXX_H__9#define __SRC4XXX_H__10 11#define SRC4XXX_RES_00 0x0012#define SRC4XXX_PWR_RST_01 0x0113#define SRC4XXX_RESET 0x8014#define SRC4XXX_POWER_DOWN 0x0015#define SRC4XXX_POWER_ENABLE 0x2016#define SRC4XXX_ENABLE_SRC 0x117#define SRC4XXX_ENABLE_SRC_SHIFT 018#define SRC4XXX_ENABLE_DIR 0x219#define SRC4XXX_ENABLE_DIR_SHIFT 120#define SRC4XXX_ENABLE_DIT 0x421#define SRC4XXX_ENABLE_DIT_SHIFT 222#define SRC4XXX_ENABLE_PORT_B 0x823#define SRC4XXX_ENABLE_PORT_B_SHIFT 324#define SRC4XXX_ENABLE_PORT_A 0x1025#define SRC4XXX_ENABLE_PORT_A_SHIFT 426 27#define SRC4XXX_PORTA_CTL_03 0x0328#define SRC4XXX_BUS_MASTER 0x829#define SRC4XXX_BUS_LEFT_J 0x030#define SRC4XXX_BUS_I2S 0x131#define SRC4XXX_BUS_RIGHT_J_16 0x432#define SRC4XXX_BUS_RIGHT_J_18 0x533#define SRC4XXX_BUS_RIGHT_J_20 0x634#define SRC4XXX_BUS_RIGHT_J_24 0x735#define SRC4XXX_BUS_FMT_MS_MASK 0xf36 37#define SRC4XXX_PORTA_CTL_04 0x0438#define SRC4XXX_MCLK_DIV_MASK 0x339 40#define SRC4XXX_BUS_FMT(id) (SRC4XXX_PORTA_CTL_03+2*id)41#define SRC4XXX_BUS_CLK(id) (SRC4XXX_PORTA_CTL_04+2*id)42 43#define SRC4XXX_PORTB_CTL_05 0x0544#define SRC4XXX_PORTB_CTL_06 0x0645 46#define SRC4XXX_TX_CTL_07 0x0747#define SRC4XXX_TX_MCLK_DIV_MASK 0x6048#define SRC4XXX_TX_MCLK_DIV_SHIFT 549 50#define SRC4XXX_TX_CTL_08 0x0851#define SRC4XXX_TX_CTL_09 0x0952#define SRC4XXX_SRC_DIT_IRQ_MSK_0B 0x0B53#define SRC4XXX_SRC_BTI_EN 0x0154#define SRC4XXX_SRC_TSLIP_EN 0x0255#define SRC4XXX_SRC_DIT_IRQ_MODE_0C 0x0C56#define SRC4XXX_RCV_CTL_0D 0x0D57#define SRC4XXX_RXCLK_RXCKI 0x058#define SRC4XXX_RXCLK_MCLK 0x859#define SRC4XXX_RCV_CTL_0E 0x0E60#define SRC4XXX_REC_MCLK_EN 0x161#define SRC4XXX_PLL2_DIV_0 (0x0<<1)62#define SRC4XXX_PLL2_DIV_2 (0x1<<1)63#define SRC4XXX_PLL2_DIV_4 (0x2<<1)64#define SRC4XXX_PLL2_DIV_8 (0x3<<1)65#define SRC4XXX_PLL2_LOL 0x866#define SRC4XXX_RCV_PLL_0F 0x0F67#define SRC4XXX_RCV_PLL_10 0x1068#define SRC4XXX_RCV_PLL_11 0x1169#define SRC4XXX_RVC_IRQ_MSK_16 0x1670#define SRC4XXX_RVC_IRQ_MSK_17 0x1771#define SRC4XXX_RVC_IRQ_MODE_18 0x1872#define SRC4XXX_RVC_IRQ_MODE_19 0x1973#define SRC4XXX_RVC_IRQ_MODE_1A 0x1A74#define SRC4XXX_GPIO_1_1B 0x1B75#define SRC4XXX_GPIO_2_1C 0x1C76#define SRC4XXX_GPIO_3_1D 0x1D77#define SRC4XXX_GPIO_4_1E 0x1E78#define SRC4XXX_SCR_CTL_2D 0x2D79#define SRC4XXX_SCR_CTL_2E 0x2E80#define SRC4XXX_SCR_CTL_2F 0x2F81#define SRC4XXX_SCR_CTL_30 0x3082#define SRC4XXX_SCR_CTL_31 0x3183#define SRC4XXX_PAGE_SEL_7F 0x7F84 85// read only registers86#define SRC4XXX_GLOBAL_ITR_STS_02 0x0287#define SRC4XXX_SRC_DIT_STS_0A 0x0A88#define SRC4XXX_NON_AUDIO_D_12 0x1289#define SRC4XXX_RVC_STS_13 0x1390#define SRC4XXX_RVC_STS_14 0x1491#define SRC4XXX_RVC_STS_15 0x1592#define SRC4XXX_SUB_CODE_1F 0x1F93#define SRC4XXX_SUB_CODE_20 0x2094#define SRC4XXX_SUB_CODE_21 0x2195#define SRC4XXX_SUB_CODE_22 0x2296#define SRC4XXX_SUB_CODE_23 0x2397#define SRC4XXX_SUB_CODE_24 0x2498#define SRC4XXX_SUB_CODE_25 0x2599#define SRC4XXX_SUB_CODE_26 0x26100#define SRC4XXX_SUB_CODE_27 0x27101#define SRC4XXX_SUB_CODE_28 0x28102#define SRC4XXX_PC_PREAMBLE_HI_29 0x29103#define SRC4XXX_PC_PREAMBLE_LO_2A 0x2A104#define SRC4XXX_PD_PREAMBLE_HI_2B 0x2B105#define SRC4XXX_PC_PREAMBLE_LO_2C 0x2C106#define SRC4XXX_IO_RATIO_32 0x32107#define SRC4XXX_IO_RATIO_33 0x33108 109int src4xxx_probe(struct device *dev, struct regmap *regmap,110 void (*switch_mode)(struct device *dev));111extern const struct regmap_config src4xxx_regmap_config;112 113#endif /* __SRC4XXX_H__ */114