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1// SPDX-License-Identifier: GPL-2.0-only2//3// Based on sound/soc/codecs/tlv320aic3x.c by Vladimir Barinov4//5// Copyright (C) 2010 Mistral Solutions Pvt Ltd.6// Author: Shahina Shaik <shahina.s@mistralsolutions.com>7//8// Copyright (C) 2014-2018, Ambarella, Inc.9// Author: Dongge wu <dgwu@ambarella.com>10//11// Copyright (C) 2021 Axis Communications AB12// Author: Ricard Wanderlof <ricardw@axis.com>13//14 15#include <dt-bindings/sound/tlv320adc3xxx.h>16#include <linux/clk.h>17#include <linux/gpio/consumer.h>18#include <linux/module.h>19#include <linux/moduleparam.h>20#include <linux/io.h>21#include <linux/init.h>22#include <linux/delay.h>23#include <linux/gpio/driver.h>24#include <linux/pm.h>25#include <linux/i2c.h>26#include <linux/platform_device.h>27#include <linux/cdev.h>28#include <linux/slab.h>29#include <sound/core.h>30#include <sound/pcm.h>31#include <sound/pcm_params.h>32#include <sound/soc.h>33#include <sound/soc-dapm.h>34#include <sound/tlv.h>35#include <sound/initval.h>36 37/*38 * General definitions defining exported functionality.39 */40 41#define ADC3XXX_MICBIAS_PINS 242#define ADC3XXX_GPIO_PINS 243 44/* Number of GPIO pins exposed via the gpiolib interface */45#define ADC3XXX_GPIOS_MAX (ADC3XXX_MICBIAS_PINS + ADC3XXX_GPIO_PINS)46 47#define ADC3XXX_RATES SNDRV_PCM_RATE_8000_9600048#define ADC3XXX_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \49 SNDRV_PCM_FMTBIT_S20_3LE | \50 SNDRV_PCM_FMTBIT_S24_3LE | \51 SNDRV_PCM_FMTBIT_S32_LE)52 53/*54 * PLL modes, to be used for clk_id for set_sysclk callback.55 *56 * The default behavior (AUTO) is to take the first matching entry in the clock57 * table, which is intended to be the PLL based one if there is more than one.58 *59 * Setting the clock source using simple-card (clocks or60 * system-clock-frequency property) sets clk_id = 0 = ADC3XXX_PLL_AUTO.61 */62#define ADC3XXX_PLL_AUTO 0 /* Use first available mode */63#define ADC3XXX_PLL_ENABLE 1 /* Use PLL for clock generation */64#define ADC3XXX_PLL_BYPASS 2 /* Don't use PLL for clock generation */65 66/* Register definitions. */67 68#define ADC3XXX_PAGE_SIZE 12869#define ADC3XXX_REG(page, reg) ((page * ADC3XXX_PAGE_SIZE) + reg)70 71/*72 * Page 0 registers.73 */74 75#define ADC3XXX_PAGE_SELECT ADC3XXX_REG(0, 0)76#define ADC3XXX_RESET ADC3XXX_REG(0, 1)77 78/* 2-3 Reserved */79 80#define ADC3XXX_CLKGEN_MUX ADC3XXX_REG(0, 4)81#define ADC3XXX_PLL_PROG_PR ADC3XXX_REG(0, 5)82#define ADC3XXX_PLL_PROG_J ADC3XXX_REG(0, 6)83#define ADC3XXX_PLL_PROG_D_MSB ADC3XXX_REG(0, 7)84#define ADC3XXX_PLL_PROG_D_LSB ADC3XXX_REG(0, 8)85 86/* 9-17 Reserved */87 88#define ADC3XXX_ADC_NADC ADC3XXX_REG(0, 18)89#define ADC3XXX_ADC_MADC ADC3XXX_REG(0, 19)90#define ADC3XXX_ADC_AOSR ADC3XXX_REG(0, 20)91#define ADC3XXX_ADC_IADC ADC3XXX_REG(0, 21)92 93/* 23-24 Reserved */94 95#define ADC3XXX_CLKOUT_MUX ADC3XXX_REG(0, 25)96#define ADC3XXX_CLKOUT_M_DIV ADC3XXX_REG(0, 26)97#define ADC3XXX_INTERFACE_CTRL_1 ADC3XXX_REG(0, 27)98#define ADC3XXX_CH_OFFSET_1 ADC3XXX_REG(0, 28)99#define ADC3XXX_INTERFACE_CTRL_2 ADC3XXX_REG(0, 29)100#define ADC3XXX_BCLK_N_DIV ADC3XXX_REG(0, 30)101#define ADC3XXX_INTERFACE_CTRL_3 ADC3XXX_REG(0, 31)102#define ADC3XXX_INTERFACE_CTRL_4 ADC3XXX_REG(0, 32)103#define ADC3XXX_INTERFACE_CTRL_5 ADC3XXX_REG(0, 33)104#define ADC3XXX_I2S_SYNC ADC3XXX_REG(0, 34)105/* 35 Reserved */106#define ADC3XXX_ADC_FLAG ADC3XXX_REG(0, 36)107#define ADC3XXX_CH_OFFSET_2 ADC3XXX_REG(0, 37)108#define ADC3XXX_I2S_TDM_CTRL ADC3XXX_REG(0, 38)109/* 39-41 Reserved */110#define ADC3XXX_INTR_FLAG_1 ADC3XXX_REG(0, 42)111#define ADC3XXX_INTR_FLAG_2 ADC3XXX_REG(0, 43)112/* 44 Reserved */113#define ADC3XXX_INTR_FLAG_ADC1 ADC3XXX_REG(0, 45)114/* 46 Reserved */115#define ADC3XXX_INTR_FLAG_ADC2 ADC3XXX_REG(0, 47)116#define ADC3XXX_INT1_CTRL ADC3XXX_REG(0, 48)117#define ADC3XXX_INT2_CTRL ADC3XXX_REG(0, 49)118/* 50 Reserved */119#define ADC3XXX_GPIO2_CTRL ADC3XXX_REG(0, 51)120#define ADC3XXX_GPIO1_CTRL ADC3XXX_REG(0, 52)121#define ADC3XXX_DOUT_CTRL ADC3XXX_REG(0, 53)122/* 54-56 Reserved */123#define ADC3XXX_SYNC_CTRL_1 ADC3XXX_REG(0, 57)124#define ADC3XXX_SYNC_CTRL_2 ADC3XXX_REG(0, 58)125#define ADC3XXX_CIC_GAIN_CTRL ADC3XXX_REG(0, 59)126/* 60 Reserved */127#define ADC3XXX_PRB_SELECT ADC3XXX_REG(0, 61)128#define ADC3XXX_INST_MODE_CTRL ADC3XXX_REG(0, 62)129/* 63-79 Reserved */130#define ADC3XXX_MIC_POLARITY_CTRL ADC3XXX_REG(0, 80)131#define ADC3XXX_ADC_DIGITAL ADC3XXX_REG(0, 81)132#define ADC3XXX_ADC_FGA ADC3XXX_REG(0, 82)133#define ADC3XXX_LADC_VOL ADC3XXX_REG(0, 83)134#define ADC3XXX_RADC_VOL ADC3XXX_REG(0, 84)135#define ADC3XXX_ADC_PHASE_COMP ADC3XXX_REG(0, 85)136#define ADC3XXX_LEFT_CHN_AGC_1 ADC3XXX_REG(0, 86)137#define ADC3XXX_LEFT_CHN_AGC_2 ADC3XXX_REG(0, 87)138#define ADC3XXX_LEFT_CHN_AGC_3 ADC3XXX_REG(0, 88)139#define ADC3XXX_LEFT_CHN_AGC_4 ADC3XXX_REG(0, 89)140#define ADC3XXX_LEFT_CHN_AGC_5 ADC3XXX_REG(0, 90)141#define ADC3XXX_LEFT_CHN_AGC_6 ADC3XXX_REG(0, 91)142#define ADC3XXX_LEFT_CHN_AGC_7 ADC3XXX_REG(0, 92)143#define ADC3XXX_LEFT_AGC_GAIN ADC3XXX_REG(0, 93)144#define ADC3XXX_RIGHT_CHN_AGC_1 ADC3XXX_REG(0, 94)145#define ADC3XXX_RIGHT_CHN_AGC_2 ADC3XXX_REG(0, 95)146#define ADC3XXX_RIGHT_CHN_AGC_3 ADC3XXX_REG(0, 96)147#define ADC3XXX_RIGHT_CHN_AGC_4 ADC3XXX_REG(0, 97)148#define ADC3XXX_RIGHT_CHN_AGC_5 ADC3XXX_REG(0, 98)149#define ADC3XXX_RIGHT_CHN_AGC_6 ADC3XXX_REG(0, 99)150#define ADC3XXX_RIGHT_CHN_AGC_7 ADC3XXX_REG(0, 100)151#define ADC3XXX_RIGHT_AGC_GAIN ADC3XXX_REG(0, 101)152/* 102-127 Reserved */153 154/*155 * Page 1 registers.156 */157 158/* 1-25 Reserved */159#define ADC3XXX_DITHER_CTRL ADC3XXX_REG(1, 26)160/* 27-50 Reserved */161#define ADC3XXX_MICBIAS_CTRL ADC3XXX_REG(1, 51)162#define ADC3XXX_LEFT_PGA_SEL_1 ADC3XXX_REG(1, 52)163/* 53 Reserved */164#define ADC3XXX_LEFT_PGA_SEL_2 ADC3XXX_REG(1, 54)165#define ADC3XXX_RIGHT_PGA_SEL_1 ADC3XXX_REG(1, 55)166#define ADC3XXX_RIGHT_PGA_SEL_2 ADC3XXX_REG(1, 57)167#define ADC3XXX_LEFT_APGA_CTRL ADC3XXX_REG(1, 59)168#define ADC3XXX_RIGHT_APGA_CTRL ADC3XXX_REG(1, 60)169#define ADC3XXX_LOW_CURRENT_MODES ADC3XXX_REG(1, 61)170#define ADC3XXX_ANALOG_PGA_FLAGS ADC3XXX_REG(1, 62)171/* 63-127 Reserved */172 173/*174 * Page 4 registers. First page of coefficient memory for the miniDSP.175 */176#define ADC3XXX_LEFT_ADC_IIR_COEFF_N0_MSB ADC3XXX_REG(4, 8)177#define ADC3XXX_LEFT_ADC_IIR_COEFF_N0_LSB ADC3XXX_REG(4, 9)178#define ADC3XXX_LEFT_ADC_IIR_COEFF_N1_MSB ADC3XXX_REG(4, 10)179#define ADC3XXX_LEFT_ADC_IIR_COEFF_N1_LSB ADC3XXX_REG(4, 11)180#define ADC3XXX_LEFT_ADC_IIR_COEFF_D1_MSB ADC3XXX_REG(4, 12)181#define ADC3XXX_LEFT_ADC_IIR_COEFF_D1_LSB ADC3XXX_REG(4, 13)182 183#define ADC3XXX_RIGHT_ADC_IIR_COEFF_N0_MSB ADC3XXX_REG(4, 72)184#define ADC3XXX_RIGHT_ADC_IIR_COEFF_N0_LSB ADC3XXX_REG(4, 73)185#define ADC3XXX_RIGHT_ADC_IIR_COEFF_N1_MSB ADC3XXX_REG(4, 74)186#define ADC3XXX_RIGHT_ADC_IIR_COEFF_N1_LSB ADC3XXX_REG(4, 75)187#define ADC3XXX_RIGHT_ADC_IIR_COEFF_D1_MSB ADC3XXX_REG(4, 76)188#define ADC3XXX_RIGHT_ADC_IIR_COEFF_D1_LSB ADC3XXX_REG(4, 77)189 190/*191 * Register bits.192 */193 194/* PLL Enable bits */195#define ADC3XXX_ENABLE_PLL_SHIFT 7196#define ADC3XXX_ENABLE_PLL (1 << ADC3XXX_ENABLE_PLL_SHIFT)197#define ADC3XXX_ENABLE_NADC_SHIFT 7198#define ADC3XXX_ENABLE_NADC (1 << ADC3XXX_ENABLE_NADC_SHIFT)199#define ADC3XXX_ENABLE_MADC_SHIFT 7200#define ADC3XXX_ENABLE_MADC (1 << ADC3XXX_ENABLE_MADC_SHIFT)201#define ADC3XXX_ENABLE_BCLK_SHIFT 7202#define ADC3XXX_ENABLE_BCLK (1 << ADC3XXX_ENABLE_BCLK_SHIFT)203 204/* Power bits */205#define ADC3XXX_LADC_PWR_ON 0x80206#define ADC3XXX_RADC_PWR_ON 0x40207 208#define ADC3XXX_SOFT_RESET 0x01209#define ADC3XXX_BCLK_MASTER 0x08210#define ADC3XXX_WCLK_MASTER 0x04211 212/* Interface register masks */213#define ADC3XXX_FORMAT_MASK 0xc0214#define ADC3XXX_FORMAT_SHIFT 6215#define ADC3XXX_WLENGTH_MASK 0x30216#define ADC3XXX_WLENGTH_SHIFT 4217#define ADC3XXX_CLKDIR_MASK 0x0c218#define ADC3XXX_CLKDIR_SHIFT 2219 220/* Interface register bit patterns */221#define ADC3XXX_FORMAT_I2S (0 << ADC3XXX_FORMAT_SHIFT)222#define ADC3XXX_FORMAT_DSP (1 << ADC3XXX_FORMAT_SHIFT)223#define ADC3XXX_FORMAT_RJF (2 << ADC3XXX_FORMAT_SHIFT)224#define ADC3XXX_FORMAT_LJF (3 << ADC3XXX_FORMAT_SHIFT)225 226#define ADC3XXX_IFACE_16BITS (0 << ADC3XXX_WLENGTH_SHIFT)227#define ADC3XXX_IFACE_20BITS (1 << ADC3XXX_WLENGTH_SHIFT)228#define ADC3XXX_IFACE_24BITS (2 << ADC3XXX_WLENGTH_SHIFT)229#define ADC3XXX_IFACE_32BITS (3 << ADC3XXX_WLENGTH_SHIFT)230 231/* PLL P/R bit offsets */232#define ADC3XXX_PLLP_SHIFT 4233#define ADC3XXX_PLLR_SHIFT 0234#define ADC3XXX_PLL_PR_MASK 0x7f235#define ADC3XXX_PLLJ_MASK 0x3f236#define ADC3XXX_PLLD_MSB_MASK 0x3f237#define ADC3XXX_PLLD_LSB_MASK 0xff238#define ADC3XXX_NADC_MASK 0x7f239#define ADC3XXX_MADC_MASK 0x7f240#define ADC3XXX_AOSR_MASK 0xff241#define ADC3XXX_IADC_MASK 0xff242#define ADC3XXX_BDIV_MASK 0x7f243 244/* PLL_CLKIN bits */245#define ADC3XXX_PLL_CLKIN_SHIFT 2246#define ADC3XXX_PLL_CLKIN_MCLK 0x0247#define ADC3XXX_PLL_CLKIN_BCLK 0x1248#define ADC3XXX_PLL_CLKIN_ZERO 0x3249 250/* CODEC_CLKIN bits */251#define ADC3XXX_CODEC_CLKIN_SHIFT 0252#define ADC3XXX_CODEC_CLKIN_MCLK 0x0253#define ADC3XXX_CODEC_CLKIN_BCLK 0x1254#define ADC3XXX_CODEC_CLKIN_PLL_CLK 0x3255 256#define ADC3XXX_USE_PLL ((ADC3XXX_PLL_CLKIN_MCLK << ADC3XXX_PLL_CLKIN_SHIFT) | \257 (ADC3XXX_CODEC_CLKIN_PLL_CLK << ADC3XXX_CODEC_CLKIN_SHIFT))258#define ADC3XXX_NO_PLL ((ADC3XXX_PLL_CLKIN_ZERO << ADC3XXX_PLL_CLKIN_SHIFT) | \259 (ADC3XXX_CODEC_CLKIN_MCLK << ADC3XXX_CODEC_CLKIN_SHIFT))260 261/* Analog PGA control bits */262#define ADC3XXX_LPGA_MUTE 0x80263#define ADC3XXX_RPGA_MUTE 0x80264 265#define ADC3XXX_LPGA_GAIN_MASK 0x7f266#define ADC3XXX_RPGA_GAIN_MASK 0x7f267 268/* ADC current modes */269#define ADC3XXX_ADC_LOW_CURR_MODE 0x01270 271/* Left ADC Input selection bits */272#define ADC3XXX_LCH_SEL1_SHIFT 0273#define ADC3XXX_LCH_SEL2_SHIFT 2274#define ADC3XXX_LCH_SEL3_SHIFT 4275#define ADC3XXX_LCH_SEL4_SHIFT 6276 277#define ADC3XXX_LCH_SEL1X_SHIFT 0278#define ADC3XXX_LCH_SEL2X_SHIFT 2279#define ADC3XXX_LCH_SEL3X_SHIFT 4280#define ADC3XXX_LCH_COMMON_MODE 0x40281#define ADC3XXX_BYPASS_LPGA 0x80282 283/* Right ADC Input selection bits */284#define ADC3XXX_RCH_SEL1_SHIFT 0285#define ADC3XXX_RCH_SEL2_SHIFT 2286#define ADC3XXX_RCH_SEL3_SHIFT 4287#define ADC3XXX_RCH_SEL4_SHIFT 6288 289#define ADC3XXX_RCH_SEL1X_SHIFT 0290#define ADC3XXX_RCH_SEL2X_SHIFT 2291#define ADC3XXX_RCH_SEL3X_SHIFT 4292#define ADC3XXX_RCH_COMMON_MODE 0x40293#define ADC3XXX_BYPASS_RPGA 0x80294 295/* MICBIAS control bits */296#define ADC3XXX_MICBIAS_MASK 0x3297#define ADC3XXX_MICBIAS1_SHIFT 5298#define ADC3XXX_MICBIAS2_SHIFT 3299 300#define ADC3XXX_ADC_MAX_VOLUME 64301#define ADC3XXX_ADC_POS_VOL 24302 303/* GPIO control bits (GPIO1_CTRL and GPIO2_CTRL) */304#define ADC3XXX_GPIO_CTRL_CFG_MASK 0x3c305#define ADC3XXX_GPIO_CTRL_CFG_SHIFT 2306#define ADC3XXX_GPIO_CTRL_OUTPUT_CTRL_MASK 0x01307#define ADC3XXX_GPIO_CTRL_OUTPUT_CTRL_SHIFT 0308#define ADC3XXX_GPIO_CTRL_INPUT_VALUE_MASK 0x02309#define ADC3XXX_GPIO_CTRL_INPUT_VALUE_SHIFT 1310 311enum adc3xxx_type {312 ADC3001 = 0,313 ADC3101314};315 316struct adc3xxx {317 struct device *dev;318 enum adc3xxx_type type;319 struct clk *mclk;320 struct regmap *regmap;321 struct gpio_desc *rst_pin;322 unsigned int pll_mode;323 unsigned int sysclk;324 unsigned int gpio_cfg[ADC3XXX_GPIO_PINS]; /* value+1 (0 => not set) */325 unsigned int micbias_gpo[ADC3XXX_MICBIAS_PINS]; /* 1 => pin is GPO */326 unsigned int micbias_vg[ADC3XXX_MICBIAS_PINS];327 int master;328 u8 page_no;329 int use_pll;330 struct gpio_chip gpio_chip;331};332 333static const unsigned int adc3xxx_gpio_ctrl_reg[ADC3XXX_GPIO_PINS] = {334 ADC3XXX_GPIO1_CTRL,335 ADC3XXX_GPIO2_CTRL336};337 338static const unsigned int adc3xxx_micbias_shift[ADC3XXX_MICBIAS_PINS] = {339 ADC3XXX_MICBIAS1_SHIFT,340 ADC3XXX_MICBIAS2_SHIFT341};342 343static const struct reg_default adc3xxx_defaults[] = {344 /* Page 0 */345 { 0, 0x00 }, { 1, 0x00 }, { 2, 0x00 }, { 3, 0x00 },346 { 4, 0x00 }, { 5, 0x11 }, { 6, 0x04 }, { 7, 0x00 },347 { 8, 0x00 }, { 9, 0x00 }, { 10, 0x00 }, { 11, 0x00 },348 { 12, 0x00 }, { 13, 0x00 }, { 14, 0x00 }, { 15, 0x00 },349 { 16, 0x00 }, { 17, 0x00 }, { 18, 0x01 }, { 19, 0x01 },350 { 20, 0x80 }, { 21, 0x80 }, { 22, 0x04 }, { 23, 0x00 },351 { 24, 0x00 }, { 25, 0x00 }, { 26, 0x01 }, { 27, 0x00 },352 { 28, 0x00 }, { 29, 0x02 }, { 30, 0x01 }, { 31, 0x00 },353 { 32, 0x00 }, { 33, 0x10 }, { 34, 0x00 }, { 35, 0x00 },354 { 36, 0x00 }, { 37, 0x00 }, { 38, 0x02 }, { 39, 0x00 },355 { 40, 0x00 }, { 41, 0x00 }, { 42, 0x00 }, { 43, 0x00 },356 { 44, 0x00 }, { 45, 0x00 }, { 46, 0x00 }, { 47, 0x00 },357 { 48, 0x00 }, { 49, 0x00 }, { 50, 0x00 }, { 51, 0x00 },358 { 52, 0x00 }, { 53, 0x12 }, { 54, 0x00 }, { 55, 0x00 },359 { 56, 0x00 }, { 57, 0x00 }, { 58, 0x00 }, { 59, 0x44 },360 { 60, 0x00 }, { 61, 0x01 }, { 62, 0x00 }, { 63, 0x00 },361 { 64, 0x00 }, { 65, 0x00 }, { 66, 0x00 }, { 67, 0x00 },362 { 68, 0x00 }, { 69, 0x00 }, { 70, 0x00 }, { 71, 0x00 },363 { 72, 0x00 }, { 73, 0x00 }, { 74, 0x00 }, { 75, 0x00 },364 { 76, 0x00 }, { 77, 0x00 }, { 78, 0x00 }, { 79, 0x00 },365 { 80, 0x00 }, { 81, 0x00 }, { 82, 0x88 }, { 83, 0x00 },366 { 84, 0x00 }, { 85, 0x00 }, { 86, 0x00 }, { 87, 0x00 },367 { 88, 0x7f }, { 89, 0x00 }, { 90, 0x00 }, { 91, 0x00 },368 { 92, 0x00 }, { 93, 0x00 }, { 94, 0x00 }, { 95, 0x00 },369 { 96, 0x7f }, { 97, 0x00 }, { 98, 0x00 }, { 99, 0x00 },370 { 100, 0x00 }, { 101, 0x00 }, { 102, 0x00 }, { 103, 0x00 },371 { 104, 0x00 }, { 105, 0x00 }, { 106, 0x00 }, { 107, 0x00 },372 { 108, 0x00 }, { 109, 0x00 }, { 110, 0x00 }, { 111, 0x00 },373 { 112, 0x00 }, { 113, 0x00 }, { 114, 0x00 }, { 115, 0x00 },374 { 116, 0x00 }, { 117, 0x00 }, { 118, 0x00 }, { 119, 0x00 },375 { 120, 0x00 }, { 121, 0x00 }, { 122, 0x00 }, { 123, 0x00 },376 { 124, 0x00 }, { 125, 0x00 }, { 126, 0x00 }, { 127, 0x00 },377 378 /* Page 1 */379 { 128, 0x00 }, { 129, 0x00 }, { 130, 0x00 }, { 131, 0x00 },380 { 132, 0x00 }, { 133, 0x00 }, { 134, 0x00 }, { 135, 0x00 },381 { 136, 0x00 }, { 137, 0x00 }, { 138, 0x00 }, { 139, 0x00 },382 { 140, 0x00 }, { 141, 0x00 }, { 142, 0x00 }, { 143, 0x00 },383 { 144, 0x00 }, { 145, 0x00 }, { 146, 0x00 }, { 147, 0x00 },384 { 148, 0x00 }, { 149, 0x00 }, { 150, 0x00 }, { 151, 0x00 },385 { 152, 0x00 }, { 153, 0x00 }, { 154, 0x00 }, { 155, 0x00 },386 { 156, 0x00 }, { 157, 0x00 }, { 158, 0x00 }, { 159, 0x00 },387 { 160, 0x00 }, { 161, 0x00 }, { 162, 0x00 }, { 163, 0x00 },388 { 164, 0x00 }, { 165, 0x00 }, { 166, 0x00 }, { 167, 0x00 },389 { 168, 0x00 }, { 169, 0x00 }, { 170, 0x00 }, { 171, 0x00 },390 { 172, 0x00 }, { 173, 0x00 }, { 174, 0x00 }, { 175, 0x00 },391 { 176, 0x00 }, { 177, 0x00 }, { 178, 0x00 }, { 179, 0x00 },392 { 180, 0xff }, { 181, 0x00 }, { 182, 0x3f }, { 183, 0xff },393 { 184, 0x00 }, { 185, 0x3f }, { 186, 0x00 }, { 187, 0x80 },394 { 188, 0x80 }, { 189, 0x00 }, { 190, 0x00 }, { 191, 0x00 },395 396 /* Page 4 */397 { 1024, 0x00 }, { 1026, 0x01 }, { 1027, 0x17 },398 { 1028, 0x01 }, { 1029, 0x17 }, { 1030, 0x7d }, { 1031, 0xd3 },399 { 1032, 0x7f }, { 1033, 0xff }, { 1034, 0x00 }, { 1035, 0x00 },400 { 1036, 0x00 }, { 1037, 0x00 }, { 1038, 0x7f }, { 1039, 0xff },401 { 1040, 0x00 }, { 1041, 0x00 }, { 1042, 0x00 }, { 1043, 0x00 },402 { 1044, 0x00 }, { 1045, 0x00 }, { 1046, 0x00 }, { 1047, 0x00 },403 { 1048, 0x7f }, { 1049, 0xff }, { 1050, 0x00 }, { 1051, 0x00 },404 { 1052, 0x00 }, { 1053, 0x00 }, { 1054, 0x00 }, { 1055, 0x00 },405 { 1056, 0x00 }, { 1057, 0x00 }, { 1058, 0x7f }, { 1059, 0xff },406 { 1060, 0x00 }, { 1061, 0x00 }, { 1062, 0x00 }, { 1063, 0x00 },407 { 1064, 0x00 }, { 1065, 0x00 }, { 1066, 0x00 }, { 1067, 0x00 },408 { 1068, 0x7f }, { 1069, 0xff }, { 1070, 0x00 }, { 1071, 0x00 },409 { 1072, 0x00 }, { 1073, 0x00 }, { 1074, 0x00 }, { 1075, 0x00 },410 { 1076, 0x00 }, { 1077, 0x00 }, { 1078, 0x7f }, { 1079, 0xff },411 { 1080, 0x00 }, { 1081, 0x00 }, { 1082, 0x00 }, { 1083, 0x00 },412 { 1084, 0x00 }, { 1085, 0x00 }, { 1086, 0x00 }, { 1087, 0x00 },413 { 1088, 0x00 }, { 1089, 0x00 }, { 1090, 0x00 }, { 1091, 0x00 },414 { 1092, 0x00 }, { 1093, 0x00 }, { 1094, 0x00 }, { 1095, 0x00 },415 { 1096, 0x00 }, { 1097, 0x00 }, { 1098, 0x00 }, { 1099, 0x00 },416 { 1100, 0x00 }, { 1101, 0x00 }, { 1102, 0x00 }, { 1103, 0x00 },417 { 1104, 0x00 }, { 1105, 0x00 }, { 1106, 0x00 }, { 1107, 0x00 },418 { 1108, 0x00 }, { 1109, 0x00 }, { 1110, 0x00 }, { 1111, 0x00 },419 { 1112, 0x00 }, { 1113, 0x00 }, { 1114, 0x00 }, { 1115, 0x00 },420 { 1116, 0x00 }, { 1117, 0x00 }, { 1118, 0x00 }, { 1119, 0x00 },421 { 1120, 0x00 }, { 1121, 0x00 }, { 1122, 0x00 }, { 1123, 0x00 },422 { 1124, 0x00 }, { 1125, 0x00 }, { 1126, 0x00 }, { 1127, 0x00 },423 { 1128, 0x00 }, { 1129, 0x00 }, { 1130, 0x00 }, { 1131, 0x00 },424 { 1132, 0x00 }, { 1133, 0x00 }, { 1134, 0x00 }, { 1135, 0x00 },425 { 1136, 0x00 }, { 1137, 0x00 }, { 1138, 0x00 }, { 1139, 0x00 },426 { 1140, 0x00 }, { 1141, 0x00 }, { 1142, 0x00 }, { 1143, 0x00 },427 { 1144, 0x00 }, { 1145, 0x00 }, { 1146, 0x00 }, { 1147, 0x00 },428 { 1148, 0x00 }, { 1149, 0x00 }, { 1150, 0x00 }, { 1151, 0x00 },429};430 431static bool adc3xxx_volatile_reg(struct device *dev, unsigned int reg)432{433 switch (reg) {434 case ADC3XXX_RESET:435 return true;436 default:437 return false;438 }439}440 441static const struct regmap_range_cfg adc3xxx_ranges[] = {442 {443 .range_min = 0,444 .range_max = 5 * ADC3XXX_PAGE_SIZE,445 .selector_reg = ADC3XXX_PAGE_SELECT,446 .selector_mask = 0xff,447 .selector_shift = 0,448 .window_start = 0,449 .window_len = ADC3XXX_PAGE_SIZE,450 }451};452 453static const struct regmap_config adc3xxx_regmap = {454 .reg_bits = 8,455 .val_bits = 8,456 457 .reg_defaults = adc3xxx_defaults,458 .num_reg_defaults = ARRAY_SIZE(adc3xxx_defaults),459 460 .volatile_reg = adc3xxx_volatile_reg,461 462 .cache_type = REGCACHE_RBTREE,463 464 .ranges = adc3xxx_ranges,465 .num_ranges = ARRAY_SIZE(adc3xxx_ranges),466 .max_register = 5 * ADC3XXX_PAGE_SIZE,467};468 469struct adc3xxx_rate_divs {470 u32 mclk;471 u32 rate;472 u8 pll_p;473 u8 pll_r;474 u8 pll_j;475 u16 pll_d;476 u8 nadc;477 u8 madc;478 u8 aosr;479};480 481/*482 * PLL and Clock settings.483 * If p member is 0, PLL is not used.484 * The order of the entries in this table have the PLL entries before485 * the non-PLL entries, so that the PLL modes are preferred unless486 * the PLL mode setting says otherwise.487 */488static const struct adc3xxx_rate_divs adc3xxx_divs[] = {489 /* mclk, rate, p, r, j, d, nadc, madc, aosr */490 /* 8k rate */491 { 12000000, 8000, 1, 1, 7, 1680, 42, 2, 128 },492 { 12288000, 8000, 1, 1, 7, 0000, 42, 2, 128 },493 /* 11.025k rate */494 { 12000000, 11025, 1, 1, 6, 8208, 29, 2, 128 },495 /* 16k rate */496 { 12000000, 16000, 1, 1, 7, 1680, 21, 2, 128 },497 { 12288000, 16000, 1, 1, 7, 0000, 21, 2, 128 },498 /* 22.05k rate */499 { 12000000, 22050, 1, 1, 7, 560, 15, 2, 128 },500 /* 32k rate */501 { 12000000, 32000, 1, 1, 8, 1920, 12, 2, 128 },502 { 12288000, 32000, 1, 1, 8, 0000, 12, 2, 128 },503 /* 44.1k rate */504 { 12000000, 44100, 1, 1, 7, 5264, 8, 2, 128 },505 /* 48k rate */506 { 12000000, 48000, 1, 1, 7, 1680, 7, 2, 128 },507 { 12288000, 48000, 1, 1, 7, 0000, 7, 2, 128 },508 { 24576000, 48000, 1, 1, 3, 5000, 7, 2, 128 }, /* With PLL */509 { 24576000, 48000, 0, 0, 0, 0000, 2, 2, 128 }, /* Without PLL */510 /* 88.2k rate */511 { 12000000, 88200, 1, 1, 7, 5264, 4, 4, 64 },512 /* 96k rate */513 { 12000000, 96000, 1, 1, 8, 1920, 4, 4, 64 },514};515 516static int adc3xxx_get_divs(struct device *dev, int mclk, int rate, int pll_mode)517{518 int i;519 520 dev_dbg(dev, "mclk = %d, rate = %d, clock mode %u\n",521 mclk, rate, pll_mode);522 for (i = 0; i < ARRAY_SIZE(adc3xxx_divs); i++) {523 const struct adc3xxx_rate_divs *mode = &adc3xxx_divs[i];524 525 /* Skip this entry if it doesn't fulfill the intended clock526 * mode requirement. We consider anything besides the two527 * modes below to be the same as ADC3XXX_PLL_AUTO.528 */529 if ((pll_mode == ADC3XXX_PLL_BYPASS && mode->pll_p) ||530 (pll_mode == ADC3XXX_PLL_ENABLE && !mode->pll_p))531 continue;532 533 if (mode->rate == rate && mode->mclk == mclk)534 return i;535 }536 537 dev_info(dev, "Master clock rate %d and sample rate %d is not supported\n",538 mclk, rate);539 return -EINVAL;540}541 542static int adc3xxx_pll_delay(struct snd_soc_dapm_widget *w,543 struct snd_kcontrol *kcontrol, int event)544{545 /* 10msec delay needed after PLL power-up to allow546 * PLL and dividers to stabilize (datasheet p13).547 */548 usleep_range(10000, 20000);549 550 return 0;551}552 553static int adc3xxx_coefficient_info(struct snd_kcontrol *kcontrol,554 struct snd_ctl_elem_info *uinfo)555{556 int numcoeff = kcontrol->private_value >> 16;557 558 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;559 uinfo->count = numcoeff;560 uinfo->value.integer.min = 0;561 uinfo->value.integer.max = 0xffff; /* all coefficients are 16 bit */562 return 0;563}564 565static int adc3xxx_coefficient_get(struct snd_kcontrol *kcontrol,566 struct snd_ctl_elem_value *ucontrol)567{568 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);569 int numcoeff = kcontrol->private_value >> 16;570 int reg = kcontrol->private_value & 0xffff;571 int index = 0;572 573 for (index = 0; index < numcoeff; index++) {574 unsigned int value_msb, value_lsb, value;575 576 value_msb = snd_soc_component_read(component, reg++);577 if ((int)value_msb < 0)578 return (int)value_msb;579 580 value_lsb = snd_soc_component_read(component, reg++);581 if ((int)value_lsb < 0)582 return (int)value_lsb;583 584 value = (value_msb << 8) | value_lsb;585 ucontrol->value.integer.value[index] = value;586 }587 588 return 0;589}590 591static int adc3xxx_coefficient_put(struct snd_kcontrol *kcontrol,592 struct snd_ctl_elem_value *ucontrol)593{594 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);595 int numcoeff = kcontrol->private_value >> 16;596 int reg = kcontrol->private_value & 0xffff;597 int index = 0;598 int ret;599 600 for (index = 0; index < numcoeff; index++) {601 unsigned int value = ucontrol->value.integer.value[index];602 unsigned int value_msb = (value >> 8) & 0xff;603 unsigned int value_lsb = value & 0xff;604 605 ret = snd_soc_component_write(component, reg++, value_msb);606 if (ret)607 return ret;608 609 ret = snd_soc_component_write(component, reg++, value_lsb);610 if (ret)611 return ret;612 }613 614 return 0;615}616 617/* All on-chip filters have coefficients which are expressed in terms of618 * 16 bit values, so represent them as strings of 16-bit integers.619 */620#define TI_COEFFICIENTS(xname, reg, numcoeffs) { \621 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \622 .name = xname, \623 .info = adc3xxx_coefficient_info, \624 .get = adc3xxx_coefficient_get,\625 .put = adc3xxx_coefficient_put, \626 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, \627 .private_value = reg | (numcoeffs << 16) \628}629 630static const char * const adc_softstepping_text[] = { "1 step", "2 step", "off" };631static SOC_ENUM_SINGLE_DECL(adc_softstepping_enum, ADC3XXX_ADC_DIGITAL, 0,632 adc_softstepping_text);633 634static const char * const multiplier_text[] = { "1", "2", "4", "8", "16", "32", "64", "128" };635static SOC_ENUM_SINGLE_DECL(left_agc_attack_mult_enum,636 ADC3XXX_LEFT_CHN_AGC_4, 0, multiplier_text);637static SOC_ENUM_SINGLE_DECL(right_agc_attack_mult_enum,638 ADC3XXX_RIGHT_CHN_AGC_4, 0, multiplier_text);639static SOC_ENUM_SINGLE_DECL(left_agc_decay_mult_enum,640 ADC3XXX_LEFT_CHN_AGC_5, 0, multiplier_text);641static SOC_ENUM_SINGLE_DECL(right_agc_decay_mult_enum,642 ADC3XXX_RIGHT_CHN_AGC_5, 0, multiplier_text);643 644static const char * const dither_dc_offset_text[] = {645 "0mV", "15mV", "30mV", "45mV", "60mV", "75mV", "90mV", "105mV",646 "-15mV", "-30mV", "-45mV", "-60mV", "-75mV", "-90mV", "-105mV"647};648static const unsigned int dither_dc_offset_values[] = {649 0, 1, 2, 3, 4, 5, 6, 7, 9, 10, 11, 12, 13, 14, 15650};651static SOC_VALUE_ENUM_DOUBLE_DECL(dither_dc_offset_enum,652 ADC3XXX_DITHER_CTRL,653 4, 0, 0xf, dither_dc_offset_text,654 dither_dc_offset_values);655 656static const DECLARE_TLV_DB_SCALE(pga_tlv, 0, 50, 0);657static const DECLARE_TLV_DB_SCALE(adc_tlv, -1200, 50, 0);658static const DECLARE_TLV_DB_SCALE(adc_fine_tlv, -40, 10, 0);659/* AGC target: 8 values: -5.5, -8, -10, -12, -14, -17, -20, -24 dB */660/* It would be nice to declare these in the order above, but empirically661 * TLV_DB_SCALE_ITEM doesn't take lightly to the increment (second) parameter662 * being negative, despite there being examples to the contrary in other663 * drivers. So declare these in the order from lowest to highest, and664 * set the invert flag in the SOC_DOUBLE_R_TLV declaration instead.665 */666static const DECLARE_TLV_DB_RANGE(agc_target_tlv,667 0, 0, TLV_DB_SCALE_ITEM(-2400, 0, 0),668 1, 3, TLV_DB_SCALE_ITEM(-2000, 300, 0),669 4, 6, TLV_DB_SCALE_ITEM(-1200, 200, 0),670 7, 7, TLV_DB_SCALE_ITEM(-550, 0, 0));671/* Since the 'disabled' value (mute) is at the highest value in the dB672 * range (i.e. just before -32 dB) rather than the lowest, we need to resort673 * to using a TLV_DB_RANGE in order to get the mute value in the right place.674 */675static const DECLARE_TLV_DB_RANGE(agc_thresh_tlv,676 0, 30, TLV_DB_SCALE_ITEM(-9000, 200, 0),677 31, 31, TLV_DB_SCALE_ITEM(0, 0, 1)); /* disabled = mute */678/* AGC hysteresis: 4 values: 1, 2, 4 dB, disabled (= mute) */679static const DECLARE_TLV_DB_RANGE(agc_hysteresis_tlv,680 0, 1, TLV_DB_SCALE_ITEM(100, 100, 0),681 2, 2, TLV_DB_SCALE_ITEM(400, 0, 0),682 3, 3, TLV_DB_SCALE_ITEM(0, 0, 1)); /* disabled = mute */683static const DECLARE_TLV_DB_SCALE(agc_max_tlv, 0, 50, 0);684/* Input attenuation: -6 dB or 0 dB */685static const DECLARE_TLV_DB_SCALE(input_attenuation_tlv, -600, 600, 0);686 687static const struct snd_kcontrol_new adc3xxx_snd_controls[] = {688 SOC_DOUBLE_R_TLV("PGA Capture Volume", ADC3XXX_LEFT_APGA_CTRL,689 ADC3XXX_RIGHT_APGA_CTRL, 0, 80, 0, pga_tlv),690 SOC_DOUBLE("PGA Capture Switch", ADC3XXX_ADC_FGA, 7, 3, 1, 1),691 SOC_DOUBLE_R("AGC Capture Switch", ADC3XXX_LEFT_CHN_AGC_1,692 ADC3XXX_RIGHT_CHN_AGC_1, 7, 1, 0),693 SOC_DOUBLE_R_TLV("AGC Target Level Capture Volume", ADC3XXX_LEFT_CHN_AGC_1,694 ADC3XXX_RIGHT_CHN_AGC_2, 4, 0x07, 1, agc_target_tlv),695 SOC_DOUBLE_R_TLV("AGC Noise Threshold Capture Volume", ADC3XXX_LEFT_CHN_AGC_2,696 ADC3XXX_RIGHT_CHN_AGC_2, 1, 0x1f, 1, agc_thresh_tlv),697 SOC_DOUBLE_R_TLV("AGC Hysteresis Capture Volume", ADC3XXX_LEFT_CHN_AGC_2,698 ADC3XXX_RIGHT_CHN_AGC_2, 6, 3, 0, agc_hysteresis_tlv),699 SOC_DOUBLE_R("AGC Clip Stepping Capture Switch", ADC3XXX_LEFT_CHN_AGC_2,700 ADC3XXX_RIGHT_CHN_AGC_2, 0, 1, 0),701 /*702 * Oddly enough, the data sheet says the default value703 * for the left/right AGC maximum gain register field704 * (ADC3XXX_LEFT/RIGHT_CHN_AGC_3 bits 0..6) is 0x7f = 127705 * (verified empirically) even though this value (indeed, above706 * 0x50) is specified as 'Reserved. Do not use.' in the accompanying707 * table in the data sheet.708 */709 SOC_DOUBLE_R_TLV("AGC Maximum Capture Volume", ADC3XXX_LEFT_CHN_AGC_3,710 ADC3XXX_RIGHT_CHN_AGC_3, 0, 0x50, 0, agc_max_tlv),711 SOC_DOUBLE_R("AGC Attack Time", ADC3XXX_LEFT_CHN_AGC_4,712 ADC3XXX_RIGHT_CHN_AGC_4, 3, 0x1f, 0),713 /* Would like to have the multipliers as LR pairs, but there is714 * no SOC_ENUM_foo which accepts two values in separate registers.715 */716 SOC_ENUM("AGC Left Attack Time Multiplier", left_agc_attack_mult_enum),717 SOC_ENUM("AGC Right Attack Time Multiplier", right_agc_attack_mult_enum),718 SOC_DOUBLE_R("AGC Decay Time", ADC3XXX_LEFT_CHN_AGC_5,719 ADC3XXX_RIGHT_CHN_AGC_5, 3, 0x1f, 0),720 SOC_ENUM("AGC Left Decay Time Multiplier", left_agc_decay_mult_enum),721 SOC_ENUM("AGC Right Decay Time Multiplier", right_agc_decay_mult_enum),722 SOC_DOUBLE_R("AGC Noise Debounce", ADC3XXX_LEFT_CHN_AGC_6,723 ADC3XXX_RIGHT_CHN_AGC_6, 0, 0x1f, 0),724 SOC_DOUBLE_R("AGC Signal Debounce", ADC3XXX_LEFT_CHN_AGC_7,725 ADC3XXX_RIGHT_CHN_AGC_7, 0, 0x0f, 0),726 /* Read only register */727 SOC_DOUBLE_R_S_TLV("AGC Applied Capture Volume", ADC3XXX_LEFT_AGC_GAIN,728 ADC3XXX_RIGHT_AGC_GAIN, 0, -24, 40, 6, 0, adc_tlv),729 /* ADC soft stepping */730 SOC_ENUM("ADC Soft Stepping", adc_softstepping_enum),731 /* Left/Right Input attenuation */732 SOC_SINGLE_TLV("Left Input IN_1L Capture Volume",733 ADC3XXX_LEFT_PGA_SEL_1, 0, 1, 1, input_attenuation_tlv),734 SOC_SINGLE_TLV("Left Input IN_2L Capture Volume",735 ADC3XXX_LEFT_PGA_SEL_1, 2, 1, 1, input_attenuation_tlv),736 SOC_SINGLE_TLV("Left Input IN_3L Capture Volume",737 ADC3XXX_LEFT_PGA_SEL_1, 4, 1, 1, input_attenuation_tlv),738 SOC_SINGLE_TLV("Left Input IN_1R Capture Volume",739 ADC3XXX_LEFT_PGA_SEL_2, 0, 1, 1, input_attenuation_tlv),740 SOC_SINGLE_TLV("Left Input DIF_2L_3L Capture Volume",741 ADC3XXX_LEFT_PGA_SEL_1, 6, 1, 1, input_attenuation_tlv),742 SOC_SINGLE_TLV("Left Input DIF_1L_1R Capture Volume",743 ADC3XXX_LEFT_PGA_SEL_2, 4, 1, 1, input_attenuation_tlv),744 SOC_SINGLE_TLV("Left Input DIF_2R_3R Capture Volume",745 ADC3XXX_LEFT_PGA_SEL_2, 2, 1, 1, input_attenuation_tlv),746 SOC_SINGLE_TLV("Right Input IN_1R Capture Volume",747 ADC3XXX_RIGHT_PGA_SEL_1, 0, 1, 1, input_attenuation_tlv),748 SOC_SINGLE_TLV("Right Input IN_2R Capture Volume",749 ADC3XXX_RIGHT_PGA_SEL_1, 2, 1, 1, input_attenuation_tlv),750 SOC_SINGLE_TLV("Right Input IN_3R Capture Volume",751 ADC3XXX_RIGHT_PGA_SEL_1, 4, 1, 1, input_attenuation_tlv),752 SOC_SINGLE_TLV("Right Input IN_1L Capture Volume",753 ADC3XXX_RIGHT_PGA_SEL_2, 0, 1, 1, input_attenuation_tlv),754 SOC_SINGLE_TLV("Right Input DIF_2R_3R Capture Volume",755 ADC3XXX_RIGHT_PGA_SEL_1, 6, 1, 1, input_attenuation_tlv),756 SOC_SINGLE_TLV("Right Input DIF_1L_1R Capture Volume",757 ADC3XXX_RIGHT_PGA_SEL_2, 4, 1, 1, input_attenuation_tlv),758 SOC_SINGLE_TLV("Right Input DIF_2L_3L Capture Volume",759 ADC3XXX_RIGHT_PGA_SEL_2, 2, 1, 1, input_attenuation_tlv),760 SOC_DOUBLE_R_S_TLV("ADC Volume Control Capture Volume", ADC3XXX_LADC_VOL,761 ADC3XXX_RADC_VOL, 0, -24, 40, 6, 0, adc_tlv),762 /* Empirically, the following doesn't work the way it's supposed763 * to. Values 0, -0.1, -0.2 and -0.3 dB result in the same level, and764 * -0.4 dB drops about 0.12 dB on a specific chip.765 */766 SOC_DOUBLE_TLV("ADC Fine Volume Control Capture Volume", ADC3XXX_ADC_FGA,767 4, 0, 4, 1, adc_fine_tlv),768 SOC_SINGLE("Left ADC Unselected CM Bias Capture Switch",769 ADC3XXX_LEFT_PGA_SEL_2, 6, 1, 0),770 SOC_SINGLE("Right ADC Unselected CM Bias Capture Switch",771 ADC3XXX_RIGHT_PGA_SEL_2, 6, 1, 0),772 SOC_ENUM("Dither Control DC Offset", dither_dc_offset_enum),773 774 /* Coefficient memory for miniDSP. */775 /* For the default PRB_R1 processing block, the only available776 * filter is the first order IIR.777 */778 779 TI_COEFFICIENTS("Left ADC IIR Coefficients N0 N1 D1",780 ADC3XXX_LEFT_ADC_IIR_COEFF_N0_MSB, 3),781 782 TI_COEFFICIENTS("Right ADC IIR Coefficients N0 N1 D1",783 ADC3XXX_RIGHT_ADC_IIR_COEFF_N0_MSB, 3),784};785 786/* Left input selection, Single Ended inputs and Differential inputs */787static const struct snd_kcontrol_new left_input_mixer_controls[] = {788 SOC_DAPM_SINGLE("IN_1L Capture Switch",789 ADC3XXX_LEFT_PGA_SEL_1, 1, 0x1, 1),790 SOC_DAPM_SINGLE("IN_2L Capture Switch",791 ADC3XXX_LEFT_PGA_SEL_1, 3, 0x1, 1),792 SOC_DAPM_SINGLE("IN_3L Capture Switch",793 ADC3XXX_LEFT_PGA_SEL_1, 5, 0x1, 1),794 SOC_DAPM_SINGLE("DIF_2L_3L Capture Switch",795 ADC3XXX_LEFT_PGA_SEL_1, 7, 0x1, 1),796 SOC_DAPM_SINGLE("DIF_1L_1R Capture Switch",797 ADC3XXX_LEFT_PGA_SEL_2, 5, 0x1, 1),798 SOC_DAPM_SINGLE("DIF_2R_3R Capture Switch",799 ADC3XXX_LEFT_PGA_SEL_2, 3, 0x1, 1),800 SOC_DAPM_SINGLE("IN_1R Capture Switch",801 ADC3XXX_LEFT_PGA_SEL_2, 1, 0x1, 1),802};803 804/* Right input selection, Single Ended inputs and Differential inputs */805static const struct snd_kcontrol_new right_input_mixer_controls[] = {806 SOC_DAPM_SINGLE("IN_1R Capture Switch",807 ADC3XXX_RIGHT_PGA_SEL_1, 1, 0x1, 1),808 SOC_DAPM_SINGLE("IN_2R Capture Switch",809 ADC3XXX_RIGHT_PGA_SEL_1, 3, 0x1, 1),810 SOC_DAPM_SINGLE("IN_3R Capture Switch",811 ADC3XXX_RIGHT_PGA_SEL_1, 5, 0x1, 1),812 SOC_DAPM_SINGLE("DIF_2R_3R Capture Switch",813 ADC3XXX_RIGHT_PGA_SEL_1, 7, 0x1, 1),814 SOC_DAPM_SINGLE("DIF_1L_1R Capture Switch",815 ADC3XXX_RIGHT_PGA_SEL_2, 5, 0x1, 1),816 SOC_DAPM_SINGLE("DIF_2L_3L Capture Switch",817 ADC3XXX_RIGHT_PGA_SEL_2, 3, 0x1, 1),818 SOC_DAPM_SINGLE("IN_1L Capture Switch",819 ADC3XXX_RIGHT_PGA_SEL_2, 1, 0x1, 1),820};821 822/* Left Digital Mic input for left ADC */823static const struct snd_kcontrol_new left_input_dmic_controls[] = {824 SOC_DAPM_SINGLE("Left ADC Capture Switch",825 ADC3XXX_ADC_DIGITAL, 3, 0x1, 0),826};827 828/* Right Digital Mic input for Right ADC */829static const struct snd_kcontrol_new right_input_dmic_controls[] = {830 SOC_DAPM_SINGLE("Right ADC Capture Switch",831 ADC3XXX_ADC_DIGITAL, 2, 0x1, 0),832};833 834/* DAPM widgets */835static const struct snd_soc_dapm_widget adc3xxx_dapm_widgets[] = {836 837 /* Left Input Selection */838 SND_SOC_DAPM_MIXER("Left Input", SND_SOC_NOPM, 0, 0,839 &left_input_mixer_controls[0],840 ARRAY_SIZE(left_input_mixer_controls)),841 /* Right Input Selection */842 SND_SOC_DAPM_MIXER("Right Input", SND_SOC_NOPM, 0, 0,843 &right_input_mixer_controls[0],844 ARRAY_SIZE(right_input_mixer_controls)),845 /* PGA selection */846 SND_SOC_DAPM_PGA("Left PGA", ADC3XXX_LEFT_APGA_CTRL, 7, 1, NULL, 0),847 SND_SOC_DAPM_PGA("Right PGA", ADC3XXX_RIGHT_APGA_CTRL, 7, 1, NULL, 0),848 849 /* Digital Microphone Input Control for Left/Right ADC */850 SND_SOC_DAPM_MIXER("Left DMic Input", SND_SOC_NOPM, 0, 0,851 &left_input_dmic_controls[0],852 ARRAY_SIZE(left_input_dmic_controls)),853 SND_SOC_DAPM_MIXER("Right DMic Input", SND_SOC_NOPM, 0, 0,854 &right_input_dmic_controls[0],855 ARRAY_SIZE(right_input_dmic_controls)),856 857 /* Left/Right ADC */858 SND_SOC_DAPM_ADC("Left ADC", "Left Capture", ADC3XXX_ADC_DIGITAL, 7, 0),859 SND_SOC_DAPM_ADC("Right ADC", "Right Capture", ADC3XXX_ADC_DIGITAL, 6, 0),860 861 /* Inputs */862 SND_SOC_DAPM_INPUT("IN_1L"),863 SND_SOC_DAPM_INPUT("IN_1R"),864 SND_SOC_DAPM_INPUT("IN_2L"),865 SND_SOC_DAPM_INPUT("IN_2R"),866 SND_SOC_DAPM_INPUT("IN_3L"),867 SND_SOC_DAPM_INPUT("IN_3R"),868 SND_SOC_DAPM_INPUT("DIFL_1L_1R"),869 SND_SOC_DAPM_INPUT("DIFL_2L_3L"),870 SND_SOC_DAPM_INPUT("DIFL_2R_3R"),871 SND_SOC_DAPM_INPUT("DIFR_1L_1R"),872 SND_SOC_DAPM_INPUT("DIFR_2L_3L"),873 SND_SOC_DAPM_INPUT("DIFR_2R_3R"),874 SND_SOC_DAPM_INPUT("DMic_L"),875 SND_SOC_DAPM_INPUT("DMic_R"),876 877 /* Digital audio interface output */878 SND_SOC_DAPM_AIF_OUT("AIF_OUT", "Capture", 0, SND_SOC_NOPM, 0, 0),879 880 /* Clocks */881 SND_SOC_DAPM_SUPPLY("PLL_CLK", ADC3XXX_PLL_PROG_PR, ADC3XXX_ENABLE_PLL_SHIFT,882 0, adc3xxx_pll_delay, SND_SOC_DAPM_POST_PMU),883 884 SND_SOC_DAPM_SUPPLY("ADC_CLK", ADC3XXX_ADC_NADC, ADC3XXX_ENABLE_NADC_SHIFT,885 0, NULL, 0),886 SND_SOC_DAPM_SUPPLY("ADC_MOD_CLK", ADC3XXX_ADC_MADC, ADC3XXX_ENABLE_MADC_SHIFT,887 0, NULL, 0),888 889 /* This refers to the generated BCLK in master mode. */890 SND_SOC_DAPM_SUPPLY("BCLK", ADC3XXX_BCLK_N_DIV, ADC3XXX_ENABLE_BCLK_SHIFT,891 0, NULL, 0),892};893 894static const struct snd_soc_dapm_route adc3xxx_intercon[] = {895 /* Left input selection from switches */896 { "Left Input", "IN_1L Capture Switch", "IN_1L" },897 { "Left Input", "IN_2L Capture Switch", "IN_2L" },898 { "Left Input", "IN_3L Capture Switch", "IN_3L" },899 { "Left Input", "DIF_2L_3L Capture Switch", "DIFL_2L_3L" },900 { "Left Input", "DIF_1L_1R Capture Switch", "DIFL_1L_1R" },901 { "Left Input", "DIF_2R_3R Capture Switch", "DIFL_2R_3R" },902 { "Left Input", "IN_1R Capture Switch", "IN_1R" },903 904 /* Left input selection to left PGA */905 { "Left PGA", NULL, "Left Input" },906 907 /* Left PGA to left ADC */908 { "Left ADC", NULL, "Left PGA" },909 910 /* Right input selection from switches */911 { "Right Input", "IN_1R Capture Switch", "IN_1R" },912 { "Right Input", "IN_2R Capture Switch", "IN_2R" },913 { "Right Input", "IN_3R Capture Switch", "IN_3R" },914 { "Right Input", "DIF_2R_3R Capture Switch", "DIFR_2R_3R" },915 { "Right Input", "DIF_1L_1R Capture Switch", "DIFR_1L_1R" },916 { "Right Input", "DIF_2L_3L Capture Switch", "DIFR_2L_3L" },917 { "Right Input", "IN_1L Capture Switch", "IN_1L" },918 919 /* Right input selection to right PGA */920 { "Right PGA", NULL, "Right Input" },921 922 /* Right PGA to right ADC */923 { "Right ADC", NULL, "Right PGA" },924 925 /* Left DMic Input selection from switch */926 { "Left DMic Input", "Left ADC Capture Switch", "DMic_L" },927 928 /* Left DMic to left ADC */929 { "Left ADC", NULL, "Left DMic Input" },930 931 /* Right DMic Input selection from switch */932 { "Right DMic Input", "Right ADC Capture Switch", "DMic_R" },933 934 /* Right DMic to right ADC */935 { "Right ADC", NULL, "Right DMic Input" },936 937 /* ADC to AIF output */938 { "AIF_OUT", NULL, "Left ADC" },939 { "AIF_OUT", NULL, "Right ADC" },940 941 /* Clocking */942 { "ADC_MOD_CLK", NULL, "ADC_CLK" },943 { "Left ADC", NULL, "ADC_MOD_CLK" },944 { "Right ADC", NULL, "ADC_MOD_CLK" },945 946 { "BCLK", NULL, "ADC_CLK" },947};948 949static const struct snd_soc_dapm_route adc3xxx_pll_intercon[] = {950 { "ADC_CLK", NULL, "PLL_CLK" },951};952 953static const struct snd_soc_dapm_route adc3xxx_bclk_out_intercon[] = {954 { "AIF_OUT", NULL, "BCLK" }955};956 957static int adc3xxx_gpio_request(struct gpio_chip *chip, unsigned int offset)958{959 struct adc3xxx *adc3xxx = gpiochip_get_data(chip);960 961 if (offset >= ADC3XXX_GPIOS_MAX)962 return -EINVAL;963 964 if (offset >= 0 && offset < ADC3XXX_GPIO_PINS) {965 /* GPIO1 is offset 0, GPIO2 is offset 1 */966 /* We check here that the GPIO pins are either not configured967 * in the DT, or that they purposely are set as outputs.968 * (Input mode not yet implemented).969 */970 if (adc3xxx->gpio_cfg[offset] != 0 &&971 adc3xxx->gpio_cfg[offset] != ADC3XXX_GPIO_GPO + 1)972 return -EINVAL;973 } else if (offset >= ADC3XXX_GPIO_PINS && offset < ADC3XXX_GPIOS_MAX) {974 /* MICBIAS1 is offset 2, MICBIAS2 is offset 3 */975 /* We check here if the MICBIAS pins are in fact configured976 * as GPOs.977 */978 if (!adc3xxx->micbias_gpo[offset - ADC3XXX_GPIO_PINS])979 return -EINVAL;980 }981 982 return 0;983}984 985static int adc3xxx_gpio_direction_out(struct gpio_chip *chip,986 unsigned int offset, int value)987{988 struct adc3xxx *adc3xxx = gpiochip_get_data(chip);989 990 /* For the MICBIAS pins, they are by definition outputs. */991 if (offset >= ADC3XXX_GPIO_PINS) {992 unsigned int vg;993 unsigned int micbias = offset - ADC3XXX_GPIO_PINS;994 995 if (value)996 vg = adc3xxx->micbias_vg[micbias];997 else998 vg = ADC3XXX_MICBIAS_OFF;999 return regmap_update_bits(adc3xxx->regmap,1000 ADC3XXX_MICBIAS_CTRL,1001 ADC3XXX_MICBIAS_MASK << adc3xxx_micbias_shift[micbias],1002 vg << adc3xxx_micbias_shift[micbias]);1003 }1004 1005 /* Set GPIO output function. */1006 return regmap_update_bits(adc3xxx->regmap,1007 adc3xxx_gpio_ctrl_reg[offset],1008 ADC3XXX_GPIO_CTRL_CFG_MASK |1009 ADC3XXX_GPIO_CTRL_OUTPUT_CTRL_MASK,1010 ADC3XXX_GPIO_GPO << ADC3XXX_GPIO_CTRL_CFG_SHIFT |1011 !!value << ADC3XXX_GPIO_CTRL_OUTPUT_CTRL_SHIFT);1012}1013 1014/* With only GPIO outputs configured, we never get the .direction_out call,1015 * so we set the output mode and output value in the same call. Hence1016 * .set in practice does the same thing as .direction_out .1017 */1018static void adc3xxx_gpio_set(struct gpio_chip *chip, unsigned int offset,1019 int value)1020{1021 (void) adc3xxx_gpio_direction_out(chip, offset, value);1022}1023 1024/* Even though we only support GPIO output for now, some GPIO clients1025 * want to read the current pin state using the .get callback.1026 */1027static int adc3xxx_gpio_get(struct gpio_chip *chip, unsigned int offset)1028{1029 struct adc3xxx *adc3xxx = gpiochip_get_data(chip);1030 unsigned int regval;1031 int ret;1032 1033 /* We only allow output pins, so just read the value prevously set. */1034 if (offset >= ADC3XXX_GPIO_PINS) {1035 /* MICBIAS pins */1036 unsigned int micbias = offset - ADC3XXX_GPIO_PINS;1037 1038 ret = regmap_read(adc3xxx->regmap, ADC3XXX_MICBIAS_CTRL, ®val);1039 if (ret)1040 return ret;1041 return ((regval >> adc3xxx_micbias_shift[micbias]) & ADC3XXX_MICBIAS_MASK) !=1042 ADC3XXX_MICBIAS_OFF;1043 }1044 ret = regmap_read(adc3xxx->regmap, adc3xxx_gpio_ctrl_reg[offset], ®val);1045 if (ret)1046 return ret;1047 return !!(regval & ADC3XXX_GPIO_CTRL_OUTPUT_CTRL_MASK);1048}1049 1050static const struct gpio_chip adc3xxx_gpio_chip = {1051 .label = "adc3xxx",1052 .owner = THIS_MODULE,1053 .request = adc3xxx_gpio_request,1054 .direction_output = adc3xxx_gpio_direction_out,1055 .set = adc3xxx_gpio_set,1056 .get = adc3xxx_gpio_get,1057 .can_sleep = 1,1058};1059 1060static void adc3xxx_free_gpio(struct adc3xxx *adc3xxx)1061{1062#ifdef CONFIG_GPIOLIB1063 gpiochip_remove(&adc3xxx->gpio_chip);1064#endif1065}1066 1067static void adc3xxx_init_gpio(struct adc3xxx *adc3xxx)1068{1069 int gpio, micbias;1070 int ret;1071 1072 adc3xxx->gpio_chip = adc3xxx_gpio_chip;1073 adc3xxx->gpio_chip.ngpio = ADC3XXX_GPIOS_MAX;1074 adc3xxx->gpio_chip.parent = adc3xxx->dev;1075 adc3xxx->gpio_chip.base = -1;1076 1077 ret = gpiochip_add_data(&adc3xxx->gpio_chip, adc3xxx);1078 if (ret)1079 dev_err(adc3xxx->dev, "Failed to add gpios: %d\n", ret);1080 1081 /* Set up potential GPIO configuration from the devicetree.1082 * This allows us to set up things which are not software1083 * controllable GPIOs, such as PDM microphone I/O,1084 */1085 for (gpio = 0; gpio < ADC3XXX_GPIO_PINS; gpio++) {1086 unsigned int cfg = adc3xxx->gpio_cfg[gpio];1087 1088 if (cfg) {1089 cfg--; /* actual value to use is stored +1 */1090 regmap_update_bits(adc3xxx->regmap,1091 adc3xxx_gpio_ctrl_reg[gpio],1092 ADC3XXX_GPIO_CTRL_CFG_MASK,1093 cfg << ADC3XXX_GPIO_CTRL_CFG_SHIFT);1094 }1095 }1096 1097 /* Set up micbias voltage. */1098 /* If pin is configured as GPO, set off initially. */1099 for (micbias = 0; micbias < ADC3XXX_MICBIAS_PINS; micbias++) {1100 unsigned int vg;1101 1102 if (adc3xxx->micbias_gpo[micbias])1103 vg = ADC3XXX_MICBIAS_OFF;1104 else1105 vg = adc3xxx->micbias_vg[micbias];1106 1107 regmap_update_bits(adc3xxx->regmap,1108 ADC3XXX_MICBIAS_CTRL,1109 ADC3XXX_MICBIAS_MASK << adc3xxx_micbias_shift[micbias],1110 vg << adc3xxx_micbias_shift[micbias]);1111 }1112}1113 1114static int adc3xxx_parse_dt_gpio(struct adc3xxx *adc3xxx,1115 const char *propname, unsigned int *cfg)1116{1117 struct device *dev = adc3xxx->dev;1118 struct device_node *np = dev->of_node;1119 unsigned int val;1120 1121 if (!of_property_read_u32(np, propname, &val)) {1122 if (val & ~15 || val == 7 || val >= 11) {1123 dev_err(dev, "Invalid property value for '%s'\n", propname);1124 return -EINVAL;1125 }1126 if (val == ADC3XXX_GPIO_GPI)1127 dev_warn(dev, "GPIO Input read not yet implemented\n");1128 *cfg = val + 1; /* 0 => not set up, all others shifted +1 */1129 }1130 return 0;1131}1132 1133static int adc3xxx_parse_dt_micbias_gpo(struct adc3xxx *adc3xxx,1134 const char *propname,1135 unsigned int *cfg)1136{1137 struct device *dev = adc3xxx->dev;1138 struct device_node *np = dev->of_node;1139 1140 *cfg = of_property_read_bool(np, propname);1141 return 0;1142}1143 1144static int adc3xxx_parse_dt_micbias_vg(struct adc3xxx *adc3xxx,1145 const char *propname, unsigned int *vg)1146{1147 struct device *dev = adc3xxx->dev;1148 struct device_node *np = dev->of_node;1149 unsigned int val;1150 1151 if (!of_property_read_u32(np, propname, &val)) {1152 if (val > ADC3XXX_MICBIAS_AVDD) {1153 dev_err(dev, "Invalid property value for '%s'\n", propname);1154 return -EINVAL;1155 }1156 *vg = val;1157 }1158 return 0;1159}1160 1161static int adc3xxx_parse_pll_mode(uint32_t val, unsigned int *pll_mode)1162{1163 if (val != ADC3XXX_PLL_ENABLE && val != ADC3XXX_PLL_BYPASS &&1164 val != ADC3XXX_PLL_AUTO)1165 return -EINVAL;1166 1167 *pll_mode = val;1168 1169 return 0;1170}1171 1172static void adc3xxx_setup_pll(struct snd_soc_component *component,1173 int div_entry)1174{1175 int i = div_entry;1176 1177 /* P & R values */1178 snd_soc_component_write(component, ADC3XXX_PLL_PROG_PR,1179 (adc3xxx_divs[i].pll_p << ADC3XXX_PLLP_SHIFT) |1180 (adc3xxx_divs[i].pll_r << ADC3XXX_PLLR_SHIFT));1181 /* J value */1182 snd_soc_component_write(component, ADC3XXX_PLL_PROG_J,1183 adc3xxx_divs[i].pll_j & ADC3XXX_PLLJ_MASK);1184 /* D value */1185 snd_soc_component_write(component, ADC3XXX_PLL_PROG_D_LSB,1186 adc3xxx_divs[i].pll_d & ADC3XXX_PLLD_LSB_MASK);1187 snd_soc_component_write(component, ADC3XXX_PLL_PROG_D_MSB,1188 (adc3xxx_divs[i].pll_d >> 8) & ADC3XXX_PLLD_MSB_MASK);1189}1190 1191static int adc3xxx_hw_params(struct snd_pcm_substream *substream,1192 struct snd_pcm_hw_params *params,1193 struct snd_soc_dai *dai)1194{1195 struct snd_soc_component *component = dai->component;1196 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(dai->component);1197 struct adc3xxx *adc3xxx = snd_soc_component_get_drvdata(component);1198 int i, width = 16;1199 u8 iface_len, bdiv;1200 1201 i = adc3xxx_get_divs(component->dev, adc3xxx->sysclk,1202 params_rate(params), adc3xxx->pll_mode);1203 1204 if (i < 0)1205 return i;1206 1207 /* select data word length */1208 switch (params_width(params)) {1209 case 16:1210 iface_len = ADC3XXX_IFACE_16BITS;1211 width = 16;1212 break;1213 case 20:1214 iface_len = ADC3XXX_IFACE_20BITS;1215 width = 20;1216 break;1217 case 24:1218 iface_len = ADC3XXX_IFACE_24BITS;1219 width = 24;1220 break;1221 case 32:1222 iface_len = ADC3XXX_IFACE_32BITS;1223 width = 32;1224 break;1225 default:1226 dev_err(component->dev, "Unsupported serial data format\n");1227 return -EINVAL;1228 }1229 snd_soc_component_update_bits(component, ADC3XXX_INTERFACE_CTRL_1,1230 ADC3XXX_WLENGTH_MASK, iface_len);1231 if (adc3xxx_divs[i].pll_p) { /* If PLL used for this mode */1232 adc3xxx_setup_pll(component, i);1233 snd_soc_component_write(component, ADC3XXX_CLKGEN_MUX, ADC3XXX_USE_PLL);1234 if (!adc3xxx->use_pll) {1235 snd_soc_dapm_add_routes(dapm, adc3xxx_pll_intercon,1236 ARRAY_SIZE(adc3xxx_pll_intercon));1237 adc3xxx->use_pll = 1;1238 }1239 } else {1240 snd_soc_component_write(component, ADC3XXX_CLKGEN_MUX, ADC3XXX_NO_PLL);1241 if (adc3xxx->use_pll) {1242 snd_soc_dapm_del_routes(dapm, adc3xxx_pll_intercon,1243 ARRAY_SIZE(adc3xxx_pll_intercon));1244 adc3xxx->use_pll = 0;1245 }1246 }1247 1248 /* NADC */1249 snd_soc_component_update_bits(component, ADC3XXX_ADC_NADC,1250 ADC3XXX_NADC_MASK, adc3xxx_divs[i].nadc);1251 /* MADC */1252 snd_soc_component_update_bits(component, ADC3XXX_ADC_MADC,1253 ADC3XXX_MADC_MASK, adc3xxx_divs[i].madc);1254 /* AOSR */1255 snd_soc_component_update_bits(component, ADC3XXX_ADC_AOSR,1256 ADC3XXX_AOSR_MASK, adc3xxx_divs[i].aosr);1257 /* BDIV N Value */1258 /* BCLK is (by default) set up to be derived from ADC_CLK */1259 bdiv = (adc3xxx_divs[i].aosr * adc3xxx_divs[i].madc) / (2 * width);1260 snd_soc_component_update_bits(component, ADC3XXX_BCLK_N_DIV,1261 ADC3XXX_BDIV_MASK, bdiv);1262 1263 return 0;1264}1265 1266static const char *adc3xxx_pll_mode_text(int pll_mode)1267{1268 switch (pll_mode) {1269 case ADC3XXX_PLL_AUTO:1270 return "PLL auto";1271 case ADC3XXX_PLL_ENABLE:1272 return "PLL enable";1273 case ADC3XXX_PLL_BYPASS:1274 return "PLL bypass";1275 default:1276 break;1277 }1278 1279 return "PLL unknown";1280}1281 1282static int adc3xxx_set_dai_sysclk(struct snd_soc_dai *codec_dai,1283 int clk_id, unsigned int freq, int dir)1284{1285 struct snd_soc_component *component = codec_dai->component;1286 struct adc3xxx *adc3xxx = snd_soc_component_get_drvdata(component);1287 int ret;1288 1289 ret = adc3xxx_parse_pll_mode(clk_id, &adc3xxx->pll_mode);1290 if (ret < 0)1291 return ret;1292 1293 adc3xxx->sysclk = freq;1294 dev_dbg(component->dev, "Set sysclk to %u Hz, %s\n",1295 freq, adc3xxx_pll_mode_text(adc3xxx->pll_mode));1296 return 0;1297}1298 1299static int adc3xxx_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)1300{1301 struct snd_soc_component *component = codec_dai->component;1302 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);1303 struct adc3xxx *adc3xxx = snd_soc_component_get_drvdata(component);1304 u8 clkdir = 0, format = 0;1305 int master = 0;1306 int ret;1307 1308 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {1309 case SND_SOC_DAIFMT_CBP_CFP:1310 master = 1;1311 clkdir = ADC3XXX_BCLK_MASTER | ADC3XXX_WCLK_MASTER;1312 break;1313 case SND_SOC_DAIFMT_CBC_CFC:1314 master = 0;1315 break;1316 default:1317 dev_err(component->dev, "Invalid DAI clock setup\n");1318 return -EINVAL;1319 }1320 1321 /*1322 * match both interface format and signal polarities since they1323 * are fixed1324 */1325 switch (fmt & (SND_SOC_DAIFMT_FORMAT_MASK | SND_SOC_DAIFMT_INV_MASK)) {1326 case SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF:1327 format = ADC3XXX_FORMAT_I2S;1328 break;1329 case SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_IB_NF:1330 format = ADC3XXX_FORMAT_DSP;1331 break;1332 case SND_SOC_DAIFMT_DSP_B | SND_SOC_DAIFMT_IB_NF:1333 format = ADC3XXX_FORMAT_DSP;1334 break;1335 case SND_SOC_DAIFMT_RIGHT_J | SND_SOC_DAIFMT_NB_NF:1336 format = ADC3XXX_FORMAT_RJF;1337 break;1338 case SND_SOC_DAIFMT_LEFT_J | SND_SOC_DAIFMT_NB_NF:1339 format = ADC3XXX_FORMAT_LJF;1340 break;1341 default:1342 dev_err(component->dev, "Invalid DAI format\n");1343 return -EINVAL;1344 }1345 1346 /* Add/del route enabling BCLK output as applicable */1347 if (master && !adc3xxx->master)1348 snd_soc_dapm_add_routes(dapm, adc3xxx_bclk_out_intercon,1349 ARRAY_SIZE(adc3xxx_bclk_out_intercon));1350 else if (!master && adc3xxx->master)1351 snd_soc_dapm_del_routes(dapm, adc3xxx_bclk_out_intercon,1352 ARRAY_SIZE(adc3xxx_bclk_out_intercon));1353 adc3xxx->master = master;1354 1355 /* set clock direction and format */1356 ret = snd_soc_component_update_bits(component,1357 ADC3XXX_INTERFACE_CTRL_1,1358 ADC3XXX_CLKDIR_MASK | ADC3XXX_FORMAT_MASK,1359 clkdir | format);1360 if (ret < 0)1361 return ret;1362 return 0;1363}1364 1365static const struct snd_soc_dai_ops adc3xxx_dai_ops = {1366 .hw_params = adc3xxx_hw_params,1367 .set_sysclk = adc3xxx_set_dai_sysclk,1368 .set_fmt = adc3xxx_set_dai_fmt,1369};1370 1371static struct snd_soc_dai_driver adc3xxx_dai = {1372 .name = "tlv320adc3xxx-hifi",1373 .capture = {1374 .stream_name = "Capture",1375 .channels_min = 1,1376 .channels_max = 2,1377 .rates = ADC3XXX_RATES,1378 .formats = ADC3XXX_FORMATS,1379 },1380 .ops = &adc3xxx_dai_ops,1381};1382 1383static const struct snd_soc_component_driver soc_component_dev_adc3xxx = {1384 .controls = adc3xxx_snd_controls,1385 .num_controls = ARRAY_SIZE(adc3xxx_snd_controls),1386 .dapm_widgets = adc3xxx_dapm_widgets,1387 .num_dapm_widgets = ARRAY_SIZE(adc3xxx_dapm_widgets),1388 .dapm_routes = adc3xxx_intercon,1389 .num_dapm_routes = ARRAY_SIZE(adc3xxx_intercon),1390 .endianness = 1,1391};1392 1393static const struct i2c_device_id adc3xxx_i2c_id[] = {1394 { "tlv320adc3001", ADC3001 },1395 { "tlv320adc3101", ADC3101 },1396 {}1397};1398MODULE_DEVICE_TABLE(i2c, adc3xxx_i2c_id);1399 1400static int adc3xxx_i2c_probe(struct i2c_client *i2c)1401{1402 struct device *dev = &i2c->dev;1403 struct adc3xxx *adc3xxx = NULL;1404 const struct i2c_device_id *id;1405 int ret;1406 1407 adc3xxx = devm_kzalloc(dev, sizeof(struct adc3xxx), GFP_KERNEL);1408 if (!adc3xxx)1409 return -ENOMEM;1410 adc3xxx->dev = dev;1411 1412 adc3xxx->rst_pin = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);1413 if (IS_ERR(adc3xxx->rst_pin)) {1414 return dev_err_probe(dev, PTR_ERR(adc3xxx->rst_pin),1415 "Failed to request rst_pin\n");1416 }1417 1418 adc3xxx->mclk = devm_clk_get(dev, NULL);1419 if (IS_ERR(adc3xxx->mclk)) {1420 /*1421 * The chip itself supports running off the BCLK either1422 * directly or via the PLL, but the driver does not (yet), so1423 * having a specified mclk is required. Otherwise, we could1424 * use the lack of a clocks property to indicate when BCLK is1425 * intended as the clock source.1426 */1427 return dev_err_probe(dev, PTR_ERR(adc3xxx->mclk),1428 "Failed to acquire MCLK\n");1429 } else if (adc3xxx->mclk) {1430 ret = clk_prepare_enable(adc3xxx->mclk);1431 if (ret < 0)1432 return ret;1433 dev_dbg(dev, "Enabled MCLK, freq %lu Hz\n", clk_get_rate(adc3xxx->mclk));1434 }1435 1436 /* Configure mode for DMDIN/GPIO1 pin */1437 ret = adc3xxx_parse_dt_gpio(adc3xxx, "ti,dmdin-gpio1", &adc3xxx->gpio_cfg[0]);1438 if (ret < 0)1439 goto err_unprepare_mclk;1440 /* Configure mode for DMCLK/GPIO2 pin */1441 ret = adc3xxx_parse_dt_gpio(adc3xxx, "ti,dmclk-gpio2", &adc3xxx->gpio_cfg[1]);1442 if (ret < 0)1443 goto err_unprepare_mclk;1444 /* Configure mode for MICBIAS1: as Mic Bias output or GPO */1445 ret = adc3xxx_parse_dt_micbias_gpo(adc3xxx, "ti,micbias1-gpo", &adc3xxx->micbias_gpo[0]);1446 if (ret < 0)1447 goto err_unprepare_mclk;1448 /* Configure mode for MICBIAS2: as Mic Bias output or GPO */1449 ret = adc3xxx_parse_dt_micbias_gpo(adc3xxx, "ti,micbias2-gpo", &adc3xxx->micbias_gpo[1]);1450 if (ret < 0)1451 goto err_unprepare_mclk;1452 /* Configure voltage for MICBIAS1 pin (ON voltage when used as GPO) */1453 ret = adc3xxx_parse_dt_micbias_vg(adc3xxx, "ti,micbias1-vg", &adc3xxx->micbias_vg[0]);1454 if (ret < 0)1455 goto err_unprepare_mclk;1456 /* Configure voltage for MICBIAS2 pin (ON voltage when used as GPO) */1457 ret = adc3xxx_parse_dt_micbias_vg(adc3xxx, "ti,micbias2-vg", &adc3xxx->micbias_vg[1]);1458 if (ret < 0)1459 goto err_unprepare_mclk;1460 1461 adc3xxx->regmap = devm_regmap_init_i2c(i2c, &adc3xxx_regmap);1462 if (IS_ERR(adc3xxx->regmap)) {1463 ret = PTR_ERR(adc3xxx->regmap);1464 goto err_unprepare_mclk;1465 }1466 1467 i2c_set_clientdata(i2c, adc3xxx);1468 1469 id = i2c_match_id(adc3xxx_i2c_id, i2c);1470 adc3xxx->type = id->driver_data;1471 1472 /* Reset codec chip */1473 gpiod_set_value_cansleep(adc3xxx->rst_pin, 1);1474 usleep_range(2000, 100000); /* Requirement: > 10 ns (datasheet p13) */1475 gpiod_set_value_cansleep(adc3xxx->rst_pin, 0);1476 1477 /* Potentially set up pins used as GPIOs */1478 adc3xxx_init_gpio(adc3xxx);1479 1480 ret = snd_soc_register_component(dev,1481 &soc_component_dev_adc3xxx, &adc3xxx_dai, 1);1482 if (ret < 0) {1483 dev_err(dev, "Failed to register codec: %d\n", ret);1484 goto err_unprepare_mclk;1485 }1486 1487 return 0;1488 1489err_unprepare_mclk:1490 clk_disable_unprepare(adc3xxx->mclk);1491 return ret;1492}1493 1494static void adc3xxx_i2c_remove(struct i2c_client *client)1495{1496 struct adc3xxx *adc3xxx = i2c_get_clientdata(client);1497 1498 if (adc3xxx->mclk)1499 clk_disable_unprepare(adc3xxx->mclk);1500 adc3xxx_free_gpio(adc3xxx);1501 snd_soc_unregister_component(&client->dev);1502}1503 1504static const struct of_device_id tlv320adc3xxx_of_match[] = {1505 { .compatible = "ti,tlv320adc3001", },1506 { .compatible = "ti,tlv320adc3101", },1507 {},1508};1509MODULE_DEVICE_TABLE(of, tlv320adc3xxx_of_match);1510 1511static struct i2c_driver adc3xxx_i2c_driver = {1512 .driver = {1513 .name = "tlv320adc3xxx-codec",1514 .of_match_table = tlv320adc3xxx_of_match,1515 },1516 .probe = adc3xxx_i2c_probe,1517 .remove = adc3xxx_i2c_remove,1518 .id_table = adc3xxx_i2c_id,1519};1520 1521module_i2c_driver(adc3xxx_i2c_driver);1522 1523MODULE_DESCRIPTION("ASoC TLV320ADC3xxx codec driver");1524MODULE_AUTHOR("shahina.s@mistralsolutions.com");1525MODULE_LICENSE("GPL v2");1526