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1// SPDX-License-Identifier: GPL-2.02// TLV320ADCX140 Sound driver3// Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/4 5#ifndef _TLV320ADCX140_H6#define _TLV320ADCX140_H7 8#define ADCX140_RATES (SNDRV_PCM_RATE_44100 | \9 SNDRV_PCM_RATE_48000 | \10 SNDRV_PCM_RATE_96000 | \11 SNDRV_PCM_RATE_192000)12 13#define ADCX140_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \14 SNDRV_PCM_FMTBIT_S20_3LE | \15 SNDRV_PCM_FMTBIT_S24_3LE | \16 SNDRV_PCM_FMTBIT_S24_LE | \17 SNDRV_PCM_FMTBIT_S32_LE)18 19#define ADCX140_PAGE_SELECT 0x0020#define ADCX140_SW_RESET 0x0121#define ADCX140_SLEEP_CFG 0x0222#define ADCX140_SHDN_CFG 0x0523#define ADCX140_ASI_CFG0 0x0724#define ADCX140_ASI_CFG1 0x0825#define ADCX140_ASI_CFG2 0x0926#define ADCX140_ASI_CH1 0x0b27#define ADCX140_ASI_CH2 0x0c28#define ADCX140_ASI_CH3 0x0d29#define ADCX140_ASI_CH4 0x0e30#define ADCX140_ASI_CH5 0x0f31#define ADCX140_ASI_CH6 0x1032#define ADCX140_ASI_CH7 0x1133#define ADCX140_ASI_CH8 0x1234#define ADCX140_MST_CFG0 0x1335#define ADCX140_MST_CFG1 0x1436#define ADCX140_ASI_STS 0x1537#define ADCX140_CLK_SRC 0x1638#define ADCX140_PDMCLK_CFG 0x1f39#define ADCX140_PDM_CFG 0x2040#define ADCX140_GPIO_CFG0 0x2141#define ADCX140_GPO_CFG0 0x2242#define ADCX140_GPO_CFG1 0x2343#define ADCX140_GPO_CFG2 0x2444#define ADCX140_GPO_CFG3 0x2545#define ADCX140_GPO_VAL 0x2946#define ADCX140_GPIO_MON 0x2a47#define ADCX140_GPI_CFG0 0x2b48#define ADCX140_GPI_CFG1 0x2c49#define ADCX140_GPI_MON 0x2f50#define ADCX140_INT_CFG 0x3251#define ADCX140_INT_MASK0 0x3352#define ADCX140_INT_LTCH0 0x3653#define ADCX140_BIAS_CFG 0x3b54#define ADCX140_CH1_CFG0 0x3c55#define ADCX140_CH1_CFG1 0x3d56#define ADCX140_CH1_CFG2 0x3e57#define ADCX140_CH1_CFG3 0x3f58#define ADCX140_CH1_CFG4 0x4059#define ADCX140_CH2_CFG0 0x4160#define ADCX140_CH2_CFG1 0x4261#define ADCX140_CH2_CFG2 0x4362#define ADCX140_CH2_CFG3 0x4463#define ADCX140_CH2_CFG4 0x4564#define ADCX140_CH3_CFG0 0x4665#define ADCX140_CH3_CFG1 0x4766#define ADCX140_CH3_CFG2 0x4867#define ADCX140_CH3_CFG3 0x4968#define ADCX140_CH3_CFG4 0x4a69#define ADCX140_CH4_CFG0 0x4b70#define ADCX140_CH4_CFG1 0x4c71#define ADCX140_CH4_CFG2 0x4d72#define ADCX140_CH4_CFG3 0x4e73#define ADCX140_CH4_CFG4 0x4f74#define ADCX140_CH5_CFG2 0x5275#define ADCX140_CH5_CFG3 0x5376#define ADCX140_CH5_CFG4 0x5477#define ADCX140_CH6_CFG2 0x5778#define ADCX140_CH6_CFG3 0x5879#define ADCX140_CH6_CFG4 0x5980#define ADCX140_CH7_CFG2 0x5c81#define ADCX140_CH7_CFG3 0x5d82#define ADCX140_CH7_CFG4 0x5e83#define ADCX140_CH8_CFG2 0x6184#define ADCX140_CH8_CFG3 0x6285#define ADCX140_CH8_CFG4 0x6386#define ADCX140_DSP_CFG0 0x6b87#define ADCX140_DSP_CFG1 0x6c88#define ADCX140_DRE_CFG0 0x6d89#define ADCX140_AGC_CFG0 0x7090#define ADCX140_IN_CH_EN 0x7391#define ADCX140_ASI_OUT_CH_EN 0x7492#define ADCX140_PWR_CFG 0x7593#define ADCX140_DEV_STS0 0x7694#define ADCX140_DEV_STS1 0x7795#define ADCX140_PHASE_CALIB 0X7b96 97#define ADCX140_RESET BIT(0)98 99#define ADCX140_WAKE_DEV BIT(0)100#define ADCX140_AREG_INTERNAL BIT(7)101 102#define ADCX140_BCLKINV_BIT BIT(2)103#define ADCX140_FSYNCINV_BIT BIT(3)104#define ADCX140_INV_MSK (ADCX140_BCLKINV_BIT | ADCX140_FSYNCINV_BIT)105#define ADCX140_BCLK_FSYNC_MASTER BIT(7)106#define ADCX140_I2S_MODE_BIT BIT(6)107#define ADCX140_LEFT_JUST_BIT BIT(7)108#define ADCX140_ASI_FORMAT_MSK (ADCX140_I2S_MODE_BIT | ADCX140_LEFT_JUST_BIT)109 110#define ADCX140_16_BIT_WORD 0x0111#define ADCX140_20_BIT_WORD BIT(4)112#define ADCX140_24_BIT_WORD BIT(5)113#define ADCX140_32_BIT_WORD (BIT(4) | BIT(5))114#define ADCX140_WORD_LEN_MSK 0x30115 116#define ADCX140_MAX_CHANNELS 8117 118#define ADCX140_MIC_BIAS_VAL_VREF 0119#define ADCX140_MIC_BIAS_VAL_VREF_1096 1120#define ADCX140_MIC_BIAS_VAL_AVDD 6121#define ADCX140_MIC_BIAS_VAL_MSK GENMASK(6, 4)122#define ADCX140_MIC_BIAS_SHIFT 4123 124#define ADCX140_MIC_BIAS_VREF_275V 0125#define ADCX140_MIC_BIAS_VREF_25V 1126#define ADCX140_MIC_BIAS_VREF_1375V 2127#define ADCX140_MIC_BIAS_VREF_MSK GENMASK(1, 0)128 129#define ADCX140_PWR_CTRL_MSK GENMASK(7, 5)130#define ADCX140_PWR_CFG_BIAS_PDZ BIT(7)131#define ADCX140_PWR_CFG_ADC_PDZ BIT(6)132#define ADCX140_PWR_CFG_PLL_PDZ BIT(5)133 134#define ADCX140_TX_OFFSET_MASK GENMASK(4, 0)135 136#define ADCX140_NUM_PDM_EDGES 4137#define ADCX140_PDM_EDGE_SHIFT 7138 139#define ADCX140_NUM_GPI_PINS 4140#define ADCX140_GPI_SHIFT 4141#define ADCX140_GPI1_INDEX 0142#define ADCX140_GPI2_INDEX 1143#define ADCX140_GPI3_INDEX 2144#define ADCX140_GPI4_INDEX 3145 146#define ADCX140_NUM_GPOS 4147#define ADCX140_NUM_GPO_CFGS 2148#define ADCX140_GPO_SHIFT 4149#define ADCX140_GPO_CFG_MAX 4150#define ADCX140_GPO_DRV_MAX 5151 152#define ADCX140_TX_FILL BIT(0)153 154#define ADCX140_NUM_GPIO_CFGS 2155#define ADCX140_GPIO_SHIFT 4156#define ADCX140_GPIO_CFG_MAX 15157#define ADCX140_GPIO_DRV_MAX 5158 159#endif /* _TLV320ADCX140_ */160