1856 lines · c
1// SPDX-License-Identifier: GPL-2.02/*3 * ALSA SoC TLV320AIC31xx CODEC Driver4 *5 * Copyright (C) 2014-2017 Texas Instruments Incorporated - https://www.ti.com/6 * Jyri Sarha <jsarha@ti.com>7 *8 * Based on ground work by: Ajit Kulkarni <x0175765@ti.com>9 *10 * The TLV320AIC31xx series of audio codecs are low-power, highly integrated11 * high performance codecs which provides a stereo DAC, a mono ADC,12 * and mono/stereo Class-D speaker driver.13 */14 15#include <linux/unaligned.h>16#include <linux/module.h>17#include <linux/moduleparam.h>18#include <linux/init.h>19#include <linux/clk.h>20#include <linux/delay.h>21#include <linux/pm.h>22#include <linux/i2c.h>23#include <linux/gpio/consumer.h>24#include <linux/regulator/consumer.h>25#include <linux/acpi.h>26#include <linux/firmware.h>27#include <linux/of.h>28#include <linux/slab.h>29#include <sound/core.h>30#include <sound/jack.h>31#include <sound/pcm.h>32#include <sound/pcm_params.h>33#include <sound/soc.h>34#include <sound/initval.h>35#include <sound/tlv.h>36#include <dt-bindings/sound/tlv320aic31xx.h>37 38#include "tlv320aic31xx.h"39 40static int aic31xx_set_jack(struct snd_soc_component *component,41 struct snd_soc_jack *jack, void *data);42 43static const struct reg_default aic31xx_reg_defaults[] = {44 { AIC31XX_CLKMUX, 0x00 },45 { AIC31XX_PLLPR, 0x11 },46 { AIC31XX_PLLJ, 0x04 },47 { AIC31XX_PLLDMSB, 0x00 },48 { AIC31XX_PLLDLSB, 0x00 },49 { AIC31XX_NDAC, 0x01 },50 { AIC31XX_MDAC, 0x01 },51 { AIC31XX_DOSRMSB, 0x00 },52 { AIC31XX_DOSRLSB, 0x80 },53 { AIC31XX_NADC, 0x01 },54 { AIC31XX_MADC, 0x01 },55 { AIC31XX_AOSR, 0x80 },56 { AIC31XX_IFACE1, 0x00 },57 { AIC31XX_DATA_OFFSET, 0x00 },58 { AIC31XX_IFACE2, 0x00 },59 { AIC31XX_BCLKN, 0x01 },60 { AIC31XX_DACSETUP, 0x14 },61 { AIC31XX_DACMUTE, 0x0c },62 { AIC31XX_LDACVOL, 0x00 },63 { AIC31XX_RDACVOL, 0x00 },64 { AIC31XX_ADCSETUP, 0x00 },65 { AIC31XX_ADCFGA, 0x80 },66 { AIC31XX_ADCVOL, 0x00 },67 { AIC31XX_HPDRIVER, 0x04 },68 { AIC31XX_SPKAMP, 0x06 },69 { AIC31XX_DACMIXERROUTE, 0x00 },70 { AIC31XX_LANALOGHPL, 0x7f },71 { AIC31XX_RANALOGHPR, 0x7f },72 { AIC31XX_LANALOGSPL, 0x7f },73 { AIC31XX_RANALOGSPR, 0x7f },74 { AIC31XX_HPLGAIN, 0x02 },75 { AIC31XX_HPRGAIN, 0x02 },76 { AIC31XX_SPLGAIN, 0x00 },77 { AIC31XX_SPRGAIN, 0x00 },78 { AIC31XX_MICBIAS, 0x00 },79 { AIC31XX_MICPGA, 0x80 },80 { AIC31XX_MICPGAPI, 0x00 },81 { AIC31XX_MICPGAMI, 0x00 },82};83 84static bool aic31xx_volatile(struct device *dev, unsigned int reg)85{86 switch (reg) {87 case AIC31XX_PAGECTL: /* regmap implementation requires this */88 case AIC31XX_RESET: /* always clears after write */89 case AIC31XX_OT_FLAG:90 case AIC31XX_ADCFLAG:91 case AIC31XX_DACFLAG1:92 case AIC31XX_DACFLAG2:93 case AIC31XX_OFFLAG: /* Sticky interrupt flags */94 case AIC31XX_INTRDACFLAG: /* Sticky interrupt flags */95 case AIC31XX_INTRADCFLAG: /* Sticky interrupt flags */96 case AIC31XX_INTRDACFLAG2:97 case AIC31XX_INTRADCFLAG2:98 case AIC31XX_HSDETECT:99 return true;100 }101 return false;102}103 104static bool aic31xx_writeable(struct device *dev, unsigned int reg)105{106 switch (reg) {107 case AIC31XX_OT_FLAG:108 case AIC31XX_ADCFLAG:109 case AIC31XX_DACFLAG1:110 case AIC31XX_DACFLAG2:111 case AIC31XX_OFFLAG: /* Sticky interrupt flags */112 case AIC31XX_INTRDACFLAG: /* Sticky interrupt flags */113 case AIC31XX_INTRADCFLAG: /* Sticky interrupt flags */114 case AIC31XX_INTRDACFLAG2:115 case AIC31XX_INTRADCFLAG2:116 return false;117 }118 return true;119}120 121static const struct regmap_range_cfg aic31xx_ranges[] = {122 {123 .range_min = 0,124 .range_max = 12 * 128,125 .selector_reg = AIC31XX_PAGECTL,126 .selector_mask = 0xff,127 .selector_shift = 0,128 .window_start = 0,129 .window_len = 128,130 },131};132 133static const struct regmap_config aic31xx_i2c_regmap = {134 .reg_bits = 8,135 .val_bits = 8,136 .writeable_reg = aic31xx_writeable,137 .volatile_reg = aic31xx_volatile,138 .reg_defaults = aic31xx_reg_defaults,139 .num_reg_defaults = ARRAY_SIZE(aic31xx_reg_defaults),140 .cache_type = REGCACHE_RBTREE,141 .ranges = aic31xx_ranges,142 .num_ranges = ARRAY_SIZE(aic31xx_ranges),143 .max_register = 12 * 128,144};145 146static const char * const aic31xx_supply_names[] = {147 "HPVDD",148 "SPRVDD",149 "SPLVDD",150 "AVDD",151 "IOVDD",152 "DVDD",153};154 155#define AIC31XX_NUM_SUPPLIES ARRAY_SIZE(aic31xx_supply_names)156 157struct aic31xx_disable_nb {158 struct notifier_block nb;159 struct aic31xx_priv *aic31xx;160};161 162struct aic31xx_priv {163 struct snd_soc_component *component;164 u8 i2c_regs_status;165 struct device *dev;166 struct regmap *regmap;167 enum aic31xx_type codec_type;168 struct gpio_desc *gpio_reset;169 int micbias_vg;170 struct aic31xx_pdata pdata;171 struct regulator_bulk_data supplies[AIC31XX_NUM_SUPPLIES];172 struct aic31xx_disable_nb disable_nb[AIC31XX_NUM_SUPPLIES];173 struct snd_soc_jack *jack;174 u32 sysclk_id;175 unsigned int sysclk;176 u8 p_div;177 int rate_div_line;178 bool master_dapm_route_applied;179 int irq;180 u8 ocmv; /* output common-mode voltage */181};182 183struct aic31xx_rate_divs {184 u32 mclk_p;185 u32 rate;186 u8 pll_r;187 u8 pll_j;188 u16 pll_d;189 u16 dosr;190 u8 ndac;191 u8 mdac;192 u8 aosr;193 u8 nadc;194 u8 madc;195};196 197/* ADC dividers can be disabled by configuring them to 0 */198static const struct aic31xx_rate_divs aic31xx_divs[] = {199 /* mclk/p rate pll: r j d dosr ndac mdac aors nadc madc */200 /* 8k rate */201 { 512000, 8000, 4, 48, 0, 128, 48, 2, 128, 48, 2},202 {12000000, 8000, 1, 8, 1920, 128, 48, 2, 128, 48, 2},203 {12000000, 8000, 1, 8, 1920, 128, 32, 3, 128, 32, 3},204 {12500000, 8000, 1, 7, 8643, 128, 48, 2, 128, 48, 2},205 /* 11.025k rate */206 { 705600, 11025, 3, 48, 0, 128, 24, 3, 128, 24, 3},207 {12000000, 11025, 1, 7, 5264, 128, 32, 2, 128, 32, 2},208 {12000000, 11025, 1, 8, 4672, 128, 24, 3, 128, 24, 3},209 {12500000, 11025, 1, 7, 2253, 128, 32, 2, 128, 32, 2},210 /* 16k rate */211 { 512000, 16000, 4, 48, 0, 128, 16, 3, 128, 16, 3},212 { 1024000, 16000, 2, 48, 0, 128, 16, 3, 128, 16, 3},213 {12000000, 16000, 1, 8, 1920, 128, 24, 2, 128, 24, 2},214 {12000000, 16000, 1, 8, 1920, 128, 16, 3, 128, 16, 3},215 {12500000, 16000, 1, 7, 8643, 128, 24, 2, 128, 24, 2},216 /* 22.05k rate */217 { 705600, 22050, 4, 36, 0, 128, 12, 3, 128, 12, 3},218 { 1411200, 22050, 2, 36, 0, 128, 12, 3, 128, 12, 3},219 {12000000, 22050, 1, 7, 5264, 128, 16, 2, 128, 16, 2},220 {12000000, 22050, 1, 8, 4672, 128, 12, 3, 128, 12, 3},221 {12500000, 22050, 1, 7, 2253, 128, 16, 2, 128, 16, 2},222 /* 32k rate */223 { 1024000, 32000, 2, 48, 0, 128, 12, 2, 128, 12, 2},224 { 2048000, 32000, 1, 48, 0, 128, 12, 2, 128, 12, 2},225 {12000000, 32000, 1, 8, 1920, 128, 12, 2, 128, 12, 2},226 {12000000, 32000, 1, 8, 1920, 128, 8, 3, 128, 8, 3},227 {12500000, 32000, 1, 7, 8643, 128, 12, 2, 128, 12, 2},228 /* 44.1k rate */229 { 1411200, 44100, 2, 32, 0, 128, 8, 2, 128, 8, 2},230 { 2822400, 44100, 1, 32, 0, 128, 8, 2, 128, 8, 2},231 {12000000, 44100, 1, 7, 5264, 128, 8, 2, 128, 8, 2},232 {12000000, 44100, 1, 8, 4672, 128, 6, 3, 128, 6, 3},233 {12500000, 44100, 1, 7, 2253, 128, 8, 2, 128, 8, 2},234 /* 48k rate */235 { 1536000, 48000, 2, 32, 0, 128, 8, 2, 128, 8, 2},236 { 3072000, 48000, 1, 32, 0, 128, 8, 2, 128, 8, 2},237 {12000000, 48000, 1, 8, 1920, 128, 8, 2, 128, 8, 2},238 {12000000, 48000, 1, 7, 6800, 96, 5, 4, 96, 5, 4},239 {12500000, 48000, 1, 7, 8643, 128, 8, 2, 128, 8, 2},240 /* 88.2k rate */241 { 2822400, 88200, 2, 16, 0, 64, 8, 2, 64, 8, 2},242 { 5644800, 88200, 1, 16, 0, 64, 8, 2, 64, 8, 2},243 {12000000, 88200, 1, 7, 5264, 64, 8, 2, 64, 8, 2},244 {12000000, 88200, 1, 8, 4672, 64, 6, 3, 64, 6, 3},245 {12500000, 88200, 1, 7, 2253, 64, 8, 2, 64, 8, 2},246 /* 96k rate */247 { 3072000, 96000, 2, 16, 0, 64, 8, 2, 64, 8, 2},248 { 6144000, 96000, 1, 16, 0, 64, 8, 2, 64, 8, 2},249 {12000000, 96000, 1, 8, 1920, 64, 8, 2, 64, 8, 2},250 {12000000, 96000, 1, 7, 6800, 48, 5, 4, 48, 5, 4},251 {12500000, 96000, 1, 7, 8643, 64, 8, 2, 64, 8, 2},252 /* 176.4k rate */253 { 5644800, 176400, 2, 8, 0, 32, 8, 2, 32, 8, 2},254 {11289600, 176400, 1, 8, 0, 32, 8, 2, 32, 8, 2},255 {12000000, 176400, 1, 7, 5264, 32, 8, 2, 32, 8, 2},256 {12000000, 176400, 1, 8, 4672, 32, 6, 3, 32, 6, 3},257 {12500000, 176400, 1, 7, 2253, 32, 8, 2, 32, 8, 2},258 /* 192k rate */259 { 6144000, 192000, 2, 8, 0, 32, 8, 2, 32, 8, 2},260 {12288000, 192000, 1, 8, 0, 32, 8, 2, 32, 8, 2},261 {12000000, 192000, 1, 8, 1920, 32, 8, 2, 32, 8, 2},262 {12000000, 192000, 1, 7, 6800, 24, 5, 4, 24, 5, 4},263 {12500000, 192000, 1, 7, 8643, 32, 8, 2, 32, 8, 2},264};265 266static const char * const ldac_in_text[] = {267 "Off", "Left Data", "Right Data", "Mono"268};269 270static const char * const rdac_in_text[] = {271 "Off", "Right Data", "Left Data", "Mono"272};273 274static SOC_ENUM_SINGLE_DECL(ldac_in_enum, AIC31XX_DACSETUP, 4, ldac_in_text);275 276static SOC_ENUM_SINGLE_DECL(rdac_in_enum, AIC31XX_DACSETUP, 2, rdac_in_text);277 278static const char * const mic_select_text[] = {279 "Off", "FFR 10 Ohm", "FFR 20 Ohm", "FFR 40 Ohm"280};281 282static SOC_ENUM_SINGLE_DECL(mic1lp_p_enum, AIC31XX_MICPGAPI, 6,283 mic_select_text);284static SOC_ENUM_SINGLE_DECL(mic1rp_p_enum, AIC31XX_MICPGAPI, 4,285 mic_select_text);286static SOC_ENUM_SINGLE_DECL(mic1lm_p_enum, AIC31XX_MICPGAPI, 2,287 mic_select_text);288 289static SOC_ENUM_SINGLE_DECL(mic1lm_m_enum, AIC31XX_MICPGAMI, 4,290 mic_select_text);291 292static const char * const hp_poweron_time_text[] = {293 "0us", "15.3us", "153us", "1.53ms", "15.3ms", "76.2ms",294 "153ms", "304ms", "610ms", "1.22s", "3.04s", "6.1s" };295 296static SOC_ENUM_SINGLE_DECL(hp_poweron_time_enum, AIC31XX_HPPOP, 3,297 hp_poweron_time_text);298 299static const char * const hp_rampup_step_text[] = {300 "0ms", "0.98ms", "1.95ms", "3.9ms" };301 302static SOC_ENUM_SINGLE_DECL(hp_rampup_step_enum, AIC31XX_HPPOP, 1,303 hp_rampup_step_text);304 305static const char * const vol_soft_step_mode_text[] = {306 "fast", "slow", "disabled" };307 308static SOC_ENUM_SINGLE_DECL(vol_soft_step_mode_enum, AIC31XX_DACSETUP, 0,309 vol_soft_step_mode_text);310 311static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -6350, 50, 0);312static const DECLARE_TLV_DB_SCALE(adc_fgain_tlv, 0, 10, 0);313static const DECLARE_TLV_DB_SCALE(adc_cgain_tlv, -2000, 50, 0);314static const DECLARE_TLV_DB_SCALE(mic_pga_tlv, 0, 50, 0);315static const DECLARE_TLV_DB_SCALE(hp_drv_tlv, 0, 100, 0);316static const DECLARE_TLV_DB_SCALE(class_D_drv_tlv, 600, 600, 0);317static const DECLARE_TLV_DB_SCALE(hp_vol_tlv, -6350, 50, 0);318static const DECLARE_TLV_DB_SCALE(sp_vol_tlv, -6350, 50, 0);319 320/*321 * controls to be exported to the user space322 */323static const struct snd_kcontrol_new common31xx_snd_controls[] = {324 SOC_DOUBLE_R_S_TLV("DAC Playback Volume", AIC31XX_LDACVOL,325 AIC31XX_RDACVOL, 0, -127, 48, 7, 0, dac_vol_tlv),326 327 SOC_DOUBLE_R("HP Driver Playback Switch", AIC31XX_HPLGAIN,328 AIC31XX_HPRGAIN, 2, 1, 0),329 SOC_DOUBLE_R_TLV("HP Driver Playback Volume", AIC31XX_HPLGAIN,330 AIC31XX_HPRGAIN, 3, 0x09, 0, hp_drv_tlv),331 332 SOC_DOUBLE_R_TLV("HP Analog Playback Volume", AIC31XX_LANALOGHPL,333 AIC31XX_RANALOGHPR, 0, 0x7F, 1, hp_vol_tlv),334 335 /* HP de-pop control: apply power not immediately but via ramp336 * function with these psarameters. Note that power up sequence337 * has to wait for this to complete; this is implemented by338 * polling HP driver status in aic31xx_dapm_power_event()339 */340 SOC_ENUM("HP Output Driver Power-On time", hp_poweron_time_enum),341 SOC_ENUM("HP Output Driver Ramp-up step", hp_rampup_step_enum),342 343 SOC_ENUM("Volume Soft Stepping", vol_soft_step_mode_enum),344};345 346static const struct snd_kcontrol_new aic31xx_snd_controls[] = {347 SOC_SINGLE_TLV("ADC Fine Capture Volume", AIC31XX_ADCFGA, 4, 4, 1,348 adc_fgain_tlv),349 350 SOC_SINGLE("ADC Capture Switch", AIC31XX_ADCFGA, 7, 1, 1),351 SOC_DOUBLE_R_S_TLV("ADC Capture Volume", AIC31XX_ADCVOL, AIC31XX_ADCVOL,352 0, -24, 40, 6, 0, adc_cgain_tlv),353 354 SOC_SINGLE_TLV("Mic PGA Capture Volume", AIC31XX_MICPGA, 0,355 119, 0, mic_pga_tlv),356};357 358static const struct snd_kcontrol_new aic311x_snd_controls[] = {359 SOC_DOUBLE_R("Speaker Driver Playback Switch", AIC31XX_SPLGAIN,360 AIC31XX_SPRGAIN, 2, 1, 0),361 SOC_DOUBLE_R_TLV("Speaker Driver Playback Volume", AIC31XX_SPLGAIN,362 AIC31XX_SPRGAIN, 3, 3, 0, class_D_drv_tlv),363 364 SOC_DOUBLE_R_TLV("Speaker Analog Playback Volume", AIC31XX_LANALOGSPL,365 AIC31XX_RANALOGSPR, 0, 0x7F, 1, sp_vol_tlv),366};367 368static const struct snd_kcontrol_new aic310x_snd_controls[] = {369 SOC_SINGLE("Speaker Driver Playback Switch", AIC31XX_SPLGAIN,370 2, 1, 0),371 SOC_SINGLE_TLV("Speaker Driver Playback Volume", AIC31XX_SPLGAIN,372 3, 3, 0, class_D_drv_tlv),373 374 SOC_SINGLE_TLV("Speaker Analog Playback Volume", AIC31XX_LANALOGSPL,375 0, 0x7F, 1, sp_vol_tlv),376};377 378static const struct snd_kcontrol_new ldac_in_control =379 SOC_DAPM_ENUM("DAC Left Input", ldac_in_enum);380 381static const struct snd_kcontrol_new rdac_in_control =382 SOC_DAPM_ENUM("DAC Right Input", rdac_in_enum);383 384static int aic31xx_wait_bits(struct aic31xx_priv *aic31xx, unsigned int reg,385 unsigned int mask, unsigned int wbits, int sleep,386 int count)387{388 unsigned int bits;389 int counter = count;390 int ret = regmap_read(aic31xx->regmap, reg, &bits);391 392 while ((bits & mask) != wbits && counter && !ret) {393 usleep_range(sleep, sleep * 2);394 ret = regmap_read(aic31xx->regmap, reg, &bits);395 counter--;396 }397 if ((bits & mask) != wbits) {398 dev_err(aic31xx->dev,399 "%s: Failed! 0x%x was 0x%x expected 0x%x (%d, 0x%x, %d us)\n",400 __func__, reg, bits, wbits, ret, mask,401 (count - counter) * sleep);402 ret = -1;403 }404 return ret;405}406 407#define WIDGET_BIT(reg, shift) (((shift) << 8) | (reg))408 409static int aic31xx_dapm_power_event(struct snd_soc_dapm_widget *w,410 struct snd_kcontrol *kcontrol, int event)411{412 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);413 struct aic31xx_priv *aic31xx = snd_soc_component_get_drvdata(component);414 unsigned int reg = AIC31XX_DACFLAG1;415 unsigned int mask;416 unsigned int timeout = 500 * USEC_PER_MSEC;417 418 switch (WIDGET_BIT(w->reg, w->shift)) {419 case WIDGET_BIT(AIC31XX_DACSETUP, 7):420 mask = AIC31XX_LDACPWRSTATUS_MASK;421 break;422 case WIDGET_BIT(AIC31XX_DACSETUP, 6):423 mask = AIC31XX_RDACPWRSTATUS_MASK;424 break;425 case WIDGET_BIT(AIC31XX_HPDRIVER, 7):426 mask = AIC31XX_HPLDRVPWRSTATUS_MASK;427 if (event == SND_SOC_DAPM_POST_PMU)428 timeout = 7 * USEC_PER_SEC;429 break;430 case WIDGET_BIT(AIC31XX_HPDRIVER, 6):431 mask = AIC31XX_HPRDRVPWRSTATUS_MASK;432 if (event == SND_SOC_DAPM_POST_PMU)433 timeout = 7 * USEC_PER_SEC;434 break;435 case WIDGET_BIT(AIC31XX_SPKAMP, 7):436 mask = AIC31XX_SPLDRVPWRSTATUS_MASK;437 break;438 case WIDGET_BIT(AIC31XX_SPKAMP, 6):439 mask = AIC31XX_SPRDRVPWRSTATUS_MASK;440 break;441 case WIDGET_BIT(AIC31XX_ADCSETUP, 7):442 mask = AIC31XX_ADCPWRSTATUS_MASK;443 reg = AIC31XX_ADCFLAG;444 break;445 default:446 dev_err(component->dev, "Unknown widget '%s' calling %s\n",447 w->name, __func__);448 return -EINVAL;449 }450 451 switch (event) {452 case SND_SOC_DAPM_POST_PMU:453 return aic31xx_wait_bits(aic31xx, reg, mask, mask,454 5000, timeout / 5000);455 case SND_SOC_DAPM_POST_PMD:456 return aic31xx_wait_bits(aic31xx, reg, mask, 0,457 5000, timeout / 5000);458 default:459 dev_dbg(component->dev,460 "Unhandled dapm widget event %d from %s\n",461 event, w->name);462 }463 return 0;464}465 466static const struct snd_kcontrol_new aic31xx_left_output_switches[] = {467 SOC_DAPM_SINGLE("From Left DAC", AIC31XX_DACMIXERROUTE, 6, 1, 0),468 SOC_DAPM_SINGLE("From MIC1LP", AIC31XX_DACMIXERROUTE, 5, 1, 0),469 SOC_DAPM_SINGLE("From MIC1RP", AIC31XX_DACMIXERROUTE, 4, 1, 0),470};471 472static const struct snd_kcontrol_new aic31xx_right_output_switches[] = {473 SOC_DAPM_SINGLE("From Right DAC", AIC31XX_DACMIXERROUTE, 2, 1, 0),474 SOC_DAPM_SINGLE("From MIC1RP", AIC31XX_DACMIXERROUTE, 1, 1, 0),475};476 477static const struct snd_kcontrol_new dac31xx_left_output_switches[] = {478 SOC_DAPM_SINGLE("From Left DAC", AIC31XX_DACMIXERROUTE, 6, 1, 0),479 SOC_DAPM_SINGLE("From AIN1", AIC31XX_DACMIXERROUTE, 5, 1, 0),480 SOC_DAPM_SINGLE("From AIN2", AIC31XX_DACMIXERROUTE, 4, 1, 0),481};482 483static const struct snd_kcontrol_new dac31xx_right_output_switches[] = {484 SOC_DAPM_SINGLE("From Right DAC", AIC31XX_DACMIXERROUTE, 2, 1, 0),485 SOC_DAPM_SINGLE("From AIN2", AIC31XX_DACMIXERROUTE, 1, 1, 0),486};487 488static const struct snd_kcontrol_new p_term_mic1lp =489 SOC_DAPM_ENUM("MIC1LP P-Terminal", mic1lp_p_enum);490 491static const struct snd_kcontrol_new p_term_mic1rp =492 SOC_DAPM_ENUM("MIC1RP P-Terminal", mic1rp_p_enum);493 494static const struct snd_kcontrol_new p_term_mic1lm =495 SOC_DAPM_ENUM("MIC1LM P-Terminal", mic1lm_p_enum);496 497static const struct snd_kcontrol_new m_term_mic1lm =498 SOC_DAPM_ENUM("MIC1LM M-Terminal", mic1lm_m_enum);499 500static const struct snd_kcontrol_new aic31xx_dapm_hpl_switch =501 SOC_DAPM_SINGLE("Switch", AIC31XX_LANALOGHPL, 7, 1, 0);502 503static const struct snd_kcontrol_new aic31xx_dapm_hpr_switch =504 SOC_DAPM_SINGLE("Switch", AIC31XX_RANALOGHPR, 7, 1, 0);505 506static const struct snd_kcontrol_new aic31xx_dapm_spl_switch =507 SOC_DAPM_SINGLE("Switch", AIC31XX_LANALOGSPL, 7, 1, 0);508 509static const struct snd_kcontrol_new aic31xx_dapm_spr_switch =510 SOC_DAPM_SINGLE("Switch", AIC31XX_RANALOGSPR, 7, 1, 0);511 512static int mic_bias_event(struct snd_soc_dapm_widget *w,513 struct snd_kcontrol *kcontrol, int event)514{515 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);516 struct aic31xx_priv *aic31xx = snd_soc_component_get_drvdata(component);517 518 switch (event) {519 case SND_SOC_DAPM_POST_PMU:520 /* change mic bias voltage to user defined */521 snd_soc_component_update_bits(component, AIC31XX_MICBIAS,522 AIC31XX_MICBIAS_MASK,523 aic31xx->micbias_vg <<524 AIC31XX_MICBIAS_SHIFT);525 dev_dbg(component->dev, "%s: turned on\n", __func__);526 break;527 case SND_SOC_DAPM_PRE_PMD:528 /* turn mic bias off */529 snd_soc_component_update_bits(component, AIC31XX_MICBIAS,530 AIC31XX_MICBIAS_MASK, 0);531 dev_dbg(component->dev, "%s: turned off\n", __func__);532 break;533 }534 return 0;535}536 537static const struct snd_soc_dapm_widget common31xx_dapm_widgets[] = {538 SND_SOC_DAPM_AIF_IN("AIF IN", "Playback", 0, SND_SOC_NOPM, 0, 0),539 540 SND_SOC_DAPM_MUX("DAC Left Input",541 SND_SOC_NOPM, 0, 0, &ldac_in_control),542 SND_SOC_DAPM_MUX("DAC Right Input",543 SND_SOC_NOPM, 0, 0, &rdac_in_control),544 /* DACs */545 SND_SOC_DAPM_DAC_E("DAC Left", "Left Playback",546 AIC31XX_DACSETUP, 7, 0, aic31xx_dapm_power_event,547 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),548 549 SND_SOC_DAPM_DAC_E("DAC Right", "Right Playback",550 AIC31XX_DACSETUP, 6, 0, aic31xx_dapm_power_event,551 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),552 553 /* HP */554 SND_SOC_DAPM_SWITCH("HP Left", SND_SOC_NOPM, 0, 0,555 &aic31xx_dapm_hpl_switch),556 SND_SOC_DAPM_SWITCH("HP Right", SND_SOC_NOPM, 0, 0,557 &aic31xx_dapm_hpr_switch),558 559 /* Output drivers */560 SND_SOC_DAPM_OUT_DRV_E("HPL Driver", AIC31XX_HPDRIVER, 7, 0,561 NULL, 0, aic31xx_dapm_power_event,562 SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_POST_PMU),563 SND_SOC_DAPM_OUT_DRV_E("HPR Driver", AIC31XX_HPDRIVER, 6, 0,564 NULL, 0, aic31xx_dapm_power_event,565 SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_POST_PMU),566 567 /* Mic Bias */568 SND_SOC_DAPM_SUPPLY("MICBIAS", SND_SOC_NOPM, 0, 0, mic_bias_event,569 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),570 571 /* Keep BCLK/WCLK enabled even if DAC/ADC is powered down */572 SND_SOC_DAPM_SUPPLY("Activate I2S clocks", AIC31XX_IFACE2, 2, 0,573 NULL, 0),574 575 /* Outputs */576 SND_SOC_DAPM_OUTPUT("HPL"),577 SND_SOC_DAPM_OUTPUT("HPR"),578};579 580static const struct snd_soc_dapm_widget dac31xx_dapm_widgets[] = {581 /* Inputs */582 SND_SOC_DAPM_INPUT("AIN1"),583 SND_SOC_DAPM_INPUT("AIN2"),584 585 /* Output Mixers */586 SND_SOC_DAPM_MIXER("Output Left", SND_SOC_NOPM, 0, 0,587 dac31xx_left_output_switches,588 ARRAY_SIZE(dac31xx_left_output_switches)),589 SND_SOC_DAPM_MIXER("Output Right", SND_SOC_NOPM, 0, 0,590 dac31xx_right_output_switches,591 ARRAY_SIZE(dac31xx_right_output_switches)),592};593 594static const struct snd_soc_dapm_widget aic31xx_dapm_widgets[] = {595 /* Inputs */596 SND_SOC_DAPM_INPUT("MIC1LP"),597 SND_SOC_DAPM_INPUT("MIC1RP"),598 SND_SOC_DAPM_INPUT("MIC1LM"),599 600 /* Input Selection to MIC_PGA */601 SND_SOC_DAPM_MUX("MIC1LP P-Terminal", SND_SOC_NOPM, 0, 0,602 &p_term_mic1lp),603 SND_SOC_DAPM_MUX("MIC1RP P-Terminal", SND_SOC_NOPM, 0, 0,604 &p_term_mic1rp),605 SND_SOC_DAPM_MUX("MIC1LM P-Terminal", SND_SOC_NOPM, 0, 0,606 &p_term_mic1lm),607 608 /* ADC */609 SND_SOC_DAPM_ADC_E("ADC", "Capture", AIC31XX_ADCSETUP, 7, 0,610 aic31xx_dapm_power_event, SND_SOC_DAPM_POST_PMU |611 SND_SOC_DAPM_POST_PMD),612 613 SND_SOC_DAPM_MUX("MIC1LM M-Terminal", SND_SOC_NOPM, 0, 0,614 &m_term_mic1lm),615 616 /* Enabling & Disabling MIC Gain Ctl */617 SND_SOC_DAPM_PGA("MIC_GAIN_CTL", AIC31XX_MICPGA,618 7, 1, NULL, 0),619 620 /* Output Mixers */621 SND_SOC_DAPM_MIXER("Output Left", SND_SOC_NOPM, 0, 0,622 aic31xx_left_output_switches,623 ARRAY_SIZE(aic31xx_left_output_switches)),624 SND_SOC_DAPM_MIXER("Output Right", SND_SOC_NOPM, 0, 0,625 aic31xx_right_output_switches,626 ARRAY_SIZE(aic31xx_right_output_switches)),627 628 SND_SOC_DAPM_AIF_OUT("AIF OUT", "Capture", 0, SND_SOC_NOPM, 0, 0),629};630 631static const struct snd_soc_dapm_widget aic311x_dapm_widgets[] = {632 /* AIC3111 and AIC3110 have stereo class-D amplifier */633 SND_SOC_DAPM_OUT_DRV_E("SPL ClassD", AIC31XX_SPKAMP, 7, 0, NULL, 0,634 aic31xx_dapm_power_event, SND_SOC_DAPM_POST_PMU |635 SND_SOC_DAPM_POST_PMD),636 SND_SOC_DAPM_OUT_DRV_E("SPR ClassD", AIC31XX_SPKAMP, 6, 0, NULL, 0,637 aic31xx_dapm_power_event, SND_SOC_DAPM_POST_PMU |638 SND_SOC_DAPM_POST_PMD),639 SND_SOC_DAPM_SWITCH("Speaker Left", SND_SOC_NOPM, 0, 0,640 &aic31xx_dapm_spl_switch),641 SND_SOC_DAPM_SWITCH("Speaker Right", SND_SOC_NOPM, 0, 0,642 &aic31xx_dapm_spr_switch),643 SND_SOC_DAPM_OUTPUT("SPL"),644 SND_SOC_DAPM_OUTPUT("SPR"),645};646 647/* AIC3100 and AIC3120 have only mono class-D amplifier */648static const struct snd_soc_dapm_widget aic310x_dapm_widgets[] = {649 SND_SOC_DAPM_OUT_DRV_E("SPK ClassD", AIC31XX_SPKAMP, 7, 0, NULL, 0,650 aic31xx_dapm_power_event, SND_SOC_DAPM_POST_PMU |651 SND_SOC_DAPM_POST_PMD),652 SND_SOC_DAPM_SWITCH("Speaker", SND_SOC_NOPM, 0, 0,653 &aic31xx_dapm_spl_switch),654 SND_SOC_DAPM_OUTPUT("SPK"),655};656 657static const struct snd_soc_dapm_route658common31xx_audio_map[] = {659 /* DAC Input Routing */660 {"DAC Left Input", "Left Data", "AIF IN"},661 {"DAC Left Input", "Right Data", "AIF IN"},662 {"DAC Left Input", "Mono", "AIF IN"},663 {"DAC Right Input", "Left Data", "AIF IN"},664 {"DAC Right Input", "Right Data", "AIF IN"},665 {"DAC Right Input", "Mono", "AIF IN"},666 {"DAC Left", NULL, "DAC Left Input"},667 {"DAC Right", NULL, "DAC Right Input"},668 669 /* HPL path */670 {"HP Left", "Switch", "Output Left"},671 {"HPL Driver", NULL, "HP Left"},672 {"HPL", NULL, "HPL Driver"},673 674 /* HPR path */675 {"HP Right", "Switch", "Output Right"},676 {"HPR Driver", NULL, "HP Right"},677 {"HPR", NULL, "HPR Driver"},678};679 680static const struct snd_soc_dapm_route681dac31xx_audio_map[] = {682 /* Left Output */683 {"Output Left", "From Left DAC", "DAC Left"},684 {"Output Left", "From AIN1", "AIN1"},685 {"Output Left", "From AIN2", "AIN2"},686 687 /* Right Output */688 {"Output Right", "From Right DAC", "DAC Right"},689 {"Output Right", "From AIN2", "AIN2"},690};691 692static const struct snd_soc_dapm_route693aic31xx_audio_map[] = {694 /* Mic input */695 {"MIC1LP P-Terminal", "FFR 10 Ohm", "MIC1LP"},696 {"MIC1LP P-Terminal", "FFR 20 Ohm", "MIC1LP"},697 {"MIC1LP P-Terminal", "FFR 40 Ohm", "MIC1LP"},698 {"MIC1RP P-Terminal", "FFR 10 Ohm", "MIC1RP"},699 {"MIC1RP P-Terminal", "FFR 20 Ohm", "MIC1RP"},700 {"MIC1RP P-Terminal", "FFR 40 Ohm", "MIC1RP"},701 {"MIC1LM P-Terminal", "FFR 10 Ohm", "MIC1LM"},702 {"MIC1LM P-Terminal", "FFR 20 Ohm", "MIC1LM"},703 {"MIC1LM P-Terminal", "FFR 40 Ohm", "MIC1LM"},704 705 {"MIC1LM M-Terminal", "FFR 10 Ohm", "MIC1LM"},706 {"MIC1LM M-Terminal", "FFR 20 Ohm", "MIC1LM"},707 {"MIC1LM M-Terminal", "FFR 40 Ohm", "MIC1LM"},708 709 {"MIC_GAIN_CTL", NULL, "MIC1LP P-Terminal"},710 {"MIC_GAIN_CTL", NULL, "MIC1RP P-Terminal"},711 {"MIC_GAIN_CTL", NULL, "MIC1LM P-Terminal"},712 {"MIC_GAIN_CTL", NULL, "MIC1LM M-Terminal"},713 714 {"ADC", NULL, "MIC_GAIN_CTL"},715 716 {"AIF OUT", NULL, "ADC"},717 718 /* Left Output */719 {"Output Left", "From Left DAC", "DAC Left"},720 {"Output Left", "From MIC1LP", "MIC1LP"},721 {"Output Left", "From MIC1RP", "MIC1RP"},722 723 /* Right Output */724 {"Output Right", "From Right DAC", "DAC Right"},725 {"Output Right", "From MIC1RP", "MIC1RP"},726};727 728static const struct snd_soc_dapm_route729aic311x_audio_map[] = {730 /* SP L path */731 {"Speaker Left", "Switch", "Output Left"},732 {"SPL ClassD", NULL, "Speaker Left"},733 {"SPL", NULL, "SPL ClassD"},734 735 /* SP R path */736 {"Speaker Right", "Switch", "Output Right"},737 {"SPR ClassD", NULL, "Speaker Right"},738 {"SPR", NULL, "SPR ClassD"},739};740 741static const struct snd_soc_dapm_route742aic310x_audio_map[] = {743 /* SP L path */744 {"Speaker", "Switch", "Output Left"},745 {"SPK ClassD", NULL, "Speaker"},746 {"SPK", NULL, "SPK ClassD"},747};748 749/*750 * Always connected DAPM routes for codec clock master modes.751 * If the codec is the master on the I2S bus, we need to power up components752 * to have valid DAC_CLK.753 *754 * In order to have the I2S clocks on the bus either the DACs/ADC need to be755 * enabled, or the P0/R29/D2 (Keep bclk/wclk in power down) need to be set.756 *757 * Otherwise the codec will not generate clocks on the bus.758 */759static const struct snd_soc_dapm_route760common31xx_cm_audio_map[] = {761 {"HPL", NULL, "AIF IN"},762 {"HPR", NULL, "AIF IN"},763 764 {"AIF IN", NULL, "Activate I2S clocks"},765};766 767static const struct snd_soc_dapm_route768aic31xx_cm_audio_map[] = {769 {"AIF OUT", NULL, "MIC1LP"},770 {"AIF OUT", NULL, "MIC1RP"},771 {"AIF OUT", NULL, "MIC1LM"},772 773 {"AIF OUT", NULL, "Activate I2S clocks"},774};775 776static int aic31xx_add_controls(struct snd_soc_component *component)777{778 int ret = 0;779 struct aic31xx_priv *aic31xx = snd_soc_component_get_drvdata(component);780 781 if (!(aic31xx->codec_type & DAC31XX_BIT))782 ret = snd_soc_add_component_controls(783 component, aic31xx_snd_controls,784 ARRAY_SIZE(aic31xx_snd_controls));785 if (ret)786 return ret;787 788 if (aic31xx->codec_type & AIC31XX_STEREO_CLASS_D_BIT)789 ret = snd_soc_add_component_controls(790 component, aic311x_snd_controls,791 ARRAY_SIZE(aic311x_snd_controls));792 else793 ret = snd_soc_add_component_controls(794 component, aic310x_snd_controls,795 ARRAY_SIZE(aic310x_snd_controls));796 797 return ret;798}799 800static int aic31xx_add_widgets(struct snd_soc_component *component)801{802 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);803 struct aic31xx_priv *aic31xx = snd_soc_component_get_drvdata(component);804 int ret = 0;805 806 if (aic31xx->codec_type & DAC31XX_BIT) {807 ret = snd_soc_dapm_new_controls(808 dapm, dac31xx_dapm_widgets,809 ARRAY_SIZE(dac31xx_dapm_widgets));810 if (ret)811 return ret;812 813 ret = snd_soc_dapm_add_routes(dapm, dac31xx_audio_map,814 ARRAY_SIZE(dac31xx_audio_map));815 if (ret)816 return ret;817 } else {818 ret = snd_soc_dapm_new_controls(819 dapm, aic31xx_dapm_widgets,820 ARRAY_SIZE(aic31xx_dapm_widgets));821 if (ret)822 return ret;823 824 ret = snd_soc_dapm_add_routes(dapm, aic31xx_audio_map,825 ARRAY_SIZE(aic31xx_audio_map));826 if (ret)827 return ret;828 }829 830 if (aic31xx->codec_type & AIC31XX_STEREO_CLASS_D_BIT) {831 ret = snd_soc_dapm_new_controls(832 dapm, aic311x_dapm_widgets,833 ARRAY_SIZE(aic311x_dapm_widgets));834 if (ret)835 return ret;836 837 ret = snd_soc_dapm_add_routes(dapm, aic311x_audio_map,838 ARRAY_SIZE(aic311x_audio_map));839 if (ret)840 return ret;841 } else {842 ret = snd_soc_dapm_new_controls(843 dapm, aic310x_dapm_widgets,844 ARRAY_SIZE(aic310x_dapm_widgets));845 if (ret)846 return ret;847 848 ret = snd_soc_dapm_add_routes(dapm, aic310x_audio_map,849 ARRAY_SIZE(aic310x_audio_map));850 if (ret)851 return ret;852 }853 854 return 0;855}856 857static int aic31xx_setup_pll(struct snd_soc_component *component,858 struct snd_pcm_hw_params *params)859{860 struct aic31xx_priv *aic31xx = snd_soc_component_get_drvdata(component);861 int bclk_score = snd_soc_params_to_frame_size(params);862 int mclk_p;863 int bclk_n = 0;864 int match = -1;865 int i;866 867 if (!aic31xx->sysclk || !aic31xx->p_div) {868 dev_err(component->dev, "Master clock not supplied\n");869 return -EINVAL;870 }871 mclk_p = aic31xx->sysclk / aic31xx->p_div;872 873 /* Use PLL as CODEC_CLKIN and DAC_CLK as BDIV_CLKIN */874 snd_soc_component_update_bits(component, AIC31XX_CLKMUX,875 AIC31XX_CODEC_CLKIN_MASK, AIC31XX_CODEC_CLKIN_PLL);876 snd_soc_component_update_bits(component, AIC31XX_IFACE2,877 AIC31XX_BDIVCLK_MASK, AIC31XX_DAC2BCLK);878 879 for (i = 0; i < ARRAY_SIZE(aic31xx_divs); i++) {880 if (aic31xx_divs[i].rate == params_rate(params) &&881 aic31xx_divs[i].mclk_p == mclk_p) {882 int s = (aic31xx_divs[i].dosr * aic31xx_divs[i].mdac) %883 snd_soc_params_to_frame_size(params);884 int bn = (aic31xx_divs[i].dosr * aic31xx_divs[i].mdac) /885 snd_soc_params_to_frame_size(params);886 if (s < bclk_score && bn > 0) {887 match = i;888 bclk_n = bn;889 bclk_score = s;890 }891 }892 }893 894 if (match == -1) {895 dev_err(component->dev,896 "%s: Sample rate (%u) and format not supported\n",897 __func__, params_rate(params));898 /* See below for details on how to fix this. */899 return -EINVAL;900 }901 if (bclk_score != 0) {902 dev_warn(component->dev, "Can not produce exact bitclock");903 /* This is fine if using dsp format, but if using i2s904 there may be trouble. To fix the issue edit the905 aic31xx_divs table for your mclk and sample906 rate. Details can be found from:907 https://www.ti.com/lit/ds/symlink/tlv320aic3100.pdf908 Section: 5.6 CLOCK Generation and PLL909 */910 }911 i = match;912 913 /* PLL configuration */914 snd_soc_component_update_bits(component, AIC31XX_PLLPR, AIC31XX_PLL_MASK,915 (aic31xx->p_div << 4) | aic31xx_divs[i].pll_r);916 snd_soc_component_write(component, AIC31XX_PLLJ, aic31xx_divs[i].pll_j);917 918 snd_soc_component_write(component, AIC31XX_PLLDMSB,919 aic31xx_divs[i].pll_d >> 8);920 snd_soc_component_write(component, AIC31XX_PLLDLSB,921 aic31xx_divs[i].pll_d & 0xff);922 923 /* DAC dividers configuration */924 snd_soc_component_update_bits(component, AIC31XX_NDAC, AIC31XX_PLL_MASK,925 aic31xx_divs[i].ndac);926 snd_soc_component_update_bits(component, AIC31XX_MDAC, AIC31XX_PLL_MASK,927 aic31xx_divs[i].mdac);928 929 snd_soc_component_write(component, AIC31XX_DOSRMSB, aic31xx_divs[i].dosr >> 8);930 snd_soc_component_write(component, AIC31XX_DOSRLSB, aic31xx_divs[i].dosr & 0xff);931 932 /* ADC dividers configuration. Write reset value 1 if not used. */933 snd_soc_component_update_bits(component, AIC31XX_NADC, AIC31XX_PLL_MASK,934 aic31xx_divs[i].nadc ? aic31xx_divs[i].nadc : 1);935 snd_soc_component_update_bits(component, AIC31XX_MADC, AIC31XX_PLL_MASK,936 aic31xx_divs[i].madc ? aic31xx_divs[i].madc : 1);937 938 snd_soc_component_write(component, AIC31XX_AOSR, aic31xx_divs[i].aosr);939 940 /* Bit clock divider configuration. */941 snd_soc_component_update_bits(component, AIC31XX_BCLKN,942 AIC31XX_PLL_MASK, bclk_n);943 944 aic31xx->rate_div_line = i;945 946 dev_dbg(component->dev,947 "pll %d.%04d/%d dosr %d n %d m %d aosr %d n %d m %d bclk_n %d\n",948 aic31xx_divs[i].pll_j,949 aic31xx_divs[i].pll_d,950 aic31xx->p_div,951 aic31xx_divs[i].dosr,952 aic31xx_divs[i].ndac,953 aic31xx_divs[i].mdac,954 aic31xx_divs[i].aosr,955 aic31xx_divs[i].nadc,956 aic31xx_divs[i].madc,957 bclk_n958 );959 960 return 0;961}962 963static int aic31xx_hw_params(struct snd_pcm_substream *substream,964 struct snd_pcm_hw_params *params,965 struct snd_soc_dai *dai)966{967 struct snd_soc_component *component = dai->component;968 struct aic31xx_priv *aic31xx = snd_soc_component_get_drvdata(component);969 u8 data = 0;970 971 dev_dbg(component->dev, "## %s: width %d rate %d\n",972 __func__, params_width(params),973 params_rate(params));974 975 switch (params_width(params)) {976 case 16:977 break;978 case 20:979 data = (AIC31XX_WORD_LEN_20BITS <<980 AIC31XX_IFACE1_DATALEN_SHIFT);981 break;982 case 24:983 data = (AIC31XX_WORD_LEN_24BITS <<984 AIC31XX_IFACE1_DATALEN_SHIFT);985 break;986 case 32:987 data = (AIC31XX_WORD_LEN_32BITS <<988 AIC31XX_IFACE1_DATALEN_SHIFT);989 break;990 default:991 dev_err(component->dev, "%s: Unsupported width %d\n",992 __func__, params_width(params));993 return -EINVAL;994 }995 996 snd_soc_component_update_bits(component, AIC31XX_IFACE1,997 AIC31XX_IFACE1_DATALEN_MASK,998 data);999 1000 /*1001 * If BCLK is used as PLL input, the sysclk is determined by the hw1002 * params. So it must be updated here to match the input frequency.1003 */1004 if (aic31xx->sysclk_id == AIC31XX_PLL_CLKIN_BCLK) {1005 aic31xx->sysclk = params_rate(params) * params_width(params) *1006 params_channels(params);1007 aic31xx->p_div = 1;1008 }1009 1010 return aic31xx_setup_pll(component, params);1011}1012 1013static int aic31xx_dac_mute(struct snd_soc_dai *codec_dai, int mute,1014 int direction)1015{1016 struct snd_soc_component *component = codec_dai->component;1017 1018 if (mute) {1019 snd_soc_component_update_bits(component, AIC31XX_DACMUTE,1020 AIC31XX_DACMUTE_MASK,1021 AIC31XX_DACMUTE_MASK);1022 } else {1023 snd_soc_component_update_bits(component, AIC31XX_DACMUTE,1024 AIC31XX_DACMUTE_MASK, 0x0);1025 }1026 1027 return 0;1028}1029 1030static int aic31xx_clock_master_routes(struct snd_soc_component *component,1031 unsigned int fmt)1032{1033 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);1034 struct aic31xx_priv *aic31xx = snd_soc_component_get_drvdata(component);1035 int ret;1036 1037 fmt &= SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK;1038 if (fmt == SND_SOC_DAIFMT_CBC_CFC &&1039 aic31xx->master_dapm_route_applied) {1040 /*1041 * Remove the DAPM route(s) for codec clock master modes,1042 * if applied1043 */1044 ret = snd_soc_dapm_del_routes(dapm, common31xx_cm_audio_map,1045 ARRAY_SIZE(common31xx_cm_audio_map));1046 if (!ret && !(aic31xx->codec_type & DAC31XX_BIT))1047 ret = snd_soc_dapm_del_routes(dapm,1048 aic31xx_cm_audio_map,1049 ARRAY_SIZE(aic31xx_cm_audio_map));1050 1051 if (ret)1052 return ret;1053 1054 aic31xx->master_dapm_route_applied = false;1055 } else if (fmt != SND_SOC_DAIFMT_CBC_CFC &&1056 !aic31xx->master_dapm_route_applied) {1057 /*1058 * Add the needed DAPM route(s) for codec clock master modes,1059 * if it is not done already1060 */1061 ret = snd_soc_dapm_add_routes(dapm, common31xx_cm_audio_map,1062 ARRAY_SIZE(common31xx_cm_audio_map));1063 if (!ret && !(aic31xx->codec_type & DAC31XX_BIT))1064 ret = snd_soc_dapm_add_routes(dapm,1065 aic31xx_cm_audio_map,1066 ARRAY_SIZE(aic31xx_cm_audio_map));1067 1068 if (ret)1069 return ret;1070 1071 aic31xx->master_dapm_route_applied = true;1072 }1073 1074 return 0;1075}1076 1077static int aic31xx_set_dai_fmt(struct snd_soc_dai *codec_dai,1078 unsigned int fmt)1079{1080 struct snd_soc_component *component = codec_dai->component;1081 u8 iface_reg1 = 0;1082 u8 iface_reg2 = 0;1083 u8 dsp_a_val = 0;1084 1085 dev_dbg(component->dev, "## %s: fmt = 0x%x\n", __func__, fmt);1086 1087 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {1088 case SND_SOC_DAIFMT_CBP_CFP:1089 iface_reg1 |= AIC31XX_BCLK_MASTER | AIC31XX_WCLK_MASTER;1090 break;1091 case SND_SOC_DAIFMT_CBC_CFP:1092 iface_reg1 |= AIC31XX_WCLK_MASTER;1093 break;1094 case SND_SOC_DAIFMT_CBP_CFC:1095 iface_reg1 |= AIC31XX_BCLK_MASTER;1096 break;1097 case SND_SOC_DAIFMT_CBC_CFC:1098 break;1099 default:1100 dev_err(component->dev, "Invalid DAI clock provider\n");1101 return -EINVAL;1102 }1103 1104 /* signal polarity */1105 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {1106 case SND_SOC_DAIFMT_NB_NF:1107 break;1108 case SND_SOC_DAIFMT_IB_NF:1109 iface_reg2 |= AIC31XX_BCLKINV_MASK;1110 break;1111 default:1112 dev_err(component->dev, "Invalid DAI clock signal polarity\n");1113 return -EINVAL;1114 }1115 1116 /* interface format */1117 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {1118 case SND_SOC_DAIFMT_I2S:1119 break;1120 case SND_SOC_DAIFMT_DSP_A:1121 dsp_a_val = 0x1;1122 fallthrough;1123 case SND_SOC_DAIFMT_DSP_B:1124 /*1125 * NOTE: This CODEC samples on the falling edge of BCLK in1126 * DSP mode, this is inverted compared to what most DAIs1127 * expect, so we invert for this mode1128 */1129 iface_reg2 ^= AIC31XX_BCLKINV_MASK;1130 iface_reg1 |= (AIC31XX_DSP_MODE <<1131 AIC31XX_IFACE1_DATATYPE_SHIFT);1132 break;1133 case SND_SOC_DAIFMT_RIGHT_J:1134 iface_reg1 |= (AIC31XX_RIGHT_JUSTIFIED_MODE <<1135 AIC31XX_IFACE1_DATATYPE_SHIFT);1136 break;1137 case SND_SOC_DAIFMT_LEFT_J:1138 iface_reg1 |= (AIC31XX_LEFT_JUSTIFIED_MODE <<1139 AIC31XX_IFACE1_DATATYPE_SHIFT);1140 break;1141 default:1142 dev_err(component->dev, "Invalid DAI interface format\n");1143 return -EINVAL;1144 }1145 1146 snd_soc_component_update_bits(component, AIC31XX_IFACE1,1147 AIC31XX_IFACE1_DATATYPE_MASK |1148 AIC31XX_IFACE1_MASTER_MASK,1149 iface_reg1);1150 snd_soc_component_update_bits(component, AIC31XX_DATA_OFFSET,1151 AIC31XX_DATA_OFFSET_MASK,1152 dsp_a_val);1153 snd_soc_component_update_bits(component, AIC31XX_IFACE2,1154 AIC31XX_BCLKINV_MASK,1155 iface_reg2);1156 1157 return aic31xx_clock_master_routes(component, fmt);1158}1159 1160static int aic31xx_set_dai_sysclk(struct snd_soc_dai *codec_dai,1161 int clk_id, unsigned int freq, int dir)1162{1163 struct snd_soc_component *component = codec_dai->component;1164 struct aic31xx_priv *aic31xx = snd_soc_component_get_drvdata(component);1165 int i;1166 1167 dev_dbg(component->dev, "## %s: clk_id = %d, freq = %d, dir = %d\n",1168 __func__, clk_id, freq, dir);1169 1170 for (i = 1; i < 8; i++)1171 if (freq / i <= 20000000)1172 break;1173 if (freq/i > 20000000) {1174 dev_err(aic31xx->dev, "%s: Too high mclk frequency %u\n",1175 __func__, freq);1176 return -EINVAL;1177 }1178 aic31xx->p_div = i;1179 1180 for (i = 0; i < ARRAY_SIZE(aic31xx_divs); i++)1181 if (aic31xx_divs[i].mclk_p == freq / aic31xx->p_div)1182 break;1183 if (i == ARRAY_SIZE(aic31xx_divs)) {1184 dev_err(aic31xx->dev, "%s: Unsupported frequency %d\n",1185 __func__, freq);1186 return -EINVAL;1187 }1188 1189 /* set clock on MCLK, BCLK, or GPIO1 as PLL input */1190 snd_soc_component_update_bits(component, AIC31XX_CLKMUX, AIC31XX_PLL_CLKIN_MASK,1191 clk_id << AIC31XX_PLL_CLKIN_SHIFT);1192 1193 aic31xx->sysclk_id = clk_id;1194 aic31xx->sysclk = freq;1195 1196 return 0;1197}1198 1199static int aic31xx_regulator_event(struct notifier_block *nb,1200 unsigned long event, void *data)1201{1202 struct aic31xx_disable_nb *disable_nb =1203 container_of(nb, struct aic31xx_disable_nb, nb);1204 struct aic31xx_priv *aic31xx = disable_nb->aic31xx;1205 1206 if (event & REGULATOR_EVENT_DISABLE) {1207 /*1208 * Put codec to reset and as at least one of the1209 * supplies was disabled.1210 */1211 if (aic31xx->gpio_reset)1212 gpiod_set_value_cansleep(aic31xx->gpio_reset, 1);1213 1214 regcache_mark_dirty(aic31xx->regmap);1215 dev_dbg(aic31xx->dev, "## %s: DISABLE received\n", __func__);1216 }1217 1218 return 0;1219}1220 1221static int aic31xx_reset(struct aic31xx_priv *aic31xx)1222{1223 int ret = 0;1224 1225 if (aic31xx->gpio_reset) {1226 gpiod_set_value_cansleep(aic31xx->gpio_reset, 1);1227 ndelay(10); /* At least 10ns */1228 gpiod_set_value_cansleep(aic31xx->gpio_reset, 0);1229 } else {1230 ret = regmap_write(aic31xx->regmap, AIC31XX_RESET, 1);1231 }1232 mdelay(1); /* At least 1ms */1233 1234 return ret;1235}1236 1237static void aic31xx_clk_on(struct snd_soc_component *component)1238{1239 struct aic31xx_priv *aic31xx = snd_soc_component_get_drvdata(component);1240 u8 mask = AIC31XX_PM_MASK;1241 u8 on = AIC31XX_PM_MASK;1242 1243 dev_dbg(component->dev, "codec clock -> on (rate %d)\n",1244 aic31xx_divs[aic31xx->rate_div_line].rate);1245 snd_soc_component_update_bits(component, AIC31XX_PLLPR, mask, on);1246 mdelay(10);1247 snd_soc_component_update_bits(component, AIC31XX_NDAC, mask, on);1248 snd_soc_component_update_bits(component, AIC31XX_MDAC, mask, on);1249 if (aic31xx_divs[aic31xx->rate_div_line].nadc)1250 snd_soc_component_update_bits(component, AIC31XX_NADC, mask, on);1251 if (aic31xx_divs[aic31xx->rate_div_line].madc)1252 snd_soc_component_update_bits(component, AIC31XX_MADC, mask, on);1253 snd_soc_component_update_bits(component, AIC31XX_BCLKN, mask, on);1254}1255 1256static void aic31xx_clk_off(struct snd_soc_component *component)1257{1258 u8 mask = AIC31XX_PM_MASK;1259 u8 off = 0;1260 1261 dev_dbg(component->dev, "codec clock -> off\n");1262 snd_soc_component_update_bits(component, AIC31XX_BCLKN, mask, off);1263 snd_soc_component_update_bits(component, AIC31XX_MADC, mask, off);1264 snd_soc_component_update_bits(component, AIC31XX_NADC, mask, off);1265 snd_soc_component_update_bits(component, AIC31XX_MDAC, mask, off);1266 snd_soc_component_update_bits(component, AIC31XX_NDAC, mask, off);1267 snd_soc_component_update_bits(component, AIC31XX_PLLPR, mask, off);1268}1269 1270static int aic31xx_power_on(struct snd_soc_component *component)1271{1272 struct aic31xx_priv *aic31xx = snd_soc_component_get_drvdata(component);1273 int ret;1274 1275 ret = regulator_bulk_enable(ARRAY_SIZE(aic31xx->supplies),1276 aic31xx->supplies);1277 if (ret)1278 return ret;1279 1280 regcache_cache_only(aic31xx->regmap, false);1281 1282 /* Reset device registers for a consistent power-on like state */1283 ret = aic31xx_reset(aic31xx);1284 if (ret < 0)1285 dev_err(aic31xx->dev, "Could not reset device: %d\n", ret);1286 1287 ret = regcache_sync(aic31xx->regmap);1288 if (ret) {1289 dev_err(component->dev,1290 "Failed to restore cache: %d\n", ret);1291 regcache_cache_only(aic31xx->regmap, true);1292 regulator_bulk_disable(ARRAY_SIZE(aic31xx->supplies),1293 aic31xx->supplies);1294 return ret;1295 }1296 1297 /*1298 * The jack detection configuration is in the same register1299 * that is used to report jack detect status so is volatile1300 * and not covered by the cache sync, restore it separately.1301 */1302 aic31xx_set_jack(component, aic31xx->jack, NULL);1303 1304 return 0;1305}1306 1307static void aic31xx_power_off(struct snd_soc_component *component)1308{1309 struct aic31xx_priv *aic31xx = snd_soc_component_get_drvdata(component);1310 1311 regcache_cache_only(aic31xx->regmap, true);1312 regulator_bulk_disable(ARRAY_SIZE(aic31xx->supplies),1313 aic31xx->supplies);1314}1315 1316static int aic31xx_set_bias_level(struct snd_soc_component *component,1317 enum snd_soc_bias_level level)1318{1319 dev_dbg(component->dev, "## %s: %d -> %d\n", __func__,1320 snd_soc_component_get_bias_level(component), level);1321 1322 switch (level) {1323 case SND_SOC_BIAS_ON:1324 break;1325 case SND_SOC_BIAS_PREPARE:1326 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_STANDBY)1327 aic31xx_clk_on(component);1328 break;1329 case SND_SOC_BIAS_STANDBY:1330 switch (snd_soc_component_get_bias_level(component)) {1331 case SND_SOC_BIAS_OFF:1332 aic31xx_power_on(component);1333 break;1334 case SND_SOC_BIAS_PREPARE:1335 aic31xx_clk_off(component);1336 break;1337 default:1338 BUG();1339 }1340 break;1341 case SND_SOC_BIAS_OFF:1342 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_STANDBY)1343 aic31xx_power_off(component);1344 break;1345 }1346 1347 return 0;1348}1349 1350static int aic31xx_set_jack(struct snd_soc_component *component,1351 struct snd_soc_jack *jack, void *data)1352{1353 struct aic31xx_priv *aic31xx = snd_soc_component_get_drvdata(component);1354 1355 aic31xx->jack = jack;1356 1357 /* Enable/Disable jack detection */1358 regmap_write(aic31xx->regmap, AIC31XX_HSDETECT,1359 jack ? AIC31XX_HSD_ENABLE : 0);1360 1361 return 0;1362}1363 1364static int aic31xx_codec_probe(struct snd_soc_component *component)1365{1366 struct aic31xx_priv *aic31xx = snd_soc_component_get_drvdata(component);1367 int i, ret;1368 1369 dev_dbg(aic31xx->dev, "## %s\n", __func__);1370 1371 aic31xx->component = component;1372 1373 for (i = 0; i < ARRAY_SIZE(aic31xx->supplies); i++) {1374 aic31xx->disable_nb[i].nb.notifier_call =1375 aic31xx_regulator_event;1376 aic31xx->disable_nb[i].aic31xx = aic31xx;1377 ret = devm_regulator_register_notifier(1378 aic31xx->supplies[i].consumer,1379 &aic31xx->disable_nb[i].nb);1380 if (ret) {1381 dev_err(component->dev,1382 "Failed to request regulator notifier: %d\n",1383 ret);1384 return ret;1385 }1386 }1387 1388 regcache_cache_only(aic31xx->regmap, true);1389 regcache_mark_dirty(aic31xx->regmap);1390 1391 ret = aic31xx_add_controls(component);1392 if (ret)1393 return ret;1394 1395 ret = aic31xx_add_widgets(component);1396 if (ret)1397 return ret;1398 1399 /* set output common-mode voltage */1400 snd_soc_component_update_bits(component, AIC31XX_HPDRIVER,1401 AIC31XX_HPD_OCMV_MASK,1402 aic31xx->ocmv << AIC31XX_HPD_OCMV_SHIFT);1403 1404 return 0;1405}1406 1407static const struct snd_soc_component_driver soc_codec_driver_aic31xx = {1408 .probe = aic31xx_codec_probe,1409 .set_jack = aic31xx_set_jack,1410 .set_bias_level = aic31xx_set_bias_level,1411 .controls = common31xx_snd_controls,1412 .num_controls = ARRAY_SIZE(common31xx_snd_controls),1413 .dapm_widgets = common31xx_dapm_widgets,1414 .num_dapm_widgets = ARRAY_SIZE(common31xx_dapm_widgets),1415 .dapm_routes = common31xx_audio_map,1416 .num_dapm_routes = ARRAY_SIZE(common31xx_audio_map),1417 .suspend_bias_off = 1,1418 .idle_bias_on = 1,1419 .use_pmdown_time = 1,1420 .endianness = 1,1421};1422 1423static const struct snd_soc_dai_ops aic31xx_dai_ops = {1424 .hw_params = aic31xx_hw_params,1425 .set_sysclk = aic31xx_set_dai_sysclk,1426 .set_fmt = aic31xx_set_dai_fmt,1427 .mute_stream = aic31xx_dac_mute,1428 .no_capture_mute = 1,1429};1430 1431static struct snd_soc_dai_driver dac31xx_dai_driver[] = {1432 {1433 .name = "tlv320dac31xx-hifi",1434 .playback = {1435 .stream_name = "Playback",1436 .channels_min = 2,1437 .channels_max = 2,1438 .rates = AIC31XX_RATES,1439 .formats = AIC31XX_FORMATS,1440 },1441 .ops = &aic31xx_dai_ops,1442 .symmetric_rate = 1,1443 }1444};1445 1446static struct snd_soc_dai_driver aic31xx_dai_driver[] = {1447 {1448 .name = "tlv320aic31xx-hifi",1449 .playback = {1450 .stream_name = "Playback",1451 .channels_min = 2,1452 .channels_max = 2,1453 .rates = AIC31XX_RATES,1454 .formats = AIC31XX_FORMATS,1455 },1456 .capture = {1457 .stream_name = "Capture",1458 .channels_min = 2,1459 .channels_max = 2,1460 .rates = AIC31XX_RATES,1461 .formats = AIC31XX_FORMATS,1462 },1463 .ops = &aic31xx_dai_ops,1464 .symmetric_rate = 1,1465 }1466};1467 1468#if defined(CONFIG_OF)1469static const struct of_device_id tlv320aic31xx_of_match[] = {1470 { .compatible = "ti,tlv320aic310x" },1471 { .compatible = "ti,tlv320aic311x" },1472 { .compatible = "ti,tlv320aic3100" },1473 { .compatible = "ti,tlv320aic3110" },1474 { .compatible = "ti,tlv320aic3120" },1475 { .compatible = "ti,tlv320aic3111" },1476 { .compatible = "ti,tlv320dac3100" },1477 { .compatible = "ti,tlv320dac3101" },1478 {},1479};1480MODULE_DEVICE_TABLE(of, tlv320aic31xx_of_match);1481#endif /* CONFIG_OF */1482 1483#ifdef CONFIG_ACPI1484static const struct acpi_device_id aic31xx_acpi_match[] = {1485 { "10TI3100", 0 },1486 { }1487};1488MODULE_DEVICE_TABLE(acpi, aic31xx_acpi_match);1489#endif1490 1491static irqreturn_t aic31xx_irq(int irq, void *data)1492{1493 struct aic31xx_priv *aic31xx = data;1494 struct device *dev = aic31xx->dev;1495 unsigned int value;1496 bool handled = false;1497 int ret;1498 1499 ret = regmap_read(aic31xx->regmap, AIC31XX_INTRDACFLAG, &value);1500 if (ret) {1501 dev_err(dev, "Failed to read interrupt mask: %d\n", ret);1502 goto exit;1503 }1504 1505 if (value)1506 handled = true;1507 else1508 goto read_overflow;1509 1510 if (value & AIC31XX_HPLSCDETECT)1511 dev_err(dev, "Short circuit on Left output is detected\n");1512 if (value & AIC31XX_HPRSCDETECT)1513 dev_err(dev, "Short circuit on Right output is detected\n");1514 if (value & (AIC31XX_HSPLUG | AIC31XX_BUTTONPRESS)) {1515 unsigned int val;1516 int status = 0;1517 1518 ret = regmap_read(aic31xx->regmap, AIC31XX_INTRDACFLAG2,1519 &val);1520 if (ret) {1521 dev_err(dev, "Failed to read interrupt mask: %d\n",1522 ret);1523 goto exit;1524 }1525 1526 if (val & AIC31XX_BUTTONPRESS)1527 status |= SND_JACK_BTN_0;1528 1529 ret = regmap_read(aic31xx->regmap, AIC31XX_HSDETECT, &val);1530 if (ret) {1531 dev_err(dev, "Failed to read headset type: %d\n", ret);1532 goto exit;1533 }1534 1535 switch ((val & AIC31XX_HSD_TYPE_MASK) >>1536 AIC31XX_HSD_TYPE_SHIFT) {1537 case AIC31XX_HSD_HP:1538 status |= SND_JACK_HEADPHONE;1539 break;1540 case AIC31XX_HSD_HS:1541 status |= SND_JACK_HEADSET;1542 break;1543 default:1544 break;1545 }1546 1547 if (aic31xx->jack)1548 snd_soc_jack_report(aic31xx->jack, status,1549 AIC31XX_JACK_MASK);1550 }1551 if (value & ~(AIC31XX_HPLSCDETECT |1552 AIC31XX_HPRSCDETECT |1553 AIC31XX_HSPLUG |1554 AIC31XX_BUTTONPRESS))1555 dev_err(dev, "Unknown DAC interrupt flags: 0x%08x\n", value);1556 1557read_overflow:1558 ret = regmap_read(aic31xx->regmap, AIC31XX_OFFLAG, &value);1559 if (ret) {1560 dev_err(dev, "Failed to read overflow flag: %d\n", ret);1561 goto exit;1562 }1563 1564 if (value)1565 handled = true;1566 else1567 goto exit;1568 1569 if (value & AIC31XX_DAC_OF_LEFT)1570 dev_warn(dev, "Left-channel DAC overflow has occurred\n");1571 if (value & AIC31XX_DAC_OF_RIGHT)1572 dev_warn(dev, "Right-channel DAC overflow has occurred\n");1573 if (value & AIC31XX_DAC_OF_SHIFTER)1574 dev_warn(dev, "DAC barrel shifter overflow has occurred\n");1575 if (value & AIC31XX_ADC_OF)1576 dev_warn(dev, "ADC overflow has occurred\n");1577 if (value & AIC31XX_ADC_OF_SHIFTER)1578 dev_warn(dev, "ADC barrel shifter overflow has occurred\n");1579 if (value & ~(AIC31XX_DAC_OF_LEFT |1580 AIC31XX_DAC_OF_RIGHT |1581 AIC31XX_DAC_OF_SHIFTER |1582 AIC31XX_ADC_OF |1583 AIC31XX_ADC_OF_SHIFTER))1584 dev_warn(dev, "Unknown overflow interrupt flags: 0x%08x\n", value);1585 1586exit:1587 if (handled)1588 return IRQ_HANDLED;1589 else1590 return IRQ_NONE;1591}1592 1593static void aic31xx_configure_ocmv(struct aic31xx_priv *priv)1594{1595 struct device *dev = priv->dev;1596 int dvdd, avdd;1597 u32 value;1598 1599 if (dev->fwnode &&1600 fwnode_property_read_u32(dev->fwnode, "ai31xx-ocmv", &value)) {1601 /* OCMV setting is forced by DT */1602 if (value <= 3) {1603 priv->ocmv = value;1604 return;1605 }1606 }1607 1608 avdd = regulator_get_voltage(priv->supplies[3].consumer);1609 dvdd = regulator_get_voltage(priv->supplies[5].consumer);1610 1611 if (avdd > 3600000 || dvdd > 1950000) {1612 dev_warn(dev,1613 "Too high supply voltage(s) AVDD: %d, DVDD: %d\n",1614 avdd, dvdd);1615 } else if (avdd == 3600000 && dvdd == 1950000) {1616 priv->ocmv = AIC31XX_HPD_OCMV_1_8V;1617 } else if (avdd >= 3300000 && dvdd >= 1800000) {1618 priv->ocmv = AIC31XX_HPD_OCMV_1_65V;1619 } else if (avdd >= 3000000 && dvdd >= 1650000) {1620 priv->ocmv = AIC31XX_HPD_OCMV_1_5V;1621 } else if (avdd >= 2700000 && dvdd >= 1525000) {1622 priv->ocmv = AIC31XX_HPD_OCMV_1_35V;1623 } else {1624 dev_warn(dev,1625 "Invalid supply voltage(s) AVDD: %d, DVDD: %d\n",1626 avdd, dvdd);1627 }1628}1629 1630static const struct i2c_device_id aic31xx_i2c_id[] = {1631 { "tlv320aic310x", AIC3100 },1632 { "tlv320aic311x", AIC3110 },1633 { "tlv320aic3100", AIC3100 },1634 { "tlv320aic3110", AIC3110 },1635 { "tlv320aic3120", AIC3120 },1636 { "tlv320aic3111", AIC3111 },1637 { "tlv320dac3100", DAC3100 },1638 { "tlv320dac3101", DAC3101 },1639 { }1640};1641MODULE_DEVICE_TABLE(i2c, aic31xx_i2c_id);1642 1643static int tlv320dac3100_fw_load(struct aic31xx_priv *aic31xx,1644 const u8 *data, size_t size)1645{1646 int ret, reg;1647 u16 val16;1648 1649 /*1650 * Coefficients firmware binary structure. Multi-byte values are big-endian.1651 *1652 * @0, 16bits: Magic (0xB30C)1653 * @2, 16bits: Version (0x0100 for version 1.0)1654 * @4, 8bits: DAC Processing Block Selection1655 * @5, 62 16-bit values: Page 8 buffer A DAC programmable filter coefficients1656 * @129, 12 16-bit values: Page 9 Buffer A DAC programmable filter coefficients1657 *1658 * Filter coefficients are interpreted as two's complement values1659 * ranging from -32 768 to 32 767. For more details on filter coefficients,1660 * please refer to the TLV320DAC3100 datasheet, tables 6-120 and 6-123.1661 */1662 1663 if (size != 153) {1664 dev_err(aic31xx->dev, "firmware size is %zu, expected 153 bytes\n", size);1665 return -EINVAL;1666 }1667 1668 /* Check magic */1669 val16 = get_unaligned_be16(data);1670 if (val16 != 0xb30c) {1671 dev_err(aic31xx->dev, "fw magic is 0x%04x expected 0xb30c\n", val16);1672 return -EINVAL;1673 }1674 data += 2;1675 1676 /* Check version */1677 val16 = get_unaligned_be16(data);1678 if (val16 != 0x0100) {1679 dev_err(aic31xx->dev, "invalid firmware version 0x%04x! expected 1", val16);1680 return -EINVAL;1681 }1682 data += 2;1683 1684 ret = regmap_write(aic31xx->regmap, AIC31XX_DACPRB, *data);1685 if (ret) {1686 dev_err(aic31xx->dev, "failed to write PRB index: err %d\n", ret);1687 return ret;1688 }1689 data += 1;1690 1691 /* Page 8 Buffer A coefficients */1692 for (reg = 2; reg < 126; reg++) {1693 ret = regmap_write(aic31xx->regmap, AIC31XX_REG(8, reg), *data);1694 if (ret) {1695 dev_err(aic31xx->dev,1696 "failed to write page 8 filter coefficient %d: err %d\n", reg, ret);1697 return ret;1698 }1699 data++;1700 }1701 1702 /* Page 9 Buffer A coefficients */1703 for (reg = 2; reg < 26; reg++) {1704 ret = regmap_write(aic31xx->regmap, AIC31XX_REG(9, reg), *data);1705 if (ret) {1706 dev_err(aic31xx->dev,1707 "failed to write page 9 filter coefficient %d: err %d\n", reg, ret);1708 return ret;1709 }1710 data++;1711 }1712 1713 dev_info(aic31xx->dev, "done loading DAC filter coefficients\n");1714 1715 return ret;1716}1717 1718static int tlv320dac3100_load_coeffs(struct aic31xx_priv *aic31xx,1719 const char *fw_name)1720{1721 const struct firmware *fw;1722 int ret;1723 1724 ret = request_firmware(&fw, fw_name, aic31xx->dev);1725 if (ret)1726 return ret;1727 1728 ret = tlv320dac3100_fw_load(aic31xx, fw->data, fw->size);1729 1730 release_firmware(fw);1731 1732 return ret;1733}1734 1735static int aic31xx_i2c_probe(struct i2c_client *i2c)1736{1737 struct aic31xx_priv *aic31xx;1738 unsigned int micbias_value = MICBIAS_2_0V;1739 const struct i2c_device_id *id = i2c_match_id(aic31xx_i2c_id, i2c);1740 int i, ret;1741 1742 dev_dbg(&i2c->dev, "## %s: %s codec_type = %d\n", __func__,1743 id->name, (int)id->driver_data);1744 1745 aic31xx = devm_kzalloc(&i2c->dev, sizeof(*aic31xx), GFP_KERNEL);1746 if (!aic31xx)1747 return -ENOMEM;1748 1749 aic31xx->regmap = devm_regmap_init_i2c(i2c, &aic31xx_i2c_regmap);1750 if (IS_ERR(aic31xx->regmap)) {1751 ret = PTR_ERR(aic31xx->regmap);1752 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",1753 ret);1754 return ret;1755 }1756 regcache_cache_only(aic31xx->regmap, true);1757 1758 aic31xx->dev = &i2c->dev;1759 aic31xx->irq = i2c->irq;1760 1761 aic31xx->codec_type = id->driver_data;1762 1763 dev_set_drvdata(aic31xx->dev, aic31xx);1764 1765 fwnode_property_read_u32(aic31xx->dev->fwnode, "ai31xx-micbias-vg",1766 &micbias_value);1767 switch (micbias_value) {1768 case MICBIAS_2_0V:1769 case MICBIAS_2_5V:1770 case MICBIAS_AVDDV:1771 aic31xx->micbias_vg = micbias_value;1772 break;1773 default:1774 dev_err(aic31xx->dev, "Bad ai31xx-micbias-vg value %d\n",1775 micbias_value);1776 aic31xx->micbias_vg = MICBIAS_2_0V;1777 }1778 1779 if (dev_get_platdata(aic31xx->dev)) {1780 memcpy(&aic31xx->pdata, dev_get_platdata(aic31xx->dev), sizeof(aic31xx->pdata));1781 aic31xx->codec_type = aic31xx->pdata.codec_type;1782 aic31xx->micbias_vg = aic31xx->pdata.micbias_vg;1783 }1784 1785 aic31xx->gpio_reset = devm_gpiod_get_optional(aic31xx->dev, "reset",1786 GPIOD_OUT_LOW);1787 if (IS_ERR(aic31xx->gpio_reset))1788 return dev_err_probe(aic31xx->dev, PTR_ERR(aic31xx->gpio_reset),1789 "not able to acquire gpio\n");1790 1791 for (i = 0; i < ARRAY_SIZE(aic31xx->supplies); i++)1792 aic31xx->supplies[i].supply = aic31xx_supply_names[i];1793 1794 ret = devm_regulator_bulk_get(aic31xx->dev,1795 ARRAY_SIZE(aic31xx->supplies),1796 aic31xx->supplies);1797 if (ret)1798 return dev_err_probe(aic31xx->dev, ret, "Failed to request supplies\n");1799 1800 aic31xx_configure_ocmv(aic31xx);1801 1802 if (aic31xx->irq > 0) {1803 regmap_update_bits(aic31xx->regmap, AIC31XX_GPIO1,1804 AIC31XX_GPIO1_FUNC_MASK,1805 AIC31XX_GPIO1_INT1 <<1806 AIC31XX_GPIO1_FUNC_SHIFT);1807 1808 regmap_write(aic31xx->regmap, AIC31XX_INT1CTRL,1809 AIC31XX_HSPLUGDET |1810 AIC31XX_BUTTONPRESSDET |1811 AIC31XX_SC |1812 AIC31XX_ENGINE);1813 1814 ret = devm_request_threaded_irq(aic31xx->dev, aic31xx->irq,1815 NULL, aic31xx_irq,1816 IRQF_ONESHOT, "aic31xx-irq",1817 aic31xx);1818 if (ret) {1819 dev_err(aic31xx->dev, "Unable to request IRQ\n");1820 return ret;1821 }1822 }1823 1824 if (aic31xx->codec_type == DAC3100) {1825 ret = tlv320dac3100_load_coeffs(aic31xx, "tlv320dac3100-coeffs.bin");1826 if (ret)1827 dev_warn(aic31xx->dev, "Did not load any filter coefficients\n");1828 }1829 1830 if (aic31xx->codec_type & DAC31XX_BIT)1831 return devm_snd_soc_register_component(&i2c->dev,1832 &soc_codec_driver_aic31xx,1833 dac31xx_dai_driver,1834 ARRAY_SIZE(dac31xx_dai_driver));1835 else1836 return devm_snd_soc_register_component(&i2c->dev,1837 &soc_codec_driver_aic31xx,1838 aic31xx_dai_driver,1839 ARRAY_SIZE(aic31xx_dai_driver));1840}1841 1842static struct i2c_driver aic31xx_i2c_driver = {1843 .driver = {1844 .name = "tlv320aic31xx-codec",1845 .of_match_table = of_match_ptr(tlv320aic31xx_of_match),1846 .acpi_match_table = ACPI_PTR(aic31xx_acpi_match),1847 },1848 .probe = aic31xx_i2c_probe,1849 .id_table = aic31xx_i2c_id,1850};1851module_i2c_driver(aic31xx_i2c_driver);1852 1853MODULE_AUTHOR("Jyri Sarha <jsarha@ti.com>");1854MODULE_DESCRIPTION("ASoC TLV320AIC31xx CODEC Driver");1855MODULE_LICENSE("GPL v2");1856