345 lines · c
1/* SPDX-License-Identifier: GPL-2.0-only */2/*3 * ALSA SoC TLV320AIC3X codec driver4 *5 * Author: Vladimir Barinov, <vbarinov@embeddedalley.com>6 * Copyright: (C) 2007 MontaVista Software, Inc., <source@mvista.com>7 */8 9#ifndef _AIC3X_H10#define _AIC3X_H11 12struct device;13struct regmap_config;14 15extern const struct regmap_config aic3x_regmap;16int aic3x_probe(struct device *dev, struct regmap *regmap, kernel_ulong_t driver_data);17void aic3x_remove(struct device *dev);18 19#define AIC3X_MODEL_3X 020#define AIC3X_MODEL_33 121#define AIC3X_MODEL_3007 222#define AIC3X_MODEL_3104 323#define AIC3X_MODEL_3106 424 25/* AIC3X register space */26#define AIC3X_CACHEREGNUM 11027 28/* Page select register */29#define AIC3X_PAGE_SELECT 030/* Software reset register */31#define AIC3X_RESET 132/* Codec Sample rate select register */33#define AIC3X_SAMPLE_RATE_SEL_REG 234/* PLL progrramming register A */35#define AIC3X_PLL_PROGA_REG 336/* PLL progrramming register B */37#define AIC3X_PLL_PROGB_REG 438/* PLL progrramming register C */39#define AIC3X_PLL_PROGC_REG 540/* PLL progrramming register D */41#define AIC3X_PLL_PROGD_REG 642/* Codec datapath setup register */43#define AIC3X_CODEC_DATAPATH_REG 744/* Audio serial data interface control register A */45#define AIC3X_ASD_INTF_CTRLA 846/* Audio serial data interface control register B */47#define AIC3X_ASD_INTF_CTRLB 948/* Audio serial data interface control register C */49#define AIC3X_ASD_INTF_CTRLC 1050/* Audio overflow status and PLL R value programming register */51#define AIC3X_OVRF_STATUS_AND_PLLR_REG 1152/* Audio codec digital filter control register */53#define AIC3X_CODEC_DFILT_CTRL 1254/* Headset/button press detection register */55#define AIC3X_HEADSET_DETECT_CTRL_A 1356#define AIC3X_HEADSET_DETECT_CTRL_B 1457/* ADC PGA Gain control registers */58#define LADC_VOL 1559#define RADC_VOL 1660/* MIC3 control registers */61#define MIC3LR_2_LADC_CTRL 1762#define MIC3LR_2_RADC_CTRL 1863/* Line1 Input control registers */64#define LINE1L_2_LADC_CTRL 1965#define LINE1R_2_LADC_CTRL 2166#define LINE1R_2_RADC_CTRL 2267#define LINE1L_2_RADC_CTRL 2468/* Line2 Input control registers */69#define LINE2L_2_LADC_CTRL 2070#define LINE2R_2_RADC_CTRL 2371/* MICBIAS Control Register */72#define MICBIAS_CTRL 2573 74/* AGC Control Registers A, B, C */75#define LAGC_CTRL_A 2676#define LAGC_CTRL_B 2777#define LAGC_CTRL_C 2878#define RAGC_CTRL_A 2979#define RAGC_CTRL_B 3080#define RAGC_CTRL_C 3181 82/* DAC Power and Left High Power Output control registers */83#define DAC_PWR 3784#define HPLCOM_CFG 3785/* Right High Power Output control registers */86#define HPRCOM_CFG 3887/* High Power Output Stage Control Register */88#define HPOUT_SC 4089/* DAC Output Switching control registers */90#define DAC_LINE_MUX 4191/* High Power Output Driver Pop Reduction registers */92#define HPOUT_POP_REDUCTION 4293/* DAC Digital control registers */94#define LDAC_VOL 4395#define RDAC_VOL 4496/* Left High Power Output control registers */97#define LINE2L_2_HPLOUT_VOL 4598#define PGAL_2_HPLOUT_VOL 4699#define DACL1_2_HPLOUT_VOL 47100#define LINE2R_2_HPLOUT_VOL 48101#define PGAR_2_HPLOUT_VOL 49102#define DACR1_2_HPLOUT_VOL 50103#define HPLOUT_CTRL 51104/* Left High Power COM control registers */105#define LINE2L_2_HPLCOM_VOL 52106#define PGAL_2_HPLCOM_VOL 53107#define DACL1_2_HPLCOM_VOL 54108#define LINE2R_2_HPLCOM_VOL 55109#define PGAR_2_HPLCOM_VOL 56110#define DACR1_2_HPLCOM_VOL 57111#define HPLCOM_CTRL 58112/* Right High Power Output control registers */113#define LINE2L_2_HPROUT_VOL 59114#define PGAL_2_HPROUT_VOL 60115#define DACL1_2_HPROUT_VOL 61116#define LINE2R_2_HPROUT_VOL 62117#define PGAR_2_HPROUT_VOL 63118#define DACR1_2_HPROUT_VOL 64119#define HPROUT_CTRL 65120/* Right High Power COM control registers */121#define LINE2L_2_HPRCOM_VOL 66122#define PGAL_2_HPRCOM_VOL 67123#define DACL1_2_HPRCOM_VOL 68124#define LINE2R_2_HPRCOM_VOL 69125#define PGAR_2_HPRCOM_VOL 70126#define DACR1_2_HPRCOM_VOL 71127#define HPRCOM_CTRL 72128/* Mono Line Output Plus/Minus control registers */129#define LINE2L_2_MONOLOPM_VOL 73130#define PGAL_2_MONOLOPM_VOL 74131#define DACL1_2_MONOLOPM_VOL 75132#define LINE2R_2_MONOLOPM_VOL 76133#define PGAR_2_MONOLOPM_VOL 77134#define DACR1_2_MONOLOPM_VOL 78135#define MONOLOPM_CTRL 79136/* Class-D speaker driver on tlv320aic3007 */137#define CLASSD_CTRL 73138/* Left Line Output Plus/Minus control registers */139#define LINE2L_2_LLOPM_VOL 80140#define PGAL_2_LLOPM_VOL 81141#define DACL1_2_LLOPM_VOL 82142#define LINE2R_2_LLOPM_VOL 83143#define PGAR_2_LLOPM_VOL 84144#define DACR1_2_LLOPM_VOL 85145#define LLOPM_CTRL 86146/* Right Line Output Plus/Minus control registers */147#define LINE2L_2_RLOPM_VOL 87148#define PGAL_2_RLOPM_VOL 88149#define DACL1_2_RLOPM_VOL 89150#define LINE2R_2_RLOPM_VOL 90151#define PGAR_2_RLOPM_VOL 91152#define DACR1_2_RLOPM_VOL 92153#define RLOPM_CTRL 93154/* GPIO/IRQ registers */155#define AIC3X_STICKY_IRQ_FLAGS_REG 96156#define AIC3X_RT_IRQ_FLAGS_REG 97157#define AIC3X_GPIO1_REG 98158#define AIC3X_GPIO2_REG 99159#define AIC3X_GPIOA_REG 100160#define AIC3X_GPIOB_REG 101161/* Clock generation control register */162#define AIC3X_CLKGEN_CTRL_REG 102163/* New AGC registers */164#define LAGCN_ATTACK 103165#define LAGCN_DECAY 104166#define RAGCN_ATTACK 105167#define RAGCN_DECAY 106168/* New Programmable ADC Digital Path and I2C Bus Condition Register */169#define NEW_ADC_DIGITALPATH 107170/* Passive Analog Signal Bypass Selection During Powerdown Register */171#define PASSIVE_BYPASS 108172/* DAC Quiescent Current Adjustment Register */173#define DAC_ICC_ADJ 109174 175/* Page select register bits */176#define PAGE0_SELECT 0177#define PAGE1_SELECT 1178 179/* Audio serial data interface control register A bits */180#define BIT_CLK_MASTER 0x80181#define WORD_CLK_MASTER 0x40182#define DOUT_TRISTATE 0x20183 184/* Codec Datapath setup register 7 */185#define FSREF_44100 (1 << 7)186#define FSREF_48000 (0 << 7)187#define DUAL_RATE_MODE ((1 << 5) | (1 << 6))188#define LDAC2LCH (0x1 << 3)189#define RDAC2RCH (0x1 << 1)190#define LDAC2RCH (0x2 << 3)191#define RDAC2LCH (0x2 << 1)192#define LDAC2MONOMIX (0x3 << 3)193#define RDAC2MONOMIX (0x3 << 1)194 195/* PLL registers bitfields */196#define PLLP_SHIFT 0197#define PLLP_MASK 7198#define PLLQ_SHIFT 3199#define PLLR_SHIFT 0200#define PLLJ_SHIFT 2201#define PLLD_MSB_SHIFT 0202#define PLLD_LSB_SHIFT 2203 204/* Clock generation register bits */205#define CODEC_CLKIN_PLLDIV 0206#define CODEC_CLKIN_CLKDIV 1207#define PLL_CLKIN_SHIFT 4208#define MCLK_SOURCE 0x0209#define PLL_CLKDIV_SHIFT 0210#define PLLCLK_IN_MASK 0x30211#define PLLCLK_IN_SHIFT 4212#define CLKDIV_IN_MASK 0xc0213#define CLKDIV_IN_SHIFT 6214/* clock in source */215#define CLKIN_MCLK 0216#define CLKIN_GPIO2 1217#define CLKIN_BCLK 2218 219/* Software reset register bits */220#define SOFT_RESET 0x80221 222/* PLL progrramming register A bits */223#define PLL_ENABLE 0x80224 225/* Route bits */226#define ROUTE_ON 0x80227 228/* Mute bits */229#define UNMUTE 0x08230#define MUTE_ON 0x80231 232/* Power bits */233#define LADC_PWR_ON 0x04234#define RADC_PWR_ON 0x04235#define LDAC_PWR_ON 0x80236#define RDAC_PWR_ON 0x40237#define HPLOUT_PWR_ON 0x01238#define HPROUT_PWR_ON 0x01239#define HPLCOM_PWR_ON 0x01240#define HPRCOM_PWR_ON 0x01241#define MONOLOPM_PWR_ON 0x01242#define LLOPM_PWR_ON 0x01243#define RLOPM_PWR_ON 0x01244 245#define INVERT_VOL(val) (0x7f - val)246 247/* Default output volume (inverted) */248#define DEFAULT_VOL INVERT_VOL(0x50)249/* Default input volume */250#define DEFAULT_GAIN 0x20251 252/* MICBIAS Control Register */253#define MICBIAS_LEVEL_SHIFT (6)254#define MICBIAS_LEVEL_MASK (3 << 6)255 256/* HPOUT_SC */257#define HPOUT_SC_OCMV_MASK (3 << 6)258#define HPOUT_SC_OCMV_SHIFT (6)259#define HPOUT_SC_OCMV_1_35V 0260#define HPOUT_SC_OCMV_1_5V 1261#define HPOUT_SC_OCMV_1_65V 2262#define HPOUT_SC_OCMV_1_8V 3263 264/* headset detection / button API */265 266/* The AIC3x supports detection of stereo headsets (GND + left + right signal)267 * and cellular headsets (GND + speaker output + microphone input).268 * It is recommended to enable MIC bias for this function to work properly.269 * For more information, please refer to the datasheet. */270enum {271 AIC3X_HEADSET_DETECT_OFF = 0,272 AIC3X_HEADSET_DETECT_STEREO = 1,273 AIC3X_HEADSET_DETECT_CELLULAR = 2,274 AIC3X_HEADSET_DETECT_BOTH = 3275};276 277enum {278 AIC3X_HEADSET_DEBOUNCE_16MS = 0,279 AIC3X_HEADSET_DEBOUNCE_32MS = 1,280 AIC3X_HEADSET_DEBOUNCE_64MS = 2,281 AIC3X_HEADSET_DEBOUNCE_128MS = 3,282 AIC3X_HEADSET_DEBOUNCE_256MS = 4,283 AIC3X_HEADSET_DEBOUNCE_512MS = 5284};285 286enum {287 AIC3X_BUTTON_DEBOUNCE_0MS = 0,288 AIC3X_BUTTON_DEBOUNCE_8MS = 1,289 AIC3X_BUTTON_DEBOUNCE_16MS = 2,290 AIC3X_BUTTON_DEBOUNCE_32MS = 3291};292 293#define AIC3X_HEADSET_DETECT_ENABLED 0x80294#define AIC3X_HEADSET_DETECT_SHIFT 5295#define AIC3X_HEADSET_DETECT_MASK 3296#define AIC3X_HEADSET_DEBOUNCE_SHIFT 2297#define AIC3X_HEADSET_DEBOUNCE_MASK 7298#define AIC3X_BUTTON_DEBOUNCE_SHIFT 0299#define AIC3X_BUTTON_DEBOUNCE_MASK 3300 301/* GPIO API */302enum {303 AIC3X_GPIO1_FUNC_DISABLED = 0,304 AIC3X_GPIO1_FUNC_AUDIO_WORDCLK_ADC = 1,305 AIC3X_GPIO1_FUNC_CLOCK_MUX = 2,306 AIC3X_GPIO1_FUNC_CLOCK_MUX_DIV2 = 3,307 AIC3X_GPIO1_FUNC_CLOCK_MUX_DIV4 = 4,308 AIC3X_GPIO1_FUNC_CLOCK_MUX_DIV8 = 5,309 AIC3X_GPIO1_FUNC_SHORT_CIRCUIT_IRQ = 6,310 AIC3X_GPIO1_FUNC_AGC_NOISE_IRQ = 7,311 AIC3X_GPIO1_FUNC_INPUT = 8,312 AIC3X_GPIO1_FUNC_OUTPUT = 9,313 AIC3X_GPIO1_FUNC_DIGITAL_MIC_MODCLK = 10,314 AIC3X_GPIO1_FUNC_AUDIO_WORDCLK = 11,315 AIC3X_GPIO1_FUNC_BUTTON_IRQ = 12,316 AIC3X_GPIO1_FUNC_HEADSET_DETECT_IRQ = 13,317 AIC3X_GPIO1_FUNC_HEADSET_DETECT_OR_BUTTON_IRQ = 14,318 AIC3X_GPIO1_FUNC_ALL_IRQ = 16319};320 321enum {322 AIC3X_GPIO2_FUNC_DISABLED = 0,323 AIC3X_GPIO2_FUNC_HEADSET_DETECT_IRQ = 2,324 AIC3X_GPIO2_FUNC_INPUT = 3,325 AIC3X_GPIO2_FUNC_OUTPUT = 4,326 AIC3X_GPIO2_FUNC_DIGITAL_MIC_INPUT = 5,327 AIC3X_GPIO2_FUNC_AUDIO_BITCLK = 8,328 AIC3X_GPIO2_FUNC_HEADSET_DETECT_OR_BUTTON_IRQ = 9,329 AIC3X_GPIO2_FUNC_ALL_IRQ = 10,330 AIC3X_GPIO2_FUNC_SHORT_CIRCUIT_OR_AGC_IRQ = 11,331 AIC3X_GPIO2_FUNC_HEADSET_OR_BUTTON_PRESS_OR_SHORT_CIRCUIT_IRQ = 12,332 AIC3X_GPIO2_FUNC_SHORT_CIRCUIT_IRQ = 13,333 AIC3X_GPIO2_FUNC_AGC_NOISE_IRQ = 14,334 AIC3X_GPIO2_FUNC_BUTTON_PRESS_IRQ = 15335};336 337enum aic3x_micbias_voltage {338 AIC3X_MICBIAS_OFF = 0,339 AIC3X_MICBIAS_2_0V = 1,340 AIC3X_MICBIAS_2_5V = 2,341 AIC3X_MICBIAS_AVDDV = 3,342};343 344#endif /* _AIC3X_H */345